r100d.h revision 267654
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __R100D_H__ 29#define __R100D_H__ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: releng/9.3/sys/dev/drm2/radeon/r100d.h 254885 2013-08-25 19:37:15Z dumbbell $"); 33 34#define CP_PACKET0 0x00000000 35#define PACKET0_BASE_INDEX_SHIFT 0 36#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 37#define PACKET0_COUNT_SHIFT 16 38#define PACKET0_COUNT_MASK (0x3fff << 16) 39#define CP_PACKET1 0x40000000 40#define CP_PACKET2 0x80000000 41#define PACKET2_PAD_SHIFT 0 42#define PACKET2_PAD_MASK (0x3fffffff << 0) 43#define CP_PACKET3 0xC0000000 44#define PACKET3_IT_OPCODE_SHIFT 8 45#define PACKET3_IT_OPCODE_MASK (0xff << 8) 46#define PACKET3_COUNT_SHIFT 16 47#define PACKET3_COUNT_MASK (0x3fff << 16) 48/* PACKET3 op code */ 49#define PACKET3_NOP 0x10 50#define PACKET3_3D_DRAW_VBUF 0x28 51#define PACKET3_3D_DRAW_IMMD 0x29 52#define PACKET3_3D_DRAW_INDX 0x2A 53#define PACKET3_3D_LOAD_VBPNTR 0x2F 54#define PACKET3_3D_CLEAR_ZMASK 0x32 55#define PACKET3_INDX_BUFFER 0x33 56#define PACKET3_3D_DRAW_VBUF_2 0x34 57#define PACKET3_3D_DRAW_IMMD_2 0x35 58#define PACKET3_3D_DRAW_INDX_2 0x36 59#define PACKET3_3D_CLEAR_HIZ 0x37 60#define PACKET3_BITBLT_MULTI 0x9B 61 62#define PACKET0(reg, n) (CP_PACKET0 | \ 63 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 64 REG_SET(PACKET0_COUNT, (n))) 65#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 66#define PACKET3(op, n) (CP_PACKET3 | \ 67 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 68 REG_SET(PACKET3_COUNT, (n))) 69 70#define PACKET_TYPE0 0 71#define PACKET_TYPE1 1 72#define PACKET_TYPE2 2 73#define PACKET_TYPE3 3 74 75#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 76#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 77#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 78#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 79#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 80 81/* Registers */ 82#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 83#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 84#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 85#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 86#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 87#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 88#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 89#define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 90#define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 91#define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 92#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 93#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 94#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 95#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 96#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 97#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 98#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 99#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 100#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 101#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 102#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 103#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 104#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 105#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 106#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 107#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 108#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 109#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 110#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 111#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 112#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 113#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 114#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 115#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 116#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 117#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 118#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 119#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 120#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 121#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 122#define R_000030_BUS_CNTL 0x000030 123#define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 124#define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 125#define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 126#define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 127#define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 128#define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 129#define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 130#define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 131#define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 132#define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 133#define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 134#define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 135#define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 136#define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 137#define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 138#define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 139#define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 140#define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 141#define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 142#define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 143#define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 144#define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 145#define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 146#define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 147#define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 148#define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 149#define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 150#define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 151#define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 152#define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 153#define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 154#define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 155#define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 156#define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 157#define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 158#define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 159#define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 160#define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 161#define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 162#define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 163#define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 164#define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 165#define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 166#define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 167#define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 168#define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 169#define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 170#define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 171#define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 172#define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 173#define C_000030_BUS_RETRY_WS 0xFFF0FFFF 174#define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 175#define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 176#define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 177#define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 178#define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 179#define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 180#define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 181#define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 182#define C_000030_BUS_SUSPEND 0xFFBFFFFF 183#define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 184#define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 185#define C_000030_LAT_16X 0xFF7FFFFF 186#define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 187#define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 188#define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 189#define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 190#define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 191#define C_000030_ENFRCWRDY 0xFDFFFFFF 192#define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 193#define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 194#define C_000030_BUS_MSTR_WS 0xFBFFFFFF 195#define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 196#define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 197#define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 198#define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 199#define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 200#define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 201#define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 202#define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 203#define C_000030_SERR_EN 0xDFFFFFFF 204#define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 205#define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 206#define C_000030_BUS_READ_BURST 0xBFFFFFFF 207#define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 208#define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 209#define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 210#define R_000040_GEN_INT_CNTL 0x000040 211#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 212#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 213#define C_000040_CRTC_VBLANK 0xFFFFFFFE 214#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 215#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 216#define C_000040_CRTC_VLINE 0xFFFFFFFD 217#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 218#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 219#define C_000040_CRTC_VSYNC 0xFFFFFFFB 220#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 221#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 222#define C_000040_SNAPSHOT 0xFFFFFFF7 223#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 224#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 225#define C_000040_FP_DETECT 0xFFFFFFEF 226#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 227#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 228#define C_000040_CRTC2_VLINE 0xFFFFFFDF 229#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 230#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 231#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 232#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 233#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 234#define C_000040_CRTC2_VSYNC 0xFFFFFFBF 235#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 236#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 237#define C_000040_SNAPSHOT2 0xFFFFFF7F 238#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 239#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 240#define C_000040_CRTC2_VBLANK 0xFFFFFDFF 241#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 242#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 243#define C_000040_FP2_DETECT 0xFFFFFBFF 244#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 245#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 246#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 247#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 248#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 249#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 250#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 251#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 252#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 253#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 254#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 255#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 256#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 257#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 258#define C_000040_I2C_INT_EN 0xFFFDFFFF 259#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 260#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 261#define C_000040_GUI_IDLE 0xFFF7FFFF 262#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 263#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 264#define C_000040_VIPH_INT_EN 0xFEFFFFFF 265#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 266#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 267#define C_000040_SW_INT_EN 0xFDFFFFFF 268#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 269#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 270#define C_000040_GEYSERVILLE 0xF7FFFFFF 271#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 272#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 273#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 274#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 275#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 276#define C_000040_DVI_I2C_INT 0xDFFFFFFF 277#define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 278#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 279#define C_000040_GUIDMA 0xBFFFFFFF 280#define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 281#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 282#define C_000040_VIDDMA 0x7FFFFFFF 283#define R_000044_GEN_INT_STATUS 0x000044 284#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 285#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 286#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 287#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 288#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 289#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 290#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 291#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 292#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 293#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 294#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 295#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 296#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 297#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 298#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 299#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 300#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 301#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 302#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 303#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 304#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 305#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 306#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 307#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 308#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 309#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 310#define C_000044_FP_DETECT_STAT 0xFFFFFFEF 311#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 312#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 313#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 314#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 315#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 316#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 317#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 318#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 319#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 320#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 321#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 322#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 323#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 324#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 325#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 326#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 327#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 328#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 329#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 330#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 331#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 332#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 333#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 334#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 335#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 336#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 337#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 338#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 339#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 340#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 341#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 342#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 343#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 344#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 345#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 346#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 347#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 348#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 349#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 350#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 351#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 352#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 353#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 354#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 355#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 356#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 357#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 358#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 359#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 360#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 361#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 362#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 363#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 364#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 365#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 366#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 367#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 368#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 369#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 370#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 371#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 372#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 373#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 374#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 375#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 376#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 377#define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 378#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 379#define C_000044_I2C_INT 0xFFFDFFFF 380#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 381#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 382#define C_000044_I2C_INT_AK 0xFFFDFFFF 383#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 384#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 385#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 386#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 387#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 388#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 389#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 390#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 391#define C_000044_VIPH_INT 0xFEFFFFFF 392#define S_000044_SW_INT(x) (((x) & 0x1) << 25) 393#define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 394#define C_000044_SW_INT 0xFDFFFFFF 395#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 396#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 397#define C_000044_SW_INT_AK 0xFDFFFFFF 398#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 399#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 400#define C_000044_SW_INT_SET 0xFBFFFFFF 401#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 402#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 403#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 404#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 405#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 406#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 407#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 408#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 409#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 410#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 411#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 412#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 413#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 414#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 415#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 416#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 417#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 418#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 419#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 420#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 421#define C_000044_GUIDMA_STAT 0xBFFFFFFF 422#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 423#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 424#define C_000044_GUIDMA_AK 0xBFFFFFFF 425#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 426#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 427#define C_000044_VIDDMA_STAT 0x7FFFFFFF 428#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 429#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 430#define C_000044_VIDDMA_AK 0x7FFFFFFF 431#define R_000050_CRTC_GEN_CNTL 0x000050 432#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 433#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 434#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 435#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 436#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 437#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 438#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 439#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 440#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 441#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 442#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 443#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 444#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 445#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 446#define C_000050_CRTC_ICON_EN 0xFFFF7FFF 447#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 448#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 449#define C_000050_CRTC_CUR_EN 0xFFFEFFFF 450#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 451#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 452#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 453#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 454#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 455#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 456#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 457#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 458#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 459#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 460#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 461#define C_000050_CRTC_EN 0xFDFFFFFF 462#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 463#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 464#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 465#define R_000054_CRTC_EXT_CNTL 0x000054 466#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 467#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 468#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 469#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 470#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 471#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 472#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 473#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 474#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 475#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 476#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 477#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 478#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 479#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 480#define C_000054_VGA_TEXT_132 0xFFFFFFDF 481#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 482#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 483#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 484#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 485#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 486#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 487#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 488#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 489#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 490#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 491#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 492#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 493#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 494#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 495#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 496#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 497#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 498#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 499#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 500#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 501#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 502#define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 503#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 504#define C_000054_CRT_ON 0xFFFF7FFF 505#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 506#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 507#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 508#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 509#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 510#define C_000054_VGA_PACK_DIS 0xFFFBFFFF 511#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 512#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 513#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 514#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 515#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 516#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 517#define R_000148_MC_FB_LOCATION 0x000148 518#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 519#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 520#define C_000148_MC_FB_START 0xFFFF0000 521#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 522#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 523#define C_000148_MC_FB_TOP 0x0000FFFF 524#define R_00014C_MC_AGP_LOCATION 0x00014C 525#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 526#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 527#define C_00014C_MC_AGP_START 0xFFFF0000 528#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 529#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 530#define C_00014C_MC_AGP_TOP 0x0000FFFF 531#define R_000170_AGP_BASE 0x000170 532#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 533#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 534#define C_000170_AGP_BASE_ADDR 0x00000000 535#define R_00023C_DISPLAY_BASE_ADDR 0x00023C 536#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 537#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 538#define C_00023C_DISPLAY_BASE_ADDR 0x00000000 539#define R_000260_CUR_OFFSET 0x000260 540#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 541#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 542#define C_000260_CUR_OFFSET 0xF8000000 543#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 544#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 545#define C_000260_CUR_LOCK 0x7FFFFFFF 546#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 547#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 548#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 549#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 550#define R_000360_CUR2_OFFSET 0x000360 551#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 552#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 553#define C_000360_CUR2_OFFSET 0xF8000000 554#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 555#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 556#define C_000360_CUR2_LOCK 0x7FFFFFFF 557#define R_0003C2_GENMO_WT 0x0003C2 558#define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 559#define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 560#define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 561#define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 562#define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 563#define C_0003C2_VGA_RAM_EN 0xFD 564#define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 565#define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 566#define C_0003C2_VGA_CKSEL 0xF3 567#define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 568#define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 569#define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 570#define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 571#define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 572#define C_0003C2_VGA_HSYNC_POL 0xBF 573#define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 574#define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 575#define C_0003C2_VGA_VSYNC_POL 0x7F 576#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 577#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 578#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 579#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 580#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 581#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 582#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 583#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 584#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 585#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 586#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 587#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 588#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 589#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 590#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 591#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 592#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 593#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 594#define C_0003F8_CRT2_ON 0xFFFFFF7F 595#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 596#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 597#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 598#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 599#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 600#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 601#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 602#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 603#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 604#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 605#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 606#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 607#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 608#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 609#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 610#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 611#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 612#define C_0003F8_CRTC2_EN 0xFDFFFFFF 613#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 614#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 615#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 616#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 617#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 618#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 619#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 620#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 621#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 622#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 623#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 624#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 625#define R_000420_OV0_SCALE_CNTL 0x000420 626#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 627#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 628#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 629#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 630#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 631#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 632#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 633#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 634#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 635#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 636#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 637#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 638#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 639#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 640#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 641#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 642#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 643#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 644#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 645#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 646#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 647#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 648#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 649#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 650#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 651#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 652#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 653#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 654#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 655#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 656#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 657#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 658#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 659#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 660#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 661#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 662#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 663#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 664#define C_000420_OV0_INT_EMU 0xDFFFFFFF 665#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 666#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 667#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 668#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 669#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 670#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 671#define R_00070C_CP_RB_RPTR_ADDR 0x00070C 672#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 673#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 674#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 675#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 676#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 677#define C_00070C_RB_RPTR_ADDR 0x00000003 678#define R_000740_CP_CSQ_CNTL 0x000740 679#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 680#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 681#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 682#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 683#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 684#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 685#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 686#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 687#define C_000740_CSQ_MODE 0x0FFFFFFF 688#define R_000770_SCRATCH_UMSK 0x000770 689#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 690#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 691#define C_000770_SCRATCH_UMSK 0xFFFFFFC0 692#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 693#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 694#define C_000770_SCRATCH_SWAP 0xFFFCFFFF 695#define R_000774_SCRATCH_ADDR 0x000774 696#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 697#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 698#define C_000774_SCRATCH_ADDR 0x0000001F 699#define R_0007C0_CP_STAT 0x0007C0 700#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 701#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 702#define C_0007C0_MRU_BUSY 0xFFFFFFFE 703#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 704#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 705#define C_0007C0_MWU_BUSY 0xFFFFFFFD 706#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 707#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 708#define C_0007C0_RSIU_BUSY 0xFFFFFFFB 709#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 710#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 711#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 712#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 713#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 714#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 715#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 716#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 717#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 718#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 719#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 720#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 721#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 722#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 723#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 724#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 725#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 726#define C_0007C0_CSI_BUSY 0xFFFFDFFF 727#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 728#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 729#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 730#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 731#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 732#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 733#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 734#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 735#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 736#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 737#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 738#define C_0007C0_CP_BUSY 0x7FFFFFFF 739#define R_000E40_RBBM_STATUS 0x000E40 740#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 741#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 742#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 743#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 744#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 745#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 746#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 747#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 748#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 749#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 750#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 751#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 752#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 753#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 754#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 755#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 756#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 757#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 758#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 759#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 760#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 761#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 762#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 763#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 764#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 765#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 766#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 767#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 768#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 769#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 770#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 771#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 772#define C_000E40_E2_BUSY 0xFFFDFFFF 773#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 774#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 775#define C_000E40_RB2D_BUSY 0xFFFBFFFF 776#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 777#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 778#define C_000E40_RB3D_BUSY 0xFFF7FFFF 779#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 780#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 781#define C_000E40_SE_BUSY 0xFFEFFFFF 782#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 783#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 784#define C_000E40_RE_BUSY 0xFFDFFFFF 785#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 786#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 787#define C_000E40_TAM_BUSY 0xFFBFFFFF 788#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 789#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 790#define C_000E40_TDM_BUSY 0xFF7FFFFF 791#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 792#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 793#define C_000E40_PB_BUSY 0xFEFFFFFF 794#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 795#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 796#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 797 798 799#define R_00000D_SCLK_CNTL 0x00000D 800#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 801#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 802#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 803#define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 804#define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 805#define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 806#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 807#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 808#define C_00000D_FORCE_CP 0xFFFEFFFF 809#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 810#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 811#define C_00000D_FORCE_HDP 0xFFFDFFFF 812#define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 813#define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 814#define C_00000D_FORCE_DISP 0xFFFBFFFF 815#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 816#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 817#define C_00000D_FORCE_TOP 0xFFF7FFFF 818#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 819#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 820#define C_00000D_FORCE_E2 0xFFEFFFFF 821#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 822#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 823#define C_00000D_FORCE_SE 0xFFDFFFFF 824#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 825#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 826#define C_00000D_FORCE_IDCT 0xFFBFFFFF 827#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 828#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 829#define C_00000D_FORCE_VIP 0xFF7FFFFF 830#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 831#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 832#define C_00000D_FORCE_RE 0xFEFFFFFF 833#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 834#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 835#define C_00000D_FORCE_PB 0xFDFFFFFF 836#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 837#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 838#define C_00000D_FORCE_TAM 0xFBFFFFFF 839#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 840#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 841#define C_00000D_FORCE_TDM 0xF7FFFFFF 842#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 843#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 844#define C_00000D_FORCE_RB 0xEFFFFFFF 845 846/* PLL regs */ 847#define SCLK_CNTL 0xd 848#define FORCE_HDP (1 << 17) 849#define CLK_PWRMGT_CNTL 0x14 850#define GLOBAL_PMAN_EN (1 << 10) 851#define DISP_PM (1 << 20) 852#define PLL_PWRMGT_CNTL 0x15 853#define MPLL_TURNOFF (1 << 0) 854#define SPLL_TURNOFF (1 << 1) 855#define PPLL_TURNOFF (1 << 2) 856#define P2PLL_TURNOFF (1 << 3) 857#define TVPLL_TURNOFF (1 << 4) 858#define MOBILE_SU (1 << 16) 859#define SU_SCLK_USE_BCLK (1 << 17) 860#define SCLK_CNTL2 0x1e 861#define REDUCED_SPEED_SCLK_MODE (1 << 16) 862#define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 863#define MCLK_MISC 0x1f 864#define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 865#define SCLK_MORE_CNTL 0x35 866#define REDUCED_SPEED_SCLK_EN (1 << 16) 867#define IO_CG_VOLTAGE_DROP (1 << 17) 868#define VOLTAGE_DELAY_SEL(x) ((x) << 20) 869#define VOLTAGE_DROP_SYNC (1 << 19) 870 871/* mmreg */ 872#define DISP_PWR_MAN 0xd08 873#define DISP_D3_GRPH_RST (1 << 18) 874#define DISP_D3_SUBPIC_RST (1 << 19) 875#define DISP_D3_OV0_RST (1 << 20) 876#define DISP_D1D2_GRPH_RST (1 << 21) 877#define DISP_D1D2_SUBPIC_RST (1 << 22) 878#define DISP_D1D2_OV0_RST (1 << 23) 879#define DISP_DVO_ENABLE_RST (1 << 24) 880#define TV_ENABLE_RST (1 << 25) 881#define AUTO_PWRUP_EN (1 << 26) 882 883#endif 884