intel_hdmi.c revision 261631
1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/9/sys/dev/drm2/i915/intel_hdmi.c 261631 2014-02-08 10:57:46Z dumbbell $"); 31 32#include <dev/drm2/drmP.h> 33#include <dev/drm2/drm.h> 34#include <dev/drm2/drm_crtc.h> 35#include <dev/drm2/drm_edid.h> 36#include <dev/drm2/i915/i915_drm.h> 37#include <dev/drm2/i915/i915_drv.h> 38#include <dev/drm2/i915/intel_drv.h> 39 40struct intel_hdmi { 41 struct intel_encoder base; 42 u32 sdvox_reg; 43 int ddc_bus; 44 uint32_t color_range; 45 bool has_hdmi_sink; 46 bool has_audio; 47 enum hdmi_force_audio force_audio; 48 void (*write_infoframe)(struct drm_encoder *encoder, 49 struct dip_infoframe *frame); 50}; 51 52static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 53{ 54 return container_of(encoder, struct intel_hdmi, base.base); 55} 56 57static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 58{ 59 return container_of(intel_attached_encoder(connector), 60 struct intel_hdmi, base); 61} 62 63void intel_dip_infoframe_csum(struct dip_infoframe *frame) 64{ 65 uint8_t *data = (uint8_t *)frame; 66 uint8_t sum = 0; 67 unsigned i; 68 69 frame->checksum = 0; 70 frame->ecc = 0; 71 72 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 73 sum += data[i]; 74 75 frame->checksum = 0x100 - sum; 76} 77 78static u32 intel_infoframe_index(struct dip_infoframe *frame) 79{ 80 u32 flags = 0; 81 82 switch (frame->type) { 83 case DIP_TYPE_AVI: 84 flags |= VIDEO_DIP_SELECT_AVI; 85 break; 86 case DIP_TYPE_SPD: 87 flags |= VIDEO_DIP_SELECT_SPD; 88 break; 89 default: 90 DRM_DEBUG("unknown info frame type %d\n", frame->type); 91 break; 92 } 93 94 return flags; 95} 96 97static u32 intel_infoframe_flags(struct dip_infoframe *frame) 98{ 99 u32 flags = 0; 100 101 switch (frame->type) { 102 case DIP_TYPE_AVI: 103 flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; 104 break; 105 case DIP_TYPE_SPD: 106 flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; 107 break; 108 default: 109 DRM_DEBUG("unknown info frame type %d\n", frame->type); 110 break; 111 } 112 113 return flags; 114} 115 116static void i9xx_write_infoframe(struct drm_encoder *encoder, 117 struct dip_infoframe *frame) 118{ 119 uint32_t *data = (uint32_t *)frame; 120 struct drm_device *dev = encoder->dev; 121 struct drm_i915_private *dev_priv = dev->dev_private; 122 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 123 u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); 124 unsigned i, len = DIP_HEADER_SIZE + frame->len; 125 126 127 /* XXX first guess at handling video port, is this corrent? */ 128 if (intel_hdmi->sdvox_reg == SDVOB) 129 port = VIDEO_DIP_PORT_B; 130 else if (intel_hdmi->sdvox_reg == SDVOC) 131 port = VIDEO_DIP_PORT_C; 132 else 133 return; 134 135 flags = intel_infoframe_index(frame); 136 137 val &= ~VIDEO_DIP_SELECT_MASK; 138 139 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 140 141 for (i = 0; i < len; i += 4) { 142 I915_WRITE(VIDEO_DIP_DATA, *data); 143 data++; 144 } 145 146 flags |= intel_infoframe_flags(frame); 147 148 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 149} 150 151static void ironlake_write_infoframe(struct drm_encoder *encoder, 152 struct dip_infoframe *frame) 153{ 154 uint32_t *data = (uint32_t *)frame; 155 struct drm_device *dev = encoder->dev; 156 struct drm_i915_private *dev_priv = dev->dev_private; 157 struct drm_crtc *crtc = encoder->crtc; 158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 159 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 160 unsigned i, len = DIP_HEADER_SIZE + frame->len; 161 u32 flags, val = I915_READ(reg); 162 163 intel_wait_for_vblank(dev, intel_crtc->pipe); 164 165 flags = intel_infoframe_index(frame); 166 167 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 168 169 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 170 171 for (i = 0; i < len; i += 4) { 172 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 173 data++; 174 } 175 176 flags |= intel_infoframe_flags(frame); 177 178 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 179} 180 181static void intel_set_infoframe(struct drm_encoder *encoder, 182 struct dip_infoframe *frame) 183{ 184 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 185 186 if (!intel_hdmi->has_hdmi_sink) 187 return; 188 189 intel_dip_infoframe_csum(frame); 190 intel_hdmi->write_infoframe(encoder, frame); 191} 192 193static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 194{ 195 struct dip_infoframe avi_if = { 196 .type = DIP_TYPE_AVI, 197 .ver = DIP_VERSION_AVI, 198 .len = DIP_LEN_AVI, 199 }; 200 201 intel_set_infoframe(encoder, &avi_if); 202} 203 204static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 205{ 206 struct dip_infoframe spd_if; 207 208 memset(&spd_if, 0, sizeof(spd_if)); 209 spd_if.type = DIP_TYPE_SPD; 210 spd_if.ver = DIP_VERSION_SPD; 211 spd_if.len = DIP_LEN_SPD; 212 strcpy(spd_if.body.spd.vn, "Intel"); 213 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 214 spd_if.body.spd.sdi = DIP_SPD_PC; 215 216 intel_set_infoframe(encoder, &spd_if); 217} 218 219static void intel_hdmi_mode_set(struct drm_encoder *encoder, 220 struct drm_display_mode *mode, 221 struct drm_display_mode *adjusted_mode) 222{ 223 struct drm_device *dev = encoder->dev; 224 struct drm_i915_private *dev_priv = dev->dev_private; 225 struct drm_crtc *crtc = encoder->crtc; 226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 227 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 228 u32 sdvox; 229 230 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; 231 if (!HAS_PCH_SPLIT(dev)) 232 sdvox |= intel_hdmi->color_range; 233 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 234 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 235 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 236 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 237 238 if (intel_crtc->bpp > 24) 239 sdvox |= COLOR_FORMAT_12bpc; 240 else 241 sdvox |= COLOR_FORMAT_8bpc; 242 243 /* Required on CPT */ 244 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 245 sdvox |= HDMI_MODE_SELECT; 246 247 if (intel_hdmi->has_audio) { 248 DRM_DEBUG_KMS("Enabling HDMI audio on pipe %c\n", 249 pipe_name(intel_crtc->pipe)); 250 sdvox |= SDVO_AUDIO_ENABLE; 251 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; 252 intel_write_eld(encoder, adjusted_mode); 253 } 254 255 if (HAS_PCH_CPT(dev)) 256 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 257 else if (intel_crtc->pipe == 1) 258 sdvox |= SDVO_PIPE_B_SELECT; 259 260 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 261 POSTING_READ(intel_hdmi->sdvox_reg); 262 263 intel_hdmi_set_avi_infoframe(encoder); 264 intel_hdmi_set_spd_infoframe(encoder); 265} 266 267static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 268{ 269 struct drm_device *dev = encoder->dev; 270 struct drm_i915_private *dev_priv = dev->dev_private; 271 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 272 u32 temp; 273 u32 enable_bits = SDVO_ENABLE; 274 275 if (intel_hdmi->has_audio) 276 enable_bits |= SDVO_AUDIO_ENABLE; 277 278 temp = I915_READ(intel_hdmi->sdvox_reg); 279 280 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 281 * we do this anyway which shows more stable in testing. 282 */ 283 if (HAS_PCH_SPLIT(dev)) { 284 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 285 POSTING_READ(intel_hdmi->sdvox_reg); 286 } 287 288 if (mode != DRM_MODE_DPMS_ON) { 289 temp &= ~enable_bits; 290 } else { 291 temp |= enable_bits; 292 } 293 294 I915_WRITE(intel_hdmi->sdvox_reg, temp); 295 POSTING_READ(intel_hdmi->sdvox_reg); 296 297 /* HW workaround, need to write this twice for issue that may result 298 * in first write getting masked. 299 */ 300 if (HAS_PCH_SPLIT(dev)) { 301 I915_WRITE(intel_hdmi->sdvox_reg, temp); 302 POSTING_READ(intel_hdmi->sdvox_reg); 303 } 304} 305 306static int intel_hdmi_mode_valid(struct drm_connector *connector, 307 struct drm_display_mode *mode) 308{ 309 if (mode->clock > 165000) 310 return MODE_CLOCK_HIGH; 311 if (mode->clock < 20000) 312 return MODE_CLOCK_LOW; 313 314 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 315 return MODE_NO_DBLESCAN; 316 317 return MODE_OK; 318} 319 320static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 321 const struct drm_display_mode *mode, 322 struct drm_display_mode *adjusted_mode) 323{ 324 return true; 325} 326 327static enum drm_connector_status 328intel_hdmi_detect(struct drm_connector *connector, bool force) 329{ 330 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 331 struct drm_i915_private *dev_priv = connector->dev->dev_private; 332 struct edid *edid; 333 enum drm_connector_status status = connector_status_disconnected; 334 335 intel_hdmi->has_hdmi_sink = false; 336 intel_hdmi->has_audio = false; 337 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 338 339 if (edid) { 340 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 341 status = connector_status_connected; 342 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 343 intel_hdmi->has_hdmi_sink = 344 drm_detect_hdmi_monitor(edid); 345 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 346 } 347 connector->display_info.raw_edid = NULL; 348 free(edid, DRM_MEM_KMS); 349 } else { 350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] got no edid, ddc port %d\n", 351 connector->base.id, drm_get_connector_name(connector), 352 intel_hdmi->ddc_bus); 353 } 354 355 if (status == connector_status_connected) { 356 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 357 intel_hdmi->has_audio = 358 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 359 } 360 361 return status; 362} 363 364static int intel_hdmi_get_modes(struct drm_connector *connector) 365{ 366 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 367 struct drm_i915_private *dev_priv = connector->dev->dev_private; 368 369 /* We should parse the EDID data and find out if it's an HDMI sink so 370 * we can send audio to it. 371 */ 372 373 return intel_ddc_get_modes(connector, 374 dev_priv->gmbus[intel_hdmi->ddc_bus]); 375} 376 377static bool 378intel_hdmi_detect_audio(struct drm_connector *connector) 379{ 380 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 381 struct drm_i915_private *dev_priv = connector->dev->dev_private; 382 struct edid *edid; 383 bool has_audio = false; 384 385 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 386 if (edid) { 387 if (edid->input & DRM_EDID_INPUT_DIGITAL) 388 has_audio = drm_detect_monitor_audio(edid); 389 390 connector->display_info.raw_edid = NULL; 391 free(edid, DRM_MEM_KMS); 392 } 393 394 return has_audio; 395} 396 397static int 398intel_hdmi_set_property(struct drm_connector *connector, 399 struct drm_property *property, 400 uint64_t val) 401{ 402 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 403 struct drm_i915_private *dev_priv = connector->dev->dev_private; 404 int ret; 405 406 ret = drm_connector_property_set_value(connector, property, val); 407 if (ret) 408 return ret; 409 410 if (property == dev_priv->force_audio_property) { 411 enum hdmi_force_audio i = val; 412 bool has_audio; 413 414 if (i == intel_hdmi->force_audio) 415 return 0; 416 417 intel_hdmi->force_audio = i; 418 419 if (i == HDMI_AUDIO_AUTO) 420 has_audio = intel_hdmi_detect_audio(connector); 421 else 422 has_audio = (i == HDMI_AUDIO_ON); 423 424 if (i == HDMI_AUDIO_OFF_DVI) 425 intel_hdmi->has_hdmi_sink = 0; 426 427 intel_hdmi->has_audio = has_audio; 428 goto done; 429 } 430 431 if (property == dev_priv->broadcast_rgb_property) { 432 if (val == !!intel_hdmi->color_range) 433 return 0; 434 435 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 436 goto done; 437 } 438 439 return -EINVAL; 440 441done: 442 if (intel_hdmi->base.base.crtc) { 443 struct drm_crtc *crtc = intel_hdmi->base.base.crtc; 444 drm_crtc_helper_set_mode(crtc, &crtc->mode, 445 crtc->x, crtc->y, 446 crtc->fb); 447 } 448 449 return 0; 450} 451 452static void intel_hdmi_destroy(struct drm_connector *connector) 453{ 454#if 0 455 drm_sysfs_connector_remove(connector); 456#endif 457 drm_connector_cleanup(connector); 458 free(connector, DRM_MEM_KMS); 459} 460 461static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 462 .dpms = intel_hdmi_dpms, 463 .mode_fixup = intel_hdmi_mode_fixup, 464 .prepare = intel_encoder_prepare, 465 .mode_set = intel_hdmi_mode_set, 466 .commit = intel_encoder_commit, 467}; 468 469static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 470 .dpms = drm_helper_connector_dpms, 471 .detect = intel_hdmi_detect, 472 .fill_modes = drm_helper_probe_single_connector_modes, 473 .set_property = intel_hdmi_set_property, 474 .destroy = intel_hdmi_destroy, 475}; 476 477static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 478 .get_modes = intel_hdmi_get_modes, 479 .mode_valid = intel_hdmi_mode_valid, 480 .best_encoder = intel_best_encoder, 481}; 482 483static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 484 .destroy = intel_encoder_destroy, 485}; 486 487static void 488intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 489{ 490 intel_attach_force_audio_property(connector); 491 intel_attach_broadcast_rgb_property(connector); 492} 493 494void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 495{ 496 struct drm_i915_private *dev_priv = dev->dev_private; 497 struct drm_connector *connector; 498 struct intel_encoder *intel_encoder; 499 struct intel_connector *intel_connector; 500 struct intel_hdmi *intel_hdmi; 501 int i; 502 503 intel_hdmi = malloc(sizeof(struct intel_hdmi), DRM_MEM_KMS, 504 M_WAITOK | M_ZERO); 505 intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, 506 M_WAITOK | M_ZERO); 507 508 intel_encoder = &intel_hdmi->base; 509 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 510 DRM_MODE_ENCODER_TMDS); 511 512 connector = &intel_connector->base; 513 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 514 DRM_MODE_CONNECTOR_HDMIA); 515 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 516 517 intel_encoder->type = INTEL_OUTPUT_HDMI; 518 519 connector->polled = DRM_CONNECTOR_POLL_HPD; 520 connector->interlace_allowed = 1; 521 connector->doublescan_allowed = 0; 522 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 523 524 /* Set up the DDC bus. */ 525 if (sdvox_reg == SDVOB) { 526 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); 527 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 528 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 529 } else if (sdvox_reg == SDVOC) { 530 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); 531 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 532 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 533 } else if (sdvox_reg == HDMIB) { 534 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); 535 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 536 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 537 } else if (sdvox_reg == HDMIC) { 538 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); 539 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 540 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 541 } else if (sdvox_reg == HDMID) { 542 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); 543 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 544 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; 545 } 546 547 548 intel_hdmi->sdvox_reg = sdvox_reg; 549 550 if (!HAS_PCH_SPLIT(dev)) { 551 intel_hdmi->write_infoframe = i9xx_write_infoframe; 552 I915_WRITE(VIDEO_DIP_CTL, 0); 553 } else { 554 intel_hdmi->write_infoframe = ironlake_write_infoframe; 555 for_each_pipe(i) 556 I915_WRITE(TVIDEO_DIP_CTL(i), 0); 557 } 558 559 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 560 561 intel_hdmi_add_properties(intel_hdmi, connector); 562 563 intel_connector_attach_encoder(intel_connector, intel_encoder); 564#if 0 565 drm_sysfs_connector_add(connector); 566#endif 567 568 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 569 * 0xd. Failure to do so will result in spurious interrupts being 570 * generated on the port when a cable is not attached. 571 */ 572 if (IS_G4X(dev) && !IS_GM45(dev)) { 573 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 574 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 575 } 576} 577