1235783Skib/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2235783Skib */ 3235783Skib/* 4235783Skib * 5235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6235783Skib * All Rights Reserved. 7235783Skib * 8235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 9235783Skib * copy of this software and associated documentation files (the 10235783Skib * "Software"), to deal in the Software without restriction, including 11235783Skib * without limitation the rights to use, copy, modify, merge, publish, 12235783Skib * distribute, sub license, and/or sell copies of the Software, and to 13235783Skib * permit persons to whom the Software is furnished to do so, subject to 14235783Skib * the following conditions: 15235783Skib * 16235783Skib * The above copyright notice and this permission notice (including the 17235783Skib * next paragraph) shall be included in all copies or substantial portions 18235783Skib * of the Software. 19235783Skib * 20235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27235783Skib * 28235783Skib */ 29235783Skib 30235783Skib#include <sys/cdefs.h> 31235783Skib__FBSDID("$FreeBSD$"); 32235783Skib 33235783Skib#ifndef _I915_DRV_H_ 34235783Skib#define _I915_DRV_H_ 35235783Skib 36235783Skib#include <dev/agp/agp_i810.h> 37235783Skib#include <dev/drm2/drm_mm.h> 38235783Skib#include <dev/drm2/i915/i915_reg.h> 39235783Skib#include <dev/drm2/i915/intel_ringbuffer.h> 40235783Skib#include <dev/drm2/i915/intel_bios.h> 41235783Skib 42235783Skib/* General customization: 43235783Skib */ 44235783Skib 45235783Skib#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46235783Skib 47235783Skib#define DRIVER_NAME "i915" 48235783Skib#define DRIVER_DESC "Intel Graphics" 49235783Skib#define DRIVER_DATE "20080730" 50235783Skib 51235783SkibMALLOC_DECLARE(DRM_I915_GEM); 52235783Skib 53235783Skibenum pipe { 54235783Skib PIPE_A = 0, 55235783Skib PIPE_B, 56235783Skib PIPE_C, 57235783Skib I915_MAX_PIPES 58235783Skib}; 59235783Skib#define pipe_name(p) ((p) + 'A') 60235783Skib#define I915_NUM_PIPE 2 61235783Skib 62235783Skibenum plane { 63235783Skib PLANE_A = 0, 64235783Skib PLANE_B, 65235783Skib PLANE_C, 66235783Skib}; 67235783Skib#define plane_name(p) ((p) + 'A') 68235783Skib 69235783Skib#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 70235783Skib 71235783Skib#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 72235783Skib 73235783Skib/* Interface history: 74235783Skib * 75235783Skib * 1.1: Original. 76235783Skib * 1.2: Add Power Management 77235783Skib * 1.3: Add vblank support 78235783Skib * 1.4: Fix cmdbuffer path, add heap destroy 79235783Skib * 1.5: Add vblank pipe configuration 80235783Skib * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 81235783Skib * - Support vertical blank on secondary display pipe 82235783Skib */ 83235783Skib#define DRIVER_MAJOR 1 84235783Skib#define DRIVER_MINOR 6 85235783Skib#define DRIVER_PATCHLEVEL 0 86235783Skib 87235783Skib#define WATCH_COHERENCY 0 88235783Skib#define WATCH_BUF 0 89235783Skib#define WATCH_EXEC 0 90235783Skib#define WATCH_LRU 0 91235783Skib#define WATCH_RELOC 0 92235783Skib#define WATCH_INACTIVE 0 93235783Skib#define WATCH_PWRITE 0 94235783Skib 95235783Skib#define I915_GEM_PHYS_CURSOR_0 1 96235783Skib#define I915_GEM_PHYS_CURSOR_1 2 97235783Skib#define I915_GEM_PHYS_OVERLAY_REGS 3 98235783Skib#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 99235783Skib 100235783Skibstruct drm_i915_gem_phys_object { 101235783Skib int id; 102235783Skib drm_dma_handle_t *handle; 103235783Skib struct drm_i915_gem_object *cur_obj; 104235783Skib}; 105235783Skib 106235783Skibstruct drm_i915_private; 107235783Skib 108235783Skibstruct drm_i915_display_funcs { 109235783Skib void (*dpms)(struct drm_crtc *crtc, int mode); 110235783Skib bool (*fbc_enabled)(struct drm_device *dev); 111235783Skib void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 112235783Skib void (*disable_fbc)(struct drm_device *dev); 113235783Skib int (*get_display_clock_speed)(struct drm_device *dev); 114235783Skib int (*get_fifo_size)(struct drm_device *dev, int plane); 115235783Skib void (*update_wm)(struct drm_device *dev); 116235783Skib void (*update_sprite_wm)(struct drm_device *dev, int pipe, 117235783Skib uint32_t sprite_width, int pixel_size); 118235783Skib int (*crtc_mode_set)(struct drm_crtc *crtc, 119235783Skib struct drm_display_mode *mode, 120235783Skib struct drm_display_mode *adjusted_mode, 121235783Skib int x, int y, 122235783Skib struct drm_framebuffer *old_fb); 123235783Skib void (*write_eld)(struct drm_connector *connector, 124235783Skib struct drm_crtc *crtc); 125235783Skib void (*fdi_link_train)(struct drm_crtc *crtc); 126235783Skib void (*init_clock_gating)(struct drm_device *dev); 127235783Skib void (*init_pch_clock_gating)(struct drm_device *dev); 128235783Skib int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 129235783Skib struct drm_framebuffer *fb, 130235783Skib struct drm_i915_gem_object *obj); 131235783Skib void (*force_wake_get)(struct drm_i915_private *dev_priv); 132235783Skib void (*force_wake_put)(struct drm_i915_private *dev_priv); 133235783Skib int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 134235783Skib int x, int y); 135235783Skib /* clock updates for mode set */ 136235783Skib /* cursor updates */ 137235783Skib /* render clock increase/decrease */ 138235783Skib /* display clock increase/decrease */ 139235783Skib /* pll clock increase/decrease */ 140235783Skib}; 141235783Skib 142235783Skibstruct intel_device_info { 143235783Skib u8 gen; 144235783Skib u8 is_mobile:1; 145235783Skib u8 is_i85x:1; 146235783Skib u8 is_i915g:1; 147235783Skib u8 is_i945gm:1; 148235783Skib u8 is_g33:1; 149235783Skib u8 need_gfx_hws:1; 150235783Skib u8 is_g4x:1; 151235783Skib u8 is_pineview:1; 152235783Skib u8 is_broadwater:1; 153235783Skib u8 is_crestline:1; 154235783Skib u8 is_ivybridge:1; 155235783Skib u8 has_fbc:1; 156235783Skib u8 has_pipe_cxsr:1; 157235783Skib u8 has_hotplug:1; 158235783Skib u8 cursor_needs_physical:1; 159235783Skib u8 has_overlay:1; 160235783Skib u8 overlay_needs_physical:1; 161235783Skib u8 supports_tv:1; 162235783Skib u8 has_bsd_ring:1; 163235783Skib u8 has_blt_ring:1; 164235783Skib u8 has_llc:1; 165235783Skib}; 166235783Skib 167235783Skib#define I915_PPGTT_PD_ENTRIES 512 168235783Skib#define I915_PPGTT_PT_ENTRIES 1024 169235783Skibstruct i915_hw_ppgtt { 170235783Skib unsigned num_pd_entries; 171235783Skib vm_page_t *pt_pages; 172235783Skib uint32_t pd_offset; 173235783Skib vm_paddr_t *pt_dma_addr; 174235783Skib vm_paddr_t scratch_page_dma_addr; 175235783Skib}; 176235783Skib 177235783Skibenum no_fbc_reason { 178235783Skib FBC_NO_OUTPUT, /* no outputs enabled to compress */ 179235783Skib FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 180235783Skib FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 181235783Skib FBC_MODE_TOO_LARGE, /* mode too large for compression */ 182235783Skib FBC_BAD_PLANE, /* fbc not supported on plane */ 183235783Skib FBC_NOT_TILED, /* buffer not tiled */ 184235783Skib FBC_MULTIPLE_PIPES, /* more than one pipe active */ 185235783Skib FBC_MODULE_PARAM, 186235783Skib}; 187235783Skib 188235783Skibstruct mem_block { 189235783Skib struct mem_block *next; 190235783Skib struct mem_block *prev; 191235783Skib int start; 192235783Skib int size; 193235783Skib struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 194235783Skib}; 195235783Skib 196235783Skibstruct opregion_header; 197235783Skibstruct opregion_acpi; 198235783Skibstruct opregion_swsci; 199235783Skibstruct opregion_asle; 200235783Skib 201235783Skibstruct intel_opregion { 202235783Skib struct opregion_header *header; 203235783Skib struct opregion_acpi *acpi; 204235783Skib struct opregion_swsci *swsci; 205235783Skib struct opregion_asle *asle; 206235783Skib void *vbt; 207235783Skib u32 *lid_state; 208235783Skib}; 209235783Skib#define OPREGION_SIZE (8*1024) 210235783Skib 211235783Skib#define I915_FENCE_REG_NONE -1 212235783Skib#define I915_MAX_NUM_FENCES 16 213235783Skib/* 16 fences + sign bit for FENCE_REG_NONE */ 214235783Skib#define I915_MAX_NUM_FENCE_BITS 5 215235783Skib 216235783Skibstruct drm_i915_fence_reg { 217235783Skib struct list_head lru_list; 218235783Skib struct drm_i915_gem_object *obj; 219235783Skib uint32_t setup_seqno; 220235783Skib int pin_count; 221235783Skib}; 222235783Skib 223235783Skibstruct sdvo_device_mapping { 224235783Skib u8 initialized; 225235783Skib u8 dvo_port; 226235783Skib u8 slave_addr; 227235783Skib u8 dvo_wiring; 228235783Skib u8 i2c_pin; 229235783Skib u8 ddc_pin; 230235783Skib}; 231235783Skib 232235783Skibenum intel_pch { 233235783Skib PCH_IBX, /* Ibexpeak PCH */ 234235783Skib PCH_CPT, /* Cougarpoint PCH */ 235235783Skib}; 236235783Skib 237235783Skib#define QUIRK_PIPEA_FORCE (1<<0) 238235783Skib#define QUIRK_LVDS_SSC_DISABLE (1<<1) 239235783Skib 240235783Skibstruct intel_fbdev; 241235783Skibstruct intel_fbc_work; 242235783Skib 243235783Skibtypedef struct drm_i915_private { 244235783Skib struct drm_device *dev; 245235783Skib 246235783Skib device_t *gmbus_bridge; 247235783Skib device_t *bbbus_bridge; 248235783Skib device_t *gmbus; 249235783Skib device_t *bbbus; 250235783Skib /** gmbus_sx protects against concurrent usage of the single hw gmbus 251235783Skib * controller on different i2c buses. */ 252235783Skib struct sx gmbus_sx; 253235783Skib 254235783Skib int has_gem; 255235783Skib int relative_constants_mode; 256235783Skib 257235783Skib drm_local_map_t *sarea; 258235783Skib drm_local_map_t *mmio_map; 259235783Skib 260235783Skib /** gt_fifo_count and the subsequent register write are synchronized 261235783Skib * with dev->struct_mutex. */ 262235783Skib unsigned gt_fifo_count; 263235783Skib /** forcewake_count is protected by gt_lock */ 264235783Skib unsigned forcewake_count; 265235783Skib /** gt_lock is also taken in irq contexts. */ 266235783Skib struct mtx gt_lock; 267235783Skib 268235783Skib drm_i915_sarea_t *sarea_priv; 269235783Skib /* drm_i915_ring_buffer_t ring; */ 270235783Skib struct intel_ring_buffer rings[I915_NUM_RINGS]; 271235783Skib uint32_t next_seqno; 272235783Skib 273235783Skib drm_dma_handle_t *status_page_dmah; 274235783Skib void *hw_status_page; 275235783Skib dma_addr_t dma_status_page; 276235783Skib uint32_t counter; 277235783Skib unsigned int status_gfx_addr; 278235783Skib drm_local_map_t hws_map; 279235783Skib struct drm_gem_object *hws_obj; 280235783Skib 281235783Skib struct drm_i915_gem_object *pwrctx; 282235783Skib struct drm_i915_gem_object *renderctx; 283235783Skib 284235783Skib unsigned int cpp; 285235783Skib int back_offset; 286235783Skib int front_offset; 287235783Skib int current_page; 288235783Skib int page_flipping; 289235783Skib 290235783Skib atomic_t irq_received; 291235783Skib u32 trace_irq_seqno; 292235783Skib 293235783Skib /** Cached value of IER to avoid reads in updating the bitfield */ 294235783Skib u32 pipestat[2]; 295235783Skib u32 irq_mask; 296235783Skib u32 gt_irq_mask; 297235783Skib u32 pch_irq_mask; 298235783Skib struct mtx irq_lock; 299235783Skib 300235783Skib u32 hotplug_supported_mask; 301235783Skib 302235783Skib int tex_lru_log_granularity; 303235783Skib int allow_batchbuffer; 304235783Skib unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 305235783Skib int vblank_pipe; 306235783Skib int num_pipe; 307235783Skib 308235783Skib /* For hangcheck timer */ 309235783Skib#define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 310235783Skib int hangcheck_count; 311235783Skib uint32_t last_acthd; 312235783Skib uint32_t last_acthd_bsd; 313235783Skib uint32_t last_acthd_blt; 314235783Skib uint32_t last_instdone; 315235783Skib uint32_t last_instdone1; 316235783Skib 317235783Skib struct intel_opregion opregion; 318235783Skib 319235783Skib 320235783Skib /* overlay */ 321235783Skib struct intel_overlay *overlay; 322235783Skib bool sprite_scaling_enabled; 323235783Skib 324235783Skib /* LVDS info */ 325235783Skib int backlight_level; /* restore backlight to this value */ 326235783Skib bool backlight_enabled; 327235783Skib struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 328235783Skib struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 329235783Skib 330235783Skib /* Feature bits from the VBIOS */ 331235783Skib unsigned int int_tv_support:1; 332235783Skib unsigned int lvds_dither:1; 333235783Skib unsigned int lvds_vbt:1; 334235783Skib unsigned int int_crt_support:1; 335235783Skib unsigned int lvds_use_ssc:1; 336235783Skib unsigned int display_clock_mode:1; 337235783Skib int lvds_ssc_freq; 338235783Skib struct { 339235783Skib int rate; 340235783Skib int lanes; 341235783Skib int preemphasis; 342235783Skib int vswing; 343235783Skib 344235783Skib bool initialized; 345235783Skib bool support; 346235783Skib int bpp; 347235783Skib struct edp_power_seq pps; 348235783Skib } edp; 349235783Skib bool no_aux_handshake; 350235783Skib 351235783Skib int crt_ddc_pin; 352235783Skib struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 353235783Skib int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 354235783Skib int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 355235783Skib 356235783Skib /* PCH chipset type */ 357235783Skib enum intel_pch pch_type; 358235783Skib 359235783Skib /* Display functions */ 360235783Skib struct drm_i915_display_funcs display; 361235783Skib 362235783Skib unsigned long quirks; 363235783Skib 364235783Skib /* Register state */ 365235783Skib bool modeset_on_lid; 366235783Skib u8 saveLBB; 367235783Skib u32 saveDSPACNTR; 368235783Skib u32 saveDSPBCNTR; 369235783Skib u32 saveDSPARB; 370235783Skib u32 saveHWS; 371235783Skib u32 savePIPEACONF; 372235783Skib u32 savePIPEBCONF; 373235783Skib u32 savePIPEASRC; 374235783Skib u32 savePIPEBSRC; 375235783Skib u32 saveFPA0; 376235783Skib u32 saveFPA1; 377235783Skib u32 saveDPLL_A; 378235783Skib u32 saveDPLL_A_MD; 379235783Skib u32 saveHTOTAL_A; 380235783Skib u32 saveHBLANK_A; 381235783Skib u32 saveHSYNC_A; 382235783Skib u32 saveVTOTAL_A; 383235783Skib u32 saveVBLANK_A; 384235783Skib u32 saveVSYNC_A; 385235783Skib u32 saveBCLRPAT_A; 386235783Skib u32 saveTRANSACONF; 387235783Skib u32 saveTRANS_HTOTAL_A; 388235783Skib u32 saveTRANS_HBLANK_A; 389235783Skib u32 saveTRANS_HSYNC_A; 390235783Skib u32 saveTRANS_VTOTAL_A; 391235783Skib u32 saveTRANS_VBLANK_A; 392235783Skib u32 saveTRANS_VSYNC_A; 393235783Skib u32 savePIPEASTAT; 394235783Skib u32 saveDSPASTRIDE; 395235783Skib u32 saveDSPASIZE; 396235783Skib u32 saveDSPAPOS; 397235783Skib u32 saveDSPAADDR; 398235783Skib u32 saveDSPASURF; 399235783Skib u32 saveDSPATILEOFF; 400235783Skib u32 savePFIT_PGM_RATIOS; 401235783Skib u32 saveBLC_HIST_CTL; 402235783Skib u32 saveBLC_PWM_CTL; 403235783Skib u32 saveBLC_PWM_CTL2; 404235783Skib u32 saveBLC_CPU_PWM_CTL; 405235783Skib u32 saveBLC_CPU_PWM_CTL2; 406235783Skib u32 saveFPB0; 407235783Skib u32 saveFPB1; 408235783Skib u32 saveDPLL_B; 409235783Skib u32 saveDPLL_B_MD; 410235783Skib u32 saveHTOTAL_B; 411235783Skib u32 saveHBLANK_B; 412235783Skib u32 saveHSYNC_B; 413235783Skib u32 saveVTOTAL_B; 414235783Skib u32 saveVBLANK_B; 415235783Skib u32 saveVSYNC_B; 416235783Skib u32 saveBCLRPAT_B; 417235783Skib u32 saveTRANSBCONF; 418235783Skib u32 saveTRANS_HTOTAL_B; 419235783Skib u32 saveTRANS_HBLANK_B; 420235783Skib u32 saveTRANS_HSYNC_B; 421235783Skib u32 saveTRANS_VTOTAL_B; 422235783Skib u32 saveTRANS_VBLANK_B; 423235783Skib u32 saveTRANS_VSYNC_B; 424235783Skib u32 savePIPEBSTAT; 425235783Skib u32 saveDSPBSTRIDE; 426235783Skib u32 saveDSPBSIZE; 427235783Skib u32 saveDSPBPOS; 428235783Skib u32 saveDSPBADDR; 429235783Skib u32 saveDSPBSURF; 430235783Skib u32 saveDSPBTILEOFF; 431235783Skib u32 saveVGA0; 432235783Skib u32 saveVGA1; 433235783Skib u32 saveVGA_PD; 434235783Skib u32 saveVGACNTRL; 435235783Skib u32 saveADPA; 436235783Skib u32 saveLVDS; 437235783Skib u32 savePP_ON_DELAYS; 438235783Skib u32 savePP_OFF_DELAYS; 439235783Skib u32 saveDVOA; 440235783Skib u32 saveDVOB; 441235783Skib u32 saveDVOC; 442235783Skib u32 savePP_ON; 443235783Skib u32 savePP_OFF; 444235783Skib u32 savePP_CONTROL; 445235783Skib u32 savePP_DIVISOR; 446235783Skib u32 savePFIT_CONTROL; 447235783Skib u32 save_palette_a[256]; 448235783Skib u32 save_palette_b[256]; 449235783Skib u32 saveDPFC_CB_BASE; 450235783Skib u32 saveFBC_CFB_BASE; 451235783Skib u32 saveFBC_LL_BASE; 452235783Skib u32 saveFBC_CONTROL; 453235783Skib u32 saveFBC_CONTROL2; 454235783Skib u32 saveIER; 455235783Skib u32 saveIIR; 456235783Skib u32 saveIMR; 457235783Skib u32 saveDEIER; 458235783Skib u32 saveDEIMR; 459235783Skib u32 saveGTIER; 460235783Skib u32 saveGTIMR; 461235783Skib u32 saveFDI_RXA_IMR; 462235783Skib u32 saveFDI_RXB_IMR; 463235783Skib u32 saveCACHE_MODE_0; 464235783Skib u32 saveMI_ARB_STATE; 465235783Skib u32 saveSWF0[16]; 466235783Skib u32 saveSWF1[16]; 467235783Skib u32 saveSWF2[3]; 468235783Skib u8 saveMSR; 469235783Skib u8 saveSR[8]; 470235783Skib u8 saveGR[25]; 471235783Skib u8 saveAR_INDEX; 472235783Skib u8 saveAR[21]; 473235783Skib u8 saveDACMASK; 474235783Skib u8 saveCR[37]; 475235783Skib uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 476235783Skib u32 saveCURACNTR; 477235783Skib u32 saveCURAPOS; 478235783Skib u32 saveCURABASE; 479235783Skib u32 saveCURBCNTR; 480235783Skib u32 saveCURBPOS; 481235783Skib u32 saveCURBBASE; 482235783Skib u32 saveCURSIZE; 483235783Skib u32 saveDP_B; 484235783Skib u32 saveDP_C; 485235783Skib u32 saveDP_D; 486235783Skib u32 savePIPEA_GMCH_DATA_M; 487235783Skib u32 savePIPEB_GMCH_DATA_M; 488235783Skib u32 savePIPEA_GMCH_DATA_N; 489235783Skib u32 savePIPEB_GMCH_DATA_N; 490235783Skib u32 savePIPEA_DP_LINK_M; 491235783Skib u32 savePIPEB_DP_LINK_M; 492235783Skib u32 savePIPEA_DP_LINK_N; 493235783Skib u32 savePIPEB_DP_LINK_N; 494235783Skib u32 saveFDI_RXA_CTL; 495235783Skib u32 saveFDI_TXA_CTL; 496235783Skib u32 saveFDI_RXB_CTL; 497235783Skib u32 saveFDI_TXB_CTL; 498235783Skib u32 savePFA_CTL_1; 499235783Skib u32 savePFB_CTL_1; 500235783Skib u32 savePFA_WIN_SZ; 501235783Skib u32 savePFB_WIN_SZ; 502235783Skib u32 savePFA_WIN_POS; 503235783Skib u32 savePFB_WIN_POS; 504235783Skib u32 savePCH_DREF_CONTROL; 505235783Skib u32 saveDISP_ARB_CTL; 506235783Skib u32 savePIPEA_DATA_M1; 507235783Skib u32 savePIPEA_DATA_N1; 508235783Skib u32 savePIPEA_LINK_M1; 509235783Skib u32 savePIPEA_LINK_N1; 510235783Skib u32 savePIPEB_DATA_M1; 511235783Skib u32 savePIPEB_DATA_N1; 512235783Skib u32 savePIPEB_LINK_M1; 513235783Skib u32 savePIPEB_LINK_N1; 514235783Skib u32 saveMCHBAR_RENDER_STANDBY; 515235783Skib u32 savePCH_PORT_HOTPLUG; 516235783Skib 517235783Skib struct { 518235783Skib /** Memory allocator for GTT stolen memory */ 519235783Skib struct drm_mm stolen; 520235783Skib /** Memory allocator for GTT */ 521235783Skib struct drm_mm gtt_space; 522235783Skib /** List of all objects in gtt_space. Used to restore gtt 523235783Skib * mappings on resume */ 524235783Skib struct list_head gtt_list; 525235783Skib 526235783Skib /** Usable portion of the GTT for GEM */ 527235783Skib unsigned long gtt_start; 528235783Skib unsigned long gtt_mappable_end; 529235783Skib unsigned long gtt_end; 530235783Skib 531235783Skib /** PPGTT used for aliasing the PPGTT with the GTT */ 532235783Skib struct i915_hw_ppgtt *aliasing_ppgtt; 533235783Skib 534235783Skib /** 535235783Skib * List of objects currently involved in rendering from the 536235783Skib * ringbuffer. 537235783Skib * 538235783Skib * Includes buffers having the contents of their GPU caches 539235783Skib * flushed, not necessarily primitives. last_rendering_seqno 540235783Skib * represents when the rendering involved will be completed. 541235783Skib * 542235783Skib * A reference is held on the buffer while on this list. 543235783Skib */ 544235783Skib struct list_head active_list; 545235783Skib 546235783Skib /** 547235783Skib * List of objects which are not in the ringbuffer but which 548235783Skib * still have a write_domain which needs to be flushed before 549235783Skib * unbinding. 550235783Skib * 551235783Skib * A reference is held on the buffer while on this list. 552235783Skib */ 553235783Skib struct list_head flushing_list; 554235783Skib 555235783Skib /** 556235783Skib * LRU list of objects which are not in the ringbuffer and 557235783Skib * are ready to unbind, but are still in the GTT. 558235783Skib * 559235783Skib * last_rendering_seqno is 0 while an object is in this list. 560235783Skib * 561235783Skib * A reference is not held on the buffer while on this list, 562235783Skib * as merely being GTT-bound shouldn't prevent its being 563235783Skib * freed, and we'll pull it off the list in the free path. 564235783Skib */ 565235783Skib struct list_head inactive_list; 566235783Skib 567235783Skib /** 568235783Skib * LRU list of objects which are not in the ringbuffer but 569235783Skib * are still pinned in the GTT. 570235783Skib */ 571235783Skib struct list_head pinned_list; 572235783Skib 573235783Skib /** LRU list of objects with fence regs on them. */ 574235783Skib struct list_head fence_list; 575235783Skib 576235783Skib /** 577235783Skib * List of objects currently pending being freed. 578235783Skib * 579235783Skib * These objects are no longer in use, but due to a signal 580235783Skib * we were prevented from freeing them at the appointed time. 581235783Skib */ 582235783Skib struct list_head deferred_free_list; 583235783Skib 584235783Skib /** 585235783Skib * We leave the user IRQ off as much as possible, 586235783Skib * but this means that requests will finish and never 587235783Skib * be retired once the system goes idle. Set a timer to 588235783Skib * fire periodically while the ring is running. When it 589235783Skib * fires, go retire requests. 590235783Skib */ 591235783Skib struct timeout_task retire_task; 592235783Skib 593235783Skib /** 594235783Skib * Are we in a non-interruptible section of code like 595235783Skib * modesetting? 596235783Skib */ 597235783Skib bool interruptible; 598235783Skib 599235783Skib uint32_t next_gem_seqno; 600235783Skib 601235783Skib /** 602235783Skib * Waiting sequence number, if any 603235783Skib */ 604235783Skib uint32_t waiting_gem_seqno; 605235783Skib 606235783Skib /** 607235783Skib * Last seq seen at irq time 608235783Skib */ 609235783Skib uint32_t irq_gem_seqno; 610235783Skib 611235783Skib /** 612235783Skib * Flag if the X Server, and thus DRM, is not currently in 613235783Skib * control of the device. 614235783Skib * 615235783Skib * This is set between LeaveVT and EnterVT. It needs to be 616235783Skib * replaced with a semaphore. It also needs to be 617235783Skib * transitioned away from for kernel modesetting. 618235783Skib */ 619235783Skib int suspended; 620235783Skib 621235783Skib /** 622235783Skib * Flag if the hardware appears to be wedged. 623235783Skib * 624235783Skib * This is set when attempts to idle the device timeout. 625235783Skib * It prevents command submission from occuring and makes 626235783Skib * every pending request fail 627235783Skib */ 628235783Skib int wedged; 629235783Skib 630235783Skib /** Bit 6 swizzling required for X tiling */ 631235783Skib uint32_t bit_6_swizzle_x; 632235783Skib /** Bit 6 swizzling required for Y tiling */ 633235783Skib uint32_t bit_6_swizzle_y; 634235783Skib 635235783Skib /* storage for physical objects */ 636235783Skib struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 637235783Skib 638235783Skib /* accounting, useful for userland debugging */ 639235783Skib size_t gtt_total; 640235783Skib size_t mappable_gtt_total; 641235783Skib size_t object_memory; 642235783Skib u32 object_count; 643235783Skib 644235783Skib struct intel_gtt gtt; 645235783Skib eventhandler_tag i915_lowmem; 646235783Skib } mm; 647235783Skib 648235783Skib const struct intel_device_info *info; 649235783Skib 650235783Skib struct sdvo_device_mapping sdvo_mappings[2]; 651235783Skib /* indicate whether the LVDS_BORDER should be enabled or not */ 652235783Skib unsigned int lvds_border_bits; 653235783Skib /* Panel fitter placement and size for Ironlake+ */ 654235783Skib u32 pch_pf_pos, pch_pf_size; 655235783Skib 656235783Skib struct drm_crtc *plane_to_crtc_mapping[3]; 657235783Skib struct drm_crtc *pipe_to_crtc_mapping[3]; 658235783Skib /* wait_queue_head_t pending_flip_queue; XXXKIB */ 659235783Skib bool flip_pending_is_done; 660235783Skib 661235783Skib /* Reclocking support */ 662235783Skib bool render_reclock_avail; 663235783Skib bool lvds_downclock_avail; 664235783Skib /* indicates the reduced downclock for LVDS*/ 665235783Skib int lvds_downclock; 666235783Skib struct task idle_task; 667235783Skib struct callout idle_callout; 668235783Skib bool busy; 669235783Skib u16 orig_clock; 670235783Skib int child_dev_num; 671235783Skib struct child_device_config *child_dev; 672235783Skib struct drm_connector *int_lvds_connector; 673235783Skib struct drm_connector *int_edp_connector; 674235783Skib 675235783Skib device_t bridge_dev; 676235783Skib bool mchbar_need_disable; 677235783Skib int mch_res_rid; 678235783Skib struct resource *mch_res; 679235783Skib 680235783Skib struct mtx rps_lock; 681235783Skib u32 pm_iir; 682235783Skib struct task rps_task; 683235783Skib 684235783Skib u8 cur_delay; 685235783Skib u8 min_delay; 686235783Skib u8 max_delay; 687235783Skib u8 fmax; 688235783Skib u8 fstart; 689235783Skib 690235783Skib u64 last_count1; 691235783Skib unsigned long last_time1; 692235783Skib unsigned long chipset_power; 693235783Skib u64 last_count2; 694235783Skib struct timespec last_time2; 695235783Skib unsigned long gfx_power; 696235783Skib int c_m; 697235783Skib int r_t; 698235783Skib u8 corr; 699235783Skib struct mtx *mchdev_lock; 700235783Skib 701235783Skib enum no_fbc_reason no_fbc_reason; 702235783Skib 703235783Skib unsigned long cfb_size; 704235783Skib unsigned int cfb_fb; 705235783Skib int cfb_plane; 706235783Skib int cfb_y; 707235783Skib struct intel_fbc_work *fbc_work; 708235783Skib 709235783Skib unsigned int fsb_freq, mem_freq, is_ddr3; 710235783Skib 711235783Skib struct taskqueue *tq; 712235783Skib struct task error_task; 713235783Skib struct task hotplug_task; 714235783Skib int error_completion; 715235783Skib struct mtx error_completion_lock; 716235783Skib struct drm_i915_error_state *first_error; 717235783Skib struct mtx error_lock; 718235783Skib struct callout hangcheck_timer; 719235783Skib 720235783Skib unsigned long last_gpu_reset; 721235783Skib 722235783Skib struct intel_fbdev *fbdev; 723235783Skib 724235783Skib struct drm_property *broadcast_rgb_property; 725235783Skib struct drm_property *force_audio_property; 726235783Skib} drm_i915_private_t; 727235783Skib 728235783Skibenum hdmi_force_audio { 729235783Skib HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 730235783Skib HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 731235783Skib HDMI_AUDIO_AUTO, /* trust EDID */ 732235783Skib HDMI_AUDIO_ON, /* force turn on HDMI audio */ 733235783Skib}; 734235783Skib 735235783Skibenum i915_cache_level { 736235783Skib I915_CACHE_NONE, 737235783Skib I915_CACHE_LLC, 738235783Skib I915_CACHE_LLC_MLC, /* gen6+ */ 739235783Skib}; 740235783Skib 741235783Skibenum intel_chip_family { 742235783Skib CHIP_I8XX = 0x01, 743235783Skib CHIP_I9XX = 0x02, 744235783Skib CHIP_I915 = 0x04, 745235783Skib CHIP_I965 = 0x08, 746235783Skib}; 747235783Skib 748235783Skib/** driver private structure attached to each drm_gem_object */ 749235783Skibstruct drm_i915_gem_object { 750235783Skib struct drm_gem_object base; 751235783Skib 752235783Skib /** Current space allocated to this object in the GTT, if any. */ 753235783Skib struct drm_mm_node *gtt_space; 754235783Skib struct list_head gtt_list; 755235783Skib /** This object's place on the active/flushing/inactive lists */ 756235783Skib struct list_head ring_list; 757235783Skib struct list_head mm_list; 758235783Skib /** This object's place on GPU write list */ 759235783Skib struct list_head gpu_write_list; 760235783Skib /** This object's place in the batchbuffer or on the eviction list */ 761235783Skib struct list_head exec_list; 762235783Skib 763235783Skib /** 764235783Skib * This is set if the object is on the active or flushing lists 765235783Skib * (has pending rendering), and is not set if it's on inactive (ready 766235783Skib * to be unbound). 767235783Skib */ 768235783Skib unsigned int active:1; 769235783Skib 770235783Skib /** 771235783Skib * This is set if the object has been written to since last bound 772235783Skib * to the GTT 773235783Skib */ 774235783Skib unsigned int dirty:1; 775235783Skib 776235783Skib /** 777235783Skib * This is set if the object has been written to since the last 778235783Skib * GPU flush. 779235783Skib */ 780235783Skib unsigned int pending_gpu_write:1; 781235783Skib 782235783Skib /** 783235783Skib * Fence register bits (if any) for this object. Will be set 784235783Skib * as needed when mapped into the GTT. 785235783Skib * Protected by dev->struct_mutex. 786235783Skib */ 787235783Skib signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 788235783Skib 789235783Skib /** 790235783Skib * Advice: are the backing pages purgeable? 791235783Skib */ 792235783Skib unsigned int madv:2; 793235783Skib 794235783Skib /** 795235783Skib * Current tiling mode for the object. 796235783Skib */ 797235783Skib unsigned int tiling_mode:2; 798235783Skib unsigned int tiling_changed:1; 799235783Skib 800235783Skib /** How many users have pinned this object in GTT space. The following 801235783Skib * users can each hold at most one reference: pwrite/pread, pin_ioctl 802235783Skib * (via user_pin_count), execbuffer (objects are not allowed multiple 803235783Skib * times for the same batchbuffer), and the framebuffer code. When 804235783Skib * switching/pageflipping, the framebuffer code has at most two buffers 805235783Skib * pinned per crtc. 806235783Skib * 807235783Skib * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 808235783Skib * bits with absolutely no headroom. So use 4 bits. */ 809235783Skib unsigned int pin_count:4; 810235783Skib#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 811235783Skib 812235783Skib /** 813235783Skib * Is the object at the current location in the gtt mappable and 814235783Skib * fenceable? Used to avoid costly recalculations. 815235783Skib */ 816235783Skib unsigned int map_and_fenceable:1; 817235783Skib 818235783Skib /** 819235783Skib * Whether the current gtt mapping needs to be mappable (and isn't just 820235783Skib * mappable by accident). Track pin and fault separate for a more 821235783Skib * accurate mappable working set. 822235783Skib */ 823235783Skib unsigned int fault_mappable:1; 824235783Skib unsigned int pin_mappable:1; 825235783Skib 826235783Skib /* 827235783Skib * Is the GPU currently using a fence to access this buffer, 828235783Skib */ 829235783Skib unsigned int pending_fenced_gpu_access:1; 830235783Skib unsigned int fenced_gpu_access:1; 831235783Skib 832235783Skib unsigned int cache_level:2; 833235783Skib 834235783Skib unsigned int has_aliasing_ppgtt_mapping:1; 835235783Skib 836235783Skib vm_page_t *pages; 837235783Skib 838235783Skib /** 839235783Skib * DMAR support 840235783Skib */ 841235783Skib struct sglist *sg_list; 842235783Skib 843235783Skib /** 844235783Skib * Used for performing relocations during execbuffer insertion. 845235783Skib */ 846235783Skib LIST_ENTRY(drm_i915_gem_object) exec_node; 847235783Skib unsigned long exec_handle; 848235783Skib struct drm_i915_gem_exec_object2 *exec_entry; 849235783Skib 850235783Skib /** 851235783Skib * Current offset of the object in GTT space. 852235783Skib * 853235783Skib * This is the same as gtt_space->start 854235783Skib */ 855235783Skib uint32_t gtt_offset; 856235783Skib 857235783Skib /** Breadcrumb of last rendering to the buffer. */ 858235783Skib uint32_t last_rendering_seqno; 859235783Skib struct intel_ring_buffer *ring; 860235783Skib 861235783Skib /** Breadcrumb of last fenced GPU access to the buffer. */ 862235783Skib uint32_t last_fenced_seqno; 863235783Skib struct intel_ring_buffer *last_fenced_ring; 864235783Skib 865235783Skib /** Current tiling stride for the object, if it's tiled. */ 866235783Skib uint32_t stride; 867235783Skib 868235783Skib /** Record of address bit 17 of each page at last unbind. */ 869235783Skib unsigned long *bit_17; 870235783Skib 871235783Skib /** 872235783Skib * If present, while GEM_DOMAIN_CPU is in the read domain this array 873235783Skib * flags which individual pages are valid. 874235783Skib */ 875235783Skib uint8_t *page_cpu_valid; 876235783Skib 877235783Skib /** User space pin count and filp owning the pin */ 878235783Skib uint32_t user_pin_count; 879235783Skib struct drm_file *pin_filp; 880235783Skib 881235783Skib /** for phy allocated objects */ 882235783Skib struct drm_i915_gem_phys_object *phys_obj; 883235783Skib 884235783Skib /** 885235783Skib * Number of crtcs where this object is currently the fb, but 886235783Skib * will be page flipped away on the next vblank. When it 887235783Skib * reaches 0, dev_priv->pending_flip_queue will be woken up. 888235783Skib */ 889235783Skib int pending_flip; 890235783Skib}; 891235783Skib 892235783Skib#define to_intel_bo(x) member2struct(drm_i915_gem_object, base, (x)) 893235783Skib 894235783Skib/** 895235783Skib * Request queue structure. 896235783Skib * 897235783Skib * The request queue allows us to note sequence numbers that have been emitted 898235783Skib * and may be associated with active buffers to be retired. 899235783Skib * 900235783Skib * By keeping this list, we can avoid having to do questionable 901235783Skib * sequence-number comparisons on buffer last_rendering_seqnos, and associate 902235783Skib * an emission time with seqnos for tracking how far ahead of the GPU we are. 903235783Skib */ 904235783Skibstruct drm_i915_gem_request { 905235783Skib /** On Which ring this request was generated */ 906235783Skib struct intel_ring_buffer *ring; 907235783Skib 908235783Skib /** GEM sequence number associated with this request. */ 909235783Skib uint32_t seqno; 910235783Skib 911235783Skib /** Postion in the ringbuffer of the end of the request */ 912235783Skib u32 tail; 913235783Skib 914235783Skib /** Time at which this request was emitted, in jiffies. */ 915235783Skib unsigned long emitted_jiffies; 916235783Skib 917235783Skib /** global list entry for this request */ 918235783Skib struct list_head list; 919235783Skib 920235783Skib struct drm_i915_file_private *file_priv; 921235783Skib /** file_priv list entry for this request */ 922235783Skib struct list_head client_list; 923235783Skib}; 924235783Skib 925235783Skibstruct drm_i915_file_private { 926235783Skib struct { 927235783Skib struct list_head request_list; 928235783Skib struct mtx lck; 929235783Skib } mm; 930235783Skib}; 931235783Skib 932235783Skibstruct drm_i915_error_state { 933235783Skib u32 eir; 934235783Skib u32 pgtbl_er; 935235783Skib u32 pipestat[I915_MAX_PIPES]; 936235783Skib u32 tail[I915_NUM_RINGS]; 937235783Skib u32 head[I915_NUM_RINGS]; 938235783Skib u32 ipeir[I915_NUM_RINGS]; 939235783Skib u32 ipehr[I915_NUM_RINGS]; 940235783Skib u32 instdone[I915_NUM_RINGS]; 941235783Skib u32 acthd[I915_NUM_RINGS]; 942235783Skib u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 943235783Skib /* our own tracking of ring head and tail */ 944235783Skib u32 cpu_ring_head[I915_NUM_RINGS]; 945235783Skib u32 cpu_ring_tail[I915_NUM_RINGS]; 946235783Skib u32 error; /* gen6+ */ 947235783Skib u32 instpm[I915_NUM_RINGS]; 948235783Skib u32 instps[I915_NUM_RINGS]; 949235783Skib u32 instdone1; 950235783Skib u32 seqno[I915_NUM_RINGS]; 951235783Skib u64 bbaddr; 952235783Skib u32 fault_reg[I915_NUM_RINGS]; 953235783Skib u32 done_reg; 954235783Skib u32 faddr[I915_NUM_RINGS]; 955235783Skib u64 fence[I915_MAX_NUM_FENCES]; 956235783Skib struct timeval time; 957235783Skib struct drm_i915_error_ring { 958235783Skib struct drm_i915_error_object { 959235783Skib int page_count; 960235783Skib u32 gtt_offset; 961235783Skib u32 *pages[0]; 962235783Skib } *ringbuffer, *batchbuffer; 963235783Skib struct drm_i915_error_request { 964235783Skib long jiffies; 965235783Skib u32 seqno; 966235783Skib u32 tail; 967235783Skib } *requests; 968235783Skib int num_requests; 969235783Skib } ring[I915_NUM_RINGS]; 970235783Skib struct drm_i915_error_buffer { 971235783Skib u32 size; 972235783Skib u32 name; 973235783Skib u32 seqno; 974235783Skib u32 gtt_offset; 975235783Skib u32 read_domains; 976235783Skib u32 write_domain; 977235783Skib s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 978235783Skib s32 pinned:2; 979235783Skib u32 tiling:2; 980235783Skib u32 dirty:1; 981235783Skib u32 purgeable:1; 982235783Skib s32 ring:4; 983235783Skib u32 cache_level:2; 984235783Skib } *active_bo, *pinned_bo; 985235783Skib u32 active_bo_count, pinned_bo_count; 986235783Skib struct intel_overlay_error_state *overlay; 987235783Skib struct intel_display_error_state *display; 988235783Skib}; 989235783Skib 990235783Skib/** 991235783Skib * RC6 is a special power stage which allows the GPU to enter an very 992235783Skib * low-voltage mode when idle, using down to 0V while at this stage. This 993235783Skib * stage is entered automatically when the GPU is idle when RC6 support is 994235783Skib * enabled, and as soon as new workload arises GPU wakes up automatically as well. 995235783Skib * 996235783Skib * There are different RC6 modes available in Intel GPU, which differentiate 997235783Skib * among each other with the latency required to enter and leave RC6 and 998235783Skib * voltage consumed by the GPU in different states. 999235783Skib * 1000235783Skib * The combination of the following flags define which states GPU is allowed 1001235783Skib * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1002235783Skib * RC6pp is deepest RC6. Their support by hardware varies according to the 1003235783Skib * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1004235783Skib * which brings the most power savings; deeper states save more power, but 1005235783Skib * require higher latency to switch to and wake up. 1006235783Skib */ 1007235783Skib#define INTEL_RC6_ENABLE (1<<0) 1008235783Skib#define INTEL_RC6p_ENABLE (1<<1) 1009235783Skib#define INTEL_RC6pp_ENABLE (1<<2) 1010235783Skib 1011235783Skibextern int intel_iommu_enabled; 1012235783Skibextern struct drm_ioctl_desc i915_ioctls[]; 1013235783Skibextern struct drm_driver_info i915_driver_info; 1014235783Skibextern struct cdev_pager_ops i915_gem_pager_ops; 1015235783Skibextern unsigned int i915_fbpercrtc; 1016235783Skibextern int i915_panel_ignore_lid; 1017235783Skibextern unsigned int i915_powersave; 1018235783Skibextern int i915_semaphores; 1019235783Skibextern unsigned int i915_lvds_downclock; 1020235783Skibextern int i915_panel_use_ssc; 1021235783Skibextern int i915_vbt_sdvo_panel_type; 1022235783Skibextern int i915_enable_rc6; 1023235783Skibextern int i915_enable_fbc; 1024235783Skibextern int i915_enable_ppgtt; 1025235783Skibextern int i915_enable_hangcheck; 1026235783Skib 1027235783Skibconst struct intel_device_info *i915_get_device_id(int device); 1028235783Skib 1029235783Skibint i915_reset(struct drm_device *dev, u8 flags); 1030235783Skib 1031235783Skib/* i915_debug.c */ 1032235783Skibint i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1033235783Skib struct sysctl_oid *top); 1034235783Skibvoid i915_sysctl_cleanup(struct drm_device *dev); 1035235783Skib 1036235783Skib /* i915_dma.c */ 1037239965Skibint i915_batchbuffer(struct drm_device *dev, void *data, 1038239965Skib struct drm_file *file_priv); 1039239965Skibint i915_cmdbuffer(struct drm_device *dev, void *data, 1040239965Skib struct drm_file *file_priv); 1041239965Skibint i915_getparam(struct drm_device *dev, void *data, 1042239965Skib struct drm_file *file_priv); 1043235783Skibextern void i915_kernel_lost_context(struct drm_device * dev); 1044235783Skibextern int i915_driver_load(struct drm_device *, unsigned long flags); 1045235783Skibextern int i915_driver_unload(struct drm_device *); 1046235783Skibextern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1047235783Skibextern void i915_driver_lastclose(struct drm_device * dev); 1048235783Skibextern void i915_driver_preclose(struct drm_device *dev, 1049235783Skib struct drm_file *file_priv); 1050235783Skibextern void i915_driver_postclose(struct drm_device *dev, 1051235783Skib struct drm_file *file_priv); 1052235783Skibextern int i915_driver_device_is_agp(struct drm_device * dev); 1053235783Skibextern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1054235783Skib unsigned long arg); 1055235783Skibextern int i915_emit_box(struct drm_device *dev, 1056235783Skib struct drm_clip_rect __user *boxes, 1057235783Skib int i, int DR1, int DR4); 1058235783Skibint i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1059235783Skib int DR1, int DR4); 1060235783Skib 1061235783Skibunsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1062235783Skibunsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1063235783Skibvoid i915_update_gfx_val(struct drm_i915_private *dev_priv); 1064235783Skibunsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1065235783Skibunsigned long i915_read_mch_val(void); 1066235783Skibbool i915_gpu_raise(void); 1067235783Skibbool i915_gpu_lower(void); 1068235783Skibbool i915_gpu_busy(void); 1069235783Skibbool i915_gpu_turbo_disable(void); 1070235783Skib 1071235783Skib/* i915_irq.c */ 1072235783Skibextern int i915_irq_emit(struct drm_device *dev, void *data, 1073235783Skib struct drm_file *file_priv); 1074235783Skibextern int i915_irq_wait(struct drm_device *dev, void *data, 1075235783Skib struct drm_file *file_priv); 1076235783Skib 1077235783Skibextern void intel_irq_init(struct drm_device *dev); 1078235783Skib 1079235783Skibextern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1080235783Skib struct drm_file *file_priv); 1081235783Skibextern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1082235783Skib struct drm_file *file_priv); 1083235783Skibextern int i915_vblank_swap(struct drm_device *dev, void *data, 1084235783Skib struct drm_file *file_priv); 1085235783Skibvoid intel_enable_asle(struct drm_device *dev); 1086235783Skibvoid i915_hangcheck_elapsed(void *context); 1087235783Skibvoid i915_handle_error(struct drm_device *dev, bool wedged); 1088235783Skib 1089235783Skibvoid i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1090235783Skibvoid i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1091235783Skib 1092235783Skibvoid i915_destroy_error_state(struct drm_device *dev); 1093235783Skib 1094235783Skib/* i915_gem.c */ 1095235783Skibint i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1096235783Skib uint32_t *handle_p); 1097235783Skibint i915_gem_init_ioctl(struct drm_device *dev, void *data, 1098235783Skib struct drm_file *file_priv); 1099235783Skibint i915_gem_create_ioctl(struct drm_device *dev, void *data, 1100235783Skib struct drm_file *file_priv); 1101235783Skibint i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1102235783Skib struct drm_file *file_priv); 1103235783Skibint i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1104235783Skib struct drm_file *file_priv); 1105235783Skibint i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1106235783Skib struct drm_file *file_priv); 1107235783Skibint i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1108235783Skib struct drm_file *file_priv); 1109235783Skibint i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1110235783Skib struct drm_file *file_priv); 1111235783Skibint i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1112235783Skib struct drm_file *file_priv); 1113235783Skibint i915_gem_execbuffer(struct drm_device *dev, void *data, 1114235783Skib struct drm_file *file_priv); 1115235783Skibint i915_gem_execbuffer2(struct drm_device *dev, void *data, 1116235783Skib struct drm_file *file_priv); 1117235783Skibint i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1118235783Skib struct drm_file *file_priv); 1119235783Skibint i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1120235783Skib struct drm_file *file_priv); 1121235783Skibint i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1122235783Skib struct drm_file *file_priv); 1123235783Skibint i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1124235783Skib struct drm_file *file_priv); 1125235783Skibint i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1126235783Skib struct drm_file *file_priv); 1127235783Skibint i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1128235783Skib struct drm_file *file_priv); 1129235783Skibint i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1130235783Skib struct drm_file *file_priv); 1131235783Skibint i915_gem_set_tiling(struct drm_device *dev, void *data, 1132235783Skib struct drm_file *file_priv); 1133235783Skibint i915_gem_get_tiling(struct drm_device *dev, void *data, 1134235783Skib struct drm_file *file_priv); 1135235783Skibint i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1136235783Skib struct drm_file *file_priv); 1137235783Skibvoid i915_gem_load(struct drm_device *dev); 1138235783Skibvoid i915_gem_unload(struct drm_device *dev); 1139235783Skibint i915_gem_init_object(struct drm_gem_object *obj); 1140235783Skibvoid i915_gem_free_object(struct drm_gem_object *obj); 1141235783Skibint i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1142235783Skib bool map_and_fenceable); 1143235783Skibvoid i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1144235783Skibint i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1145235783Skibvoid i915_gem_lastclose(struct drm_device *dev); 1146235783Skibuint32_t i915_get_gem_seqno(struct drm_device *dev); 1147235783Skib 1148235783Skibstatic inline void 1149235783Skibi915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1150235783Skib{ 1151235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1152235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1153235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count++; 1154235783Skib } 1155235783Skib} 1156235783Skib 1157235783Skibstatic inline void 1158235783Skibi915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1159235783Skib{ 1160235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1161235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1162235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count--; 1163235783Skib } 1164235783Skib} 1165235783Skib 1166235783Skibvoid i915_gem_retire_requests(struct drm_device *dev); 1167235783Skibvoid i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1168235783Skibvoid i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1169235783Skibstruct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1170235783Skib size_t size); 1171235783Skibint i915_gem_do_init(struct drm_device *dev, unsigned long start, 1172235783Skib unsigned long mappable_end, unsigned long end); 1173235783Skibuint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1174235783Skib uint32_t size, int tiling_mode); 1175235783Skibint i915_mutex_lock_interruptible(struct drm_device *dev); 1176235783Skibint i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1177235783Skib bool write); 1178235783Skibint i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1179235783Skib u32 alignment, struct intel_ring_buffer *pipelined); 1180235783Skibint i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1181235783Skibint i915_gem_flush_ring(struct intel_ring_buffer *ring, 1182235783Skib uint32_t invalidate_domains, uint32_t flush_domains); 1183235783Skibvoid i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1184235783Skibint i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1185235783Skibint i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1186235783Skibint i915_gem_idle(struct drm_device *dev); 1187235783Skibint i915_gem_init_hw(struct drm_device *dev); 1188235783Skibvoid i915_gem_init_swizzling(struct drm_device *dev); 1189235783Skibvoid i915_gem_init_ppgtt(struct drm_device *dev); 1190235783Skibvoid i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1191235783Skibint i915_gpu_idle(struct drm_device *dev, bool do_retire); 1192235783Skibvoid i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1193235783Skib struct intel_ring_buffer *ring, uint32_t seqno); 1194235783Skibint i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1195235783Skib struct drm_i915_gem_request *request); 1196235783Skibint i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1197235783Skib struct intel_ring_buffer *pipelined); 1198235783Skibvoid i915_gem_reset(struct drm_device *dev); 1199235783Skibint i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1200235783Skib bool do_retire); 1201235783Skibint i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1202235783Skibint i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1203235783Skib uint64_t *phys); 1204235783Skibvoid i915_gem_release(struct drm_device *dev, struct drm_file *file); 1205235783Skibint i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1206235783Skib enum i915_cache_level cache_level); 1207235783Skib 1208235783Skibvoid i915_gem_free_all_phys_object(struct drm_device *dev); 1209235783Skibvoid i915_gem_detach_phys_object(struct drm_device *dev, 1210235783Skib struct drm_i915_gem_object *obj); 1211235783Skibint i915_gem_attach_phys_object(struct drm_device *dev, 1212235783Skib struct drm_i915_gem_object *obj, int id, int align); 1213235783Skib 1214235783Skibint i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1215235783Skib struct drm_mode_create_dumb *args); 1216235783Skibint i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1217235783Skib uint32_t handle, uint64_t *offset); 1218235783Skibint i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1219235783Skib uint32_t handle); 1220235783Skib 1221235783Skib/* i915_gem_tiling.c */ 1222235783Skibvoid i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1223235783Skibvoid i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1224235783Skibvoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1225235783Skib 1226235783Skib/* i915_gem_evict.c */ 1227235783Skibint i915_gem_evict_something(struct drm_device *dev, int min_size, 1228235783Skib unsigned alignment, bool mappable); 1229235783Skibint i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1230235783Skibint i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1231235783Skib 1232235783Skib/* i915_suspend.c */ 1233235783Skibextern int i915_save_state(struct drm_device *dev); 1234235783Skibextern int i915_restore_state(struct drm_device *dev); 1235235783Skib 1236235783Skib/* intel_iic.c */ 1237235783Skibextern int intel_setup_gmbus(struct drm_device *dev); 1238235783Skibextern void intel_teardown_gmbus(struct drm_device *dev); 1239235783Skibextern void intel_gmbus_set_speed(device_t idev, int speed); 1240235783Skibextern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1241235783Skibextern void intel_iic_reset(struct drm_device *dev); 1242235783Skib 1243235783Skib/* intel_opregion.c */ 1244235783Skibint intel_opregion_setup(struct drm_device *dev); 1245235783Skibextern int intel_opregion_init(struct drm_device *dev); 1246235783Skibextern void intel_opregion_fini(struct drm_device *dev); 1247235783Skibextern void opregion_asle_intr(struct drm_device *dev); 1248235783Skibextern void opregion_enable_asle(struct drm_device *dev); 1249235783Skib 1250235783Skib/* i915_gem_gtt.c */ 1251235783Skibint i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1252235783Skibvoid i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1253235783Skibvoid i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1254235783Skib struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1255235783Skibvoid i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1256235783Skib struct drm_i915_gem_object *obj); 1257235783Skib 1258235783Skibvoid i915_gem_restore_gtt_mappings(struct drm_device *dev); 1259235783Skibint i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1260235783Skibvoid i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1261235783Skibvoid i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1262235783Skib enum i915_cache_level cache_level); 1263235783Skib 1264235783Skib/* modesetting */ 1265235783Skibextern void intel_modeset_init(struct drm_device *dev); 1266235783Skibextern void intel_modeset_gem_init(struct drm_device *dev); 1267235783Skibextern void intel_modeset_cleanup(struct drm_device *dev); 1268235783Skibextern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1269235783Skibextern bool intel_fbc_enabled(struct drm_device *dev); 1270235783Skibextern void intel_disable_fbc(struct drm_device *dev); 1271235783Skibextern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1272235783Skibextern void ironlake_init_pch_refclk(struct drm_device *dev); 1273235783Skibextern void ironlake_enable_rc6(struct drm_device *dev); 1274235783Skibextern void gen6_set_rps(struct drm_device *dev, u8 val); 1275235783Skibextern void intel_detect_pch(struct drm_device *dev); 1276235783Skibextern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1277235783Skib 1278235783Skibextern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1279235783Skibextern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1280235783Skibextern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1281235783Skibextern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1282235783Skib 1283235783Skibextern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1284235783Skib struct drm_device *dev); 1285235783Skibextern void intel_overlay_print_error_state(struct sbuf *m, 1286235783Skib struct intel_overlay_error_state *error); 1287235783Skibextern struct intel_display_error_state *intel_display_capture_error_state( 1288235783Skib struct drm_device *dev); 1289235783Skibextern void intel_display_print_error_state(struct sbuf *m, 1290235783Skib struct drm_device *dev, struct intel_display_error_state *error); 1291235783Skib 1292235783Skibstatic inline void 1293235783Skibtrace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1294235783Skib{ 1295235783Skib 1296235783Skib CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val); 1297235783Skib} 1298235783Skib 1299235783Skib/* On SNB platform, before reading ring registers forcewake bit 1300235783Skib * must be set to prevent GT core from power down and stale values being 1301235783Skib * returned. 1302235783Skib */ 1303235783Skibvoid gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1304235783Skibvoid gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1305235783Skibint __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1306235783Skib 1307235783Skib/* We give fast paths for the really cool registers */ 1308235783Skib#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1309235783Skib (((dev_priv)->info->gen >= 6) && \ 1310235783Skib ((reg) < 0x40000) && \ 1311235783Skib ((reg) != FORCEWAKE)) 1312235783Skib 1313235783Skib#define __i915_read(x, y) \ 1314235783Skib u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1315235783Skib 1316235783Skib__i915_read(8, 8) 1317235783Skib__i915_read(16, 16) 1318235783Skib__i915_read(32, 32) 1319235783Skib__i915_read(64, 64) 1320235783Skib#undef __i915_read 1321235783Skib 1322235783Skib#define __i915_write(x, y) \ 1323235783Skib void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1324235783Skib 1325235783Skib__i915_write(8, 8) 1326235783Skib__i915_write(16, 16) 1327235783Skib__i915_write(32, 32) 1328235783Skib__i915_write(64, 64) 1329235783Skib#undef __i915_write 1330235783Skib 1331235783Skib#define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1332235783Skib#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1333235783Skib 1334235783Skib#define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1335235783Skib#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1336235783Skib#define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1337235783Skib#define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1338235783Skib 1339235783Skib#define I915_READ(reg) i915_read32(dev_priv, (reg)) 1340235783Skib#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1341235783Skib#define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1342235783Skib#define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1343235783Skib 1344235783Skib#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1345235783Skib#define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1346235783Skib 1347235783Skib#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1348235783Skib#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1349235783Skib 1350235783Skib#define I915_VERBOSE 0 1351235783Skib 1352235783Skib#define LP_RING(d) (&((struct drm_i915_private *)(d))->rings[RCS]) 1353235783Skib 1354235783Skib#define BEGIN_LP_RING(n) \ 1355235783Skib intel_ring_begin(LP_RING(dev_priv), (n)) 1356235783Skib 1357235783Skib#define OUT_RING(x) \ 1358235783Skib intel_ring_emit(LP_RING(dev_priv), x) 1359235783Skib 1360235783Skib#define ADVANCE_LP_RING() \ 1361235783Skib intel_ring_advance(LP_RING(dev_priv)) 1362235783Skib 1363235783Skib#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1364235783Skib if (LP_RING(dev->dev_private)->obj == NULL) \ 1365235783Skib LOCK_TEST_WITH_RETURN(dev, file); \ 1366235783Skib} while (0) 1367235783Skib 1368235783Skib/** 1369235783Skib * Reads a dword out of the status page, which is written to from the command 1370235783Skib * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1371235783Skib * MI_STORE_DATA_IMM. 1372235783Skib * 1373235783Skib * The following dwords have a reserved meaning: 1374235783Skib * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1375235783Skib * 0x04: ring 0 head pointer 1376235783Skib * 0x05: ring 1 head pointer (915-class) 1377235783Skib * 0x06: ring 2 head pointer (915-class) 1378235783Skib * 0x10-0x1b: Context status DWords (GM45) 1379235783Skib * 0x1f: Last written status offset. (GM45) 1380235783Skib * 1381235783Skib * The area from dword 0x20 to 0x3ff is available for driver usage. 1382235783Skib */ 1383235783Skib#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1384235783Skib#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1385235783Skib#define I915_GEM_HWS_INDEX 0x20 1386235783Skib#define I915_BREADCRUMB_INDEX 0x21 1387235783Skib 1388235783Skib#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1389235783Skib 1390235783Skib#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1391235783Skib#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1392235783Skib#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1393235783Skib#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1394235783Skib#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1395235783Skib#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1396235783Skib#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1397235783Skib#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1398235783Skib#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1399235783Skib#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1400235783Skib#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1401235783Skib#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1402235783Skib#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1403235783Skib#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1404235783Skib#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1405235783Skib#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1406235783Skib#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1407235783Skib#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1408235783Skib#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1409235783Skib#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1410235783Skib 1411235783Skib/* XXXKIB LEGACY */ 1412235783Skib#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1413235783Skib (dev)->pci_device == 0x2982 || \ 1414235783Skib (dev)->pci_device == 0x2992 || \ 1415235783Skib (dev)->pci_device == 0x29A2 || \ 1416235783Skib (dev)->pci_device == 0x2A02 || \ 1417235783Skib (dev)->pci_device == 0x2A12 || \ 1418235783Skib (dev)->pci_device == 0x2A42 || \ 1419235783Skib (dev)->pci_device == 0x2E02 || \ 1420235783Skib (dev)->pci_device == 0x2E12 || \ 1421235783Skib (dev)->pci_device == 0x2E22 || \ 1422235783Skib (dev)->pci_device == 0x2E32) 1423235783Skib 1424235783Skib#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1425235783Skib 1426235783Skib#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1427235783Skib#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1428235783Skib#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1429235783Skib 1430235783Skib#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1431235783Skib IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1432235783Skib/* XXXKIB LEGACY END */ 1433235783Skib 1434235783Skib#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1435235783Skib#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1436235783Skib#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1437235783Skib#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1438235783Skib#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1439235783Skib#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1440235783Skib 1441235783Skib#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1442235783Skib#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1443235783Skib#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1444235783Skib#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1445235783Skib 1446235783Skib#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1447235783Skib 1448235783Skib#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1449235783Skib#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1450235783Skib 1451235783Skib/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1452235783Skib * rows, which changed the alignment requirements and fence programming. 1453235783Skib */ 1454235783Skib#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1455235783Skib IS_I915GM(dev))) 1456235783Skib#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1457235783Skib#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1458235783Skib#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1459235783Skib#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1460235783Skib#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1461235783Skib#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1462235783Skib/* dsparb controlled by hw only */ 1463235783Skib#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1464235783Skib 1465235783Skib#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1466235783Skib#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1467235783Skib#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1468235783Skib 1469235783Skib#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1470235783Skib#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1471235783Skib 1472235783Skib#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1473235783Skib#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1474235783Skib#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1475235783Skib 1476235783Skib#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1477235783Skib 1478235783Skibstatic inline bool 1479235783Skibi915_seqno_passed(uint32_t seq1, uint32_t seq2) 1480235783Skib{ 1481235783Skib 1482235783Skib return ((int32_t)(seq1 - seq2) >= 0); 1483235783Skib} 1484235783Skib 1485235783Skibu32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1486235783Skib 1487235783Skib#endif 1488