1235783Skib/*- 2235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3235783Skib * All Rights Reserved. 4235783Skib * 5235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 6235783Skib * copy of this software and associated documentation files (the 7235783Skib * "Software"), to deal in the Software without restriction, including 8235783Skib * without limitation the rights to use, copy, modify, merge, publish, 9235783Skib * distribute, sub license, and/or sell copies of the Software, and to 10235783Skib * permit persons to whom the Software is furnished to do so, subject to 11235783Skib * the following conditions: 12235783Skib * 13235783Skib * The above copyright notice and this permission notice (including the 14235783Skib * next paragraph) shall be included in all copies or substantial portions 15235783Skib * of the Software. 16235783Skib * 17235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24235783Skib * 25235783Skib */ 26235783Skib 27235783Skib#include <sys/cdefs.h> 28235783Skib__FBSDID("$FreeBSD$"); 29235783Skib 30235783Skib#ifndef _I915_DRM_H_ 31235783Skib#define _I915_DRM_H_ 32235783Skib 33235783Skib/* Please note that modifications to all structs defined here are 34235783Skib * subject to backwards-compatibility constraints. 35235783Skib */ 36235783Skib 37235783Skib#include <dev/drm2/drm.h> 38235783Skib 39235783Skib/* Each region is a minimum of 16k, and there are at most 255 of them. 40235783Skib */ 41235783Skib#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 42235783Skib * of chars for next/prev indices */ 43235783Skib#define I915_LOG_MIN_TEX_REGION_SIZE 14 44235783Skib 45235783Skibtypedef struct _drm_i915_init { 46235783Skib enum { 47235783Skib I915_INIT_DMA = 0x01, 48235783Skib I915_CLEANUP_DMA = 0x02, 49235783Skib I915_RESUME_DMA = 0x03, 50235783Skib 51235783Skib /* Since this struct isn't versioned, just used a new 52235783Skib * 'func' code to indicate the presence of dri2 sarea 53235783Skib * info. */ 54235783Skib I915_INIT_DMA2 = 0x04 55235783Skib } func; 56235783Skib unsigned int mmio_offset; 57235783Skib int sarea_priv_offset; 58235783Skib unsigned int ring_start; 59235783Skib unsigned int ring_end; 60235783Skib unsigned int ring_size; 61235783Skib unsigned int front_offset; 62235783Skib unsigned int back_offset; 63235783Skib unsigned int depth_offset; 64235783Skib unsigned int w; 65235783Skib unsigned int h; 66235783Skib unsigned int pitch; 67235783Skib unsigned int pitch_bits; 68235783Skib unsigned int back_pitch; 69235783Skib unsigned int depth_pitch; 70235783Skib unsigned int cpp; 71235783Skib unsigned int chipset; 72235783Skib unsigned int sarea_handle; 73235783Skib} drm_i915_init_t; 74235783Skib 75235783Skibtypedef struct drm_i915_sarea { 76235783Skib struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77235783Skib int last_upload; /* last time texture was uploaded */ 78235783Skib int last_enqueue; /* last time a buffer was enqueued */ 79235783Skib int last_dispatch; /* age of the most recently dispatched buffer */ 80235783Skib int ctxOwner; /* last context to upload state */ 81235783Skib int texAge; 82235783Skib int pf_enabled; /* is pageflipping allowed? */ 83235783Skib int pf_active; 84235783Skib int pf_current_page; /* which buffer is being displayed? */ 85235783Skib int perf_boxes; /* performance boxes to be displayed */ 86235783Skib int width, height; /* screen size in pixels */ 87235783Skib 88235783Skib drm_handle_t front_handle; 89235783Skib int front_offset; 90235783Skib int front_size; 91235783Skib 92235783Skib drm_handle_t back_handle; 93235783Skib int back_offset; 94235783Skib int back_size; 95235783Skib 96235783Skib drm_handle_t depth_handle; 97235783Skib int depth_offset; 98235783Skib int depth_size; 99235783Skib 100235783Skib drm_handle_t tex_handle; 101235783Skib int tex_offset; 102235783Skib int tex_size; 103235783Skib int log_tex_granularity; 104235783Skib int pitch; 105235783Skib int rotation; /* 0, 90, 180 or 270 */ 106235783Skib int rotated_offset; 107235783Skib int rotated_size; 108235783Skib int rotated_pitch; 109235783Skib int virtualX, virtualY; 110235783Skib 111235783Skib unsigned int front_tiled; 112235783Skib unsigned int back_tiled; 113235783Skib unsigned int depth_tiled; 114235783Skib unsigned int rotated_tiled; 115235783Skib unsigned int rotated2_tiled; 116235783Skib 117235783Skib int planeA_x; 118235783Skib int planeA_y; 119235783Skib int planeA_w; 120235783Skib int planeA_h; 121235783Skib int planeB_x; 122235783Skib int planeB_y; 123235783Skib int planeB_w; 124235783Skib int planeB_h; 125235783Skib 126235783Skib /* Triple buffering */ 127235783Skib drm_handle_t third_handle; 128235783Skib int third_offset; 129235783Skib int third_size; 130235783Skib unsigned int third_tiled; 131235783Skib 132235783Skib /* buffer object handles for the static buffers. May change 133235783Skib * over the lifetime of the client, though it doesn't in our current 134235783Skib * implementation. 135235783Skib */ 136235783Skib unsigned int front_bo_handle; 137235783Skib unsigned int back_bo_handle; 138235783Skib unsigned int third_bo_handle; 139235783Skib unsigned int depth_bo_handle; 140235783Skib} drm_i915_sarea_t; 141235783Skib 142235783Skib/* Driver specific fence types and classes. 143235783Skib */ 144235783Skib 145235783Skib/* The only fence class we support */ 146235783Skib#define DRM_I915_FENCE_CLASS_ACCEL 0 147235783Skib/* Fence type that guarantees read-write flush */ 148235783Skib#define DRM_I915_FENCE_TYPE_RW 2 149235783Skib/* MI_FLUSH programmed just before the fence */ 150235783Skib#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 151235783Skib 152235783Skib/* Flags for perf_boxes 153235783Skib */ 154235783Skib#define I915_BOX_RING_EMPTY 0x1 155235783Skib#define I915_BOX_FLIP 0x2 156235783Skib#define I915_BOX_WAIT 0x4 157235783Skib#define I915_BOX_TEXTURE_LOAD 0x8 158235783Skib#define I915_BOX_LOST_CONTEXT 0x10 159235783Skib 160235783Skib/* I915 specific ioctls 161235783Skib * The device specific ioctl range is 0x40 to 0x79. 162235783Skib */ 163235783Skib#define DRM_I915_INIT 0x00 164235783Skib#define DRM_I915_FLUSH 0x01 165235783Skib#define DRM_I915_FLIP 0x02 166235783Skib#define DRM_I915_BATCHBUFFER 0x03 167235783Skib#define DRM_I915_IRQ_EMIT 0x04 168235783Skib#define DRM_I915_IRQ_WAIT 0x05 169235783Skib#define DRM_I915_GETPARAM 0x06 170235783Skib#define DRM_I915_SETPARAM 0x07 171235783Skib#define DRM_I915_ALLOC 0x08 172235783Skib#define DRM_I915_FREE 0x09 173235783Skib#define DRM_I915_INIT_HEAP 0x0a 174235783Skib#define DRM_I915_CMDBUFFER 0x0b 175235783Skib#define DRM_I915_DESTROY_HEAP 0x0c 176235783Skib#define DRM_I915_SET_VBLANK_PIPE 0x0d 177235783Skib#define DRM_I915_GET_VBLANK_PIPE 0x0e 178235783Skib#define DRM_I915_VBLANK_SWAP 0x0f 179235783Skib#define DRM_I915_MMIO 0x10 180235783Skib#define DRM_I915_HWS_ADDR 0x11 181235783Skib#define DRM_I915_EXECBUFFER 0x12 182235783Skib#define DRM_I915_GEM_INIT 0x13 183235783Skib#define DRM_I915_GEM_EXECBUFFER 0x14 184235783Skib#define DRM_I915_GEM_PIN 0x15 185235783Skib#define DRM_I915_GEM_UNPIN 0x16 186235783Skib#define DRM_I915_GEM_BUSY 0x17 187235783Skib#define DRM_I915_GEM_THROTTLE 0x18 188235783Skib#define DRM_I915_GEM_ENTERVT 0x19 189235783Skib#define DRM_I915_GEM_LEAVEVT 0x1a 190235783Skib#define DRM_I915_GEM_CREATE 0x1b 191235783Skib#define DRM_I915_GEM_PREAD 0x1c 192235783Skib#define DRM_I915_GEM_PWRITE 0x1d 193235783Skib#define DRM_I915_GEM_MMAP 0x1e 194235783Skib#define DRM_I915_GEM_SET_DOMAIN 0x1f 195235783Skib#define DRM_I915_GEM_SW_FINISH 0x20 196235783Skib#define DRM_I915_GEM_SET_TILING 0x21 197235783Skib#define DRM_I915_GEM_GET_TILING 0x22 198235783Skib#define DRM_I915_GEM_GET_APERTURE 0x23 199235783Skib#define DRM_I915_GEM_MMAP_GTT 0x24 200235783Skib#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 201235783Skib#define DRM_I915_GEM_MADVISE 0x26 202235783Skib#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 203235783Skib#define DRM_I915_OVERLAY_ATTRS 0x28 204235783Skib#define DRM_I915_GEM_EXECBUFFER2 0x29 205235783Skib#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 206235783Skib#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 207235783Skib 208235783Skib#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 209235783Skib#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 210235783Skib#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 211235783Skib#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 212235783Skib#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 213235783Skib#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 214235783Skib#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 215235783Skib#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 216235783Skib#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 217235783Skib#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 218235783Skib#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 219235783Skib#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 220235783Skib#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 221235783Skib#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 222235783Skib#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 223235783Skib#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 224235783Skib#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) 225235783Skib#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) 226235783Skib#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 227235783Skib#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 228235783Skib#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 229235783Skib#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 230235783Skib#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 231235783Skib#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 232235783Skib#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 233235783Skib#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 234235783Skib#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 235235783Skib#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 236235783Skib#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 237235783Skib#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 238235783Skib#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 239235783Skib#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 240235783Skib#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 241235783Skib#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 242235783Skib#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 243235783Skib#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 244235783Skib#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 245235783Skib#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 246235783Skib#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 247235783Skib#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 248235783Skib#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 249235783Skib#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 250235783Skib#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 251235783Skib 252235783Skib/* Asynchronous page flipping: 253235783Skib */ 254235783Skibtypedef struct drm_i915_flip { 255235783Skib /* 256235783Skib * This is really talking about planes, and we could rename it 257235783Skib * except for the fact that some of the duplicated i915_drm.h files 258235783Skib * out there check for HAVE_I915_FLIP and so might pick up this 259235783Skib * version. 260235783Skib */ 261235783Skib int pipes; 262235783Skib} drm_i915_flip_t; 263235783Skib 264235783Skib/* Allow drivers to submit batchbuffers directly to hardware, relying 265235783Skib * on the security mechanisms provided by hardware. 266235783Skib */ 267235783Skibtypedef struct drm_i915_batchbuffer { 268235783Skib int start; /* agp offset */ 269235783Skib int used; /* nr bytes in use */ 270235783Skib int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 271235783Skib int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 272235783Skib int num_cliprects; /* mulitpass with multiple cliprects? */ 273235783Skib struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 274235783Skib} drm_i915_batchbuffer_t; 275235783Skib 276235783Skib/* As above, but pass a pointer to userspace buffer which can be 277235783Skib * validated by the kernel prior to sending to hardware. 278235783Skib */ 279235783Skibtypedef struct _drm_i915_cmdbuffer { 280235783Skib char __user *buf; /* pointer to userspace command buffer */ 281235783Skib int sz; /* nr bytes in buf */ 282235783Skib int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 283235783Skib int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 284235783Skib int num_cliprects; /* mulitpass with multiple cliprects? */ 285235783Skib struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 286235783Skib} drm_i915_cmdbuffer_t; 287235783Skib 288235783Skib/* Userspace can request & wait on irq's: 289235783Skib */ 290235783Skibtypedef struct drm_i915_irq_emit { 291235783Skib int __user *irq_seq; 292235783Skib} drm_i915_irq_emit_t; 293235783Skib 294235783Skibtypedef struct drm_i915_irq_wait { 295235783Skib int irq_seq; 296235783Skib} drm_i915_irq_wait_t; 297235783Skib 298235783Skib/* Ioctl to query kernel params: 299235783Skib */ 300235783Skib#define I915_PARAM_IRQ_ACTIVE 1 301235783Skib#define I915_PARAM_ALLOW_BATCHBUFFER 2 302235783Skib#define I915_PARAM_LAST_DISPATCH 3 303235783Skib#define I915_PARAM_CHIPSET_ID 4 304235783Skib#define I915_PARAM_HAS_GEM 5 305235783Skib#define I915_PARAM_NUM_FENCES_AVAIL 6 306235783Skib#define I915_PARAM_HAS_OVERLAY 7 307235783Skib#define I915_PARAM_HAS_PAGEFLIPPING 8 308235783Skib#define I915_PARAM_HAS_EXECBUF2 9 309235783Skib#define I915_PARAM_HAS_BSD 10 310235783Skib#define I915_PARAM_HAS_BLT 11 311235783Skib#define I915_PARAM_HAS_RELAXED_FENCING 12 312235783Skib#define I915_PARAM_HAS_COHERENT_RINGS 13 313235783Skib#define I915_PARAM_HAS_EXEC_CONSTANTS 14 314235783Skib#define I915_PARAM_HAS_RELAXED_DELTA 15 315235783Skib#define I915_PARAM_HAS_GEN7_SOL_RESET 16 316235783Skib#define I915_PARAM_HAS_LLC 17 317235783Skib 318235783Skibtypedef struct drm_i915_getparam { 319235783Skib int param; 320235783Skib int __user *value; 321235783Skib} drm_i915_getparam_t; 322235783Skib 323235783Skib/* Ioctl to set kernel params: 324235783Skib */ 325235783Skib#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 326235783Skib#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 327235783Skib#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 328235783Skib#define I915_SETPARAM_NUM_USED_FENCES 4 329235783Skib 330235783Skibtypedef struct drm_i915_setparam { 331235783Skib int param; 332235783Skib int value; 333235783Skib} drm_i915_setparam_t; 334235783Skib 335235783Skib/* A memory manager for regions of shared memory: 336235783Skib */ 337235783Skib#define I915_MEM_REGION_AGP 1 338235783Skib 339235783Skibtypedef struct drm_i915_mem_alloc { 340235783Skib int region; 341235783Skib int alignment; 342235783Skib int size; 343235783Skib int __user *region_offset; /* offset from start of fb or agp */ 344235783Skib} drm_i915_mem_alloc_t; 345235783Skib 346235783Skibtypedef struct drm_i915_mem_free { 347235783Skib int region; 348235783Skib int region_offset; 349235783Skib} drm_i915_mem_free_t; 350235783Skib 351235783Skibtypedef struct drm_i915_mem_init_heap { 352235783Skib int region; 353235783Skib int size; 354235783Skib int start; 355235783Skib} drm_i915_mem_init_heap_t; 356235783Skib 357235783Skib/* Allow memory manager to be torn down and re-initialized (eg on 358235783Skib * rotate): 359235783Skib */ 360235783Skibtypedef struct drm_i915_mem_destroy_heap { 361235783Skib int region; 362235783Skib} drm_i915_mem_destroy_heap_t; 363235783Skib 364235783Skib/* Allow X server to configure which pipes to monitor for vblank signals 365235783Skib */ 366235783Skib#define DRM_I915_VBLANK_PIPE_A 1 367235783Skib#define DRM_I915_VBLANK_PIPE_B 2 368235783Skib 369235783Skibtypedef struct drm_i915_vblank_pipe { 370235783Skib int pipe; 371235783Skib} drm_i915_vblank_pipe_t; 372235783Skib 373235783Skib/* Schedule buffer swap at given vertical blank: 374235783Skib */ 375235783Skibtypedef struct drm_i915_vblank_swap { 376235783Skib drm_drawable_t drawable; 377235783Skib enum drm_vblank_seq_type seqtype; 378235783Skib unsigned int sequence; 379235783Skib} drm_i915_vblank_swap_t; 380235783Skib 381235783Skib#define I915_MMIO_READ 0 382235783Skib#define I915_MMIO_WRITE 1 383235783Skib 384235783Skib#define I915_MMIO_MAY_READ 0x1 385235783Skib#define I915_MMIO_MAY_WRITE 0x2 386235783Skib 387235783Skib#define MMIO_REGS_IA_PRIMATIVES_COUNT 0 388235783Skib#define MMIO_REGS_IA_VERTICES_COUNT 1 389235783Skib#define MMIO_REGS_VS_INVOCATION_COUNT 2 390235783Skib#define MMIO_REGS_GS_PRIMITIVES_COUNT 3 391235783Skib#define MMIO_REGS_GS_INVOCATION_COUNT 4 392235783Skib#define MMIO_REGS_CL_PRIMITIVES_COUNT 5 393235783Skib#define MMIO_REGS_CL_INVOCATION_COUNT 6 394235783Skib#define MMIO_REGS_PS_INVOCATION_COUNT 7 395235783Skib#define MMIO_REGS_PS_DEPTH_COUNT 8 396235783Skib 397235783Skibtypedef struct drm_i915_mmio_entry { 398235783Skib unsigned int flag; 399235783Skib unsigned int offset; 400235783Skib unsigned int size; 401235783Skib} drm_i915_mmio_entry_t; 402235783Skib 403235783Skibtypedef struct drm_i915_mmio { 404235783Skib unsigned int read_write:1; 405235783Skib unsigned int reg:31; 406235783Skib void __user *data; 407235783Skib} drm_i915_mmio_t; 408235783Skib 409235783Skibtypedef struct drm_i915_hws_addr { 410235783Skib uint64_t addr; 411235783Skib} drm_i915_hws_addr_t; 412235783Skib 413235783Skib/* 414235783Skib * Relocation header is 4 uint32_ts 415235783Skib * 0 - 32 bit reloc count 416235783Skib * 1 - 32-bit relocation type 417235783Skib * 2-3 - 64-bit user buffer handle ptr for another list of relocs. 418235783Skib */ 419235783Skib#define I915_RELOC_HEADER 4 420235783Skib 421235783Skib/* 422235783Skib * type 0 relocation has 4-uint32_t stride 423235783Skib * 0 - offset into buffer 424235783Skib * 1 - delta to add in 425235783Skib * 2 - buffer handle 426235783Skib * 3 - reserved (for optimisations later). 427235783Skib */ 428235783Skib/* 429235783Skib * type 1 relocation has 4-uint32_t stride. 430235783Skib * Hangs off the first item in the op list. 431235783Skib * Performed after all valiations are done. 432235783Skib * Try to group relocs into the same relocatee together for 433235783Skib * performance reasons. 434235783Skib * 0 - offset into buffer 435235783Skib * 1 - delta to add in 436235783Skib * 2 - buffer index in op list. 437235783Skib * 3 - relocatee index in op list. 438235783Skib */ 439235783Skib#define I915_RELOC_TYPE_0 0 440235783Skib#define I915_RELOC0_STRIDE 4 441235783Skib#define I915_RELOC_TYPE_1 1 442235783Skib#define I915_RELOC1_STRIDE 4 443235783Skib 444235783Skib 445235783Skibstruct drm_i915_op_arg { 446235783Skib uint64_t next; 447235783Skib uint64_t reloc_ptr; 448235783Skib int handled; 449235783Skib unsigned int pad64; 450235783Skib union { 451235783Skib struct drm_bo_op_req req; 452235783Skib struct drm_bo_arg_rep rep; 453235783Skib } d; 454235783Skib 455235783Skib}; 456235783Skib 457235783Skibstruct drm_i915_execbuffer { 458235783Skib uint64_t ops_list; 459235783Skib uint32_t num_buffers; 460235783Skib struct drm_i915_batchbuffer batch; 461235783Skib drm_context_t context; /* for lockless use in the future */ 462235783Skib struct drm_fence_arg fence_arg; 463235783Skib}; 464235783Skib 465235783Skibstruct drm_i915_gem_init { 466235783Skib /** 467235783Skib * Beginning offset in the GTT to be managed by the DRM memory 468235783Skib * manager. 469235783Skib */ 470235783Skib uint64_t gtt_start; 471235783Skib /** 472235783Skib * Ending offset in the GTT to be managed by the DRM memory 473235783Skib * manager. 474235783Skib */ 475235783Skib uint64_t gtt_end; 476235783Skib}; 477235783Skib 478235783Skibstruct drm_i915_gem_create { 479235783Skib /** 480235783Skib * Requested size for the object. 481235783Skib * 482235783Skib * The (page-aligned) allocated size for the object will be returned. 483235783Skib */ 484235783Skib uint64_t size; 485235783Skib /** 486235783Skib * Returned handle for the object. 487235783Skib * 488235783Skib * Object handles are nonzero. 489235783Skib */ 490235783Skib uint32_t handle; 491235783Skib uint32_t pad; 492235783Skib}; 493235783Skib 494235783Skibstruct drm_i915_gem_pread { 495235783Skib /** Handle for the object being read. */ 496235783Skib uint32_t handle; 497235783Skib uint32_t pad; 498235783Skib /** Offset into the object to read from */ 499235783Skib uint64_t offset; 500235783Skib /** Length of data to read */ 501235783Skib uint64_t size; 502235783Skib /** Pointer to write the data into. */ 503235783Skib uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 504235783Skib}; 505235783Skib 506235783Skibstruct drm_i915_gem_pwrite { 507235783Skib /** Handle for the object being written to. */ 508235783Skib uint32_t handle; 509235783Skib uint32_t pad; 510235783Skib /** Offset into the object to write to */ 511235783Skib uint64_t offset; 512235783Skib /** Length of data to write */ 513235783Skib uint64_t size; 514235783Skib /** Pointer to read the data from. */ 515235783Skib uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 516235783Skib}; 517235783Skib 518235783Skibstruct drm_i915_gem_mmap { 519235783Skib /** Handle for the object being mapped. */ 520235783Skib uint32_t handle; 521235783Skib uint32_t pad; 522235783Skib /** Offset in the object to map. */ 523235783Skib uint64_t offset; 524235783Skib /** 525235783Skib * Length of data to map. 526235783Skib * 527235783Skib * The value will be page-aligned. 528235783Skib */ 529235783Skib uint64_t size; 530235783Skib /** Returned pointer the data was mapped at */ 531235783Skib uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */ 532235783Skib}; 533235783Skib 534235783Skibstruct drm_i915_gem_mmap_gtt { 535235783Skib /** Handle for the object being mapped. */ 536235783Skib uint32_t handle; 537235783Skib uint32_t pad; 538235783Skib /** 539235783Skib * Fake offset to use for subsequent mmap call 540235783Skib * 541235783Skib * This is a fixed-size type for 32/64 compatibility. 542235783Skib */ 543235783Skib uint64_t offset; 544235783Skib}; 545235783Skib 546235783Skibstruct drm_i915_gem_set_domain { 547235783Skib /** Handle for the object */ 548235783Skib uint32_t handle; 549235783Skib 550235783Skib /** New read domains */ 551235783Skib uint32_t read_domains; 552235783Skib 553235783Skib /** New write domain */ 554235783Skib uint32_t write_domain; 555235783Skib}; 556235783Skib 557235783Skibstruct drm_i915_gem_sw_finish { 558235783Skib /** Handle for the object */ 559235783Skib uint32_t handle; 560235783Skib}; 561235783Skib 562235783Skibstruct drm_i915_gem_relocation_entry { 563235783Skib /** 564235783Skib * Handle of the buffer being pointed to by this relocation entry. 565235783Skib * 566235783Skib * It's appealing to make this be an index into the mm_validate_entry 567235783Skib * list to refer to the buffer, but this allows the driver to create 568235783Skib * a relocation list for state buffers and not re-write it per 569235783Skib * exec using the buffer. 570235783Skib */ 571235783Skib uint32_t target_handle; 572235783Skib 573235783Skib /** 574235783Skib * Value to be added to the offset of the target buffer to make up 575235783Skib * the relocation entry. 576235783Skib */ 577235783Skib uint32_t delta; 578235783Skib 579235783Skib /** Offset in the buffer the relocation entry will be written into */ 580235783Skib uint64_t offset; 581235783Skib 582235783Skib /** 583235783Skib * Offset value of the target buffer that the relocation entry was last 584235783Skib * written as. 585235783Skib * 586235783Skib * If the buffer has the same offset as last time, we can skip syncing 587235783Skib * and writing the relocation. This value is written back out by 588235783Skib * the execbuffer ioctl when the relocation is written. 589235783Skib */ 590235783Skib uint64_t presumed_offset; 591235783Skib 592235783Skib /** 593235783Skib * Target memory domains read by this operation. 594235783Skib */ 595235783Skib uint32_t read_domains; 596235783Skib 597235783Skib /** 598235783Skib * Target memory domains written by this operation. 599235783Skib * 600235783Skib * Note that only one domain may be written by the whole 601235783Skib * execbuffer operation, so that where there are conflicts, 602235783Skib * the application will get -EINVAL back. 603235783Skib */ 604235783Skib uint32_t write_domain; 605235783Skib}; 606235783Skib 607235783Skib/** @{ 608235783Skib * Intel memory domains 609235783Skib * 610235783Skib * Most of these just align with the various caches in 611235783Skib * the system and are used to flush and invalidate as 612235783Skib * objects end up cached in different domains. 613235783Skib */ 614235783Skib/** CPU cache */ 615235783Skib#define I915_GEM_DOMAIN_CPU 0x00000001 616235783Skib/** Render cache, used by 2D and 3D drawing */ 617235783Skib#define I915_GEM_DOMAIN_RENDER 0x00000002 618235783Skib/** Sampler cache, used by texture engine */ 619235783Skib#define I915_GEM_DOMAIN_SAMPLER 0x00000004 620235783Skib/** Command queue, used to load batch buffers */ 621235783Skib#define I915_GEM_DOMAIN_COMMAND 0x00000008 622235783Skib/** Instruction cache, used by shader programs */ 623235783Skib#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 624235783Skib/** Vertex address cache */ 625235783Skib#define I915_GEM_DOMAIN_VERTEX 0x00000020 626235783Skib/** GTT domain - aperture and scanout */ 627235783Skib#define I915_GEM_DOMAIN_GTT 0x00000040 628235783Skib/** @} */ 629235783Skib 630235783Skibstruct drm_i915_gem_exec_object { 631235783Skib /** 632235783Skib * User's handle for a buffer to be bound into the GTT for this 633235783Skib * operation. 634235783Skib */ 635235783Skib uint32_t handle; 636235783Skib 637235783Skib /** Number of relocations to be performed on this buffer */ 638235783Skib uint32_t relocation_count; 639235783Skib /** 640235783Skib * Pointer to array of struct drm_i915_gem_relocation_entry containing 641235783Skib * the relocations to be performed in this buffer. 642235783Skib */ 643235783Skib uint64_t relocs_ptr; 644235783Skib 645235783Skib /** Required alignment in graphics aperture */ 646235783Skib uint64_t alignment; 647235783Skib 648235783Skib /** 649235783Skib * Returned value of the updated offset of the object, for future 650235783Skib * presumed_offset writes. 651235783Skib */ 652235783Skib uint64_t offset; 653235783Skib}; 654235783Skib 655235783Skibstruct drm_i915_gem_execbuffer { 656235783Skib /** 657235783Skib * List of buffers to be validated with their relocations to be 658235783Skib * performend on them. 659235783Skib * 660235783Skib * This is a pointer to an array of struct drm_i915_gem_validate_entry. 661235783Skib * 662235783Skib * These buffers must be listed in an order such that all relocations 663235783Skib * a buffer is performing refer to buffers that have already appeared 664235783Skib * in the validate list. 665235783Skib */ 666235783Skib uint64_t buffers_ptr; 667235783Skib uint32_t buffer_count; 668235783Skib 669235783Skib /** Offset in the batchbuffer to start execution from. */ 670235783Skib uint32_t batch_start_offset; 671235783Skib /** Bytes used in batchbuffer from batch_start_offset */ 672235783Skib uint32_t batch_len; 673235783Skib uint32_t DR1; 674235783Skib uint32_t DR4; 675235783Skib uint32_t num_cliprects; 676235783Skib uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */ 677235783Skib}; 678235783Skib 679235783Skibstruct drm_i915_gem_exec_object2 { 680235783Skib /** 681235783Skib * User's handle for a buffer to be bound into the GTT for this 682235783Skib * operation. 683235783Skib */ 684235783Skib uint32_t handle; 685235783Skib 686235783Skib /** Number of relocations to be performed on this buffer */ 687235783Skib uint32_t relocation_count; 688235783Skib /** 689235783Skib * Pointer to array of struct drm_i915_gem_relocation_entry containing 690235783Skib * the relocations to be performed in this buffer. 691235783Skib */ 692235783Skib uint64_t relocs_ptr; 693235783Skib 694235783Skib /** Required alignment in graphics aperture */ 695235783Skib uint64_t alignment; 696235783Skib 697235783Skib /** 698235783Skib * Returned value of the updated offset of the object, for future 699235783Skib * presumed_offset writes. 700235783Skib */ 701235783Skib uint64_t offset; 702235783Skib 703235783Skib#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 704235783Skib uint64_t flags; 705235783Skib uint64_t rsvd1; 706235783Skib uint64_t rsvd2; 707235783Skib}; 708235783Skib 709235783Skibstruct drm_i915_gem_execbuffer2 { 710235783Skib /** 711235783Skib * List of gem_exec_object2 structs 712235783Skib */ 713235783Skib uint64_t buffers_ptr; 714235783Skib uint32_t buffer_count; 715235783Skib 716235783Skib /** Offset in the batchbuffer to start execution from. */ 717235783Skib uint32_t batch_start_offset; 718235783Skib /** Bytes used in batchbuffer from batch_start_offset */ 719235783Skib uint32_t batch_len; 720235783Skib uint32_t DR1; 721235783Skib uint32_t DR4; 722235783Skib uint32_t num_cliprects; 723235783Skib /** This is a struct drm_clip_rect *cliprects */ 724235783Skib uint64_t cliprects_ptr; 725235783Skib#define I915_EXEC_RING_MASK (7<<0) 726235783Skib#define I915_EXEC_DEFAULT (0<<0) 727235783Skib#define I915_EXEC_RENDER (1<<0) 728235783Skib#define I915_EXEC_BSD (2<<0) 729235783Skib#define I915_EXEC_BLT (3<<0) 730235783Skib 731235783Skib/* Used for switching the constants addressing mode on gen4+ RENDER ring. 732235783Skib * Gen6+ only supports relative addressing to dynamic state (default) and 733235783Skib * absolute addressing. 734235783Skib * 735235783Skib * These flags are ignored for the BSD and BLT rings. 736235783Skib */ 737235783Skib#define I915_EXEC_CONSTANTS_MASK (3<<6) 738235783Skib#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 739235783Skib#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 740235783Skib#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 741235783Skib uint64_t flags; 742235783Skib uint64_t rsvd1; 743235783Skib uint64_t rsvd2; 744235783Skib}; 745235783Skib 746235783Skib/** Resets the SO write offset registers for transform feedback on gen7. */ 747235783Skib#define I915_EXEC_GEN7_SOL_RESET (1<<8) 748235783Skib 749235783Skibstruct drm_i915_gem_pin { 750235783Skib /** Handle of the buffer to be pinned. */ 751235783Skib uint32_t handle; 752235783Skib uint32_t pad; 753235783Skib 754235783Skib /** alignment required within the aperture */ 755235783Skib uint64_t alignment; 756235783Skib 757235783Skib /** Returned GTT offset of the buffer. */ 758235783Skib uint64_t offset; 759235783Skib}; 760235783Skib 761235783Skibstruct drm_i915_gem_unpin { 762235783Skib /** Handle of the buffer to be unpinned. */ 763235783Skib uint32_t handle; 764235783Skib uint32_t pad; 765235783Skib}; 766235783Skib 767235783Skibstruct drm_i915_gem_busy { 768235783Skib /** Handle of the buffer to check for busy */ 769235783Skib uint32_t handle; 770235783Skib 771235783Skib /** Return busy status (1 if busy, 0 if idle) */ 772235783Skib uint32_t busy; 773235783Skib}; 774235783Skib 775235783Skib#define I915_TILING_NONE 0 776235783Skib#define I915_TILING_X 1 777235783Skib#define I915_TILING_Y 2 778235783Skib 779235783Skib#define I915_BIT_6_SWIZZLE_NONE 0 780235783Skib#define I915_BIT_6_SWIZZLE_9 1 781235783Skib#define I915_BIT_6_SWIZZLE_9_10 2 782235783Skib#define I915_BIT_6_SWIZZLE_9_11 3 783235783Skib#define I915_BIT_6_SWIZZLE_9_10_11 4 784235783Skib/* Not seen by userland */ 785235783Skib#define I915_BIT_6_SWIZZLE_UNKNOWN 5 786235783Skib/* Seen by userland. */ 787235783Skib#define I915_BIT_6_SWIZZLE_9_17 6 788235783Skib#define I915_BIT_6_SWIZZLE_9_10_17 7 789235783Skib 790235783Skibstruct drm_i915_gem_set_tiling { 791235783Skib /** Handle of the buffer to have its tiling state updated */ 792235783Skib uint32_t handle; 793235783Skib 794235783Skib /** 795235783Skib * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 796235783Skib * I915_TILING_Y). 797235783Skib * 798235783Skib * This value is to be set on request, and will be updated by the 799235783Skib * kernel on successful return with the actual chosen tiling layout. 800235783Skib * 801235783Skib * The tiling mode may be demoted to I915_TILING_NONE when the system 802235783Skib * has bit 6 swizzling that can't be managed correctly by GEM. 803235783Skib * 804235783Skib * Buffer contents become undefined when changing tiling_mode. 805235783Skib */ 806235783Skib uint32_t tiling_mode; 807235783Skib 808235783Skib /** 809235783Skib * Stride in bytes for the object when in I915_TILING_X or 810235783Skib * I915_TILING_Y. 811235783Skib */ 812235783Skib uint32_t stride; 813235783Skib 814235783Skib /** 815235783Skib * Returned address bit 6 swizzling required for CPU access through 816235783Skib * mmap mapping. 817235783Skib */ 818235783Skib uint32_t swizzle_mode; 819235783Skib}; 820235783Skib 821235783Skibstruct drm_i915_gem_get_tiling { 822235783Skib /** Handle of the buffer to get tiling state for. */ 823235783Skib uint32_t handle; 824235783Skib 825235783Skib /** 826235783Skib * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 827235783Skib * I915_TILING_Y). 828235783Skib */ 829235783Skib uint32_t tiling_mode; 830235783Skib 831235783Skib /** 832235783Skib * Returned address bit 6 swizzling required for CPU access through 833235783Skib * mmap mapping. 834235783Skib */ 835235783Skib uint32_t swizzle_mode; 836235783Skib}; 837235783Skib 838235783Skibstruct drm_i915_gem_get_aperture { 839235783Skib /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 840235783Skib uint64_t aper_size; 841235783Skib 842235783Skib /** 843235783Skib * Available space in the aperture used by i915_gem_execbuffer, in 844235783Skib * bytes 845235783Skib */ 846235783Skib uint64_t aper_available_size; 847235783Skib}; 848235783Skib 849235783Skibstruct drm_i915_get_pipe_from_crtc_id { 850235783Skib /** ID of CRTC being requested **/ 851235783Skib uint32_t crtc_id; 852235783Skib 853235783Skib /** pipe of requested CRTC **/ 854235783Skib uint32_t pipe; 855235783Skib}; 856235783Skib 857235783Skib#define I915_MADV_WILLNEED 0 858235783Skib#define I915_MADV_DONTNEED 1 859235783Skib#define I915_MADV_PURGED_INTERNAL 2 /* internal state */ 860235783Skib 861235783Skibstruct drm_i915_gem_madvise { 862235783Skib /** Handle of the buffer to change the backing store advice */ 863235783Skib uint32_t handle; 864235783Skib 865235783Skib /* Advice: either the buffer will be needed again in the near future, 866235783Skib * or wont be and could be discarded under memory pressure. 867235783Skib */ 868235783Skib uint32_t madv; 869235783Skib 870235783Skib /** Whether the backing store still exists. */ 871235783Skib uint32_t retained; 872235783Skib}; 873235783Skib 874235783Skib#define I915_OVERLAY_TYPE_MASK 0xff 875235783Skib#define I915_OVERLAY_YUV_PLANAR 0x01 876235783Skib#define I915_OVERLAY_YUV_PACKED 0x02 877235783Skib#define I915_OVERLAY_RGB 0x03 878235783Skib 879235783Skib#define I915_OVERLAY_DEPTH_MASK 0xff00 880235783Skib#define I915_OVERLAY_RGB24 0x1000 881235783Skib#define I915_OVERLAY_RGB16 0x2000 882235783Skib#define I915_OVERLAY_RGB15 0x3000 883235783Skib#define I915_OVERLAY_YUV422 0x0100 884235783Skib#define I915_OVERLAY_YUV411 0x0200 885235783Skib#define I915_OVERLAY_YUV420 0x0300 886235783Skib#define I915_OVERLAY_YUV410 0x0400 887235783Skib 888235783Skib#define I915_OVERLAY_SWAP_MASK 0xff0000 889235783Skib#define I915_OVERLAY_NO_SWAP 0x000000 890235783Skib#define I915_OVERLAY_UV_SWAP 0x010000 891235783Skib#define I915_OVERLAY_Y_SWAP 0x020000 892235783Skib#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 893235783Skib 894235783Skib#define I915_OVERLAY_FLAGS_MASK 0xff000000 895235783Skib#define I915_OVERLAY_ENABLE 0x01000000 896235783Skib 897235783Skibstruct drm_intel_overlay_put_image { 898235783Skib /* various flags and src format description */ 899235783Skib uint32_t flags; 900235783Skib /* source picture description */ 901235783Skib uint32_t bo_handle; 902235783Skib /* stride values and offsets are in bytes, buffer relative */ 903235783Skib uint16_t stride_Y; /* stride for packed formats */ 904235783Skib uint16_t stride_UV; 905235783Skib uint32_t offset_Y; /* offset for packet formats */ 906235783Skib uint32_t offset_U; 907235783Skib uint32_t offset_V; 908235783Skib /* in pixels */ 909235783Skib uint16_t src_width; 910235783Skib uint16_t src_height; 911235783Skib /* to compensate the scaling factors for partially covered surfaces */ 912235783Skib uint16_t src_scan_width; 913235783Skib uint16_t src_scan_height; 914235783Skib /* output crtc description */ 915235783Skib uint32_t crtc_id; 916235783Skib uint16_t dst_x; 917235783Skib uint16_t dst_y; 918235783Skib uint16_t dst_width; 919235783Skib uint16_t dst_height; 920235783Skib}; 921235783Skib 922235783Skib/* flags */ 923235783Skib#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 924235783Skib#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 925235783Skibstruct drm_intel_overlay_attrs { 926235783Skib uint32_t flags; 927235783Skib uint32_t color_key; 928235783Skib int32_t brightness; 929235783Skib uint32_t contrast; 930235783Skib uint32_t saturation; 931235783Skib uint32_t gamma0; 932235783Skib uint32_t gamma1; 933235783Skib uint32_t gamma2; 934235783Skib uint32_t gamma3; 935235783Skib uint32_t gamma4; 936235783Skib uint32_t gamma5; 937235783Skib}; 938235783Skib 939235783Skib/* 940235783Skib * Intel sprite handling 941235783Skib * 942235783Skib * Color keying works with a min/mask/max tuple. Both source and destination 943235783Skib * color keying is allowed. 944235783Skib * 945235783Skib * Source keying: 946235783Skib * Sprite pixels within the min & max values, masked against the color channels 947235783Skib * specified in the mask field, will be transparent. All other pixels will 948235783Skib * be displayed on top of the primary plane. For RGB surfaces, only the min 949235783Skib * and mask fields will be used; ranged compares are not allowed. 950235783Skib * 951235783Skib * Destination keying: 952235783Skib * Primary plane pixels that match the min value, masked against the color 953235783Skib * channels specified in the mask field, will be replaced by corresponding 954235783Skib * pixels from the sprite plane. 955235783Skib * 956235783Skib * Note that source & destination keying are exclusive; only one can be 957235783Skib * active on a given plane. 958235783Skib */ 959235783Skib 960235783Skib#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 961235783Skib#define I915_SET_COLORKEY_DESTINATION (1<<1) 962235783Skib#define I915_SET_COLORKEY_SOURCE (1<<2) 963235783Skibstruct drm_intel_sprite_colorkey { 964235783Skib uint32_t plane_id; 965235783Skib uint32_t min_value; 966235783Skib uint32_t channel_mask; 967235783Skib uint32_t max_value; 968235783Skib uint32_t flags; 969235783Skib}; 970235783Skib 971235783Skib#endif /* _I915_DRM_H_ */ 972