drm_dp_helper.h revision 235783
1/* 2 * Copyright �� 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 * 22 * $FreeBSD: head/sys/dev/drm2/drm_dp_helper.h 235783 2012-05-22 11:07:44Z kib $ 23 */ 24 25#ifndef _DRM_DP_HELPER_H_ 26#define _DRM_DP_HELPER_H_ 27 28/* From the VESA DisplayPort spec */ 29 30#define AUX_NATIVE_WRITE 0x8 31#define AUX_NATIVE_READ 0x9 32#define AUX_I2C_WRITE 0x0 33#define AUX_I2C_READ 0x1 34#define AUX_I2C_STATUS 0x2 35#define AUX_I2C_MOT 0x4 36 37#define AUX_NATIVE_REPLY_ACK (0x0 << 4) 38#define AUX_NATIVE_REPLY_NACK (0x1 << 4) 39#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 40#define AUX_NATIVE_REPLY_MASK (0x3 << 4) 41 42#define AUX_I2C_REPLY_ACK (0x0 << 6) 43#define AUX_I2C_REPLY_NACK (0x1 << 6) 44#define AUX_I2C_REPLY_DEFER (0x2 << 6) 45#define AUX_I2C_REPLY_MASK (0x3 << 6) 46 47/* AUX CH addresses */ 48/* DPCD */ 49#define DP_DPCD_REV 0x000 50 51#define DP_MAX_LINK_RATE 0x001 52 53#define DP_MAX_LANE_COUNT 0x002 54# define DP_MAX_LANE_COUNT_MASK 0x1f 55# define DP_TPS3_SUPPORTED (1 << 6) 56# define DP_ENHANCED_FRAME_CAP (1 << 7) 57 58#define DP_MAX_DOWNSPREAD 0x003 59# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 60 61#define DP_NORP 0x004 62 63#define DP_DOWNSTREAMPORT_PRESENT 0x005 64# define DP_DWN_STRM_PORT_PRESENT (1 << 0) 65# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 66/* 00b = DisplayPort */ 67/* 01b = Analog */ 68/* 10b = TMDS or HDMI */ 69/* 11b = Other */ 70# define DP_FORMAT_CONVERSION (1 << 3) 71 72#define DP_MAIN_LINK_CHANNEL_CODING 0x006 73 74#define DP_TRAINING_AUX_RD_INTERVAL 0x00e 75 76#define DP_PSR_SUPPORT 0x070 77# define DP_PSR_IS_SUPPORTED 1 78#define DP_PSR_CAPS 0x071 79# define DP_PSR_NO_TRAIN_ON_EXIT 1 80# define DP_PSR_SETUP_TIME_330 (0 << 1) 81# define DP_PSR_SETUP_TIME_275 (1 << 1) 82# define DP_PSR_SETUP_TIME_220 (2 << 1) 83# define DP_PSR_SETUP_TIME_165 (3 << 1) 84# define DP_PSR_SETUP_TIME_110 (4 << 1) 85# define DP_PSR_SETUP_TIME_55 (5 << 1) 86# define DP_PSR_SETUP_TIME_0 (6 << 1) 87# define DP_PSR_SETUP_TIME_MASK (7 << 1) 88# define DP_PSR_SETUP_TIME_SHIFT 1 89 90/* link configuration */ 91#define DP_LINK_BW_SET 0x100 92# define DP_LINK_BW_1_62 0x06 93# define DP_LINK_BW_2_7 0x0a 94# define DP_LINK_BW_5_4 0x14 95 96#define DP_LANE_COUNT_SET 0x101 97# define DP_LANE_COUNT_MASK 0x0f 98# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 99 100#define DP_TRAINING_PATTERN_SET 0x102 101# define DP_TRAINING_PATTERN_DISABLE 0 102# define DP_TRAINING_PATTERN_1 1 103# define DP_TRAINING_PATTERN_2 2 104# define DP_TRAINING_PATTERN_3 3 105# define DP_TRAINING_PATTERN_MASK 0x3 106 107# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 108# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 109# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 110# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 111# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 112 113# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 114# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 115 116# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 117# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 118# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 119# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 120 121#define DP_TRAINING_LANE0_SET 0x103 122#define DP_TRAINING_LANE1_SET 0x104 123#define DP_TRAINING_LANE2_SET 0x105 124#define DP_TRAINING_LANE3_SET 0x106 125 126# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 127# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 128# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 129# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 130# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 131# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 132# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 133 134# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 135# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 136# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 137# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 138# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 139 140# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 141# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 142 143#define DP_DOWNSPREAD_CTRL 0x107 144# define DP_SPREAD_AMP_0_5 (1 << 4) 145 146#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 147# define DP_SET_ANSI_8B10B (1 << 0) 148 149#define DP_PSR_EN_CFG 0x170 150# define DP_PSR_ENABLE (1 << 0) 151# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 152# define DP_PSR_CRC_VERIFICATION (1 << 2) 153# define DP_PSR_FRAME_CAPTURE (1 << 3) 154 155#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 156# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 157# define DP_AUTOMATED_TEST_REQUEST (1 << 1) 158# define DP_CP_IRQ (1 << 2) 159# define DP_SINK_SPECIFIC_IRQ (1 << 6) 160 161#define DP_LANE0_1_STATUS 0x202 162#define DP_LANE2_3_STATUS 0x203 163# define DP_LANE_CR_DONE (1 << 0) 164# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 165# define DP_LANE_SYMBOL_LOCKED (1 << 2) 166 167#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 168 DP_LANE_CHANNEL_EQ_DONE | \ 169 DP_LANE_SYMBOL_LOCKED) 170 171#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 172 173#define DP_INTERLANE_ALIGN_DONE (1 << 0) 174#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 175#define DP_LINK_STATUS_UPDATED (1 << 7) 176 177#define DP_SINK_STATUS 0x205 178 179#define DP_RECEIVE_PORT_0_STATUS (1 << 0) 180#define DP_RECEIVE_PORT_1_STATUS (1 << 1) 181 182#define DP_ADJUST_REQUEST_LANE0_1 0x206 183#define DP_ADJUST_REQUEST_LANE2_3 0x207 184# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 185# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 186# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 187# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 188# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 189# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 190# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 191# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 192 193#define DP_TEST_REQUEST 0x218 194# define DP_TEST_LINK_TRAINING (1 << 0) 195# define DP_TEST_LINK_PATTERN (1 << 1) 196# define DP_TEST_LINK_EDID_READ (1 << 2) 197# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 198 199#define DP_TEST_LINK_RATE 0x219 200# define DP_LINK_RATE_162 (0x6) 201# define DP_LINK_RATE_27 (0xa) 202 203#define DP_TEST_LANE_COUNT 0x220 204 205#define DP_TEST_PATTERN 0x221 206 207#define DP_TEST_RESPONSE 0x260 208# define DP_TEST_ACK (1 << 0) 209# define DP_TEST_NAK (1 << 1) 210# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 211 212#define DP_SET_POWER 0x600 213# define DP_SET_POWER_D0 0x1 214# define DP_SET_POWER_D3 0x2 215 216#define DP_PSR_ERROR_STATUS 0x2006 217# define DP_PSR_LINK_CRC_ERROR (1 << 0) 218# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 219 220#define DP_PSR_ESI 0x2007 221# define DP_PSR_CAPS_CHANGE (1 << 0) 222 223#define DP_PSR_STATUS 0x2008 224# define DP_PSR_SINK_INACTIVE 0 225# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 226# define DP_PSR_SINK_ACTIVE_RFB 2 227# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 228# define DP_PSR_SINK_ACTIVE_RESYNC 4 229# define DP_PSR_SINK_INTERNAL_ERROR 7 230# define DP_PSR_SINK_STATE_MASK 0x07 231 232#define MODE_I2C_START 1 233#define MODE_I2C_WRITE 2 234#define MODE_I2C_READ 4 235#define MODE_I2C_STOP 8 236 237struct iic_dp_aux_data { 238 bool running; 239 u16 address; 240 void *priv; 241 int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte, 242 uint8_t *read_byte); 243 device_t port; 244}; 245 246int iic_dp_aux_add_bus(device_t dev, const char *name, 247 int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte), 248 void *priv, device_t *bus, device_t *adapter); 249 250#endif /* _DRM_DP_HELPER_H_ */ 251