1203288Srnoland/*- 2203288Srnoland * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. 3203288Srnoland * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. 4203288Srnoland * 5203288Srnoland * Permission is hereby granted, free of charge, to any person obtaining a 6203288Srnoland * copy of this software and associated documentation files (the "Software"), 7203288Srnoland * to deal in the Software without restriction, including without limitation 8203288Srnoland * the rights to use, copy, modify, merge, publish, distribute, sub license, 9203288Srnoland * and/or sell copies of the Software, and to permit persons to whom the 10203288Srnoland * Software is furnished to do so, subject to the following conditions: 11203288Srnoland * 12203288Srnoland * The above copyright notice and this permission notice (including the 13203288Srnoland * next paragraph) shall be included in all copies or substantial portions 14203288Srnoland * of the Software. 15203288Srnoland * 16203288Srnoland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17203288Srnoland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18203288Srnoland * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19203288Srnoland * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20203288Srnoland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21203288Srnoland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22203288Srnoland * DEALINGS IN THE SOFTWARE. 23203288Srnoland */ 24203288Srnoland 25203288Srnoland#include <sys/cdefs.h> 26203288Srnoland__FBSDID("$FreeBSD$"); 27203288Srnoland 28203288Srnoland#ifndef _VIA_DRM_H_ 29203288Srnoland#define _VIA_DRM_H_ 30203288Srnoland 31203288Srnoland/* WARNING: These defines must be the same as what the Xserver uses. 32203288Srnoland * if you change them, you must change the defines in the Xserver. 33203288Srnoland */ 34203288Srnoland 35203288Srnoland#ifndef _VIA_DEFINES_ 36203288Srnoland#define _VIA_DEFINES_ 37203288Srnoland 38203288Srnoland#if !defined(__KERNEL__) && !defined(_KERNEL) 39203288Srnoland#include "via_drmclient.h" 40203288Srnoland#endif 41203288Srnoland 42203288Srnoland#define VIA_NR_SAREA_CLIPRECTS 8 43203288Srnoland#define VIA_NR_XVMC_PORTS 10 44203288Srnoland#define VIA_NR_XVMC_LOCKS 5 45203288Srnoland#define VIA_MAX_CACHELINE_SIZE 64 46203288Srnoland#define XVMCLOCKPTR(saPriv,lockNo) \ 47203288Srnoland ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ 48203288Srnoland (VIA_MAX_CACHELINE_SIZE - 1)) & \ 49203288Srnoland ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ 50203288Srnoland VIA_MAX_CACHELINE_SIZE*(lockNo))) 51203288Srnoland 52203288Srnoland/* Each region is a minimum of 64k, and there are at most 64 of them. 53203288Srnoland */ 54203288Srnoland#define VIA_NR_TEX_REGIONS 64 55203288Srnoland#define VIA_LOG_MIN_TEX_REGION_SIZE 16 56203288Srnoland#endif 57203288Srnoland 58203288Srnoland#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 59203288Srnoland#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 60203288Srnoland#define VIA_UPLOAD_CTX 0x4 61203288Srnoland#define VIA_UPLOAD_BUFFERS 0x8 62203288Srnoland#define VIA_UPLOAD_TEX0 0x10 63203288Srnoland#define VIA_UPLOAD_TEX1 0x20 64203288Srnoland#define VIA_UPLOAD_CLIPRECTS 0x40 65203288Srnoland#define VIA_UPLOAD_ALL 0xff 66203288Srnoland 67203288Srnoland/* VIA specific ioctls */ 68203288Srnoland#define DRM_VIA_ALLOCMEM 0x00 69203288Srnoland#define DRM_VIA_FREEMEM 0x01 70203288Srnoland#define DRM_VIA_AGP_INIT 0x02 71203288Srnoland#define DRM_VIA_FB_INIT 0x03 72203288Srnoland#define DRM_VIA_MAP_INIT 0x04 73203288Srnoland#define DRM_VIA_DEC_FUTEX 0x05 74203288Srnoland#define NOT_USED 75203288Srnoland#define DRM_VIA_DMA_INIT 0x07 76203288Srnoland#define DRM_VIA_CMDBUFFER 0x08 77203288Srnoland#define DRM_VIA_FLUSH 0x09 78203288Srnoland#define DRM_VIA_PCICMD 0x0a 79203288Srnoland#define DRM_VIA_CMDBUF_SIZE 0x0b 80203288Srnoland#define NOT_USED 81203288Srnoland#define DRM_VIA_WAIT_IRQ 0x0d 82203288Srnoland#define DRM_VIA_DMA_BLIT 0x0e 83203288Srnoland#define DRM_VIA_BLIT_SYNC 0x0f 84203288Srnoland 85203288Srnoland#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) 86203288Srnoland#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) 87203288Srnoland#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) 88203288Srnoland#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) 89203288Srnoland#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) 90203288Srnoland#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) 91203288Srnoland#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) 92203288Srnoland#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) 93203288Srnoland#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) 94203288Srnoland#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) 95203288Srnoland#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ 96203288Srnoland drm_via_cmdbuf_size_t) 97203288Srnoland#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) 98203288Srnoland#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) 99203288Srnoland#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) 100203288Srnoland 101203288Srnoland/* Indices into buf.Setup where various bits of state are mirrored per 102203288Srnoland * context and per buffer. These can be fired at the card as a unit, 103203288Srnoland * or in a piecewise fashion as required. 104203288Srnoland */ 105203288Srnoland 106203288Srnoland#define VIA_TEX_SETUP_SIZE 8 107203288Srnoland 108203288Srnoland/* Flags for clear ioctl 109203288Srnoland */ 110203288Srnoland#define VIA_FRONT 0x1 111203288Srnoland#define VIA_BACK 0x2 112203288Srnoland#define VIA_DEPTH 0x4 113203288Srnoland#define VIA_STENCIL 0x8 114203288Srnoland#define VIA_MEM_VIDEO 0 /* matches drm constant */ 115203288Srnoland#define VIA_MEM_AGP 1 /* matches drm constant */ 116203288Srnoland#define VIA_MEM_SYSTEM 2 117203288Srnoland#define VIA_MEM_MIXED 3 118203288Srnoland#define VIA_MEM_UNKNOWN 4 119203288Srnoland 120203288Srnolandtypedef struct { 121203288Srnoland u32 offset; 122203288Srnoland u32 size; 123203288Srnoland} drm_via_agp_t; 124203288Srnoland 125203288Srnolandtypedef struct { 126203288Srnoland u32 offset; 127203288Srnoland u32 size; 128203288Srnoland} drm_via_fb_t; 129203288Srnoland 130203288Srnolandtypedef struct { 131203288Srnoland u32 context; 132203288Srnoland u32 type; 133203288Srnoland u32 size; 134203288Srnoland unsigned long index; 135203288Srnoland unsigned long offset; 136203288Srnoland} drm_via_mem_t; 137203288Srnoland 138203288Srnolandtypedef struct _drm_via_init { 139203288Srnoland enum { 140203288Srnoland VIA_INIT_MAP = 0x01, 141203288Srnoland VIA_CLEANUP_MAP = 0x02 142203288Srnoland } func; 143203288Srnoland 144203288Srnoland unsigned long sarea_priv_offset; 145203288Srnoland unsigned long fb_offset; 146203288Srnoland unsigned long mmio_offset; 147203288Srnoland unsigned long agpAddr; 148203288Srnoland} drm_via_init_t; 149203288Srnoland 150203288Srnolandtypedef struct _drm_via_futex { 151203288Srnoland enum { 152203288Srnoland VIA_FUTEX_WAIT = 0x00, 153203288Srnoland VIA_FUTEX_WAKE = 0X01 154203288Srnoland } func; 155203288Srnoland u32 ms; 156203288Srnoland u32 lock; 157203288Srnoland u32 val; 158203288Srnoland} drm_via_futex_t; 159203288Srnoland 160203288Srnolandtypedef struct _drm_via_dma_init { 161203288Srnoland enum { 162203288Srnoland VIA_INIT_DMA = 0x01, 163203288Srnoland VIA_CLEANUP_DMA = 0x02, 164203288Srnoland VIA_DMA_INITIALIZED = 0x03 165203288Srnoland } func; 166203288Srnoland 167203288Srnoland unsigned long offset; 168203288Srnoland unsigned long size; 169203288Srnoland unsigned long reg_pause_addr; 170203288Srnoland} drm_via_dma_init_t; 171203288Srnoland 172203288Srnolandtypedef struct _drm_via_cmdbuffer { 173203288Srnoland char __user *buf; 174203288Srnoland unsigned long size; 175203288Srnoland} drm_via_cmdbuffer_t; 176203288Srnoland 177203288Srnoland/* Warning: If you change the SAREA structure you must change the Xserver 178203288Srnoland * structure as well */ 179203288Srnoland 180203288Srnolandtypedef struct _drm_via_tex_region { 181203288Srnoland unsigned char next, prev; /* indices to form a circular LRU */ 182203288Srnoland unsigned char inUse; /* owned by a client, or free? */ 183203288Srnoland int age; /* tracked by clients to update local LRU's */ 184203288Srnoland} drm_via_tex_region_t; 185203288Srnoland 186203288Srnolandtypedef struct _drm_via_sarea { 187203288Srnoland unsigned int dirty; 188203288Srnoland unsigned int nbox; 189203288Srnoland struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; 190203288Srnoland drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; 191203288Srnoland int texAge; /* last time texture was uploaded */ 192203288Srnoland int ctxOwner; /* last context to upload state */ 193203288Srnoland int vertexPrim; 194203288Srnoland 195203288Srnoland /* 196203288Srnoland * Below is for XvMC. 197203288Srnoland * We want the lock integers alone on, and aligned to, a cache line. 198203288Srnoland * Therefore this somewhat strange construct. 199203288Srnoland */ 200203288Srnoland 201203288Srnoland char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; 202203288Srnoland 203203288Srnoland unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; 204203288Srnoland unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; 205203288Srnoland unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ 206203288Srnoland 207203288Srnoland /* Used by the 3d driver only at this point, for pageflipping: 208203288Srnoland */ 209203288Srnoland unsigned int pfCurrentOffset; 210203288Srnoland} drm_via_sarea_t; 211203288Srnoland 212203288Srnolandtypedef struct _drm_via_cmdbuf_size { 213203288Srnoland enum { 214203288Srnoland VIA_CMDBUF_SPACE = 0x01, 215203288Srnoland VIA_CMDBUF_LAG = 0x02 216203288Srnoland } func; 217203288Srnoland int wait; 218203288Srnoland u32 size; 219203288Srnoland} drm_via_cmdbuf_size_t; 220203288Srnoland 221203288Srnolandtypedef enum { 222203288Srnoland VIA_IRQ_ABSOLUTE = 0x0, 223203288Srnoland VIA_IRQ_RELATIVE = 0x1, 224203288Srnoland VIA_IRQ_SIGNAL = 0x10000000, 225203288Srnoland VIA_IRQ_FORCE_SEQUENCE = 0x20000000 226203288Srnoland} via_irq_seq_type_t; 227203288Srnoland 228203288Srnoland#define VIA_IRQ_FLAGS_MASK 0xF0000000 229203288Srnoland 230203288Srnolandenum drm_via_irqs { 231203288Srnoland drm_via_irq_hqv0 = 0, 232203288Srnoland drm_via_irq_hqv1, 233203288Srnoland drm_via_irq_dma0_dd, 234203288Srnoland drm_via_irq_dma0_td, 235203288Srnoland drm_via_irq_dma1_dd, 236203288Srnoland drm_via_irq_dma1_td, 237203288Srnoland drm_via_irq_num 238203288Srnoland}; 239203288Srnoland 240203288Srnolandstruct drm_via_wait_irq_request { 241203288Srnoland unsigned irq; 242203288Srnoland via_irq_seq_type_t type; 243203288Srnoland u32 sequence; 244203288Srnoland u32 signal; 245203288Srnoland}; 246203288Srnoland 247203288Srnolandtypedef union drm_via_irqwait { 248203288Srnoland struct drm_via_wait_irq_request request; 249203288Srnoland struct drm_wait_vblank_reply reply; 250203288Srnoland} drm_via_irqwait_t; 251203288Srnoland 252203288Srnolandtypedef struct drm_via_blitsync { 253203288Srnoland u32 sync_handle; 254203288Srnoland unsigned engine; 255203288Srnoland} drm_via_blitsync_t; 256203288Srnoland 257203288Srnoland/* - * Below,"flags" is currently unused but will be used for possible future 258203288Srnoland * extensions like kernel space bounce buffers for bad alignments and 259203288Srnoland * blit engine busy-wait polling for better latency in the absence of 260203288Srnoland * interrupts. 261203288Srnoland */ 262203288Srnoland 263203288Srnolandtypedef struct drm_via_dmablit { 264203288Srnoland u32 num_lines; 265203288Srnoland u32 line_length; 266203288Srnoland 267203288Srnoland u32 fb_addr; 268203288Srnoland u32 fb_stride; 269203288Srnoland 270203288Srnoland unsigned char *mem_addr; 271203288Srnoland u32 mem_stride; 272203288Srnoland 273203288Srnoland u32 flags; 274203288Srnoland int to_fb; 275203288Srnoland 276203288Srnoland drm_via_blitsync_t sync; 277203288Srnoland} drm_via_dmablit_t; 278203288Srnoland 279203288Srnoland#endif /* _VIA_DRM_H_ */ 280