1152909Sanholt/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2152909Sanholt * 395584Sanholt * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 495584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5112015Sanholt * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 695584Sanholt * All rights reserved. 795584Sanholt * 895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 995584Sanholt * copy of this software and associated documentation files (the "Software"), 1095584Sanholt * to deal in the Software without restriction, including without limitation 1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1395584Sanholt * Software is furnished to do so, subject to the following conditions: 1495584Sanholt * 1595584Sanholt * The above copyright notice and this permission notice (including the next 1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1795584Sanholt * Software. 1895584Sanholt * 1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2295584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2595584Sanholt * DEALINGS IN THE SOFTWARE. 2695584Sanholt * 2795584Sanholt * Authors: 2895584Sanholt * Kevin E. Martin <martin@valinux.com> 2995584Sanholt * Gareth Hughes <gareth@valinux.com> 30112015Sanholt * Keith Whitwell <keith@tungstengraphics.com> 3195584Sanholt */ 3295584Sanholt 33152909Sanholt#include <sys/cdefs.h> 34152909Sanholt__FBSDID("$FreeBSD$"); 35152909Sanholt 3695584Sanholt#ifndef __RADEON_DRM_H__ 3795584Sanholt#define __RADEON_DRM_H__ 3895584Sanholt 3995584Sanholt/* WARNING: If you change any of these defines, make sure to change the 4095584Sanholt * defines in the X server file (radeon_sarea.h) 4195584Sanholt */ 4295584Sanholt#ifndef __RADEON_SAREA_DEFINES__ 4395584Sanholt#define __RADEON_SAREA_DEFINES__ 4495584Sanholt 45112015Sanholt/* Old style state flags, required for sarea interface (1.1 and 1.2 46112015Sanholt * clears) and 1.2 drm_vertex2 ioctl. 4795584Sanholt */ 4895584Sanholt#define RADEON_UPLOAD_CONTEXT 0x00000001 4995584Sanholt#define RADEON_UPLOAD_VERTFMT 0x00000002 5095584Sanholt#define RADEON_UPLOAD_LINE 0x00000004 5195584Sanholt#define RADEON_UPLOAD_BUMPMAP 0x00000008 5295584Sanholt#define RADEON_UPLOAD_MASKS 0x00000010 5395584Sanholt#define RADEON_UPLOAD_VIEWPORT 0x00000020 5495584Sanholt#define RADEON_UPLOAD_SETUP 0x00000040 5595584Sanholt#define RADEON_UPLOAD_TCL 0x00000080 5695584Sanholt#define RADEON_UPLOAD_MISC 0x00000100 5795584Sanholt#define RADEON_UPLOAD_TEX0 0x00000200 5895584Sanholt#define RADEON_UPLOAD_TEX1 0x00000400 5995584Sanholt#define RADEON_UPLOAD_TEX2 0x00000800 6095584Sanholt#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 6195584Sanholt#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 6295584Sanholt#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 63145132Sanholt#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 6495584Sanholt#define RADEON_REQUIRE_QUIESCENCE 0x00010000 65145132Sanholt#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 66112015Sanholt#define RADEON_UPLOAD_ALL 0x003effff 67112015Sanholt#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 6895584Sanholt 69112015Sanholt/* New style per-packet identifiers for use in cmd_buffer ioctl with 70112015Sanholt * the RADEON_EMIT_PACKET command. Comments relate new packets to old 71112015Sanholt * state bits and the packet size: 72112015Sanholt */ 73145132Sanholt#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 74145132Sanholt#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 75145132Sanholt#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 76145132Sanholt#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 77145132Sanholt#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 78145132Sanholt#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 79145132Sanholt#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 80145132Sanholt#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 81145132Sanholt#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 82145132Sanholt#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 83145132Sanholt#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 84145132Sanholt#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 85145132Sanholt#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 86145132Sanholt#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 87145132Sanholt#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 88145132Sanholt#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 89145132Sanholt#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 90145132Sanholt#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 91145132Sanholt#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 92145132Sanholt#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 93145132Sanholt#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 94145132Sanholt#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 95145132Sanholt#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 96145132Sanholt#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 97145132Sanholt#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 98145132Sanholt#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 99145132Sanholt#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 100145132Sanholt#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 101145132Sanholt#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 102145132Sanholt#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 103145132Sanholt#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 104145132Sanholt#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 105145132Sanholt#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 106145132Sanholt#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 107145132Sanholt#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 108145132Sanholt#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 109145132Sanholt#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 110145132Sanholt#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 111145132Sanholt#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 112145132Sanholt#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 113145132Sanholt#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 114145132Sanholt#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 115145132Sanholt#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 116145132Sanholt#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 117145132Sanholt#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 118145132Sanholt#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 119145132Sanholt#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 120145132Sanholt#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 121145132Sanholt#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 122145132Sanholt#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 123145132Sanholt#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 124145132Sanholt#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 125145132Sanholt#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 126145132Sanholt#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 127145132Sanholt#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 128145132Sanholt#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 129145132Sanholt#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 130145132Sanholt#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 131145132Sanholt#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 132145132Sanholt#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 133145132Sanholt#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 134112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_0 61 135112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 136112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_1 63 137112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 138112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_2 65 139112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 140112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_3 67 141112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 142112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_4 69 143112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 144112015Sanholt#define R200_EMIT_PP_CUBIC_FACES_5 71 145112015Sanholt#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 146119098Sanholt#define RADEON_EMIT_PP_TEX_SIZE_0 73 147119098Sanholt#define RADEON_EMIT_PP_TEX_SIZE_1 74 148119098Sanholt#define RADEON_EMIT_PP_TEX_SIZE_2 75 149130331Sanholt#define R200_EMIT_RB3D_BLENDCOLOR 76 150145132Sanholt#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 151145132Sanholt#define RADEON_EMIT_PP_CUBIC_FACES_0 78 152145132Sanholt#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 153145132Sanholt#define RADEON_EMIT_PP_CUBIC_FACES_1 80 154145132Sanholt#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 155145132Sanholt#define RADEON_EMIT_PP_CUBIC_FACES_2 82 156145132Sanholt#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 157145132Sanholt#define R200_EMIT_PP_TRI_PERF_CNTL 84 158152909Sanholt#define R200_EMIT_PP_AFS_0 85 159152909Sanholt#define R200_EMIT_PP_AFS_1 86 160152909Sanholt#define R200_EMIT_ATF_TFACTOR 87 161152909Sanholt#define R200_EMIT_PP_TXCTLALL_0 88 162152909Sanholt#define R200_EMIT_PP_TXCTLALL_1 89 163152909Sanholt#define R200_EMIT_PP_TXCTLALL_2 90 164152909Sanholt#define R200_EMIT_PP_TXCTLALL_3 91 165152909Sanholt#define R200_EMIT_PP_TXCTLALL_4 92 166152909Sanholt#define R200_EMIT_PP_TXCTLALL_5 93 167162132Sanholt#define R200_EMIT_VAP_PVS_CNTL 94 168162132Sanholt#define RADEON_MAX_STATE_PACKETS 95 169112015Sanholt 170112015Sanholt/* Commands understood by cmd_buffer ioctl. More can be added but 171112015Sanholt * obviously these can't be removed or changed: 172112015Sanholt */ 173145132Sanholt#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 174145132Sanholt#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 175145132Sanholt#define RADEON_CMD_VECTORS 3 /* emit vector data */ 176145132Sanholt#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 177145132Sanholt#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 178145132Sanholt#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 179145132Sanholt#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 180145132Sanholt#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 181145132Sanholt * doesn't make the cpu wait, just 182145132Sanholt * the graphics hardware */ 183162132Sanholt#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 184112015Sanholt 185112015Sanholttypedef union { 186112015Sanholt int i; 187145132Sanholt struct { 188112015Sanholt unsigned char cmd_type, pad0, pad1, pad2; 189112015Sanholt } header; 190145132Sanholt struct { 191112015Sanholt unsigned char cmd_type, packet_id, pad0, pad1; 192112015Sanholt } packet; 193145132Sanholt struct { 194145132Sanholt unsigned char cmd_type, offset, stride, count; 195112015Sanholt } scalars; 196145132Sanholt struct { 197145132Sanholt unsigned char cmd_type, offset, stride, count; 198112015Sanholt } vectors; 199145132Sanholt struct { 200162132Sanholt unsigned char cmd_type, addr_lo, addr_hi, count; 201162132Sanholt } veclinear; 202162132Sanholt struct { 203145132Sanholt unsigned char cmd_type, buf_idx, pad0, pad1; 204112015Sanholt } dma; 205145132Sanholt struct { 206145132Sanholt unsigned char cmd_type, flags, pad0, pad1; 207112015Sanholt } wait; 208112015Sanholt} drm_radeon_cmd_header_t; 209112015Sanholt 210112015Sanholt#define RADEON_WAIT_2D 0x1 211112015Sanholt#define RADEON_WAIT_3D 0x2 212112015Sanholt 213148211Sanholt/* Allowed parameters for R300_CMD_PACKET3 214148211Sanholt */ 215148211Sanholt#define R300_CMD_PACKET3_CLEAR 0 216148211Sanholt#define R300_CMD_PACKET3_RAW 1 217148211Sanholt 218148211Sanholt/* Commands understood by cmd_buffer ioctl for R300. 219148211Sanholt * The interface has not been stabilized, so some of these may be removed 220148211Sanholt * and eventually reordered before stabilization. 221148211Sanholt */ 222157617Sanholt#define R300_CMD_PACKET0 1 223157617Sanholt#define R300_CMD_VPU 2 /* emit vertex program upload */ 224157617Sanholt#define R300_CMD_PACKET3 3 /* emit a packet3 */ 225157617Sanholt#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 226148211Sanholt#define R300_CMD_CP_DELAY 5 227148211Sanholt#define R300_CMD_DMA_DISCARD 6 228148211Sanholt#define R300_CMD_WAIT 7 229182080Srnoland# define R300_WAIT_2D 0x1 230182080Srnoland# define R300_WAIT_3D 0x2 231182080Srnoland/* these two defines are DOING IT WRONG - however 232182080Srnoland * we have userspace which relies on using these. 233182080Srnoland * The wait interface is backwards compat new 234182080Srnoland * code should use the NEW_WAIT defines below 235182080Srnoland * THESE ARE NOT BIT FIELDS 236182080Srnoland */ 237182080Srnoland# define R300_WAIT_2D_CLEAN 0x3 238182080Srnoland# define R300_WAIT_3D_CLEAN 0x4 239182080Srnoland 240182080Srnoland# define R300_NEW_WAIT_2D_3D 0x3 241182080Srnoland# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 242182080Srnoland# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 243182080Srnoland# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 244182080Srnoland 245157617Sanholt#define R300_CMD_SCRATCH 8 246182080Srnoland#define R300_CMD_R500FP 9 247148211Sanholt 248148211Sanholttypedef union { 249148211Sanholt unsigned int u; 250148211Sanholt struct { 251148211Sanholt unsigned char cmd_type, pad0, pad1, pad2; 252148211Sanholt } header; 253148211Sanholt struct { 254148211Sanholt unsigned char cmd_type, count, reglo, reghi; 255148211Sanholt } packet0; 256148211Sanholt struct { 257148211Sanholt unsigned char cmd_type, count, adrlo, adrhi; 258148211Sanholt } vpu; 259148211Sanholt struct { 260148211Sanholt unsigned char cmd_type, packet, pad0, pad1; 261148211Sanholt } packet3; 262148211Sanholt struct { 263148211Sanholt unsigned char cmd_type, packet; 264157617Sanholt unsigned short count; /* amount of packet2 to emit */ 265148211Sanholt } delay; 266148211Sanholt struct { 267148211Sanholt unsigned char cmd_type, buf_idx, pad0, pad1; 268148211Sanholt } dma; 269148211Sanholt struct { 270157617Sanholt unsigned char cmd_type, flags, pad0, pad1; 271148211Sanholt } wait; 272157617Sanholt struct { 273157617Sanholt unsigned char cmd_type, reg, n_bufs, flags; 274157617Sanholt } scratch; 275182080Srnoland struct { 276182080Srnoland unsigned char cmd_type, count, adrlo, adrhi_flags; 277182080Srnoland } r500fp; 278148211Sanholt} drm_r300_cmd_header_t; 279148211Sanholt 28095584Sanholt#define RADEON_FRONT 0x1 28195584Sanholt#define RADEON_BACK 0x2 28295584Sanholt#define RADEON_DEPTH 0x4 283157617Sanholt#define RADEON_STENCIL 0x8 284145132Sanholt#define RADEON_CLEAR_FASTZ 0x80000000 285145132Sanholt#define RADEON_USE_HIERZ 0x40000000 286145132Sanholt#define RADEON_USE_COMP_ZBUF 0x20000000 28795584Sanholt 288182080Srnoland#define R500FP_CONSTANT_TYPE (1 << 1) 289182080Srnoland#define R500FP_CONSTANT_CLAMP (1 << 2) 290182080Srnoland 29195584Sanholt/* Primitive types 29295584Sanholt */ 29395584Sanholt#define RADEON_POINTS 0x1 29495584Sanholt#define RADEON_LINES 0x2 29595584Sanholt#define RADEON_LINE_STRIP 0x3 29695584Sanholt#define RADEON_TRIANGLES 0x4 29795584Sanholt#define RADEON_TRIANGLE_FAN 0x5 29895584Sanholt#define RADEON_TRIANGLE_STRIP 0x6 29995584Sanholt 30095584Sanholt/* Vertex/indirect buffer size 30195584Sanholt */ 30295584Sanholt#define RADEON_BUFFER_SIZE 65536 30395584Sanholt 30495584Sanholt/* Byte offsets for indirect buffer data 30595584Sanholt */ 30695584Sanholt#define RADEON_INDEX_PRIM_OFFSET 20 30795584Sanholt 30895584Sanholt#define RADEON_SCRATCH_REG_OFFSET 32 309189499Srnoland#define R600_SCRATCH_REG_OFFSET 256 31095584Sanholt 31195584Sanholt#define RADEON_NR_SAREA_CLIPRECTS 12 31295584Sanholt 313119895Sanholt/* There are 2 heaps (local/GART). Each region within a heap is a 31495584Sanholt * minimum of 64k, and there are at most 64 of them per heap. 31595584Sanholt */ 31695584Sanholt#define RADEON_LOCAL_TEX_HEAP 0 317119895Sanholt#define RADEON_GART_TEX_HEAP 1 31895584Sanholt#define RADEON_NR_TEX_HEAPS 2 31995584Sanholt#define RADEON_NR_TEX_REGIONS 64 32095584Sanholt#define RADEON_LOG_TEX_GRANULARITY 16 32195584Sanholt 322112015Sanholt#define RADEON_MAX_TEXTURE_LEVELS 12 32395584Sanholt#define RADEON_MAX_TEXTURE_UNITS 3 32495584Sanholt 325145132Sanholt#define RADEON_MAX_SURFACES 8 326145132Sanholt 327130331Sanholt/* Blits have strict offset rules. All blit offset must be aligned on 328130331Sanholt * a 1K-byte boundary. 329130331Sanholt */ 330130331Sanholt#define RADEON_OFFSET_SHIFT 10 331130331Sanholt#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 332130331Sanholt#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 333130331Sanholt 334145132Sanholt#endif /* __RADEON_SAREA_DEFINES__ */ 33595584Sanholt 33695584Sanholttypedef struct { 33795584Sanholt unsigned int red; 33895584Sanholt unsigned int green; 33995584Sanholt unsigned int blue; 34095584Sanholt unsigned int alpha; 34195584Sanholt} radeon_color_regs_t; 34295584Sanholt 34395584Sanholttypedef struct { 34495584Sanholt /* Context state */ 345145132Sanholt unsigned int pp_misc; /* 0x1c14 */ 34695584Sanholt unsigned int pp_fog_color; 34795584Sanholt unsigned int re_solid_color; 34895584Sanholt unsigned int rb3d_blendcntl; 34995584Sanholt unsigned int rb3d_depthoffset; 35095584Sanholt unsigned int rb3d_depthpitch; 35195584Sanholt unsigned int rb3d_zstencilcntl; 35295584Sanholt 353145132Sanholt unsigned int pp_cntl; /* 0x1c38 */ 35495584Sanholt unsigned int rb3d_cntl; 35595584Sanholt unsigned int rb3d_coloroffset; 35695584Sanholt unsigned int re_width_height; 35795584Sanholt unsigned int rb3d_colorpitch; 35895584Sanholt unsigned int se_cntl; 35995584Sanholt 36095584Sanholt /* Vertex format state */ 361145132Sanholt unsigned int se_coord_fmt; /* 0x1c50 */ 36295584Sanholt 36395584Sanholt /* Line state */ 364145132Sanholt unsigned int re_line_pattern; /* 0x1cd0 */ 36595584Sanholt unsigned int re_line_state; 36695584Sanholt 367145132Sanholt unsigned int se_line_width; /* 0x1db8 */ 36895584Sanholt 36995584Sanholt /* Bumpmap state */ 370145132Sanholt unsigned int pp_lum_matrix; /* 0x1d00 */ 37195584Sanholt 372145132Sanholt unsigned int pp_rot_matrix_0; /* 0x1d58 */ 37395584Sanholt unsigned int pp_rot_matrix_1; 37495584Sanholt 37595584Sanholt /* Mask state */ 376145132Sanholt unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 37795584Sanholt unsigned int rb3d_ropcntl; 37895584Sanholt unsigned int rb3d_planemask; 37995584Sanholt 38095584Sanholt /* Viewport state */ 381145132Sanholt unsigned int se_vport_xscale; /* 0x1d98 */ 38295584Sanholt unsigned int se_vport_xoffset; 38395584Sanholt unsigned int se_vport_yscale; 38495584Sanholt unsigned int se_vport_yoffset; 38595584Sanholt unsigned int se_vport_zscale; 38695584Sanholt unsigned int se_vport_zoffset; 38795584Sanholt 38895584Sanholt /* Setup state */ 389145132Sanholt unsigned int se_cntl_status; /* 0x2140 */ 39095584Sanholt 39195584Sanholt /* Misc state */ 392145132Sanholt unsigned int re_top_left; /* 0x26c0 */ 39395584Sanholt unsigned int re_misc; 39495584Sanholt} drm_radeon_context_regs_t; 39595584Sanholt 396112015Sanholttypedef struct { 397112015Sanholt /* Zbias state */ 398145132Sanholt unsigned int se_zbias_factor; /* 0x1dac */ 399112015Sanholt unsigned int se_zbias_constant; 400112015Sanholt} drm_radeon_context2_regs_t; 401112015Sanholt 40295584Sanholt/* Setup registers for each texture unit 40395584Sanholt */ 40495584Sanholttypedef struct { 40595584Sanholt unsigned int pp_txfilter; 40695584Sanholt unsigned int pp_txformat; 40795584Sanholt unsigned int pp_txoffset; 40895584Sanholt unsigned int pp_txcblend; 40995584Sanholt unsigned int pp_txablend; 41095584Sanholt unsigned int pp_tfactor; 41195584Sanholt unsigned int pp_border_color; 41295584Sanholt} drm_radeon_texture_regs_t; 41395584Sanholt 41495584Sanholttypedef struct { 415112015Sanholt unsigned int start; 416112015Sanholt unsigned int finish; 417112015Sanholt unsigned int prim:8; 418112015Sanholt unsigned int stateidx:8; 419145132Sanholt unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 420145132Sanholt unsigned int vc_format; /* vertex format */ 421112015Sanholt} drm_radeon_prim_t; 422112015Sanholt 423112015Sanholttypedef struct { 424112015Sanholt drm_radeon_context_regs_t context; 425112015Sanholt drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 426112015Sanholt drm_radeon_context2_regs_t context2; 427112015Sanholt unsigned int dirty; 428112015Sanholt} drm_radeon_state_t; 429112015Sanholt 430112015Sanholttypedef struct { 431112015Sanholt /* The channel for communication of state information to the 432112015Sanholt * kernel on firing a vertex buffer with either of the 433112015Sanholt * obsoleted vertex/index ioctls. 43495584Sanholt */ 43595584Sanholt drm_radeon_context_regs_t context_state; 43695584Sanholt drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 43795584Sanholt unsigned int dirty; 43895584Sanholt unsigned int vertsize; 43995584Sanholt unsigned int vc_format; 44095584Sanholt 44195584Sanholt /* The current cliprects, or a subset thereof. 44295584Sanholt */ 443182080Srnoland struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 44495584Sanholt unsigned int nbox; 44595584Sanholt 44695584Sanholt /* Counters for client-side throttling of rendering clients. 44795584Sanholt */ 44895584Sanholt unsigned int last_frame; 44995584Sanholt unsigned int last_dispatch; 45095584Sanholt unsigned int last_clear; 45195584Sanholt 452182080Srnoland struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 453145132Sanholt 1]; 454119098Sanholt unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 45595584Sanholt int ctx_owner; 456145132Sanholt int pfState; /* number of 3d windows (0,1,2ormore) */ 457145132Sanholt int pfCurrentPage; /* which buffer is being displayed? */ 458145132Sanholt int crtc2_base; /* CRTC2 frame offset */ 459145132Sanholt int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 46095584Sanholt} drm_radeon_sarea_t; 46195584Sanholt 46295584Sanholt/* WARNING: If you change any of these defines, make sure to change the 46395584Sanholt * defines in the Xserver file (xf86drmRadeon.h) 464112015Sanholt * 465112015Sanholt * KW: actually it's illegal to change any of this (backwards compatibility). 46695584Sanholt */ 46795746Sanholt 468112015Sanholt/* Radeon specific ioctls 469112015Sanholt * The device specific ioctl range is 0x40 to 0x79. 470112015Sanholt */ 471145132Sanholt#define DRM_RADEON_CP_INIT 0x00 472145132Sanholt#define DRM_RADEON_CP_START 0x01 473130331Sanholt#define DRM_RADEON_CP_STOP 0x02 474130331Sanholt#define DRM_RADEON_CP_RESET 0x03 475130331Sanholt#define DRM_RADEON_CP_IDLE 0x04 476145132Sanholt#define DRM_RADEON_RESET 0x05 477130331Sanholt#define DRM_RADEON_FULLSCREEN 0x06 478145132Sanholt#define DRM_RADEON_SWAP 0x07 479145132Sanholt#define DRM_RADEON_CLEAR 0x08 480130331Sanholt#define DRM_RADEON_VERTEX 0x09 481130331Sanholt#define DRM_RADEON_INDICES 0x0A 482130331Sanholt#define DRM_RADEON_NOT_USED 483130331Sanholt#define DRM_RADEON_STIPPLE 0x0C 484130331Sanholt#define DRM_RADEON_INDIRECT 0x0D 485130331Sanholt#define DRM_RADEON_TEXTURE 0x0E 486130331Sanholt#define DRM_RADEON_VERTEX2 0x0F 487130331Sanholt#define DRM_RADEON_CMDBUF 0x10 488130331Sanholt#define DRM_RADEON_GETPARAM 0x11 489130331Sanholt#define DRM_RADEON_FLIP 0x12 490130331Sanholt#define DRM_RADEON_ALLOC 0x13 491130331Sanholt#define DRM_RADEON_FREE 0x14 492130331Sanholt#define DRM_RADEON_INIT_HEAP 0x15 493130331Sanholt#define DRM_RADEON_IRQ_EMIT 0x16 494130331Sanholt#define DRM_RADEON_IRQ_WAIT 0x17 495130331Sanholt#define DRM_RADEON_CP_RESUME 0x18 496130331Sanholt#define DRM_RADEON_SETPARAM 0x19 497145132Sanholt#define DRM_RADEON_SURF_ALLOC 0x1a 498145132Sanholt#define DRM_RADEON_SURF_FREE 0x1b 49995746Sanholt 500196470Srnoland#define DRM_RADEON_CS 0x26 501196470Srnoland 502130331Sanholt#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 503130331Sanholt#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 504130331Sanholt#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 505130331Sanholt#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 506130331Sanholt#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 507130331Sanholt#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 508130331Sanholt#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 509130331Sanholt#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 510130331Sanholt#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 511130331Sanholt#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 512130331Sanholt#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 513130331Sanholt#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 514130331Sanholt#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 515130331Sanholt#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 516130331Sanholt#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 517130331Sanholt#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 518130331Sanholt#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 519130331Sanholt#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 520130331Sanholt#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 521130331Sanholt#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 522130331Sanholt#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 523130331Sanholt#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 524130331Sanholt#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 525130331Sanholt#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 526130331Sanholt#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 527145132Sanholt#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 528145132Sanholt#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 529196470Srnoland#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 530130331Sanholt 53195584Sanholttypedef struct drm_radeon_init { 53295584Sanholt enum { 533145132Sanholt RADEON_INIT_CP = 0x01, 534112015Sanholt RADEON_CLEANUP_CP = 0x02, 535145132Sanholt RADEON_INIT_R200_CP = 0x03, 536189499Srnoland RADEON_INIT_R300_CP = 0x04, 537189499Srnoland RADEON_INIT_R600_CP = 0x05, 53895584Sanholt } func; 53995584Sanholt unsigned long sarea_priv_offset; 540152909Sanholt int is_pci; /* for overriding only */ 54195584Sanholt int cp_mode; 542119895Sanholt int gart_size; 54395584Sanholt int ring_size; 54495584Sanholt int usec_timeout; 54595584Sanholt 54695584Sanholt unsigned int fb_bpp; 54795584Sanholt unsigned int front_offset, front_pitch; 54895584Sanholt unsigned int back_offset, back_pitch; 54995584Sanholt unsigned int depth_bpp; 55095584Sanholt unsigned int depth_offset, depth_pitch; 55195584Sanholt 552152909Sanholt unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */ 553152909Sanholt unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */ 55495584Sanholt unsigned long ring_offset; 55595584Sanholt unsigned long ring_rptr_offset; 55695584Sanholt unsigned long buffers_offset; 557119895Sanholt unsigned long gart_textures_offset; 55895584Sanholt} drm_radeon_init_t; 55995584Sanholt 56095584Sanholttypedef struct drm_radeon_cp_stop { 56195584Sanholt int flush; 56295584Sanholt int idle; 56395584Sanholt} drm_radeon_cp_stop_t; 56495584Sanholt 56595584Sanholttypedef struct drm_radeon_fullscreen { 56695584Sanholt enum { 567145132Sanholt RADEON_INIT_FULLSCREEN = 0x01, 56895584Sanholt RADEON_CLEANUP_FULLSCREEN = 0x02 56995584Sanholt } func; 57095584Sanholt} drm_radeon_fullscreen_t; 57195584Sanholt 57295584Sanholt#define CLEAR_X1 0 57395584Sanholt#define CLEAR_Y1 1 57495584Sanholt#define CLEAR_X2 2 57595584Sanholt#define CLEAR_Y2 3 57695584Sanholt#define CLEAR_DEPTH 4 57795584Sanholt 57895584Sanholttypedef union drm_radeon_clear_rect { 57995584Sanholt float f[5]; 58095584Sanholt unsigned int ui[5]; 58195584Sanholt} drm_radeon_clear_rect_t; 58295584Sanholt 58395584Sanholttypedef struct drm_radeon_clear { 58495584Sanholt unsigned int flags; 58595584Sanholt unsigned int clear_color; 58695584Sanholt unsigned int clear_depth; 58795584Sanholt unsigned int color_mask; 588145132Sanholt unsigned int depth_mask; /* misnamed field: should be stencil */ 589145132Sanholt drm_radeon_clear_rect_t __user *depth_boxes; 59095584Sanholt} drm_radeon_clear_t; 59195584Sanholt 59295584Sanholttypedef struct drm_radeon_vertex { 59395584Sanholt int prim; 594145132Sanholt int idx; /* Index of vertex buffer */ 595145132Sanholt int count; /* Number of vertices in buffer */ 596145132Sanholt int discard; /* Client finished with buffer? */ 59795584Sanholt} drm_radeon_vertex_t; 59895584Sanholt 59995584Sanholttypedef struct drm_radeon_indices { 60095584Sanholt int prim; 60195584Sanholt int idx; 60295584Sanholt int start; 60395584Sanholt int end; 604145132Sanholt int discard; /* Client finished with buffer? */ 60595584Sanholt} drm_radeon_indices_t; 60695584Sanholt 607112015Sanholt/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 608112015Sanholt * - allows multiple primitives and state changes in a single ioctl 609112015Sanholt * - supports driver change to emit native primitives 610112015Sanholt */ 611112015Sanholttypedef struct drm_radeon_vertex2 { 612145132Sanholt int idx; /* Index of vertex buffer */ 613145132Sanholt int discard; /* Client finished with buffer? */ 614112015Sanholt int nr_states; 615145132Sanholt drm_radeon_state_t __user *state; 616112015Sanholt int nr_prims; 617145132Sanholt drm_radeon_prim_t __user *prim; 618112015Sanholt} drm_radeon_vertex2_t; 619112015Sanholt 620112015Sanholt/* v1.3 - obsoletes drm_radeon_vertex2 621145132Sanholt * - allows arbitarily large cliprect list 622112015Sanholt * - allows updating of tcl packet, vector and scalar state 623112015Sanholt * - allows memory-efficient description of state updates 624145132Sanholt * - allows state to be emitted without a primitive 625112015Sanholt * (for clears, ctx switches) 626112015Sanholt * - allows more than one dma buffer to be referenced per ioctl 627112015Sanholt * - supports tcl driver 628112015Sanholt * - may be extended in future versions with new cmd types, packets 629112015Sanholt */ 630112015Sanholttypedef struct drm_radeon_cmd_buffer { 631112015Sanholt int bufsz; 632145132Sanholt char __user *buf; 633112015Sanholt int nbox; 634182080Srnoland struct drm_clip_rect __user *boxes; 635112015Sanholt} drm_radeon_cmd_buffer_t; 636112015Sanholt 63795584Sanholttypedef struct drm_radeon_tex_image { 638145132Sanholt unsigned int x, y; /* Blit coordinates */ 63995584Sanholt unsigned int width, height; 640145132Sanholt const void __user *data; 64195584Sanholt} drm_radeon_tex_image_t; 64295584Sanholt 64395584Sanholttypedef struct drm_radeon_texture { 644122580Sanholt unsigned int offset; 64595584Sanholt int pitch; 64695584Sanholt int format; 647145132Sanholt int width; /* Texture image coordinates */ 64895584Sanholt int height; 649145132Sanholt drm_radeon_tex_image_t __user *image; 65095584Sanholt} drm_radeon_texture_t; 65195584Sanholt 65295584Sanholttypedef struct drm_radeon_stipple { 653145132Sanholt unsigned int __user *mask; 65495584Sanholt} drm_radeon_stipple_t; 65595584Sanholt 65695584Sanholttypedef struct drm_radeon_indirect { 65795584Sanholt int idx; 65895584Sanholt int start; 65995584Sanholt int end; 66095584Sanholt int discard; 66195584Sanholt} drm_radeon_indirect_t; 66295584Sanholt 663189499Srnoland#define RADEON_INDIRECT_DISCARD (1 << 0) 664189499Srnoland#define RADEON_INDIRECT_NOFLUSH (1 << 1) 665189499Srnoland 666157617Sanholt/* enum for card type parameters */ 667157617Sanholt#define RADEON_CARD_PCI 0 668157617Sanholt#define RADEON_CARD_AGP 1 669157617Sanholt#define RADEON_CARD_PCIE 2 670157617Sanholt 671112015Sanholt/* 1.3: An ioctl to get parameters that aren't available to the 3d 672145132Sanholt * client any other way. 673112015Sanholt */ 674145132Sanholt#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 675112015Sanholt#define RADEON_PARAM_LAST_FRAME 2 676112015Sanholt#define RADEON_PARAM_LAST_DISPATCH 3 677112015Sanholt#define RADEON_PARAM_LAST_CLEAR 4 678119098Sanholt/* Added with DRM version 1.6. */ 679112015Sanholt#define RADEON_PARAM_IRQ_NR 5 680145132Sanholt#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 681119098Sanholt/* Added with DRM version 1.8. */ 682145132Sanholt#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 683113995Sanholt#define RADEON_PARAM_STATUS_HANDLE 8 684113995Sanholt#define RADEON_PARAM_SAREA_HANDLE 9 685119895Sanholt#define RADEON_PARAM_GART_TEX_HANDLE 10 686122580Sanholt#define RADEON_PARAM_SCRATCH_OFFSET 11 687157617Sanholt#define RADEON_PARAM_CARD_TYPE 12 688182080Srnoland#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 689182080Srnoland#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 690182080Srnoland#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 691196471Srnoland#define RADEON_PARAM_DEVICE_ID 16 692196471Srnoland#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 693112015Sanholt 694112015Sanholttypedef struct drm_radeon_getparam { 695112015Sanholt int param; 696145132Sanholt void __user *value; 697112015Sanholt} drm_radeon_getparam_t; 698112015Sanholt 699112015Sanholt/* 1.6: Set up a memory manager for regions of shared memory: 700112015Sanholt */ 701119895Sanholt#define RADEON_MEM_REGION_GART 1 702119895Sanholt#define RADEON_MEM_REGION_FB 2 703112015Sanholt 704112015Sanholttypedef struct drm_radeon_mem_alloc { 705112015Sanholt int region; 706112015Sanholt int alignment; 707112015Sanholt int size; 708145132Sanholt int __user *region_offset; /* offset from start of fb or GART */ 709112015Sanholt} drm_radeon_mem_alloc_t; 710112015Sanholt 711112015Sanholttypedef struct drm_radeon_mem_free { 712112015Sanholt int region; 713112015Sanholt int region_offset; 714112015Sanholt} drm_radeon_mem_free_t; 715112015Sanholt 716112015Sanholttypedef struct drm_radeon_mem_init_heap { 717112015Sanholt int region; 718112015Sanholt int size; 719145132Sanholt int start; 720112015Sanholt} drm_radeon_mem_init_heap_t; 721112015Sanholt 722112015Sanholt/* 1.6: Userspace can request & wait on irq's: 723112015Sanholt */ 724112015Sanholttypedef struct drm_radeon_irq_emit { 725145132Sanholt int __user *irq_seq; 726112015Sanholt} drm_radeon_irq_emit_t; 727112015Sanholt 728112015Sanholttypedef struct drm_radeon_irq_wait { 729112015Sanholt int irq_seq; 730112015Sanholt} drm_radeon_irq_wait_t; 731112015Sanholt 732122580Sanholt/* 1.10: Clients tell the DRM where they think the framebuffer is located in 733122580Sanholt * the card's address space, via a new generic ioctl to set parameters 734122580Sanholt */ 735122580Sanholt 736122580Sanholttypedef struct drm_radeon_setparam { 737122580Sanholt unsigned int param; 738145132Sanholt int64_t value; 739122580Sanholt} drm_radeon_setparam_t; 740122580Sanholt 741145132Sanholt#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 742145132Sanholt#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 743157617Sanholt#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 744122580Sanholt 745157617Sanholt#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 746182080Srnoland#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 747182080Srnoland#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 748145132Sanholt/* 1.14: Clients can allocate/free a surface 749145132Sanholt */ 750145132Sanholttypedef struct drm_radeon_surface_alloc { 751145132Sanholt unsigned int address; 752145132Sanholt unsigned int size; 753145132Sanholt unsigned int flags; 754145132Sanholt} drm_radeon_surface_alloc_t; 755122580Sanholt 756145132Sanholttypedef struct drm_radeon_surface_free { 757145132Sanholt unsigned int address; 758145132Sanholt} drm_radeon_surface_free_t; 759145132Sanholt 760182080Srnoland#define DRM_RADEON_VBLANK_CRTC1 1 761182080Srnoland#define DRM_RADEON_VBLANK_CRTC2 2 762145132Sanholt 763196470Srnoland/* New interface which obsolete all previous interface. 764196470Srnoland */ 765196470Srnoland#define RADEON_CHUNK_ID_RELOCS 0x01 766196470Srnoland#define RADEON_CHUNK_ID_IB 0x02 767196470Srnoland#define RADEON_CHUNK_ID_OLD 0xff 768196470Srnoland 769196470Srnolandstruct drm_radeon_cs_chunk { 770196470Srnoland uint32_t chunk_id; 771196470Srnoland uint32_t length_dw; 772196470Srnoland uint64_t chunk_data; 773196470Srnoland}; 774196470Srnoland 775196470Srnolandstruct drm_radeon_cs { 776196470Srnoland uint32_t num_chunks; 777196470Srnoland uint32_t cs_id; 778196470Srnoland uint64_t chunks; /* this points to uint64_t * which point to 779196470Srnoland cs chunks */ 780196470Srnoland}; 781196470Srnoland 78295584Sanholt#endif 783