195584Sanholt/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 2152909Sanholt * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com 3152909Sanholt */ 4139749Simp/*- 595584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 695584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 795584Sanholt * All rights reserved. 895584Sanholt * 995584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 1095584Sanholt * copy of this software and associated documentation files (the "Software"), 1195584Sanholt * to deal in the Software without restriction, including without limitation 1295584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1395584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1495584Sanholt * Software is furnished to do so, subject to the following conditions: 1595584Sanholt * 1695584Sanholt * The above copyright notice and this permission notice (including the next 1795584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1895584Sanholt * Software. 1995584Sanholt * 2095584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2195584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2295584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2395584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2495584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2595584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2695584Sanholt * DEALINGS IN THE SOFTWARE. 2795584Sanholt * 2895584Sanholt * Authors: 2995584Sanholt * Rickard E. (Rik) Faith <faith@valinux.com> 3095584Sanholt * Kevin E. Martin <martin@valinux.com> 3195584Sanholt * Gareth Hughes <gareth@valinux.com> 32145132Sanholt * Michel D���zer <daenzerm@student.ethz.ch> 3395584Sanholt */ 3495584Sanholt 35152909Sanholt#include <sys/cdefs.h> 36152909Sanholt__FBSDID("$FreeBSD$"); 37152909Sanholt 3895584Sanholt#ifndef __R128_DRV_H__ 3995584Sanholt#define __R128_DRV_H__ 4095584Sanholt 41145132Sanholt/* General customization: 42145132Sanholt */ 43145132Sanholt#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 44145132Sanholt 45145132Sanholt#define DRIVER_NAME "r128" 46145132Sanholt#define DRIVER_DESC "ATI Rage 128" 47145132Sanholt#define DRIVER_DATE "20030725" 48145132Sanholt 49145132Sanholt/* Interface history: 50145132Sanholt * 51145132Sanholt * ?? - ?? 52145132Sanholt * 2.4 - Add support for ycbcr textures (no new ioctls) 53145132Sanholt * 2.5 - Add FLIP ioctl, disable FULLSCREEN. 54145132Sanholt */ 55145132Sanholt#define DRIVER_MAJOR 2 56145132Sanholt#define DRIVER_MINOR 5 57145132Sanholt#define DRIVER_PATCHLEVEL 0 58145132Sanholt 59121447Sanholt#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) 6095584Sanholt 6195584Sanholttypedef struct drm_r128_freelist { 62145132Sanholt unsigned int age; 63182080Srnoland struct drm_buf *buf; 64145132Sanholt struct drm_r128_freelist *next; 65145132Sanholt struct drm_r128_freelist *prev; 6695584Sanholt} drm_r128_freelist_t; 6795584Sanholt 6895584Sanholttypedef struct drm_r128_ring_buffer { 6995584Sanholt u32 *start; 7095584Sanholt u32 *end; 7195584Sanholt int size; 7295584Sanholt int size_l2qw; 7395584Sanholt 7495584Sanholt u32 tail; 7595584Sanholt u32 tail_mask; 7695584Sanholt int space; 7795584Sanholt 7895584Sanholt int high_mark; 7995584Sanholt} drm_r128_ring_buffer_t; 8095584Sanholt 8195584Sanholttypedef struct drm_r128_private { 8295584Sanholt drm_r128_ring_buffer_t ring; 8395584Sanholt drm_r128_sarea_t *sarea_priv; 8495584Sanholt 8595584Sanholt int cce_mode; 8695584Sanholt int cce_fifo_size; 8795584Sanholt int cce_running; 8895584Sanholt 89145132Sanholt drm_r128_freelist_t *head; 90145132Sanholt drm_r128_freelist_t *tail; 9195584Sanholt 9295584Sanholt int usec_timeout; 9395584Sanholt int is_pci; 9495584Sanholt unsigned long cce_buffers_offset; 9595584Sanholt 9695584Sanholt atomic_t idle_count; 9795584Sanholt 9895584Sanholt int page_flipping; 9995584Sanholt int current_page; 10095584Sanholt u32 crtc_offset; 10195584Sanholt u32 crtc_offset_cntl; 10295584Sanholt 103182080Srnoland atomic_t vbl_received; 104182080Srnoland 10595584Sanholt u32 color_fmt; 10695584Sanholt unsigned int front_offset; 10795584Sanholt unsigned int front_pitch; 10895584Sanholt unsigned int back_offset; 10995584Sanholt unsigned int back_pitch; 11095584Sanholt 11195584Sanholt u32 depth_fmt; 11295584Sanholt unsigned int depth_offset; 11395584Sanholt unsigned int depth_pitch; 11495584Sanholt unsigned int span_offset; 11595584Sanholt 11695584Sanholt u32 front_pitch_offset_c; 11795584Sanholt u32 back_pitch_offset_c; 11895584Sanholt u32 depth_pitch_offset_c; 11995584Sanholt u32 span_pitch_offset_c; 12095584Sanholt 121112015Sanholt drm_local_map_t *sarea; 122112015Sanholt drm_local_map_t *mmio; 123112015Sanholt drm_local_map_t *cce_ring; 124112015Sanholt drm_local_map_t *ring_rptr; 125112015Sanholt drm_local_map_t *agp_textures; 126182080Srnoland struct drm_ati_pcigart_info gart_info; 12795584Sanholt} drm_r128_private_t; 12895584Sanholt 12995584Sanholttypedef struct drm_r128_buf_priv { 13095584Sanholt u32 age; 13195584Sanholt int prim; 13295584Sanholt int discard; 13395584Sanholt int dispatched; 134145132Sanholt drm_r128_freelist_t *list_entry; 13595584Sanholt} drm_r128_buf_priv_t; 13695584Sanholt 137182080Srnolandextern struct drm_ioctl_desc r128_ioctls[]; 138152909Sanholtextern int r128_max_ioctl; 139152909Sanholt 14095584Sanholt /* r128_cce.c */ 141182080Srnolandextern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 142182080Srnolandextern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 143182080Srnolandextern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 144182080Srnolandextern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 145182080Srnolandextern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 146182080Srnolandextern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 147182080Srnolandextern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 148182080Srnolandextern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 14995584Sanholt 150182080Srnolandextern void r128_freelist_reset(struct drm_device * dev); 15195584Sanholt 152145132Sanholtextern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); 15395584Sanholt 154145132Sanholtextern int r128_do_cce_idle(drm_r128_private_t * dev_priv); 155182080Srnolandextern int r128_do_cleanup_cce(struct drm_device * dev); 15695584Sanholt 157182080Srnolandextern int r128_enable_vblank(struct drm_device *dev, int crtc); 158182080Srnolandextern void r128_disable_vblank(struct drm_device *dev, int crtc); 159182080Srnolandextern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc); 160145132Sanholtextern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); 161182080Srnolandextern void r128_driver_irq_preinstall(struct drm_device * dev); 162182080Srnolandextern int r128_driver_irq_postinstall(struct drm_device * dev); 163182080Srnolandextern void r128_driver_irq_uninstall(struct drm_device * dev); 164182080Srnolandextern void r128_driver_lastclose(struct drm_device * dev); 165189130Srnolandextern int r128_driver_load(struct drm_device * dev, unsigned long flags); 166182080Srnolandextern void r128_driver_preclose(struct drm_device * dev, 167182080Srnoland struct drm_file *file_priv); 16895584Sanholt 169152909Sanholtextern long r128_compat_ioctl(struct file *filp, unsigned int cmd, 170152909Sanholt unsigned long arg); 171152909Sanholt 17295584Sanholt/* Register definitions, register access macros and drmAddMap constants 17395584Sanholt * for Rage 128 kernel driver. 17495584Sanholt */ 17595584Sanholt 17695584Sanholt#define R128_AUX_SC_CNTL 0x1660 17795584Sanholt# define R128_AUX1_SC_EN (1 << 0) 17895584Sanholt# define R128_AUX1_SC_MODE_OR (0 << 1) 17995584Sanholt# define R128_AUX1_SC_MODE_NAND (1 << 1) 18095584Sanholt# define R128_AUX2_SC_EN (1 << 2) 18195584Sanholt# define R128_AUX2_SC_MODE_OR (0 << 3) 18295584Sanholt# define R128_AUX2_SC_MODE_NAND (1 << 3) 18395584Sanholt# define R128_AUX3_SC_EN (1 << 4) 18495584Sanholt# define R128_AUX3_SC_MODE_OR (0 << 5) 18595584Sanholt# define R128_AUX3_SC_MODE_NAND (1 << 5) 18695584Sanholt#define R128_AUX1_SC_LEFT 0x1664 18795584Sanholt#define R128_AUX1_SC_RIGHT 0x1668 18895584Sanholt#define R128_AUX1_SC_TOP 0x166c 18995584Sanholt#define R128_AUX1_SC_BOTTOM 0x1670 19095584Sanholt#define R128_AUX2_SC_LEFT 0x1674 19195584Sanholt#define R128_AUX2_SC_RIGHT 0x1678 19295584Sanholt#define R128_AUX2_SC_TOP 0x167c 19395584Sanholt#define R128_AUX2_SC_BOTTOM 0x1680 19495584Sanholt#define R128_AUX3_SC_LEFT 0x1684 19595584Sanholt#define R128_AUX3_SC_RIGHT 0x1688 19695584Sanholt#define R128_AUX3_SC_TOP 0x168c 19795584Sanholt#define R128_AUX3_SC_BOTTOM 0x1690 19895584Sanholt 19995584Sanholt#define R128_BRUSH_DATA0 0x1480 20095584Sanholt#define R128_BUS_CNTL 0x0030 20195584Sanholt# define R128_BUS_MASTER_DIS (1 << 6) 20295584Sanholt 20395584Sanholt#define R128_CLOCK_CNTL_INDEX 0x0008 20495584Sanholt#define R128_CLOCK_CNTL_DATA 0x000c 20595584Sanholt# define R128_PLL_WR_EN (1 << 7) 20695584Sanholt#define R128_CONSTANT_COLOR_C 0x1d34 20795584Sanholt#define R128_CRTC_OFFSET 0x0224 20895584Sanholt#define R128_CRTC_OFFSET_CNTL 0x0228 20995584Sanholt# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) 21095584Sanholt 21195584Sanholt#define R128_DP_GUI_MASTER_CNTL 0x146c 21295584Sanholt# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 21395584Sanholt# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 21495584Sanholt# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 21595584Sanholt# define R128_GMC_BRUSH_NONE (15 << 4) 21695584Sanholt# define R128_GMC_DST_16BPP (4 << 8) 21795584Sanholt# define R128_GMC_DST_24BPP (5 << 8) 21895584Sanholt# define R128_GMC_DST_32BPP (6 << 8) 21995584Sanholt# define R128_GMC_DST_DATATYPE_SHIFT 8 22095584Sanholt# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 22195584Sanholt# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 22295584Sanholt# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 22395584Sanholt# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 22495584Sanholt# define R128_GMC_AUX_CLIP_DIS (1 << 29) 22595584Sanholt# define R128_GMC_WR_MSK_DIS (1 << 30) 22695584Sanholt# define R128_ROP3_S 0x00cc0000 22795584Sanholt# define R128_ROP3_P 0x00f00000 22895584Sanholt#define R128_DP_WRITE_MASK 0x16cc 22995584Sanholt#define R128_DST_PITCH_OFFSET_C 0x1c80 23095584Sanholt# define R128_DST_TILE (1 << 31) 23195584Sanholt 232112015Sanholt#define R128_GEN_INT_CNTL 0x0040 233112015Sanholt# define R128_CRTC_VBLANK_INT_EN (1 << 0) 234112015Sanholt#define R128_GEN_INT_STATUS 0x0044 235112015Sanholt# define R128_CRTC_VBLANK_INT (1 << 0) 236112015Sanholt# define R128_CRTC_VBLANK_INT_AK (1 << 0) 23795584Sanholt#define R128_GEN_RESET_CNTL 0x00f0 23895584Sanholt# define R128_SOFT_RESET_GUI (1 << 0) 23995584Sanholt 24095584Sanholt#define R128_GUI_SCRATCH_REG0 0x15e0 24195584Sanholt#define R128_GUI_SCRATCH_REG1 0x15e4 24295584Sanholt#define R128_GUI_SCRATCH_REG2 0x15e8 24395584Sanholt#define R128_GUI_SCRATCH_REG3 0x15ec 24495584Sanholt#define R128_GUI_SCRATCH_REG4 0x15f0 24595584Sanholt#define R128_GUI_SCRATCH_REG5 0x15f4 24695584Sanholt 24795584Sanholt#define R128_GUI_STAT 0x1740 24895584Sanholt# define R128_GUI_FIFOCNT_MASK 0x0fff 24995584Sanholt# define R128_GUI_ACTIVE (1 << 31) 25095584Sanholt 25195584Sanholt#define R128_MCLK_CNTL 0x000f 25295584Sanholt# define R128_FORCE_GCP (1 << 16) 25395584Sanholt# define R128_FORCE_PIPE3D_CP (1 << 17) 25495584Sanholt# define R128_FORCE_RCP (1 << 18) 25595584Sanholt 25695584Sanholt#define R128_PC_GUI_CTLSTAT 0x1748 25795584Sanholt#define R128_PC_NGUI_CTLSTAT 0x0184 25895584Sanholt# define R128_PC_FLUSH_GUI (3 << 0) 25995584Sanholt# define R128_PC_RI_GUI (1 << 2) 26095584Sanholt# define R128_PC_FLUSH_ALL 0x00ff 26195584Sanholt# define R128_PC_BUSY (1 << 31) 26295584Sanholt 26395584Sanholt#define R128_PCI_GART_PAGE 0x017c 26495584Sanholt#define R128_PRIM_TEX_CNTL_C 0x1cb0 26595584Sanholt 26695584Sanholt#define R128_SCALE_3D_CNTL 0x1a00 26795584Sanholt#define R128_SEC_TEX_CNTL_C 0x1d00 26895584Sanholt#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 26995584Sanholt#define R128_SETUP_CNTL 0x1bc4 27095584Sanholt#define R128_STEN_REF_MASK_C 0x1d40 27195584Sanholt 27295584Sanholt#define R128_TEX_CNTL_C 0x1c9c 27395584Sanholt# define R128_TEX_CACHE_FLUSH (1 << 23) 27495584Sanholt 27595584Sanholt#define R128_WAIT_UNTIL 0x1720 27695584Sanholt# define R128_EVENT_CRTC_OFFSET (1 << 0) 27795584Sanholt#define R128_WINDOW_XY_OFFSET 0x1bcc 27895584Sanholt 27995584Sanholt/* CCE registers 28095584Sanholt */ 28195584Sanholt#define R128_PM4_BUFFER_OFFSET 0x0700 28295584Sanholt#define R128_PM4_BUFFER_CNTL 0x0704 28395584Sanholt# define R128_PM4_MASK (15 << 28) 28495584Sanholt# define R128_PM4_NONPM4 (0 << 28) 28595584Sanholt# define R128_PM4_192PIO (1 << 28) 28695584Sanholt# define R128_PM4_192BM (2 << 28) 28795584Sanholt# define R128_PM4_128PIO_64INDBM (3 << 28) 28895584Sanholt# define R128_PM4_128BM_64INDBM (4 << 28) 28995584Sanholt# define R128_PM4_64PIO_128INDBM (5 << 28) 29095584Sanholt# define R128_PM4_64BM_128INDBM (6 << 28) 29195584Sanholt# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 29295584Sanholt# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) 29395584Sanholt# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) 294121447Sanholt# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) 29595584Sanholt 29695584Sanholt#define R128_PM4_BUFFER_WM_CNTL 0x0708 29795584Sanholt# define R128_WMA_SHIFT 0 29895584Sanholt# define R128_WMB_SHIFT 8 29995584Sanholt# define R128_WMC_SHIFT 16 30095584Sanholt# define R128_WB_WM_SHIFT 24 30195584Sanholt 30295584Sanholt#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 30395584Sanholt#define R128_PM4_BUFFER_DL_RPTR 0x0710 30495584Sanholt#define R128_PM4_BUFFER_DL_WPTR 0x0714 30595584Sanholt# define R128_PM4_BUFFER_DL_DONE (1 << 31) 30695584Sanholt 30795584Sanholt#define R128_PM4_VC_FPU_SETUP 0x071c 30895584Sanholt 30995584Sanholt#define R128_PM4_IW_INDOFF 0x0738 31095584Sanholt#define R128_PM4_IW_INDSIZE 0x073c 31195584Sanholt 31295584Sanholt#define R128_PM4_STAT 0x07b8 31395584Sanholt# define R128_PM4_FIFOCNT_MASK 0x0fff 31495584Sanholt# define R128_PM4_BUSY (1 << 16) 31595584Sanholt# define R128_PM4_GUI_ACTIVE (1 << 31) 31695584Sanholt 31795584Sanholt#define R128_PM4_MICROCODE_ADDR 0x07d4 31895584Sanholt#define R128_PM4_MICROCODE_RADDR 0x07d8 31995584Sanholt#define R128_PM4_MICROCODE_DATAH 0x07dc 32095584Sanholt#define R128_PM4_MICROCODE_DATAL 0x07e0 32195584Sanholt 32295584Sanholt#define R128_PM4_BUFFER_ADDR 0x07f0 32395584Sanholt#define R128_PM4_MICRO_CNTL 0x07fc 32495584Sanholt# define R128_PM4_MICRO_FREERUN (1 << 30) 32595584Sanholt 32695584Sanholt#define R128_PM4_FIFO_DATA_EVEN 0x1000 32795584Sanholt#define R128_PM4_FIFO_DATA_ODD 0x1004 32895584Sanholt 32995584Sanholt/* CCE command packets 33095584Sanholt */ 33195584Sanholt#define R128_CCE_PACKET0 0x00000000 33295584Sanholt#define R128_CCE_PACKET1 0x40000000 33395584Sanholt#define R128_CCE_PACKET2 0x80000000 33495584Sanholt#define R128_CCE_PACKET3 0xC0000000 33595584Sanholt# define R128_CNTL_HOSTDATA_BLT 0x00009400 33695584Sanholt# define R128_CNTL_PAINT_MULTI 0x00009A00 33795584Sanholt# define R128_CNTL_BITBLT_MULTI 0x00009B00 33895584Sanholt# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 33995584Sanholt 34095584Sanholt#define R128_CCE_PACKET_MASK 0xC0000000 34195584Sanholt#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 34295584Sanholt#define R128_CCE_PACKET0_REG_MASK 0x000007ff 34395584Sanholt#define R128_CCE_PACKET1_REG0_MASK 0x000007ff 34495584Sanholt#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 34595584Sanholt 34695584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 34795584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 34895584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 34995584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 35095584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 35195584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 35295584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 35395584Sanholt#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 35495584Sanholt#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 35595584Sanholt#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 35695584Sanholt#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 35795584Sanholt#define R128_CCE_VC_CNTL_NUM_SHIFT 16 35895584Sanholt 359119098Sanholt#define R128_DATATYPE_VQ 0 360119098Sanholt#define R128_DATATYPE_CI4 1 36195584Sanholt#define R128_DATATYPE_CI8 2 36295584Sanholt#define R128_DATATYPE_ARGB1555 3 36395584Sanholt#define R128_DATATYPE_RGB565 4 36495584Sanholt#define R128_DATATYPE_RGB888 5 36595584Sanholt#define R128_DATATYPE_ARGB8888 6 36695584Sanholt#define R128_DATATYPE_RGB332 7 367119098Sanholt#define R128_DATATYPE_Y8 8 36895584Sanholt#define R128_DATATYPE_RGB8 9 369119098Sanholt#define R128_DATATYPE_CI16 10 370119098Sanholt#define R128_DATATYPE_YVYU422 11 371119098Sanholt#define R128_DATATYPE_VYUY422 12 372119098Sanholt#define R128_DATATYPE_AYUV444 14 37395584Sanholt#define R128_DATATYPE_ARGB4444 15 37495584Sanholt 37595584Sanholt/* Constants */ 37695584Sanholt#define R128_AGP_OFFSET 0x02000000 37795584Sanholt 37895584Sanholt#define R128_WATERMARK_L 16 37995584Sanholt#define R128_WATERMARK_M 8 38095584Sanholt#define R128_WATERMARK_N 8 38195584Sanholt#define R128_WATERMARK_K 128 38295584Sanholt 38395584Sanholt#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 38495584Sanholt 38595584Sanholt#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 38695584Sanholt#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 38795584Sanholt#define R128_MAX_VB_AGE 0x7fffffff 38895584Sanholt#define R128_MAX_VB_VERTS (0xffff) 38995584Sanholt 39095584Sanholt#define R128_RING_HIGH_MARK 128 39195584Sanholt 39295584Sanholt#define R128_PERFORMANCE_BOXES 0 39395584Sanholt 394182080Srnoland#define R128_PCIGART_TABLE_SIZE 32768 395182080Srnoland 396112015Sanholt#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 397112015Sanholt#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 398112015Sanholt#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 399112015Sanholt#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 40095584Sanholt 40195584Sanholt#define R128_WRITE_PLL(addr,val) \ 40295584Sanholtdo { \ 40395584Sanholt R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ 40495584Sanholt ((addr) & 0x1f) | R128_PLL_WR_EN); \ 40595584Sanholt R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 40695584Sanholt} while (0) 40795584Sanholt 40895584Sanholt#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 40995584Sanholt ((n) << 16) | ((reg) >> 2)) 41095584Sanholt#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 41195584Sanholt (((reg1) >> 2) << 11) | ((reg0) >> 2)) 41295584Sanholt#define CCE_PACKET2() (R128_CCE_PACKET2) 41395584Sanholt#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 41495584Sanholt (pkt) | ((n) << 16)) 41595584Sanholt 416145132Sanholtstatic __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) 417121447Sanholt{ 418121447Sanholt drm_r128_ring_buffer_t *ring = &dev_priv->ring; 419145132Sanholt ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); 420145132Sanholt if (ring->space <= 0) 421121447Sanholt ring->space += ring->size; 422121447Sanholt} 423121447Sanholt 42495584Sanholt/* ================================================================ 42595584Sanholt * Misc helper macros 42695584Sanholt */ 42795584Sanholt 42895584Sanholt#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 42995584Sanholtdo { \ 43095584Sanholt drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 43195584Sanholt if ( ring->space < ring->high_mark ) { \ 43295584Sanholt for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ 433121447Sanholt r128_update_ring_snapshot( dev_priv ); \ 43495584Sanholt if ( ring->space >= ring->high_mark ) \ 43595584Sanholt goto __ring_space_done; \ 436112015Sanholt DRM_UDELAY(1); \ 43795584Sanholt } \ 43895584Sanholt DRM_ERROR( "ring space check failed!\n" ); \ 439182080Srnoland return -EBUSY; \ 44095584Sanholt } \ 44195584Sanholt __ring_space_done: \ 44297683Sanholt ; \ 44395584Sanholt} while (0) 44495584Sanholt 44595584Sanholt#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 44695584Sanholtdo { \ 44795584Sanholt drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 44895584Sanholt if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ 44995584Sanholt int __ret = r128_do_cce_idle( dev_priv ); \ 450112015Sanholt if ( __ret ) return __ret; \ 45195584Sanholt sarea_priv->last_dispatch = 0; \ 45295584Sanholt r128_freelist_reset( dev ); \ 45395584Sanholt } \ 45495584Sanholt} while (0) 45595584Sanholt 45695584Sanholt#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ 45795584Sanholt OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ 45895584Sanholt OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 45995584Sanholt} while (0) 46095584Sanholt 46195584Sanholt/* ================================================================ 46295584Sanholt * Ring control 46395584Sanholt */ 46495584Sanholt 46595584Sanholt#define R128_VERBOSE 0 46695584Sanholt 46795584Sanholt#define RING_LOCALS \ 468121447Sanholt int write, _nr; unsigned int tail_mask; volatile u32 *ring; 46995584Sanholt 47095584Sanholt#define BEGIN_RING( n ) do { \ 47195584Sanholt if ( R128_VERBOSE ) { \ 472182080Srnoland DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 47395584Sanholt } \ 47495584Sanholt if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 475121447Sanholt COMMIT_RING(); \ 47695584Sanholt r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 47795584Sanholt } \ 478121447Sanholt _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 47995584Sanholt ring = dev_priv->ring.start; \ 48095584Sanholt write = dev_priv->ring.tail; \ 48195584Sanholt tail_mask = dev_priv->ring.tail_mask; \ 48295584Sanholt} while (0) 48395584Sanholt 48495584Sanholt/* You can set this to zero if you want. If the card locks up, you'll 48595584Sanholt * need to keep this set. It works around a bug in early revs of the 48695584Sanholt * Rage 128 chipset, where the CCE would read 32 dwords past the end of 48795584Sanholt * the ring buffer before wrapping around. 48895584Sanholt */ 48995584Sanholt#define R128_BROKEN_CCE 1 49095584Sanholt 49195584Sanholt#define ADVANCE_RING() do { \ 49295584Sanholt if ( R128_VERBOSE ) { \ 49395584Sanholt DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 49495584Sanholt write, dev_priv->ring.tail ); \ 49595584Sanholt } \ 49695584Sanholt if ( R128_BROKEN_CCE && write < 32 ) { \ 49795584Sanholt memcpy( dev_priv->ring.end, \ 49895584Sanholt dev_priv->ring.start, \ 49995584Sanholt write * sizeof(u32) ); \ 50095584Sanholt } \ 501121447Sanholt if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ 502182080Srnoland DRM_ERROR( \ 503121447Sanholt "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 504121447Sanholt ((dev_priv->ring.tail + _nr) & tail_mask), \ 505121447Sanholt write, __LINE__); \ 506121447Sanholt } else \ 507121447Sanholt dev_priv->ring.tail = write; \ 50895584Sanholt} while (0) 50995584Sanholt 510121447Sanholt#define COMMIT_RING() do { \ 511121447Sanholt if ( R128_VERBOSE ) { \ 512121447Sanholt DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ 513121447Sanholt dev_priv->ring.tail ); \ 514121447Sanholt } \ 515121447Sanholt DRM_MEMORYBARRIER(); \ 516121447Sanholt R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ 517121447Sanholt R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ 518121447Sanholt} while (0) 519121447Sanholt 52095584Sanholt#define OUT_RING( x ) do { \ 52195584Sanholt if ( R128_VERBOSE ) { \ 52295584Sanholt DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 52395584Sanholt (unsigned int)(x), write ); \ 52495584Sanholt } \ 52595584Sanholt ring[write++] = cpu_to_le32( x ); \ 52695584Sanholt write &= tail_mask; \ 52795584Sanholt} while (0) 52895584Sanholt 529145132Sanholt#endif /* __R128_DRV_H__ */ 530