drm.h revision 122580
1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 * 35 * $FreeBSD: head/sys/dev/drm/drm.h 122580 2003-11-12 20:56:30Z anholt $ 36 */ 37 38 39#ifndef _DRM_H_ 40#define _DRM_H_ 41 42#if defined(__linux__) 43#include <linux/config.h> 44#include <asm/ioctl.h> /* For _IO* macros */ 45#define DRM_IOCTL_NR(n) _IOC_NR(n) 46#define DRM_IOC_VOID _IOC_NONE 47#define DRM_IOC_READ _IOC_READ 48#define DRM_IOC_WRITE _IOC_WRITE 49#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 50#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 51#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) 52#if defined(__FreeBSD__) && defined(IN_MODULE) 53/* Prevent name collision when including sys/ioccom.h */ 54#undef ioctl 55#include <sys/ioccom.h> 56#define ioctl(a,b,c) xf86ioctl(a,b,c) 57#else 58#include <sys/ioccom.h> 59#endif /* __FreeBSD__ && xf86ioctl */ 60#define DRM_IOCTL_NR(n) ((n) & 0xff) 61#define DRM_IOC_VOID IOC_VOID 62#define DRM_IOC_READ IOC_OUT 63#define DRM_IOC_WRITE IOC_IN 64#define DRM_IOC_READWRITE IOC_INOUT 65#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 66#endif 67 68#define XFREE86_VERSION(major,minor,patch,snap) \ 69 ((major << 16) | (minor << 8) | patch) 70 71#ifndef CONFIG_XFREE86_VERSION 72#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) 73#endif 74 75#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 76#define DRM_PROC_DEVICES "/proc/devices" 77#define DRM_PROC_MISC "/proc/misc" 78#define DRM_PROC_DRM "/proc/drm" 79#define DRM_DEV_DRM "/dev/drm" 80#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) 81#define DRM_DEV_UID 0 82#define DRM_DEV_GID 0 83#endif 84 85#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) 86#ifdef __OpenBSD__ 87#define DRM_MAJOR 81 88#endif 89#if defined(__linux__) || defined(__NetBSD__) 90#define DRM_MAJOR 226 91#endif 92#define DRM_MAX_MINOR 15 93#endif 94#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 95#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 96#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 97#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 98 99#define _DRM_LOCK_HELD 0x80000000 /**< Hardware lock is held */ 100#define _DRM_LOCK_CONT 0x40000000 /**< Hardware lock is contended */ 101#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 102#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 103#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 104 105 106typedef unsigned long drm_handle_t; 107typedef unsigned int drm_context_t; 108typedef unsigned int drm_drawable_t; 109typedef unsigned int drm_magic_t; 110 111 112/** 113 * Cliprect. 114 * 115 * \warning: If you change this structure, make sure you change 116 * XF86DRIClipRectRec in the server as well 117 * 118 * \note KW: Actually it's illegal to change either for 119 * backwards-compatibility reasons. 120 */ 121typedef struct drm_clip_rect { 122 unsigned short x1; 123 unsigned short y1; 124 unsigned short x2; 125 unsigned short y2; 126} drm_clip_rect_t; 127 128 129/** 130 * Texture region, 131 */ 132typedef struct drm_tex_region { 133 unsigned char next; 134 unsigned char prev; 135 unsigned char in_use; 136 unsigned char padding; 137 unsigned int age; 138} drm_tex_region_t; 139 140 141/** 142 * DRM_IOCTL_VERSION ioctl argument type. 143 * 144 * \sa drmGetVersion(). 145 */ 146typedef struct drm_version { 147 int version_major; /**< Major version */ 148 int version_minor; /**< Minor version */ 149 int version_patchlevel;/**< Patch level */ 150 size_t name_len; /**< Length of name buffer */ 151 char *name; /**< Name of driver */ 152 size_t date_len; /**< Length of date buffer */ 153 char *date; /**< User-space buffer to hold date */ 154 size_t desc_len; /**< Length of desc buffer */ 155 char *desc; /**< User-space buffer to hold desc */ 156} drm_version_t; 157 158 159/** 160 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 161 * 162 * \sa drmGetBusid() and drmSetBusId(). 163 */ 164typedef struct drm_unique { 165 size_t unique_len; /**< Length of unique */ 166 char *unique; /**< Unique name for driver instantiation */ 167} drm_unique_t; 168 169 170typedef struct drm_list { 171 int count; /**< Length of user-space structures */ 172 drm_version_t *version; 173} drm_list_t; 174 175 176typedef struct drm_block { 177 int unused; 178} drm_block_t; 179 180 181/** 182 * DRM_IOCTL_CONTROL ioctl argument type. 183 * 184 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 185 */ 186typedef struct drm_control { 187 enum { 188 DRM_ADD_COMMAND, 189 DRM_RM_COMMAND, 190 DRM_INST_HANDLER, 191 DRM_UNINST_HANDLER 192 } func; 193 int irq; 194} drm_control_t; 195 196 197/** 198 * Type of memory to map. 199 */ 200typedef enum drm_map_type { 201 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 202 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 203 _DRM_SHM = 2, /**< shared, cached */ 204 _DRM_AGP = 3, /**< AGP/GART */ 205 _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */ 206} drm_map_type_t; 207 208 209/** 210 * Memory mapping flags. 211 */ 212typedef enum drm_map_flags { 213 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 214 _DRM_READ_ONLY = 0x02, 215 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 216 _DRM_KERNEL = 0x08, /**< kernel requires access */ 217 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 218 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 219 _DRM_REMOVABLE = 0x40 /**< Removable mapping */ 220} drm_map_flags_t; 221 222 223typedef struct drm_ctx_priv_map { 224 unsigned int ctx_id; /**< Context requesting private mapping */ 225 void *handle; /**< Handle of map */ 226} drm_ctx_priv_map_t; 227 228 229/** 230 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 231 * argument type. 232 * 233 * \sa drmAddMap(). 234 */ 235typedef struct drm_map { 236 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 237 unsigned long size; /**< Requested physical size (bytes) */ 238 drm_map_type_t type; /**< Type of memory to map */ 239 drm_map_flags_t flags; /**< Flags */ 240 void *handle; /**< User-space: "Handle" to pass to mmap() */ 241 /**< Kernel-space: kernel-virtual address */ 242 int mtrr; /**< MTRR slot used */ 243 /* Private data */ 244} drm_map_t; 245 246 247/** 248 * DRM_IOCTL_GET_CLIENT ioctl argument type. 249 */ 250typedef struct drm_client { 251 int idx; /**< Which client desired? */ 252 int auth; /**< Is client authenticated? */ 253 unsigned long pid; /**< Process ID */ 254 unsigned long uid; /**< User ID */ 255 unsigned long magic; /**< Magic */ 256 unsigned long iocs; /**< Ioctl count */ 257} drm_client_t; 258 259 260typedef enum { 261 _DRM_STAT_LOCK, 262 _DRM_STAT_OPENS, 263 _DRM_STAT_CLOSES, 264 _DRM_STAT_IOCTLS, 265 _DRM_STAT_LOCKS, 266 _DRM_STAT_UNLOCKS, 267 _DRM_STAT_VALUE, /**< Generic value */ 268 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 269 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 270 271 _DRM_STAT_IRQ, /**< IRQ */ 272 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 273 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 274 _DRM_STAT_DMA, /**< DMA */ 275 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 276 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 277 278 /* Add to the *END* of the list */ 279} drm_stat_type_t; 280 281 282/** 283 * DRM_IOCTL_GET_STATS ioctl argument type. 284 */ 285typedef struct drm_stats { 286 unsigned long count; 287 struct { 288 unsigned long value; 289 drm_stat_type_t type; 290 } data[15]; 291} drm_stats_t; 292 293 294/** 295 * Hardware locking flags. 296 */ 297typedef enum drm_lock_flags { 298 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 299 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 300 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 301 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 302 /* These *HALT* flags aren't supported yet 303 -- they will be used to support the 304 full-screen DGA-like mode. */ 305 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 306 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 307} drm_lock_flags_t; 308 309 310/** 311 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 312 * 313 * \sa drmGetLock() and drmUnlock(). 314 */ 315typedef struct drm_lock { 316 int context; 317 drm_lock_flags_t flags; 318} drm_lock_t; 319 320 321/** 322 * DMA flags 323 * 324 * \warning 325 * These values \e must match xf86drm.h. 326 * 327 * \sa drm_dma. 328 */ 329typedef enum drm_dma_flags { 330 /* Flags for DMA buffer dispatch */ 331 _DRM_DMA_BLOCK = 0x01, /**< 332 * Block until buffer dispatched. 333 * 334 * \note The buffer may not yet have 335 * been processed by the hardware -- 336 * getting a hardware lock with the 337 * hardware quiescent will ensure 338 * that the buffer has been 339 * processed. 340 */ 341 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 342 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 343 344 /* Flags for DMA buffer request */ 345 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 346 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 347 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 348} drm_dma_flags_t; 349 350 351/** 352 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 353 * 354 * \sa drmAddBufs(). 355 */ 356typedef struct drm_buf_desc { 357 int count; /**< Number of buffers of this size */ 358 int size; /**< Size in bytes */ 359 int low_mark; /**< Low water mark */ 360 int high_mark; /**< High water mark */ 361 enum { 362 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 363 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 364 _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */ 365 } flags; 366 unsigned long agp_start; /**< 367 * Start address of where the AGP buffers are 368 * in the AGP aperture 369 */ 370} drm_buf_desc_t; 371 372 373/** 374 * DRM_IOCTL_INFO_BUFS ioctl argument type. 375 */ 376typedef struct drm_buf_info { 377 int count; /**< Entries in list */ 378 drm_buf_desc_t *list; 379} drm_buf_info_t; 380 381 382/** 383 * DRM_IOCTL_FREE_BUFS ioctl argument type. 384 */ 385typedef struct drm_buf_free { 386 int count; 387 int *list; 388} drm_buf_free_t; 389 390 391/** 392 * Buffer information 393 * 394 * \sa drm_buf_map. 395 */ 396typedef struct drm_buf_pub { 397 int idx; /**< Index into the master buffer list */ 398 int total; /**< Buffer size */ 399 int used; /**< Amount of buffer in use (for DMA) */ 400 void *address; /**< Address of buffer */ 401} drm_buf_pub_t; 402 403 404/** 405 * DRM_IOCTL_MAP_BUFS ioctl argument type. 406 */ 407typedef struct drm_buf_map { 408 int count; /**< Length of the buffer list */ 409 void *virtual; /**< Mmap'd area in user-virtual */ 410 drm_buf_pub_t *list; /**< Buffer information */ 411} drm_buf_map_t; 412 413 414/** 415 * DRM_IOCTL_DMA ioctl argument type. 416 * 417 * Indices here refer to the offset into the buffer list in drm_buf_get. 418 * 419 * \sa drmDMA(). 420 */ 421typedef struct drm_dma { 422 int context; /**< Context handle */ 423 int send_count; /**< Number of buffers to send */ 424 int *send_indices; /**< List of handles to buffers */ 425 int *send_sizes; /**< Lengths of data to send */ 426 drm_dma_flags_t flags; /**< Flags */ 427 int request_count; /**< Number of buffers requested */ 428 int request_size; /**< Desired size for buffers */ 429 int *request_indices; /**< Buffer information */ 430 int *request_sizes; 431 int granted_count; /**< Number of buffers granted */ 432} drm_dma_t; 433 434 435typedef enum { 436 _DRM_CONTEXT_PRESERVED = 0x01, 437 _DRM_CONTEXT_2DONLY = 0x02 438} drm_ctx_flags_t; 439 440 441/** 442 * DRM_IOCTL_ADD_CTX ioctl argument type. 443 * 444 * \sa drmCreateContext() and drmDestroyContext(). 445 */ 446typedef struct drm_ctx { 447 drm_context_t handle; 448 drm_ctx_flags_t flags; 449} drm_ctx_t; 450 451 452/** 453 * DRM_IOCTL_RES_CTX ioctl argument type. 454 */ 455typedef struct drm_ctx_res { 456 int count; 457 drm_ctx_t *contexts; 458} drm_ctx_res_t; 459 460 461/** 462 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 463 */ 464typedef struct drm_draw { 465 drm_drawable_t handle; 466} drm_draw_t; 467 468 469/** 470 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 471 */ 472typedef struct drm_auth { 473 drm_magic_t magic; 474} drm_auth_t; 475 476 477/** 478 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 479 * 480 * \sa drmGetInterruptFromBusID(). 481 */ 482typedef struct drm_irq_busid { 483 int irq; /**< IRQ number */ 484 int busnum; /**< bus number */ 485 int devnum; /**< device number */ 486 int funcnum; /**< function number */ 487} drm_irq_busid_t; 488 489 490typedef enum { 491 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 492 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 493 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 494} drm_vblank_seq_type_t; 495 496 497#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL 498 499 500struct drm_wait_vblank_request { 501 drm_vblank_seq_type_t type; 502 unsigned int sequence; 503 unsigned long signal; 504}; 505 506 507struct drm_wait_vblank_reply { 508 drm_vblank_seq_type_t type; 509 unsigned int sequence; 510 long tval_sec; 511 long tval_usec; 512}; 513 514 515/** 516 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 517 * 518 * \sa drmWaitVBlank(). 519 */ 520typedef union drm_wait_vblank { 521 struct drm_wait_vblank_request request; 522 struct drm_wait_vblank_reply reply; 523} drm_wait_vblank_t; 524 525 526/** 527 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 528 * 529 * \sa drmAgpEnable(). 530 */ 531typedef struct drm_agp_mode { 532 unsigned long mode; /**< AGP mode */ 533} drm_agp_mode_t; 534 535 536/** 537 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 538 * 539 * \sa drmAgpAlloc() and drmAgpFree(). 540 */ 541typedef struct drm_agp_buffer { 542 unsigned long size; /**< In bytes -- will round to page boundary */ 543 unsigned long handle; /**< Used for binding / unbinding */ 544 unsigned long type; /**< Type of memory to allocate */ 545 unsigned long physical; /**< Physical used by i810 */ 546} drm_agp_buffer_t; 547 548 549/** 550 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 551 * 552 * \sa drmAgpBind() and drmAgpUnbind(). 553 */ 554typedef struct drm_agp_binding { 555 unsigned long handle; /**< From drm_agp_buffer */ 556 unsigned long offset; /**< In bytes -- will round to page boundary */ 557} drm_agp_binding_t; 558 559 560/** 561 * DRM_IOCTL_AGP_INFO ioctl argument type. 562 * 563 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 564 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 565 * drmAgpVendorId() and drmAgpDeviceId(). 566 */ 567typedef struct drm_agp_info { 568 int agp_version_major; 569 int agp_version_minor; 570 unsigned long mode; 571 unsigned long aperture_base; /* physical address */ 572 unsigned long aperture_size; /* bytes */ 573 unsigned long memory_allowed; /* bytes */ 574 unsigned long memory_used; 575 576 /* PCI information */ 577 unsigned short id_vendor; 578 unsigned short id_device; 579} drm_agp_info_t; 580 581 582/** 583 * DRM_IOCTL_SG_ALLOC ioctl argument type. 584 */ 585typedef struct drm_scatter_gather { 586 unsigned long size; /**< In bytes -- will round to page boundary */ 587 unsigned long handle; /**< Used for mapping / unmapping */ 588} drm_scatter_gather_t; 589 590/** 591 * DRM_IOCTL_SET_VERSION ioctl argument type. 592 */ 593typedef struct drm_set_version { 594 int drm_di_major; 595 int drm_di_minor; 596 int drm_dd_major; 597 int drm_dd_minor; 598} drm_set_version_t; 599 600 601#define DRM_IOCTL_BASE 'd' 602#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 603#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 604#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 605#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 606 607#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) 608#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) 609#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) 610#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) 611#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) 612#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) 613#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) 614#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) 615 616#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) 617#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) 618#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) 619#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) 620#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) 621#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) 622#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) 623#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) 624#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) 625#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) 626#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) 627 628#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) 629 630#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) 631#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) 632 633#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) 634#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) 635#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) 636#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) 637#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) 638#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) 639#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) 640#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) 641#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) 642#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) 643#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) 644#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) 645#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) 646 647#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 648#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 649#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) 650#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) 651#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) 652#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) 653#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) 654#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) 655 656#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) 657#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) 658 659#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) 660 661/** 662 * Device specific ioctls should only be in their respective headers 663 * The device specific ioctl range is from 0x40 to 0x79. 664 * 665 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 666 * drmCommandReadWrite(). 667 */ 668#define DRM_COMMAND_BASE 0x40 669 670#endif 671