1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#include <sys/types.h> 35#include <sys/mbuf.h> 36#include <sys/socket.h> 37#include <sys/kernel.h> 38#include <sys/kdb.h> 39#include <sys/malloc.h> 40#include <sys/queue.h> 41#include <sys/sbuf.h> 42#include <sys/taskqueue.h> 43#include <sys/sysctl.h> 44#include <sys/smp.h> 45#include <net/bpf.h> 46#include <net/ethernet.h> 47#include <net/if.h> 48#include <net/if_vlan_var.h> 49#include <netinet/in.h> 50#include <netinet/ip.h> 51#include <netinet/ip6.h> 52#include <netinet/tcp.h> 53#include <machine/md_var.h> 54#include <vm/vm.h> 55#include <vm/pmap.h> 56 57#include "common/common.h" 58#include "common/t4_regs.h" 59#include "common/t4_regs_values.h" 60#include "common/t4_msg.h" 61 62#ifdef T4_PKT_TIMESTAMP 63#define RX_COPY_THRESHOLD (MINCLSIZE - 8) 64#else 65#define RX_COPY_THRESHOLD MINCLSIZE 66#endif 67 68/* 69 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 70 * 0-7 are valid values. 71 */ 72static int fl_pktshift = 2; 73TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 74 75/* 76 * Pad ethernet payload up to this boundary. 77 * -1: driver should figure out a good value. 78 * 0: disable padding. 79 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 80 */ 81static int fl_pad = -1; 82TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 83 84/* 85 * Status page length. 86 * -1: driver should figure out a good value. 87 * 64 or 128 are the only other valid values. 88 */ 89static int spg_len = -1; 90TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 91 92/* 93 * Congestion drops. 94 * -1: no congestion feedback (not recommended). 95 * 0: backpressure the channel instead of dropping packets right away. 96 * 1: no backpressure, drop packets for the congested queue immediately. 97 */ 98static int cong_drop = 0; 99TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 100 101/* 102 * Deliver multiple frames in the same free list buffer if they fit. 103 * -1: let the driver decide whether to enable buffer packing or not. 104 * 0: disable buffer packing. 105 * 1: enable buffer packing. 106 */ 107static int buffer_packing = -1; 108TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 109 110/* 111 * Start next frame in a packed buffer at this boundary. 112 * -1: driver should figure out a good value. 113 * T4: 114 * --- 115 * if fl_pad != 0 116 * value specified here will be overridden by fl_pad. 117 * else 118 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 119 * T5: 120 * --- 121 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 122 */ 123static int fl_pack = -1; 124static int t4_fl_pack; 125static int t5_fl_pack; 126TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 127 128/* 129 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 130 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 131 * 1: ok to create mbuf(s) within a cluster if there is room. 132 */ 133static int allow_mbufs_in_cluster = 1; 134TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 135 136/* 137 * Largest rx cluster size that the driver is allowed to allocate. 138 */ 139static int largest_rx_cluster = MJUM16BYTES; 140TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 141 142/* 143 * Size of cluster allocation that's most likely to succeed. The driver will 144 * fall back to this size if it fails to allocate clusters larger than this. 145 */ 146static int safest_rx_cluster = PAGE_SIZE; 147TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 148 149/* Used to track coalesced tx work request */ 150struct txpkts { 151 uint64_t *flitp; /* ptr to flit where next pkt should start */ 152 uint8_t npkt; /* # of packets in this work request */ 153 uint8_t nflits; /* # of flits used by this work request */ 154 uint16_t plen; /* total payload (sum of all packets) */ 155}; 156 157/* A packet's SGL. This + m_pkthdr has all info needed for tx */ 158struct sgl { 159 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 160 int nflits; /* # of flits needed for the SGL */ 161 bus_dma_segment_t seg[TX_SGL_SEGS]; 162}; 163 164static int service_iq(struct sge_iq *, int); 165static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 166 int *); 167static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 168static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 169 int); 170static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 171 char *); 172static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 173 char *); 174static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 175 bus_addr_t *, void **); 176static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 177 void *); 178static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 179 int, int); 180static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 181static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 182 struct sge_fl *); 183static int alloc_fwq(struct adapter *); 184static int free_fwq(struct adapter *); 185static int alloc_mgmtq(struct adapter *); 186static int free_mgmtq(struct adapter *); 187static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 188 struct sysctl_oid *); 189static int free_rxq(struct port_info *, struct sge_rxq *); 190#ifdef TCP_OFFLOAD 191static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 192 struct sysctl_oid *); 193static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 194#endif 195static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 196static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 197#ifdef TCP_OFFLOAD 198static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 199#endif 200static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 201static int free_eq(struct adapter *, struct sge_eq *); 202static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 203 struct sysctl_oid *); 204static int free_wrq(struct adapter *, struct sge_wrq *); 205static int alloc_txq(struct port_info *, struct sge_txq *, int, 206 struct sysctl_oid *); 207static int free_txq(struct port_info *, struct sge_txq *); 208static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 209static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 210static inline void iq_next(struct sge_iq *); 211static inline void ring_fl_db(struct adapter *, struct sge_fl *); 212static int refill_fl(struct adapter *, struct sge_fl *, int); 213static void refill_sfl(void *); 214static int alloc_fl_sdesc(struct sge_fl *); 215static void free_fl_sdesc(struct adapter *, struct sge_fl *); 216static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 217static void find_safe_refill_source(struct adapter *, struct sge_fl *); 218static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 219 220static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 221static int free_pkt_sgl(struct sge_txq *, struct sgl *); 222static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 223 struct sgl *); 224static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 225 struct mbuf *, struct sgl *); 226static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 227static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 228 struct txpkts *, struct mbuf *, struct sgl *); 229static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 230static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 231static inline void ring_eq_db(struct adapter *, struct sge_eq *); 232static inline int reclaimable(struct sge_eq *); 233static int reclaim_tx_descs(struct sge_txq *, int, int); 234static void write_eqflush_wr(struct sge_eq *); 235static __be64 get_flit(bus_dma_segment_t *, int, int); 236static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 237 struct mbuf *); 238static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 239 struct mbuf *); 240 241static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 242static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 243 244/* 245 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 246 */ 247void 248t4_sge_modload(void) 249{ 250 int pad; 251 252 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 253#if defined(__i386__) || defined(__amd64__) 254 pad = max(cpu_clflush_line_size, 16); 255#else 256 pad = max(CACHE_LINE_SIZE, 16); 257#endif 258 pad = min(pad, 4096); 259 260 if (fl_pktshift < 0 || fl_pktshift > 7) { 261 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 262 " using 2 instead.\n", fl_pktshift); 263 fl_pktshift = 2; 264 } 265 266 if (fl_pad != 0 && 267 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 268 269 if (fl_pad != -1) { 270 printf("Invalid hw.cxgbe.fl_pad value (%d)," 271 " using %d instead.\n", fl_pad, max(pad, 32)); 272 } 273 fl_pad = max(pad, 32); 274 } 275 276 /* 277 * T4 has the same pad and pack boundary. If a pad boundary is set, 278 * pack boundary must be set to the same value. Otherwise take the 279 * specified value or auto-calculate something reasonable. 280 */ 281 if (fl_pad) 282 t4_fl_pack = fl_pad; 283 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 284 t4_fl_pack = max(pad, 32); 285 else 286 t4_fl_pack = fl_pack; 287 288 /* T5's pack boundary is independent of the pad boundary. */ 289 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 290 !powerof2(fl_pack)) 291 t5_fl_pack = max(pad, CACHE_LINE_SIZE); 292 else 293 t5_fl_pack = fl_pack; 294 295 if (spg_len != 64 && spg_len != 128) { 296 int len; 297 298#if defined(__i386__) || defined(__amd64__) 299 len = cpu_clflush_line_size > 64 ? 128 : 64; 300#else 301 len = 64; 302#endif 303 if (spg_len != -1) { 304 printf("Invalid hw.cxgbe.spg_len value (%d)," 305 " using %d instead.\n", spg_len, len); 306 } 307 spg_len = len; 308 } 309 310 if (cong_drop < -1 || cong_drop > 1) { 311 printf("Invalid hw.cxgbe.cong_drop value (%d)," 312 " using 0 instead.\n", cong_drop); 313 cong_drop = 0; 314 } 315} 316 317void 318t4_init_sge_cpl_handlers(struct adapter *sc) 319{ 320 321 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 322 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 323 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 324 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 325 326 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 327} 328 329/* 330 * adap->params.vpd.cclk must be set up before this is called. 331 */ 332void 333t4_tweak_chip_settings(struct adapter *sc) 334{ 335 int i; 336 uint32_t v, m; 337 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 338 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 339 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 340 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 341 static int sge_flbuf_sizes[] = { 342 MCLBYTES, 343#if MJUMPAGESIZE != MCLBYTES 344 MJUMPAGESIZE, 345 MJUMPAGESIZE - CL_METADATA_SIZE, 346 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 347#endif 348 MJUM9BYTES, 349 MJUM16BYTES, 350 MCLBYTES - MSIZE - CL_METADATA_SIZE, 351 MJUM9BYTES - CL_METADATA_SIZE, 352 MJUM16BYTES - CL_METADATA_SIZE, 353 }; 354 355 KASSERT(sc->flags & MASTER_PF, 356 ("%s: trying to change chip settings when not master.", __func__)); 357 358 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 359 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 360 V_EGRSTATUSPAGESIZE(spg_len == 128); 361 if (is_t4(sc) && (fl_pad || buffer_packing)) { 362 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 363 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 364 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 365 } else if (is_t5(sc) && fl_pad) { 366 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 367 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 368 } 369 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 370 371 if (is_t5(sc) && buffer_packing) { 372 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 373 if (t5_fl_pack == 16) 374 v = V_INGPACKBOUNDARY(0); 375 else 376 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 377 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 378 } 379 380 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 381 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 382 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 383 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 384 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 385 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 386 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 387 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 388 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 389 390 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 391 ("%s: hw buffer size table too big", __func__)); 392 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 393 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 394 sge_flbuf_sizes[i]); 395 } 396 397 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 398 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 399 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 400 401 KASSERT(intr_timer[0] <= timer_max, 402 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 403 timer_max)); 404 for (i = 1; i < nitems(intr_timer); i++) { 405 KASSERT(intr_timer[i] >= intr_timer[i - 1], 406 ("%s: timers not listed in increasing order (%d)", 407 __func__, i)); 408 409 while (intr_timer[i] > timer_max) { 410 if (i == nitems(intr_timer) - 1) { 411 intr_timer[i] = timer_max; 412 break; 413 } 414 intr_timer[i] += intr_timer[i - 1]; 415 intr_timer[i] /= 2; 416 } 417 } 418 419 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 420 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 421 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 422 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 423 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 424 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 425 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 426 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 427 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 428 429 if (cong_drop == 0) { 430 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 431 F_TUNNELCNGDROP3; 432 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 433 } 434 435 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 436 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 437 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 438 439 m = v = F_TDDPTAGTCB; 440 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 441 442 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 443 F_RESETDDPOFFSET; 444 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 445 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 446} 447 448/* 449 * SGE wants the buffer to be at least 64B and then a multiple of the pad 450 * boundary or 16, whichever is greater. 451 */ 452static inline int 453hwsz_ok(int hwsz) 454{ 455 int mask = max(fl_pad, 16) - 1; 456 457 return (hwsz >= 64 && (hwsz & mask) == 0); 458} 459 460/* 461 * XXX: driver really should be able to deal with unexpected settings. 462 */ 463int 464t4_read_chip_settings(struct adapter *sc) 465{ 466 struct sge *s = &sc->sge; 467 int i, j, n, rc = 0; 468 uint32_t m, v, r; 469 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 470 static int sw_buf_sizes[] = { /* Sorted by size */ 471 MCLBYTES, 472#if MJUMPAGESIZE != MCLBYTES 473 MJUMPAGESIZE, 474#endif 475 MJUM9BYTES, 476 MJUM16BYTES 477 }; 478 struct sw_zone_info *swz, *safe_swz; 479 struct hw_buf_info *hwb; 480 481 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 482 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 483 V_EGRSTATUSPAGESIZE(spg_len == 128); 484 if (is_t4(sc) && (fl_pad || buffer_packing)) { 485 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 486 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 487 } else if (is_t5(sc) && fl_pad) { 488 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 489 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 490 } 491 r = t4_read_reg(sc, A_SGE_CONTROL); 492 if ((r & m) != v) { 493 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 494 rc = EINVAL; 495 } 496 497 if (is_t5(sc) && buffer_packing) { 498 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 499 if (t5_fl_pack == 16) 500 v = V_INGPACKBOUNDARY(0); 501 else 502 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 503 r = t4_read_reg(sc, A_SGE_CONTROL2); 504 if ((r & m) != v) { 505 device_printf(sc->dev, 506 "invalid SGE_CONTROL2(0x%x)\n", r); 507 rc = EINVAL; 508 } 509 } 510 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 511 512 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 513 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 514 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 515 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 516 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 517 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 518 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 519 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 520 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 521 if (r != v) { 522 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 523 rc = EINVAL; 524 } 525 526 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 527 hwb = &s->hw_buf_info[0]; 528 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 529 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 530 hwb->size = r; 531 hwb->zidx = hwsz_ok(r) ? -1 : -2; 532 hwb->next = -1; 533 } 534 535 /* 536 * Create a sorted list in decreasing order of hw buffer sizes (and so 537 * increasing order of spare area) for each software zone. 538 */ 539 n = 0; /* no usable buffer size to begin with */ 540 swz = &s->sw_zone_info[0]; 541 safe_swz = NULL; 542 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 543 int8_t head = -1, tail = -1; 544 545 swz->size = sw_buf_sizes[i]; 546 swz->zone = m_getzone(swz->size); 547 swz->type = m_gettype(swz->size); 548 549 if (swz->size == safest_rx_cluster) 550 safe_swz = swz; 551 552 hwb = &s->hw_buf_info[0]; 553 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 554 if (hwb->zidx != -1 || hwb->size > swz->size) 555 continue; 556 hwb->zidx = i; 557 if (head == -1) 558 head = tail = j; 559 else if (hwb->size < s->hw_buf_info[tail].size) { 560 s->hw_buf_info[tail].next = j; 561 tail = j; 562 } else { 563 int8_t *cur; 564 struct hw_buf_info *t; 565 566 for (cur = &head; *cur != -1; cur = &t->next) { 567 t = &s->hw_buf_info[*cur]; 568 if (hwb->size == t->size) { 569 hwb->zidx = -2; 570 break; 571 } 572 if (hwb->size > t->size) { 573 hwb->next = *cur; 574 *cur = j; 575 break; 576 } 577 } 578 } 579 } 580 swz->head_hwidx = head; 581 swz->tail_hwidx = tail; 582 583 if (tail != -1) { 584 n++; 585 if (swz->size - s->hw_buf_info[tail].size >= 586 CL_METADATA_SIZE) 587 sc->flags |= BUF_PACKING_OK; 588 } 589 } 590 if (n == 0) { 591 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 592 rc = EINVAL; 593 } 594 595 s->safe_hwidx1 = -1; 596 s->safe_hwidx2 = -1; 597 if (safe_swz != NULL) { 598 s->safe_hwidx1 = safe_swz->head_hwidx; 599 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 600 int spare; 601 602 hwb = &s->hw_buf_info[i]; 603 spare = safe_swz->size - hwb->size; 604 if (spare < CL_METADATA_SIZE) 605 continue; 606 if (s->safe_hwidx2 == -1 || 607 spare == CL_METADATA_SIZE + MSIZE) 608 s->safe_hwidx2 = i; 609 if (spare >= CL_METADATA_SIZE + MSIZE) 610 break; 611 } 612 } 613 614 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 615 s->counter_val[0] = G_THRESHOLD_0(r); 616 s->counter_val[1] = G_THRESHOLD_1(r); 617 s->counter_val[2] = G_THRESHOLD_2(r); 618 s->counter_val[3] = G_THRESHOLD_3(r); 619 620 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 621 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 622 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 623 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 624 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 625 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 626 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 627 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 628 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 629 630 if (cong_drop == 0) { 631 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 632 F_TUNNELCNGDROP3; 633 r = t4_read_reg(sc, A_TP_PARA_REG3); 634 if (r & m) { 635 device_printf(sc->dev, 636 "invalid TP_PARA_REG3(0x%x)\n", r); 637 rc = EINVAL; 638 } 639 } 640 641 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 642 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 643 if (r != v) { 644 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 645 rc = EINVAL; 646 } 647 648 m = v = F_TDDPTAGTCB; 649 r = t4_read_reg(sc, A_ULP_RX_CTL); 650 if ((r & m) != v) { 651 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 652 rc = EINVAL; 653 } 654 655 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 656 F_RESETDDPOFFSET; 657 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 658 r = t4_read_reg(sc, A_TP_PARA_REG5); 659 if ((r & m) != v) { 660 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 661 rc = EINVAL; 662 } 663 664 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 665 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 666 if (is_t4(sc)) 667 s->fl_starve_threshold2 = s->fl_starve_threshold; 668 else 669 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 670 671 /* egress queues: log2 of # of doorbells per BAR2 page */ 672 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 673 r >>= S_QUEUESPERPAGEPF0 + 674 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 675 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 676 677 /* ingress queues: log2 of # of doorbells per BAR2 page */ 678 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 679 r >>= S_QUEUESPERPAGEPF0 + 680 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 681 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 682 683 t4_init_tp_params(sc); 684 685 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 686 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 687 688 return (rc); 689} 690 691int 692t4_create_dma_tag(struct adapter *sc) 693{ 694 int rc; 695 696 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 697 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 698 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 699 NULL, &sc->dmat); 700 if (rc != 0) { 701 device_printf(sc->dev, 702 "failed to create main DMA tag: %d\n", rc); 703 } 704 705 return (rc); 706} 707 708static inline int 709enable_buffer_packing(struct adapter *sc) 710{ 711 712 if (sc->flags & BUF_PACKING_OK && 713 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 714 (is_t4(sc) && buffer_packing == 1))) 715 return (1); 716 return (0); 717} 718 719void 720t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 721 struct sysctl_oid_list *children) 722{ 723 724 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 725 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 726 "freelist buffer sizes"); 727 728 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 729 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 730 731 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 732 NULL, fl_pad, "payload pad boundary (bytes)"); 733 734 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 735 NULL, spg_len, "status page size (bytes)"); 736 737 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 738 NULL, cong_drop, "congestion drop setting"); 739 740 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 741 NULL, enable_buffer_packing(sc), 742 "pack multiple frames in one fl buffer"); 743 744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 745 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 746} 747 748int 749t4_destroy_dma_tag(struct adapter *sc) 750{ 751 if (sc->dmat) 752 bus_dma_tag_destroy(sc->dmat); 753 754 return (0); 755} 756 757/* 758 * Allocate and initialize the firmware event queue and the management queue. 759 * 760 * Returns errno on failure. Resources allocated up to that point may still be 761 * allocated. Caller is responsible for cleanup in case this function fails. 762 */ 763int 764t4_setup_adapter_queues(struct adapter *sc) 765{ 766 int rc; 767 768 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 769 770 sysctl_ctx_init(&sc->ctx); 771 sc->flags |= ADAP_SYSCTL_CTX; 772 773 /* 774 * Firmware event queue 775 */ 776 rc = alloc_fwq(sc); 777 if (rc != 0) 778 return (rc); 779 780 /* 781 * Management queue. This is just a control queue that uses the fwq as 782 * its associated iq. 783 */ 784 rc = alloc_mgmtq(sc); 785 786 return (rc); 787} 788 789/* 790 * Idempotent 791 */ 792int 793t4_teardown_adapter_queues(struct adapter *sc) 794{ 795 796 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 797 798 /* Do this before freeing the queue */ 799 if (sc->flags & ADAP_SYSCTL_CTX) { 800 sysctl_ctx_free(&sc->ctx); 801 sc->flags &= ~ADAP_SYSCTL_CTX; 802 } 803 804 free_mgmtq(sc); 805 free_fwq(sc); 806 807 return (0); 808} 809 810static inline int 811first_vector(struct port_info *pi) 812{ 813 struct adapter *sc = pi->adapter; 814 int rc = T4_EXTRA_INTR, i; 815 816 if (sc->intr_count == 1) 817 return (0); 818 819 for_each_port(sc, i) { 820 struct port_info *p = sc->port[i]; 821 822 if (i == pi->port_id) 823 break; 824 825#ifdef TCP_OFFLOAD 826 if (sc->flags & INTR_DIRECT) 827 rc += p->nrxq + p->nofldrxq; 828 else 829 rc += max(p->nrxq, p->nofldrxq); 830#else 831 /* 832 * Not compiled with offload support and intr_count > 1. Only 833 * NIC queues exist and they'd better be taking direct 834 * interrupts. 835 */ 836 KASSERT(sc->flags & INTR_DIRECT, 837 ("%s: intr_count %d, !INTR_DIRECT", __func__, 838 sc->intr_count)); 839 840 rc += p->nrxq; 841#endif 842 } 843 844 return (rc); 845} 846 847/* 848 * Given an arbitrary "index," come up with an iq that can be used by other 849 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 850 * The iq returned is guaranteed to be something that takes direct interrupts. 851 */ 852static struct sge_iq * 853port_intr_iq(struct port_info *pi, int idx) 854{ 855 struct adapter *sc = pi->adapter; 856 struct sge *s = &sc->sge; 857 struct sge_iq *iq = NULL; 858 859 if (sc->intr_count == 1) 860 return (&sc->sge.fwq); 861 862#ifdef TCP_OFFLOAD 863 if (sc->flags & INTR_DIRECT) { 864 idx %= pi->nrxq + pi->nofldrxq; 865 866 if (idx >= pi->nrxq) { 867 idx -= pi->nrxq; 868 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 869 } else 870 iq = &s->rxq[pi->first_rxq + idx].iq; 871 872 } else { 873 idx %= max(pi->nrxq, pi->nofldrxq); 874 875 if (pi->nrxq >= pi->nofldrxq) 876 iq = &s->rxq[pi->first_rxq + idx].iq; 877 else 878 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 879 } 880#else 881 /* 882 * Not compiled with offload support and intr_count > 1. Only NIC 883 * queues exist and they'd better be taking direct interrupts. 884 */ 885 KASSERT(sc->flags & INTR_DIRECT, 886 ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count)); 887 888 idx %= pi->nrxq; 889 iq = &s->rxq[pi->first_rxq + idx].iq; 890#endif 891 892 KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__)); 893 return (iq); 894} 895 896/* Maximum payload that can be delivered with a single iq descriptor */ 897static inline int 898mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 899{ 900 int payload; 901 902#ifdef TCP_OFFLOAD 903 if (toe) { 904 payload = sc->tt.rx_coalesce ? 905 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 906 } else { 907#endif 908 /* large enough even when hw VLAN extraction is disabled */ 909 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 910 mtu; 911#ifdef TCP_OFFLOAD 912 } 913#endif 914 payload = roundup2(payload, fl_pad); 915 916 return (payload); 917} 918 919int 920t4_setup_port_queues(struct port_info *pi) 921{ 922 int rc = 0, i, j, intr_idx, iqid; 923 struct sge_rxq *rxq; 924 struct sge_txq *txq; 925 struct sge_wrq *ctrlq; 926#ifdef TCP_OFFLOAD 927 struct sge_ofld_rxq *ofld_rxq; 928 struct sge_wrq *ofld_txq; 929 struct sysctl_oid *oid2 = NULL; 930#endif 931 char name[16]; 932 struct adapter *sc = pi->adapter; 933 struct ifnet *ifp = pi->ifp; 934 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 935 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 936 int maxp, pack, mtu = ifp->if_mtu; 937 938 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD, 939 NULL, "rx queues"); 940 941#ifdef TCP_OFFLOAD 942 if (is_offload(sc)) { 943 oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 944 CTLFLAG_RD, NULL, 945 "rx queues for offloaded TCP connections"); 946 } 947#endif 948 949 /* Interrupt vector to start from (when using multiple vectors) */ 950 intr_idx = first_vector(pi); 951 952 /* 953 * First pass over all rx queues (NIC and TOE): 954 * a) initialize iq and fl 955 * b) allocate queue iff it will take direct interrupts. 956 */ 957 maxp = mtu_to_max_payload(sc, mtu, 0); 958 pack = enable_buffer_packing(sc); 959 for_each_rxq(pi, i, rxq) { 960 961 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 962 RX_IQ_ESIZE); 963 964 snprintf(name, sizeof(name), "%s rxq%d-fl", 965 device_get_nameunit(pi->dev), i); 966 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 967 968 if (sc->flags & INTR_DIRECT 969#ifdef TCP_OFFLOAD 970 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq) 971#endif 972 ) { 973 rxq->iq.flags |= IQ_INTR; 974 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 975 if (rc != 0) 976 goto done; 977 intr_idx++; 978 } 979 } 980 981#ifdef TCP_OFFLOAD 982 maxp = mtu_to_max_payload(sc, mtu, 1); 983 for_each_ofld_rxq(pi, i, ofld_rxq) { 984 985 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 986 pi->qsize_rxq, RX_IQ_ESIZE); 987 988 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 989 device_get_nameunit(pi->dev), i); 990 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 991 992 if (sc->flags & INTR_DIRECT || 993 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) { 994 ofld_rxq->iq.flags |= IQ_INTR; 995 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 996 if (rc != 0) 997 goto done; 998 intr_idx++; 999 } 1000 } 1001#endif 1002 1003 /* 1004 * Second pass over all rx queues (NIC and TOE). The queues forwarding 1005 * their interrupts are allocated now. 1006 */ 1007 j = 0; 1008 for_each_rxq(pi, i, rxq) { 1009 if (rxq->iq.flags & IQ_INTR) 1010 continue; 1011 1012 intr_idx = port_intr_iq(pi, j)->abs_id; 1013 1014 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1015 if (rc != 0) 1016 goto done; 1017 j++; 1018 } 1019 1020#ifdef TCP_OFFLOAD 1021 for_each_ofld_rxq(pi, i, ofld_rxq) { 1022 if (ofld_rxq->iq.flags & IQ_INTR) 1023 continue; 1024 1025 intr_idx = port_intr_iq(pi, j)->abs_id; 1026 1027 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 1028 if (rc != 0) 1029 goto done; 1030 j++; 1031 } 1032#endif 1033 1034 /* 1035 * Now the tx queues. Only one pass needed. 1036 */ 1037 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1038 NULL, "tx queues"); 1039 j = 0; 1040 for_each_txq(pi, i, txq) { 1041 uint16_t iqid; 1042 1043 iqid = port_intr_iq(pi, j)->cntxt_id; 1044 1045 snprintf(name, sizeof(name), "%s txq%d", 1046 device_get_nameunit(pi->dev), i); 1047 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 1048 name); 1049 1050 rc = alloc_txq(pi, txq, i, oid); 1051 if (rc != 0) 1052 goto done; 1053 j++; 1054 } 1055 1056#ifdef TCP_OFFLOAD 1057 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 1058 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1059 for_each_ofld_txq(pi, i, ofld_txq) { 1060 uint16_t iqid; 1061 1062 iqid = port_intr_iq(pi, j)->cntxt_id; 1063 1064 snprintf(name, sizeof(name), "%s ofld_txq%d", 1065 device_get_nameunit(pi->dev), i); 1066 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 1067 iqid, name); 1068 1069 snprintf(name, sizeof(name), "%d", i); 1070 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1071 name, CTLFLAG_RD, NULL, "offload tx queue"); 1072 1073 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 1074 if (rc != 0) 1075 goto done; 1076 j++; 1077 } 1078#endif 1079 1080 /* 1081 * Finally, the control queue. 1082 */ 1083 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1084 NULL, "ctrl queue"); 1085 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1086 iqid = port_intr_iq(pi, 0)->cntxt_id; 1087 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 1088 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1089 rc = alloc_wrq(sc, pi, ctrlq, oid); 1090 1091done: 1092 if (rc) 1093 t4_teardown_port_queues(pi); 1094 1095 return (rc); 1096} 1097 1098/* 1099 * Idempotent 1100 */ 1101int 1102t4_teardown_port_queues(struct port_info *pi) 1103{ 1104 int i; 1105 struct adapter *sc = pi->adapter; 1106 struct sge_rxq *rxq; 1107 struct sge_txq *txq; 1108#ifdef TCP_OFFLOAD 1109 struct sge_ofld_rxq *ofld_rxq; 1110 struct sge_wrq *ofld_txq; 1111#endif 1112 1113 /* Do this before freeing the queues */ 1114 if (pi->flags & PORT_SYSCTL_CTX) { 1115 sysctl_ctx_free(&pi->ctx); 1116 pi->flags &= ~PORT_SYSCTL_CTX; 1117 } 1118 1119 /* 1120 * Take down all the tx queues first, as they reference the rx queues 1121 * (for egress updates, etc.). 1122 */ 1123 1124 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1125 1126 for_each_txq(pi, i, txq) { 1127 free_txq(pi, txq); 1128 } 1129 1130#ifdef TCP_OFFLOAD 1131 for_each_ofld_txq(pi, i, ofld_txq) { 1132 free_wrq(sc, ofld_txq); 1133 } 1134#endif 1135 1136 /* 1137 * Then take down the rx queues that forward their interrupts, as they 1138 * reference other rx queues. 1139 */ 1140 1141 for_each_rxq(pi, i, rxq) { 1142 if ((rxq->iq.flags & IQ_INTR) == 0) 1143 free_rxq(pi, rxq); 1144 } 1145 1146#ifdef TCP_OFFLOAD 1147 for_each_ofld_rxq(pi, i, ofld_rxq) { 1148 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1149 free_ofld_rxq(pi, ofld_rxq); 1150 } 1151#endif 1152 1153 /* 1154 * Then take down the rx queues that take direct interrupts. 1155 */ 1156 1157 for_each_rxq(pi, i, rxq) { 1158 if (rxq->iq.flags & IQ_INTR) 1159 free_rxq(pi, rxq); 1160 } 1161 1162#ifdef TCP_OFFLOAD 1163 for_each_ofld_rxq(pi, i, ofld_rxq) { 1164 if (ofld_rxq->iq.flags & IQ_INTR) 1165 free_ofld_rxq(pi, ofld_rxq); 1166 } 1167#endif 1168 1169 return (0); 1170} 1171 1172/* 1173 * Deals with errors and the firmware event queue. All data rx queues forward 1174 * their interrupt to the firmware event queue. 1175 */ 1176void 1177t4_intr_all(void *arg) 1178{ 1179 struct adapter *sc = arg; 1180 struct sge_iq *fwq = &sc->sge.fwq; 1181 1182 t4_intr_err(arg); 1183 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1184 service_iq(fwq, 0); 1185 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1186 } 1187} 1188 1189/* Deals with error interrupts */ 1190void 1191t4_intr_err(void *arg) 1192{ 1193 struct adapter *sc = arg; 1194 1195 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1196 t4_slow_intr_handler(sc); 1197} 1198 1199void 1200t4_intr_evt(void *arg) 1201{ 1202 struct sge_iq *iq = arg; 1203 1204 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1205 service_iq(iq, 0); 1206 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1207 } 1208} 1209 1210void 1211t4_intr(void *arg) 1212{ 1213 struct sge_iq *iq = arg; 1214 1215 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1216 service_iq(iq, 0); 1217 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1218 } 1219} 1220 1221/* 1222 * Deals with anything and everything on the given ingress queue. 1223 */ 1224static int 1225service_iq(struct sge_iq *iq, int budget) 1226{ 1227 struct sge_iq *q; 1228 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1229 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1230 struct adapter *sc = iq->adapter; 1231 struct rsp_ctrl *ctrl; 1232 const struct rss_header *rss; 1233 int ndescs = 0, limit, fl_bufs_used = 0; 1234 int rsp_type; 1235 uint32_t lq; 1236 struct mbuf *m0; 1237 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1238 1239 limit = budget ? budget : iq->qsize / 8; 1240 1241 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1242 1243 /* 1244 * We always come back and check the descriptor ring for new indirect 1245 * interrupts and other responses after running a single handler. 1246 */ 1247 for (;;) { 1248 while (is_new_response(iq, &ctrl)) { 1249 1250 rmb(); 1251 1252 m0 = NULL; 1253 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1254 lq = be32toh(ctrl->pldbuflen_qid); 1255 rss = (const void *)iq->cdesc; 1256 1257 switch (rsp_type) { 1258 case X_RSPD_TYPE_FLBUF: 1259 1260 KASSERT(iq->flags & IQ_HAS_FL, 1261 ("%s: data for an iq (%p) with no freelist", 1262 __func__, iq)); 1263 1264 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1265 if (__predict_false(m0 == NULL)) 1266 goto process_iql; 1267#ifdef T4_PKT_TIMESTAMP 1268 /* 1269 * 60 bit timestamp for the payload is 1270 * *(uint64_t *)m0->m_pktdat. Note that it is 1271 * in the leading free-space in the mbuf. The 1272 * kernel can clobber it during a pullup, 1273 * m_copymdata, etc. You need to make sure that 1274 * the mbuf reaches you unmolested if you care 1275 * about the timestamp. 1276 */ 1277 *(uint64_t *)m0->m_pktdat = 1278 be64toh(ctrl->u.last_flit) & 1279 0xfffffffffffffff; 1280#endif 1281 1282 /* fall through */ 1283 1284 case X_RSPD_TYPE_CPL: 1285 KASSERT(rss->opcode < NUM_CPL_CMDS, 1286 ("%s: bad opcode %02x.", __func__, 1287 rss->opcode)); 1288 sc->cpl_handler[rss->opcode](iq, rss, m0); 1289 break; 1290 1291 case X_RSPD_TYPE_INTR: 1292 1293 /* 1294 * Interrupts should be forwarded only to queues 1295 * that are not forwarding their interrupts. 1296 * This means service_iq can recurse but only 1 1297 * level deep. 1298 */ 1299 KASSERT(budget == 0, 1300 ("%s: budget %u, rsp_type %u", __func__, 1301 budget, rsp_type)); 1302 1303 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1304 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1305 IQS_BUSY)) { 1306 if (service_iq(q, q->qsize / 8) == 0) { 1307 atomic_cmpset_int(&q->state, 1308 IQS_BUSY, IQS_IDLE); 1309 } else { 1310 STAILQ_INSERT_TAIL(&iql, q, 1311 link); 1312 } 1313 } 1314 break; 1315 1316 default: 1317 sc->an_handler(iq, ctrl); 1318 break; 1319 } 1320 1321 if (fl_bufs_used >= 16) { 1322 FL_LOCK(fl); 1323 fl->needed += fl_bufs_used; 1324 refill_fl(sc, fl, 32); 1325 FL_UNLOCK(fl); 1326 fl_bufs_used = 0; 1327 } 1328 1329 iq_next(iq); 1330 if (++ndescs == limit) { 1331 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1332 V_CIDXINC(ndescs) | 1333 V_INGRESSQID(iq->cntxt_id) | 1334 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1335 ndescs = 0; 1336 1337 if (budget) { 1338 if (fl_bufs_used) { 1339 FL_LOCK(fl); 1340 fl->needed += fl_bufs_used; 1341 refill_fl(sc, fl, 32); 1342 FL_UNLOCK(fl); 1343 } 1344 return (EINPROGRESS); 1345 } 1346 } 1347 } 1348 1349process_iql: 1350 if (STAILQ_EMPTY(&iql)) 1351 break; 1352 1353 /* 1354 * Process the head only, and send it to the back of the list if 1355 * it's still not done. 1356 */ 1357 q = STAILQ_FIRST(&iql); 1358 STAILQ_REMOVE_HEAD(&iql, link); 1359 if (service_iq(q, q->qsize / 8) == 0) 1360 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1361 else 1362 STAILQ_INSERT_TAIL(&iql, q, link); 1363 } 1364 1365#if defined(INET) || defined(INET6) 1366 if (iq->flags & IQ_LRO_ENABLED) { 1367 struct lro_ctrl *lro = &rxq->lro; 1368 struct lro_entry *l; 1369 1370 while (!SLIST_EMPTY(&lro->lro_active)) { 1371 l = SLIST_FIRST(&lro->lro_active); 1372 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1373 tcp_lro_flush(lro, l); 1374 } 1375 } 1376#endif 1377 1378 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1379 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1380 1381 if (iq->flags & IQ_HAS_FL) { 1382 int starved; 1383 1384 FL_LOCK(fl); 1385 fl->needed += fl_bufs_used; 1386 starved = refill_fl(sc, fl, 64); 1387 FL_UNLOCK(fl); 1388 if (__predict_false(starved != 0)) 1389 add_fl_to_sfl(sc, fl); 1390 } 1391 1392 return (0); 1393} 1394 1395static inline int 1396cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1397{ 1398 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1399 1400 if (rc) 1401 MPASS(cll->region3 >= CL_METADATA_SIZE); 1402 1403 return (rc); 1404} 1405 1406static inline struct cluster_metadata * 1407cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1408 caddr_t cl) 1409{ 1410 1411 if (cl_has_metadata(fl, cll)) { 1412 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1413 1414 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1415 } 1416 return (NULL); 1417} 1418 1419static void 1420rxb_free(void *arg1, void *arg2) 1421{ 1422 uma_zone_t zone = arg1; 1423 caddr_t cl = arg2; 1424 1425 uma_zfree(zone, cl); 1426} 1427 1428/* 1429 * The mbuf returned by this function could be allocated from zone_mbuf or 1430 * constructed in spare room in the cluster. 1431 * 1432 * The mbuf carries the payload in one of these ways 1433 * a) frame inside the mbuf (mbuf from zone_mbuf) 1434 * b) m_cljset (for clusters without metadata) zone_mbuf 1435 * c) m_extaddref (cluster with metadata) inline mbuf 1436 * d) m_extaddref (cluster with metadata) zone_mbuf 1437 */ 1438static struct mbuf * 1439get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags) 1440{ 1441 struct mbuf *m; 1442 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1443 struct cluster_layout *cll = &sd->cll; 1444 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1445 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1446 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1447 int len, padded_len; 1448 caddr_t payload; 1449 1450 len = min(total, hwb->size - fl->rx_offset); 1451 padded_len = roundup2(len, fl_pad); 1452 payload = sd->cl + cll->region1 + fl->rx_offset; 1453 1454 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1455 1456 /* 1457 * Copy payload into a freshly allocated mbuf. 1458 */ 1459 1460 m = flags & M_PKTHDR ? 1461 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1462 if (m == NULL) 1463 return (NULL); 1464 fl->mbuf_allocated++; 1465#ifdef T4_PKT_TIMESTAMP 1466 /* Leave room for a timestamp */ 1467 m->m_data += 8; 1468#endif 1469 /* copy data to mbuf */ 1470 bcopy(payload, mtod(m, caddr_t), len); 1471 1472 } else if (sd->nimbuf * MSIZE < cll->region1) { 1473 1474 /* 1475 * There's spare room in the cluster for an mbuf. Create one 1476 * and associate it with the payload that's in the cluster. 1477 */ 1478 1479 MPASS(clm != NULL); 1480 m = (struct mbuf *)(sd->cl + sd->nimbuf * MSIZE); 1481 /* No bzero required */ 1482 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE)) 1483 return (NULL); 1484 fl->mbuf_inlined++; 1485 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free, 1486 swz->zone, sd->cl); 1487 sd->nimbuf++; 1488 1489 } else { 1490 1491 /* 1492 * Grab an mbuf from zone_mbuf and associate it with the 1493 * payload in the cluster. 1494 */ 1495 1496 m = flags & M_PKTHDR ? 1497 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1498 if (m == NULL) 1499 return (NULL); 1500 fl->mbuf_allocated++; 1501 if (clm != NULL) { 1502 m_extaddref(m, payload, padded_len, &clm->refcount, 1503 rxb_free, swz->zone, sd->cl); 1504 sd->nembuf++; 1505 } else { 1506 m_cljset(m, sd->cl, swz->type); 1507 sd->cl = NULL; /* consumed, not a recycle candidate */ 1508 } 1509 } 1510 if (flags & M_PKTHDR) 1511 m->m_pkthdr.len = total; 1512 m->m_len = len; 1513 1514 if (fl->flags & FL_BUF_PACKING) { 1515 fl->rx_offset += roundup2(padded_len, sc->sge.pack_boundary); 1516 MPASS(fl->rx_offset <= hwb->size); 1517 if (fl->rx_offset < hwb->size) 1518 return (m); /* without advancing the cidx */ 1519 } 1520 1521 if (__predict_false(++fl->cidx == fl->cap)) 1522 fl->cidx = 0; 1523 fl->rx_offset = 0; 1524 1525 return (m); 1526} 1527 1528static struct mbuf * 1529get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1530 int *fl_bufs_used) 1531{ 1532 struct mbuf *m0, *m, **pnext; 1533 u_int nbuf, len; 1534 1535 /* 1536 * No assertion for the fl lock because we don't need it. This routine 1537 * is called only from the rx interrupt handler and it only updates 1538 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1539 * updated in the rx interrupt handler or the starvation helper routine. 1540 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1541 * lock but this routine does not). 1542 */ 1543 1544 nbuf = 0; 1545 len = G_RSPD_LEN(len_newbuf); 1546 if (__predict_false(fl->m0 != NULL)) { 1547 M_ASSERTPKTHDR(fl->m0); 1548 MPASS(len == fl->m0->m_pkthdr.len); 1549 MPASS(fl->remaining < len); 1550 1551 m0 = fl->m0; 1552 pnext = fl->pnext; 1553 len = fl->remaining; 1554 fl->m0 = NULL; 1555 goto get_segment; 1556 } 1557 1558 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1559 nbuf++; 1560 fl->rx_offset = 0; 1561 if (__predict_false(++fl->cidx == fl->cap)) 1562 fl->cidx = 0; 1563 } 1564 1565 /* 1566 * Payload starts at rx_offset in the current hw buffer. Its length is 1567 * 'len' and it may span multiple hw buffers. 1568 */ 1569 1570 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR); 1571 if (m0 == NULL) 1572 goto done; 1573 len -= m0->m_len; 1574 pnext = &m0->m_next; 1575 while (len > 0) { 1576 nbuf++; 1577get_segment: 1578 MPASS(fl->rx_offset == 0); 1579 m = get_scatter_segment(sc, fl, len, 0); 1580 if (m == NULL) { 1581 fl->m0 = m0; 1582 fl->pnext = pnext; 1583 fl->remaining = len; 1584 m0 = NULL; 1585 goto done; 1586 } 1587 *pnext = m; 1588 pnext = &m->m_next; 1589 len -= m->m_len; 1590 } 1591 *pnext = NULL; 1592 if (fl->rx_offset == 0) 1593 nbuf++; 1594done: 1595 (*fl_bufs_used) += nbuf; 1596 return (m0); 1597} 1598 1599static int 1600t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1601{ 1602 struct sge_rxq *rxq = iq_to_rxq(iq); 1603 struct ifnet *ifp = rxq->ifp; 1604 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1605#if defined(INET) || defined(INET6) 1606 struct lro_ctrl *lro = &rxq->lro; 1607#endif 1608 1609 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1610 rss->opcode)); 1611 1612 m0->m_pkthdr.len -= fl_pktshift; 1613 m0->m_len -= fl_pktshift; 1614 m0->m_data += fl_pktshift; 1615 1616 m0->m_pkthdr.rcvif = ifp; 1617 m0->m_flags |= M_FLOWID; 1618 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1619 1620 if (cpl->csum_calc && !cpl->err_vec) { 1621 if (ifp->if_capenable & IFCAP_RXCSUM && 1622 cpl->l2info & htobe32(F_RXF_IP)) { 1623 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1624 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1625 rxq->rxcsum++; 1626 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1627 cpl->l2info & htobe32(F_RXF_IP6)) { 1628 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1629 CSUM_PSEUDO_HDR); 1630 rxq->rxcsum++; 1631 } 1632 1633 if (__predict_false(cpl->ip_frag)) 1634 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1635 else 1636 m0->m_pkthdr.csum_data = 0xffff; 1637 } 1638 1639 if (cpl->vlan_ex) { 1640 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1641 m0->m_flags |= M_VLANTAG; 1642 rxq->vlan_extraction++; 1643 } 1644 1645#if defined(INET) || defined(INET6) 1646 if (cpl->l2info & htobe32(F_RXF_LRO) && 1647 iq->flags & IQ_LRO_ENABLED && 1648 tcp_lro_rx(lro, m0, 0) == 0) { 1649 /* queued for LRO */ 1650 } else 1651#endif 1652 ifp->if_input(ifp, m0); 1653 1654 return (0); 1655} 1656 1657/* 1658 * Doesn't fail. Holds on to work requests it can't send right away. 1659 */ 1660void 1661t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1662{ 1663 struct sge_eq *eq = &wrq->eq; 1664 int can_reclaim; 1665 caddr_t dst; 1666 1667 TXQ_LOCK_ASSERT_OWNED(wrq); 1668#ifdef TCP_OFFLOAD 1669 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1670 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1671 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1672#else 1673 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1674 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1675#endif 1676 1677 if (__predict_true(wr != NULL)) 1678 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1679 1680 can_reclaim = reclaimable(eq); 1681 if (__predict_false(eq->flags & EQ_STALLED)) { 1682 if (can_reclaim < tx_resume_threshold(eq)) 1683 return; 1684 eq->flags &= ~EQ_STALLED; 1685 eq->unstalled++; 1686 } 1687 eq->cidx += can_reclaim; 1688 eq->avail += can_reclaim; 1689 if (__predict_false(eq->cidx >= eq->cap)) 1690 eq->cidx -= eq->cap; 1691 1692 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1693 int ndesc; 1694 1695 if (__predict_false(wr->wr_len < 0 || 1696 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1697 1698#ifdef INVARIANTS 1699 panic("%s: work request with length %d", __func__, 1700 wr->wr_len); 1701#endif 1702#ifdef KDB 1703 kdb_backtrace(); 1704#endif 1705 log(LOG_ERR, "%s: %s work request with length %d", 1706 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1707 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1708 free_wrqe(wr); 1709 continue; 1710 } 1711 1712 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1713 if (eq->avail < ndesc) { 1714 wrq->no_desc++; 1715 break; 1716 } 1717 1718 dst = (void *)&eq->desc[eq->pidx]; 1719 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1720 1721 eq->pidx += ndesc; 1722 eq->avail -= ndesc; 1723 if (__predict_false(eq->pidx >= eq->cap)) 1724 eq->pidx -= eq->cap; 1725 1726 eq->pending += ndesc; 1727 if (eq->pending >= 8) 1728 ring_eq_db(sc, eq); 1729 1730 wrq->tx_wrs++; 1731 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1732 free_wrqe(wr); 1733 1734 if (eq->avail < 8) { 1735 can_reclaim = reclaimable(eq); 1736 eq->cidx += can_reclaim; 1737 eq->avail += can_reclaim; 1738 if (__predict_false(eq->cidx >= eq->cap)) 1739 eq->cidx -= eq->cap; 1740 } 1741 } 1742 1743 if (eq->pending) 1744 ring_eq_db(sc, eq); 1745 1746 if (wr != NULL) { 1747 eq->flags |= EQ_STALLED; 1748 if (callout_pending(&eq->tx_callout) == 0) 1749 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1750 } 1751} 1752 1753/* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1754#define TXPKTS_PKT_HDR ((\ 1755 sizeof(struct ulp_txpkt) + \ 1756 sizeof(struct ulptx_idata) + \ 1757 sizeof(struct cpl_tx_pkt_core) \ 1758 ) / 8) 1759 1760/* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1761#define TXPKTS_WR_HDR (\ 1762 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1763 TXPKTS_PKT_HDR) 1764 1765/* Header of a tx WR, before SGL of first packet (in flits) */ 1766#define TXPKT_WR_HDR ((\ 1767 sizeof(struct fw_eth_tx_pkt_wr) + \ 1768 sizeof(struct cpl_tx_pkt_core) \ 1769 ) / 8 ) 1770 1771/* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1772#define TXPKT_LSO_WR_HDR ((\ 1773 sizeof(struct fw_eth_tx_pkt_wr) + \ 1774 sizeof(struct cpl_tx_pkt_lso_core) + \ 1775 sizeof(struct cpl_tx_pkt_core) \ 1776 ) / 8 ) 1777 1778int 1779t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1780{ 1781 struct port_info *pi = (void *)ifp->if_softc; 1782 struct adapter *sc = pi->adapter; 1783 struct sge_eq *eq = &txq->eq; 1784 struct buf_ring *br = txq->br; 1785 struct mbuf *next; 1786 int rc, coalescing, can_reclaim; 1787 struct txpkts txpkts; 1788 struct sgl sgl; 1789 1790 TXQ_LOCK_ASSERT_OWNED(txq); 1791 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1792 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1793 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1794 1795 prefetch(&eq->desc[eq->pidx]); 1796 prefetch(&txq->sdesc[eq->pidx]); 1797 1798 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1799 coalescing = 0; 1800 1801 can_reclaim = reclaimable(eq); 1802 if (__predict_false(eq->flags & EQ_STALLED)) { 1803 if (can_reclaim < tx_resume_threshold(eq)) { 1804 txq->m = m; 1805 return (0); 1806 } 1807 eq->flags &= ~EQ_STALLED; 1808 eq->unstalled++; 1809 } 1810 1811 if (__predict_false(eq->flags & EQ_DOOMED)) { 1812 m_freem(m); 1813 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1814 m_freem(m); 1815 return (ENETDOWN); 1816 } 1817 1818 if (eq->avail < 8 && can_reclaim) 1819 reclaim_tx_descs(txq, can_reclaim, 32); 1820 1821 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1822 1823 if (eq->avail < 8) 1824 break; 1825 1826 next = m->m_nextpkt; 1827 m->m_nextpkt = NULL; 1828 1829 if (next || buf_ring_peek(br)) 1830 coalescing = 1; 1831 1832 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1833 if (rc != 0) { 1834 if (rc == ENOMEM) { 1835 1836 /* Short of resources, suspend tx */ 1837 1838 m->m_nextpkt = next; 1839 break; 1840 } 1841 1842 /* 1843 * Unrecoverable error for this packet, throw it away 1844 * and move on to the next. get_pkt_sgl may already 1845 * have freed m (it will be NULL in that case and the 1846 * m_freem here is still safe). 1847 */ 1848 1849 m_freem(m); 1850 continue; 1851 } 1852 1853 if (coalescing && 1854 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1855 1856 /* Successfully absorbed into txpkts */ 1857 1858 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1859 goto doorbell; 1860 } 1861 1862 /* 1863 * We weren't coalescing to begin with, or current frame could 1864 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1865 * given to it can't be coalesced). Either way there should be 1866 * nothing in txpkts. 1867 */ 1868 KASSERT(txpkts.npkt == 0, 1869 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1870 1871 /* We're sending out individual packets now */ 1872 coalescing = 0; 1873 1874 if (eq->avail < 8) 1875 reclaim_tx_descs(txq, 0, 8); 1876 rc = write_txpkt_wr(pi, txq, m, &sgl); 1877 if (rc != 0) { 1878 1879 /* Short of hardware descriptors, suspend tx */ 1880 1881 /* 1882 * This is an unlikely but expensive failure. We've 1883 * done all the hard work (DMA mappings etc.) and now we 1884 * can't send out the packet. What's worse, we have to 1885 * spend even more time freeing up everything in sgl. 1886 */ 1887 txq->no_desc++; 1888 free_pkt_sgl(txq, &sgl); 1889 1890 m->m_nextpkt = next; 1891 break; 1892 } 1893 1894 ETHER_BPF_MTAP(ifp, m); 1895 if (sgl.nsegs == 0) 1896 m_freem(m); 1897doorbell: 1898 if (eq->pending >= 8) 1899 ring_eq_db(sc, eq); 1900 1901 can_reclaim = reclaimable(eq); 1902 if (can_reclaim >= 32) 1903 reclaim_tx_descs(txq, can_reclaim, 64); 1904 } 1905 1906 if (txpkts.npkt > 0) 1907 write_txpkts_wr(txq, &txpkts); 1908 1909 /* 1910 * m not NULL means there was an error but we haven't thrown it away. 1911 * This can happen when we're short of tx descriptors (no_desc) or maybe 1912 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 1913 * will get things going again. 1914 */ 1915 if (m && !(eq->flags & EQ_CRFLUSHED)) { 1916 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 1917 1918 /* 1919 * If EQ_CRFLUSHED is not set then we know we have at least one 1920 * available descriptor because any WR that reduces eq->avail to 1921 * 0 also sets EQ_CRFLUSHED. 1922 */ 1923 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 1924 1925 txsd->desc_used = 1; 1926 txsd->credits = 0; 1927 write_eqflush_wr(eq); 1928 } 1929 txq->m = m; 1930 1931 if (eq->pending) 1932 ring_eq_db(sc, eq); 1933 1934 reclaim_tx_descs(txq, 0, 128); 1935 1936 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 1937 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1938 1939 return (0); 1940} 1941 1942void 1943t4_update_fl_bufsize(struct ifnet *ifp) 1944{ 1945 struct port_info *pi = ifp->if_softc; 1946 struct adapter *sc = pi->adapter; 1947 struct sge_rxq *rxq; 1948#ifdef TCP_OFFLOAD 1949 struct sge_ofld_rxq *ofld_rxq; 1950#endif 1951 struct sge_fl *fl; 1952 int i, maxp, mtu = ifp->if_mtu; 1953 1954 maxp = mtu_to_max_payload(sc, mtu, 0); 1955 for_each_rxq(pi, i, rxq) { 1956 fl = &rxq->fl; 1957 1958 FL_LOCK(fl); 1959 find_best_refill_source(sc, fl, maxp); 1960 FL_UNLOCK(fl); 1961 } 1962#ifdef TCP_OFFLOAD 1963 maxp = mtu_to_max_payload(sc, mtu, 1); 1964 for_each_ofld_rxq(pi, i, ofld_rxq) { 1965 fl = &ofld_rxq->fl; 1966 1967 FL_LOCK(fl); 1968 find_best_refill_source(sc, fl, maxp); 1969 FL_UNLOCK(fl); 1970 } 1971#endif 1972} 1973 1974int 1975can_resume_tx(struct sge_eq *eq) 1976{ 1977 return (reclaimable(eq) >= tx_resume_threshold(eq)); 1978} 1979 1980static inline void 1981init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 1982 int qsize, int esize) 1983{ 1984 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 1985 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 1986 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 1987 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 1988 1989 iq->flags = 0; 1990 iq->adapter = sc; 1991 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 1992 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 1993 if (pktc_idx >= 0) { 1994 iq->intr_params |= F_QINTR_CNT_EN; 1995 iq->intr_pktc_idx = pktc_idx; 1996 } 1997 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 1998 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 1999} 2000 2001static inline void 2002init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack, 2003 char *name) 2004{ 2005 2006 fl->qsize = qsize; 2007 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2008 if (pack) 2009 fl->flags |= FL_BUF_PACKING; 2010 find_best_refill_source(sc, fl, maxp); 2011 find_safe_refill_source(sc, fl); 2012} 2013 2014static inline void 2015init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2016 uint16_t iqid, char *name) 2017{ 2018 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2019 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2020 2021 eq->flags = eqtype & EQ_TYPEMASK; 2022 eq->tx_chan = tx_chan; 2023 eq->iqid = iqid; 2024 eq->qsize = qsize; 2025 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2026 2027 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2028 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2029} 2030 2031static int 2032alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2033 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2034{ 2035 int rc; 2036 2037 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2038 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2039 if (rc != 0) { 2040 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2041 goto done; 2042 } 2043 2044 rc = bus_dmamem_alloc(*tag, va, 2045 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2046 if (rc != 0) { 2047 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2048 goto done; 2049 } 2050 2051 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2052 if (rc != 0) { 2053 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2054 goto done; 2055 } 2056done: 2057 if (rc) 2058 free_ring(sc, *tag, *map, *pa, *va); 2059 2060 return (rc); 2061} 2062 2063static int 2064free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2065 bus_addr_t pa, void *va) 2066{ 2067 if (pa) 2068 bus_dmamap_unload(tag, map); 2069 if (va) 2070 bus_dmamem_free(tag, va, map); 2071 if (tag) 2072 bus_dma_tag_destroy(tag); 2073 2074 return (0); 2075} 2076 2077/* 2078 * Allocates the ring for an ingress queue and an optional freelist. If the 2079 * freelist is specified it will be allocated and then associated with the 2080 * ingress queue. 2081 * 2082 * Returns errno on failure. Resources allocated up to that point may still be 2083 * allocated. Caller is responsible for cleanup in case this function fails. 2084 * 2085 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2086 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2087 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2088 */ 2089static int 2090alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2091 int intr_idx, int cong) 2092{ 2093 int rc, i, cntxt_id; 2094 size_t len; 2095 struct fw_iq_cmd c; 2096 struct adapter *sc = iq->adapter; 2097 __be32 v = 0; 2098 2099 len = iq->qsize * iq->esize; 2100 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2101 (void **)&iq->desc); 2102 if (rc != 0) 2103 return (rc); 2104 2105 bzero(&c, sizeof(c)); 2106 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2107 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2108 V_FW_IQ_CMD_VFN(0)); 2109 2110 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2111 FW_LEN16(c)); 2112 2113 /* Special handling for firmware event queue */ 2114 if (iq == &sc->sge.fwq) 2115 v |= F_FW_IQ_CMD_IQASYNCH; 2116 2117 if (iq->flags & IQ_INTR) { 2118 KASSERT(intr_idx < sc->intr_count, 2119 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2120 } else 2121 v |= F_FW_IQ_CMD_IQANDST; 2122 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2123 2124 c.type_to_iqandstindex = htobe32(v | 2125 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2126 V_FW_IQ_CMD_VIID(pi->viid) | 2127 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2128 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2129 F_FW_IQ_CMD_IQGTSMODE | 2130 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2131 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 2132 c.iqsize = htobe16(iq->qsize); 2133 c.iqaddr = htobe64(iq->ba); 2134 if (cong >= 0) 2135 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2136 2137 if (fl) { 2138 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2139 2140 len = fl->qsize * RX_FL_ESIZE; 2141 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2142 &fl->ba, (void **)&fl->desc); 2143 if (rc) 2144 return (rc); 2145 2146 /* Allocate space for one software descriptor per buffer. */ 2147 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 2148 rc = alloc_fl_sdesc(fl); 2149 if (rc != 0) { 2150 device_printf(sc->dev, 2151 "failed to setup fl software descriptors: %d\n", 2152 rc); 2153 return (rc); 2154 } 2155 fl->needed = fl->cap; 2156 fl->lowat = fl->flags & FL_BUF_PACKING ? 2157 roundup2(sc->sge.fl_starve_threshold2, 8) : 2158 roundup2(sc->sge.fl_starve_threshold, 8); 2159 2160 c.iqns_to_fl0congen |= 2161 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2162 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2163 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2164 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2165 0)); 2166 if (cong >= 0) { 2167 c.iqns_to_fl0congen |= 2168 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2169 F_FW_IQ_CMD_FL0CONGCIF | 2170 F_FW_IQ_CMD_FL0CONGEN); 2171 } 2172 c.fl0dcaen_to_fl0cidxfthresh = 2173 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2174 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2175 c.fl0size = htobe16(fl->qsize); 2176 c.fl0addr = htobe64(fl->ba); 2177 } 2178 2179 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2180 if (rc != 0) { 2181 device_printf(sc->dev, 2182 "failed to create ingress queue: %d\n", rc); 2183 return (rc); 2184 } 2185 2186 iq->cdesc = iq->desc; 2187 iq->cidx = 0; 2188 iq->gen = 1; 2189 iq->intr_next = iq->intr_params; 2190 iq->cntxt_id = be16toh(c.iqid); 2191 iq->abs_id = be16toh(c.physiqid); 2192 iq->flags |= IQ_ALLOCATED; 2193 2194 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2195 if (cntxt_id >= sc->sge.niq) { 2196 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2197 cntxt_id, sc->sge.niq - 1); 2198 } 2199 sc->sge.iqmap[cntxt_id] = iq; 2200 2201 if (fl) { 2202 fl->cntxt_id = be16toh(c.fl0id); 2203 fl->pidx = fl->cidx = 0; 2204 2205 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2206 if (cntxt_id >= sc->sge.neq) { 2207 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2208 __func__, cntxt_id, sc->sge.neq - 1); 2209 } 2210 sc->sge.eqmap[cntxt_id] = (void *)fl; 2211 2212 FL_LOCK(fl); 2213 /* Enough to make sure the SGE doesn't think it's starved */ 2214 refill_fl(sc, fl, fl->lowat); 2215 FL_UNLOCK(fl); 2216 2217 iq->flags |= IQ_HAS_FL; 2218 } 2219 2220 if (is_t5(sc) && cong >= 0) { 2221 uint32_t param, val; 2222 2223 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2224 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2225 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2226 if (cong == 0) 2227 val = 1 << 19; 2228 else { 2229 val = 2 << 19; 2230 for (i = 0; i < 4; i++) { 2231 if (cong & (1 << i)) 2232 val |= 1 << (i << 2); 2233 } 2234 } 2235 2236 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2237 if (rc != 0) { 2238 /* report error but carry on */ 2239 device_printf(sc->dev, 2240 "failed to set congestion manager context for " 2241 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2242 } 2243 } 2244 2245 /* Enable IQ interrupts */ 2246 atomic_store_rel_int(&iq->state, IQS_IDLE); 2247 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2248 V_INGRESSQID(iq->cntxt_id)); 2249 2250 return (0); 2251} 2252 2253static int 2254free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2255{ 2256 int rc; 2257 struct adapter *sc = iq->adapter; 2258 device_t dev; 2259 2260 if (sc == NULL) 2261 return (0); /* nothing to do */ 2262 2263 dev = pi ? pi->dev : sc->dev; 2264 2265 if (iq->flags & IQ_ALLOCATED) { 2266 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2267 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2268 fl ? fl->cntxt_id : 0xffff, 0xffff); 2269 if (rc != 0) { 2270 device_printf(dev, 2271 "failed to free queue %p: %d\n", iq, rc); 2272 return (rc); 2273 } 2274 iq->flags &= ~IQ_ALLOCATED; 2275 } 2276 2277 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2278 2279 bzero(iq, sizeof(*iq)); 2280 2281 if (fl) { 2282 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2283 fl->desc); 2284 2285 if (fl->sdesc) 2286 free_fl_sdesc(sc, fl); 2287 2288 if (mtx_initialized(&fl->fl_lock)) 2289 mtx_destroy(&fl->fl_lock); 2290 2291 bzero(fl, sizeof(*fl)); 2292 } 2293 2294 return (0); 2295} 2296 2297static void 2298add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2299 struct sge_fl *fl) 2300{ 2301 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2302 2303 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2304 "freelist"); 2305 children = SYSCTL_CHILDREN(oid); 2306 2307 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2308 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2309 "SGE context id of the freelist"); 2310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2311 0, "consumer index"); 2312 if (fl->flags & FL_BUF_PACKING) { 2313 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2314 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2315 } 2316 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2317 0, "producer index"); 2318 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2319 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2320 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2321 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2322 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2323 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2324 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2325 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2326 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2327 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2328} 2329 2330static int 2331alloc_fwq(struct adapter *sc) 2332{ 2333 int rc, intr_idx; 2334 struct sge_iq *fwq = &sc->sge.fwq; 2335 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2336 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2337 2338 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 2339 fwq->flags |= IQ_INTR; /* always */ 2340 intr_idx = sc->intr_count > 1 ? 1 : 0; 2341 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2342 if (rc != 0) { 2343 device_printf(sc->dev, 2344 "failed to create firmware event queue: %d\n", rc); 2345 return (rc); 2346 } 2347 2348 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2349 NULL, "firmware event queue"); 2350 children = SYSCTL_CHILDREN(oid); 2351 2352 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2353 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2354 "absolute id of the queue"); 2355 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2356 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2357 "SGE context id of the queue"); 2358 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2359 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2360 "consumer index"); 2361 2362 return (0); 2363} 2364 2365static int 2366free_fwq(struct adapter *sc) 2367{ 2368 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2369} 2370 2371static int 2372alloc_mgmtq(struct adapter *sc) 2373{ 2374 int rc; 2375 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2376 char name[16]; 2377 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2378 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2379 2380 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2381 NULL, "management queue"); 2382 2383 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2384 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2385 sc->sge.fwq.cntxt_id, name); 2386 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2387 if (rc != 0) { 2388 device_printf(sc->dev, 2389 "failed to create management queue: %d\n", rc); 2390 return (rc); 2391 } 2392 2393 return (0); 2394} 2395 2396static int 2397free_mgmtq(struct adapter *sc) 2398{ 2399 2400 return free_wrq(sc, &sc->sge.mgmtq); 2401} 2402 2403static inline int 2404tnl_cong(struct port_info *pi) 2405{ 2406 2407 if (cong_drop == -1) 2408 return (-1); 2409 else if (cong_drop == 1) 2410 return (0); 2411 else 2412 return (pi->rx_chan_map); 2413} 2414 2415static int 2416alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2417 struct sysctl_oid *oid) 2418{ 2419 int rc; 2420 struct sysctl_oid_list *children; 2421 char name[16]; 2422 2423 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2424 if (rc != 0) 2425 return (rc); 2426 2427 FL_LOCK(&rxq->fl); 2428 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2429 FL_UNLOCK(&rxq->fl); 2430 2431#if defined(INET) || defined(INET6) 2432 rc = tcp_lro_init(&rxq->lro); 2433 if (rc != 0) 2434 return (rc); 2435 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2436 2437 if (pi->ifp->if_capenable & IFCAP_LRO) 2438 rxq->iq.flags |= IQ_LRO_ENABLED; 2439#endif 2440 rxq->ifp = pi->ifp; 2441 2442 children = SYSCTL_CHILDREN(oid); 2443 2444 snprintf(name, sizeof(name), "%d", idx); 2445 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2446 NULL, "rx queue"); 2447 children = SYSCTL_CHILDREN(oid); 2448 2449 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2450 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2451 "absolute id of the queue"); 2452 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2453 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2454 "SGE context id of the queue"); 2455 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2456 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2457 "consumer index"); 2458#if defined(INET) || defined(INET6) 2459 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2460 &rxq->lro.lro_queued, 0, NULL); 2461 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2462 &rxq->lro.lro_flushed, 0, NULL); 2463#endif 2464 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2465 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2466 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2467 CTLFLAG_RD, &rxq->vlan_extraction, 2468 "# of times hardware extracted 802.1Q tag"); 2469 2470 add_fl_sysctls(&pi->ctx, oid, &rxq->fl); 2471 2472 return (rc); 2473} 2474 2475static int 2476free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2477{ 2478 int rc; 2479 2480#if defined(INET) || defined(INET6) 2481 if (rxq->lro.ifp) { 2482 tcp_lro_free(&rxq->lro); 2483 rxq->lro.ifp = NULL; 2484 } 2485#endif 2486 2487 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2488 if (rc == 0) 2489 bzero(rxq, sizeof(*rxq)); 2490 2491 return (rc); 2492} 2493 2494#ifdef TCP_OFFLOAD 2495static int 2496alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2497 int intr_idx, int idx, struct sysctl_oid *oid) 2498{ 2499 int rc; 2500 struct sysctl_oid_list *children; 2501 char name[16]; 2502 2503 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2504 pi->rx_chan_map); 2505 if (rc != 0) 2506 return (rc); 2507 2508 children = SYSCTL_CHILDREN(oid); 2509 2510 snprintf(name, sizeof(name), "%d", idx); 2511 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2512 NULL, "rx queue"); 2513 children = SYSCTL_CHILDREN(oid); 2514 2515 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2516 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2517 "I", "absolute id of the queue"); 2518 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2519 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2520 "I", "SGE context id of the queue"); 2521 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2522 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2523 "consumer index"); 2524 2525 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl); 2526 2527 return (rc); 2528} 2529 2530static int 2531free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2532{ 2533 int rc; 2534 2535 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2536 if (rc == 0) 2537 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2538 2539 return (rc); 2540} 2541#endif 2542 2543static int 2544ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2545{ 2546 int rc, cntxt_id; 2547 struct fw_eq_ctrl_cmd c; 2548 2549 bzero(&c, sizeof(c)); 2550 2551 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2552 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2553 V_FW_EQ_CTRL_CMD_VFN(0)); 2554 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2555 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2556 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2557 c.physeqid_pkd = htobe32(0); 2558 c.fetchszm_to_iqid = 2559 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2560 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2561 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2562 c.dcaen_to_eqsize = 2563 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2564 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2565 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2566 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2567 c.eqaddr = htobe64(eq->ba); 2568 2569 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2570 if (rc != 0) { 2571 device_printf(sc->dev, 2572 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2573 return (rc); 2574 } 2575 eq->flags |= EQ_ALLOCATED; 2576 2577 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2578 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2579 if (cntxt_id >= sc->sge.neq) 2580 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2581 cntxt_id, sc->sge.neq - 1); 2582 sc->sge.eqmap[cntxt_id] = eq; 2583 2584 return (rc); 2585} 2586 2587static int 2588eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2589{ 2590 int rc, cntxt_id; 2591 struct fw_eq_eth_cmd c; 2592 2593 bzero(&c, sizeof(c)); 2594 2595 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2596 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2597 V_FW_EQ_ETH_CMD_VFN(0)); 2598 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2599 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2600 c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2601 c.fetchszm_to_iqid = 2602 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2603 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2604 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2605 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2606 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2607 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2608 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2609 c.eqaddr = htobe64(eq->ba); 2610 2611 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2612 if (rc != 0) { 2613 device_printf(pi->dev, 2614 "failed to create Ethernet egress queue: %d\n", rc); 2615 return (rc); 2616 } 2617 eq->flags |= EQ_ALLOCATED; 2618 2619 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2620 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2621 if (cntxt_id >= sc->sge.neq) 2622 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2623 cntxt_id, sc->sge.neq - 1); 2624 sc->sge.eqmap[cntxt_id] = eq; 2625 2626 return (rc); 2627} 2628 2629#ifdef TCP_OFFLOAD 2630static int 2631ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2632{ 2633 int rc, cntxt_id; 2634 struct fw_eq_ofld_cmd c; 2635 2636 bzero(&c, sizeof(c)); 2637 2638 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2639 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2640 V_FW_EQ_OFLD_CMD_VFN(0)); 2641 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2642 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2643 c.fetchszm_to_iqid = 2644 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2645 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2646 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2647 c.dcaen_to_eqsize = 2648 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2649 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2650 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2651 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2652 c.eqaddr = htobe64(eq->ba); 2653 2654 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2655 if (rc != 0) { 2656 device_printf(pi->dev, 2657 "failed to create egress queue for TCP offload: %d\n", rc); 2658 return (rc); 2659 } 2660 eq->flags |= EQ_ALLOCATED; 2661 2662 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2663 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2664 if (cntxt_id >= sc->sge.neq) 2665 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2666 cntxt_id, sc->sge.neq - 1); 2667 sc->sge.eqmap[cntxt_id] = eq; 2668 2669 return (rc); 2670} 2671#endif 2672 2673static int 2674alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2675{ 2676 int rc; 2677 size_t len; 2678 2679 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2680 2681 len = eq->qsize * EQ_ESIZE; 2682 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2683 &eq->ba, (void **)&eq->desc); 2684 if (rc) 2685 return (rc); 2686 2687 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2688 eq->spg = (void *)&eq->desc[eq->cap]; 2689 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2690 eq->pidx = eq->cidx = 0; 2691 eq->doorbells = sc->doorbells; 2692 2693 switch (eq->flags & EQ_TYPEMASK) { 2694 case EQ_CTRL: 2695 rc = ctrl_eq_alloc(sc, eq); 2696 break; 2697 2698 case EQ_ETH: 2699 rc = eth_eq_alloc(sc, pi, eq); 2700 break; 2701 2702#ifdef TCP_OFFLOAD 2703 case EQ_OFLD: 2704 rc = ofld_eq_alloc(sc, pi, eq); 2705 break; 2706#endif 2707 2708 default: 2709 panic("%s: invalid eq type %d.", __func__, 2710 eq->flags & EQ_TYPEMASK); 2711 } 2712 if (rc != 0) { 2713 device_printf(sc->dev, 2714 "failed to allocate egress queue(%d): %d", 2715 eq->flags & EQ_TYPEMASK, rc); 2716 } 2717 2718 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2719 2720 if (isset(&eq->doorbells, DOORBELL_UDB) || 2721 isset(&eq->doorbells, DOORBELL_UDBWC) || 2722 isset(&eq->doorbells, DOORBELL_WCWR)) { 2723 uint32_t s_qpp = sc->sge.eq_s_qpp; 2724 uint32_t mask = (1 << s_qpp) - 1; 2725 volatile uint8_t *udb; 2726 2727 udb = sc->udbs_base + UDBS_DB_OFFSET; 2728 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2729 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2730 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2731 clrbit(&eq->doorbells, DOORBELL_WCWR); 2732 else { 2733 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2734 eq->udb_qid = 0; 2735 } 2736 eq->udb = (volatile void *)udb; 2737 } 2738 2739 return (rc); 2740} 2741 2742static int 2743free_eq(struct adapter *sc, struct sge_eq *eq) 2744{ 2745 int rc; 2746 2747 if (eq->flags & EQ_ALLOCATED) { 2748 switch (eq->flags & EQ_TYPEMASK) { 2749 case EQ_CTRL: 2750 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2751 eq->cntxt_id); 2752 break; 2753 2754 case EQ_ETH: 2755 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2756 eq->cntxt_id); 2757 break; 2758 2759#ifdef TCP_OFFLOAD 2760 case EQ_OFLD: 2761 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2762 eq->cntxt_id); 2763 break; 2764#endif 2765 2766 default: 2767 panic("%s: invalid eq type %d.", __func__, 2768 eq->flags & EQ_TYPEMASK); 2769 } 2770 if (rc != 0) { 2771 device_printf(sc->dev, 2772 "failed to free egress queue (%d): %d\n", 2773 eq->flags & EQ_TYPEMASK, rc); 2774 return (rc); 2775 } 2776 eq->flags &= ~EQ_ALLOCATED; 2777 } 2778 2779 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 2780 2781 if (mtx_initialized(&eq->eq_lock)) 2782 mtx_destroy(&eq->eq_lock); 2783 2784 bzero(eq, sizeof(*eq)); 2785 return (0); 2786} 2787 2788static int 2789alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 2790 struct sysctl_oid *oid) 2791{ 2792 int rc; 2793 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 2794 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2795 2796 rc = alloc_eq(sc, pi, &wrq->eq); 2797 if (rc) 2798 return (rc); 2799 2800 wrq->adapter = sc; 2801 STAILQ_INIT(&wrq->wr_list); 2802 2803 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2804 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 2805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2806 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 2807 "consumer index"); 2808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 2809 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 2810 "producer index"); 2811 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 2812 &wrq->tx_wrs, "# of work requests"); 2813 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2814 &wrq->no_desc, 0, 2815 "# of times queue ran out of hardware descriptors"); 2816 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2817 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 2818 2819 return (rc); 2820} 2821 2822static int 2823free_wrq(struct adapter *sc, struct sge_wrq *wrq) 2824{ 2825 int rc; 2826 2827 rc = free_eq(sc, &wrq->eq); 2828 if (rc) 2829 return (rc); 2830 2831 bzero(wrq, sizeof(*wrq)); 2832 return (0); 2833} 2834 2835static int 2836alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 2837 struct sysctl_oid *oid) 2838{ 2839 int rc; 2840 struct adapter *sc = pi->adapter; 2841 struct sge_eq *eq = &txq->eq; 2842 char name[16]; 2843 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2844 2845 rc = alloc_eq(sc, pi, eq); 2846 if (rc) 2847 return (rc); 2848 2849 txq->ifp = pi->ifp; 2850 2851 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 2852 M_ZERO | M_WAITOK); 2853 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 2854 2855 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 2856 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 2857 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 2858 if (rc != 0) { 2859 device_printf(sc->dev, 2860 "failed to create tx DMA tag: %d\n", rc); 2861 return (rc); 2862 } 2863 2864 /* 2865 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 2866 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 2867 * sized for the worst case. 2868 */ 2869 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 2870 M_WAITOK); 2871 if (rc != 0) { 2872 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 2873 return (rc); 2874 } 2875 2876 snprintf(name, sizeof(name), "%d", idx); 2877 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2878 NULL, "tx queue"); 2879 children = SYSCTL_CHILDREN(oid); 2880 2881 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2882 &eq->cntxt_id, 0, "SGE context id of the queue"); 2883 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2884 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 2885 "consumer index"); 2886 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2887 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 2888 "producer index"); 2889 2890 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 2891 &txq->txcsum, "# of times hardware assisted with checksum"); 2892 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 2893 CTLFLAG_RD, &txq->vlan_insertion, 2894 "# of times hardware inserted 802.1Q tag"); 2895 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 2896 &txq->tso_wrs, "# of TSO work requests"); 2897 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 2898 &txq->imm_wrs, "# of work requests with immediate data"); 2899 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 2900 &txq->sgl_wrs, "# of work requests with direct SGL"); 2901 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 2902 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 2903 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 2904 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 2905 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 2906 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 2907 2908 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 2909 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 2910 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 2911 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 2912 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2913 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 2914 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 2915 &eq->egr_update, 0, "egress update notifications from the SGE"); 2916 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2917 &eq->unstalled, 0, "# of times txq recovered after stall"); 2918 2919 return (rc); 2920} 2921 2922static int 2923free_txq(struct port_info *pi, struct sge_txq *txq) 2924{ 2925 int rc; 2926 struct adapter *sc = pi->adapter; 2927 struct sge_eq *eq = &txq->eq; 2928 2929 rc = free_eq(sc, eq); 2930 if (rc) 2931 return (rc); 2932 2933 free(txq->sdesc, M_CXGBE); 2934 2935 if (txq->txmaps.maps) 2936 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 2937 2938 buf_ring_free(txq->br, M_CXGBE); 2939 2940 if (txq->tx_tag) 2941 bus_dma_tag_destroy(txq->tx_tag); 2942 2943 bzero(txq, sizeof(*txq)); 2944 return (0); 2945} 2946 2947static void 2948oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2949{ 2950 bus_addr_t *ba = arg; 2951 2952 KASSERT(nseg == 1, 2953 ("%s meant for single segment mappings only.", __func__)); 2954 2955 *ba = error ? 0 : segs->ds_addr; 2956} 2957 2958static inline bool 2959is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 2960{ 2961 *ctrl = (void *)((uintptr_t)iq->cdesc + 2962 (iq->esize - sizeof(struct rsp_ctrl))); 2963 2964 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 2965} 2966 2967static inline void 2968iq_next(struct sge_iq *iq) 2969{ 2970 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 2971 if (__predict_false(++iq->cidx == iq->qsize - 1)) { 2972 iq->cidx = 0; 2973 iq->gen ^= 1; 2974 iq->cdesc = iq->desc; 2975 } 2976} 2977 2978#define FL_HW_IDX(x) ((x) >> 3) 2979static inline void 2980ring_fl_db(struct adapter *sc, struct sge_fl *fl) 2981{ 2982 int ndesc = fl->pending / 8; 2983 uint32_t v; 2984 2985 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 2986 ndesc--; /* hold back one credit */ 2987 2988 if (ndesc <= 0) 2989 return; /* nothing to do */ 2990 2991 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 2992 if (is_t5(sc)) 2993 v |= F_DBTYPE; 2994 2995 wmb(); 2996 2997 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 2998 fl->pending -= ndesc * 8; 2999} 3000 3001/* 3002 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3003 * 3004 * Returns non-zero to indicate that it should be added to the list of starving 3005 * freelists. 3006 */ 3007static int 3008refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3009{ 3010 __be64 *d = &fl->desc[fl->pidx]; 3011 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3012 uintptr_t pa; 3013 caddr_t cl; 3014 struct cluster_layout *cll = &fl->cll_def; /* default layout */ 3015 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 3016 struct cluster_metadata *clm; 3017 3018 FL_LOCK_ASSERT_OWNED(fl); 3019 3020 if (nbufs > fl->needed) 3021 nbufs = fl->needed; 3022 nbufs -= (fl->pidx + nbufs) % 8; 3023 3024 while (nbufs--) { 3025 3026 if (sd->cl != NULL) { 3027 3028 if (sd->nimbuf + sd->nembuf == 0) { 3029 /* 3030 * Fast recycle without involving any atomics on 3031 * the cluster's metadata (if the cluster has 3032 * metadata). This happens when all frames 3033 * received in the cluster were small enough to 3034 * fit within a single mbuf each. 3035 */ 3036 fl->cl_fast_recycled++; 3037#ifdef INVARIANTS 3038 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3039 if (clm != NULL) 3040 MPASS(clm->refcount == 1); 3041#endif 3042 goto recycled_fast; 3043 } 3044 3045 /* 3046 * Cluster is guaranteed to have metadata. Clusters 3047 * without metadata always take the fast recycle path 3048 * when they're recycled. 3049 */ 3050 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3051 MPASS(clm != NULL); 3052 3053 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3054 fl->cl_recycled++; 3055 goto recycled; 3056 } 3057 sd->cl = NULL; /* gave up my reference */ 3058 } 3059 MPASS(sd->cl == NULL); 3060alloc: 3061 cl = uma_zalloc(swz->zone, M_NOWAIT); 3062 if (__predict_false(cl == NULL)) { 3063 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3064 fl->cll_def.zidx == fl->cll_alt.zidx) 3065 break; 3066 3067 /* fall back to the safe zone */ 3068 cll = &fl->cll_alt; 3069 swz = &sc->sge.sw_zone_info[cll->zidx]; 3070 goto alloc; 3071 } 3072 fl->cl_allocated++; 3073 3074 pa = pmap_kextract((vm_offset_t)cl); 3075 pa += cll->region1; 3076 sd->cl = cl; 3077 sd->cll = *cll; 3078 *d = htobe64(pa | cll->hwidx); 3079 clm = cl_metadata(sc, fl, cll, cl); 3080 if (clm != NULL) { 3081recycled: 3082#ifdef INVARIANTS 3083 clm->sd = sd; 3084#endif 3085 clm->refcount = 1; 3086 } 3087 sd->nimbuf = 0; 3088 sd->nembuf = 0; 3089recycled_fast: 3090 fl->pending++; 3091 fl->needed--; 3092 d++; 3093 sd++; 3094 if (__predict_false(++fl->pidx == fl->cap)) { 3095 fl->pidx = 0; 3096 sd = fl->sdesc; 3097 d = fl->desc; 3098 } 3099 } 3100 3101 if (fl->pending >= 8) 3102 ring_fl_db(sc, fl); 3103 3104 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3105} 3106 3107/* 3108 * Attempt to refill all starving freelists. 3109 */ 3110static void 3111refill_sfl(void *arg) 3112{ 3113 struct adapter *sc = arg; 3114 struct sge_fl *fl, *fl_temp; 3115 3116 mtx_lock(&sc->sfl_lock); 3117 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3118 FL_LOCK(fl); 3119 refill_fl(sc, fl, 64); 3120 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3121 TAILQ_REMOVE(&sc->sfl, fl, link); 3122 fl->flags &= ~FL_STARVING; 3123 } 3124 FL_UNLOCK(fl); 3125 } 3126 3127 if (!TAILQ_EMPTY(&sc->sfl)) 3128 callout_schedule(&sc->sfl_callout, hz / 5); 3129 mtx_unlock(&sc->sfl_lock); 3130} 3131 3132static int 3133alloc_fl_sdesc(struct sge_fl *fl) 3134{ 3135 3136 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3137 M_ZERO | M_WAITOK); 3138 3139 return (0); 3140} 3141 3142static void 3143free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3144{ 3145 struct fl_sdesc *sd; 3146 struct cluster_metadata *clm; 3147 struct cluster_layout *cll; 3148 int i; 3149 3150 sd = fl->sdesc; 3151 for (i = 0; i < fl->cap; i++, sd++) { 3152 if (sd->cl == NULL) 3153 continue; 3154 3155 cll = &sd->cll; 3156 clm = cl_metadata(sc, fl, cll, sd->cl); 3157 if (sd->nimbuf + sd->nembuf == 0 || 3158 (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1)) { 3159 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3160 } 3161 sd->cl = NULL; 3162 } 3163 3164 free(fl->sdesc, M_CXGBE); 3165 fl->sdesc = NULL; 3166} 3167 3168int 3169t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3170 int flags) 3171{ 3172 struct tx_map *txm; 3173 int i, rc; 3174 3175 txmaps->map_total = txmaps->map_avail = count; 3176 txmaps->map_cidx = txmaps->map_pidx = 0; 3177 3178 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3179 M_ZERO | flags); 3180 3181 txm = txmaps->maps; 3182 for (i = 0; i < count; i++, txm++) { 3183 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3184 if (rc != 0) 3185 goto failed; 3186 } 3187 3188 return (0); 3189failed: 3190 while (--i >= 0) { 3191 txm--; 3192 bus_dmamap_destroy(tx_tag, txm->map); 3193 } 3194 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3195 3196 free(txmaps->maps, M_CXGBE); 3197 txmaps->maps = NULL; 3198 3199 return (rc); 3200} 3201 3202void 3203t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3204{ 3205 struct tx_map *txm; 3206 int i; 3207 3208 txm = txmaps->maps; 3209 for (i = 0; i < txmaps->map_total; i++, txm++) { 3210 3211 if (txm->m) { 3212 bus_dmamap_unload(tx_tag, txm->map); 3213 m_freem(txm->m); 3214 txm->m = NULL; 3215 } 3216 3217 bus_dmamap_destroy(tx_tag, txm->map); 3218 } 3219 3220 free(txmaps->maps, M_CXGBE); 3221 txmaps->maps = NULL; 3222} 3223 3224/* 3225 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3226 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3227 * of immediate data. 3228 */ 3229#define IMM_LEN ( \ 3230 2 * EQ_ESIZE \ 3231 - sizeof(struct fw_eth_tx_pkt_wr) \ 3232 - sizeof(struct cpl_tx_pkt_core)) 3233 3234/* 3235 * Returns non-zero on failure, no need to cleanup anything in that case. 3236 * 3237 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3238 * if the resulting chain still won't fit in a tx descriptor. 3239 * 3240 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3241 * does not have the TCP header in it. 3242 */ 3243static int 3244get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3245 int sgl_only) 3246{ 3247 struct mbuf *m = *fp; 3248 struct tx_maps *txmaps; 3249 struct tx_map *txm; 3250 int rc, defragged = 0, n; 3251 3252 TXQ_LOCK_ASSERT_OWNED(txq); 3253 3254 if (m->m_pkthdr.tso_segsz) 3255 sgl_only = 1; /* Do not allow immediate data with LSO */ 3256 3257start: sgl->nsegs = 0; 3258 3259 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3260 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3261 3262 txmaps = &txq->txmaps; 3263 if (txmaps->map_avail == 0) { 3264 txq->no_dmamap++; 3265 return (ENOMEM); 3266 } 3267 txm = &txmaps->maps[txmaps->map_pidx]; 3268 3269 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3270 *fp = m_pullup(m, 50); 3271 m = *fp; 3272 if (m == NULL) 3273 return (ENOBUFS); 3274 } 3275 3276 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3277 &sgl->nsegs, BUS_DMA_NOWAIT); 3278 if (rc == EFBIG && defragged == 0) { 3279 m = m_defrag(m, M_NOWAIT); 3280 if (m == NULL) 3281 return (EFBIG); 3282 3283 defragged = 1; 3284 *fp = m; 3285 goto start; 3286 } 3287 if (rc != 0) 3288 return (rc); 3289 3290 txm->m = m; 3291 txmaps->map_avail--; 3292 if (++txmaps->map_pidx == txmaps->map_total) 3293 txmaps->map_pidx = 0; 3294 3295 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3296 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3297 3298 /* 3299 * Store the # of flits required to hold this frame's SGL in nflits. An 3300 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3301 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3302 * then len1 must be set to 0. 3303 */ 3304 n = sgl->nsegs - 1; 3305 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3306 3307 return (0); 3308} 3309 3310 3311/* 3312 * Releases all the txq resources used up in the specified sgl. 3313 */ 3314static int 3315free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3316{ 3317 struct tx_maps *txmaps; 3318 struct tx_map *txm; 3319 3320 TXQ_LOCK_ASSERT_OWNED(txq); 3321 3322 if (sgl->nsegs == 0) 3323 return (0); /* didn't use any map */ 3324 3325 txmaps = &txq->txmaps; 3326 3327 /* 1 pkt uses exactly 1 map, back it out */ 3328 3329 txmaps->map_avail++; 3330 if (txmaps->map_pidx > 0) 3331 txmaps->map_pidx--; 3332 else 3333 txmaps->map_pidx = txmaps->map_total - 1; 3334 3335 txm = &txmaps->maps[txmaps->map_pidx]; 3336 bus_dmamap_unload(txq->tx_tag, txm->map); 3337 txm->m = NULL; 3338 3339 return (0); 3340} 3341 3342static int 3343write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3344 struct sgl *sgl) 3345{ 3346 struct sge_eq *eq = &txq->eq; 3347 struct fw_eth_tx_pkt_wr *wr; 3348 struct cpl_tx_pkt_core *cpl; 3349 uint32_t ctrl; /* used in many unrelated places */ 3350 uint64_t ctrl1; 3351 int nflits, ndesc, pktlen; 3352 struct tx_sdesc *txsd; 3353 caddr_t dst; 3354 3355 TXQ_LOCK_ASSERT_OWNED(txq); 3356 3357 pktlen = m->m_pkthdr.len; 3358 3359 /* 3360 * Do we have enough flits to send this frame out? 3361 */ 3362 ctrl = sizeof(struct cpl_tx_pkt_core); 3363 if (m->m_pkthdr.tso_segsz) { 3364 nflits = TXPKT_LSO_WR_HDR; 3365 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3366 } else 3367 nflits = TXPKT_WR_HDR; 3368 if (sgl->nsegs > 0) 3369 nflits += sgl->nflits; 3370 else { 3371 nflits += howmany(pktlen, 8); 3372 ctrl += pktlen; 3373 } 3374 ndesc = howmany(nflits, 8); 3375 if (ndesc > eq->avail) 3376 return (ENOMEM); 3377 3378 /* Firmware work request header */ 3379 wr = (void *)&eq->desc[eq->pidx]; 3380 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3381 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3382 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3383 if (eq->avail == ndesc) { 3384 if (!(eq->flags & EQ_CRFLUSHED)) { 3385 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3386 eq->flags |= EQ_CRFLUSHED; 3387 } 3388 eq->flags |= EQ_STALLED; 3389 } 3390 3391 wr->equiq_to_len16 = htobe32(ctrl); 3392 wr->r3 = 0; 3393 3394 if (m->m_pkthdr.tso_segsz) { 3395 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3396 struct ether_header *eh; 3397 void *l3hdr; 3398#if defined(INET) || defined(INET6) 3399 struct tcphdr *tcp; 3400#endif 3401 uint16_t eh_type; 3402 3403 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3404 F_LSO_LAST_SLICE; 3405 3406 eh = mtod(m, struct ether_header *); 3407 eh_type = ntohs(eh->ether_type); 3408 if (eh_type == ETHERTYPE_VLAN) { 3409 struct ether_vlan_header *evh = (void *)eh; 3410 3411 ctrl |= V_LSO_ETHHDR_LEN(1); 3412 l3hdr = evh + 1; 3413 eh_type = ntohs(evh->evl_proto); 3414 } else 3415 l3hdr = eh + 1; 3416 3417 switch (eh_type) { 3418#ifdef INET6 3419 case ETHERTYPE_IPV6: 3420 { 3421 struct ip6_hdr *ip6 = l3hdr; 3422 3423 /* 3424 * XXX-BZ For now we do not pretend to support 3425 * IPv6 extension headers. 3426 */ 3427 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3428 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3429 tcp = (struct tcphdr *)(ip6 + 1); 3430 ctrl |= F_LSO_IPV6; 3431 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3432 V_LSO_TCPHDR_LEN(tcp->th_off); 3433 break; 3434 } 3435#endif 3436#ifdef INET 3437 case ETHERTYPE_IP: 3438 { 3439 struct ip *ip = l3hdr; 3440 3441 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3442 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3443 V_LSO_TCPHDR_LEN(tcp->th_off); 3444 break; 3445 } 3446#endif 3447 default: 3448 panic("%s: CSUM_TSO but no supported IP version " 3449 "(0x%04x)", __func__, eh_type); 3450 } 3451 3452 lso->lso_ctrl = htobe32(ctrl); 3453 lso->ipid_ofst = htobe16(0); 3454 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3455 lso->seqno_offset = htobe32(0); 3456 lso->len = htobe32(pktlen); 3457 3458 cpl = (void *)(lso + 1); 3459 3460 txq->tso_wrs++; 3461 } else 3462 cpl = (void *)(wr + 1); 3463 3464 /* Checksum offload */ 3465 ctrl1 = 0; 3466 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3467 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3468 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3469 CSUM_TCP_IPV6 | CSUM_TSO))) 3470 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3471 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3472 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3473 txq->txcsum++; /* some hardware assistance provided */ 3474 3475 /* VLAN tag insertion */ 3476 if (m->m_flags & M_VLANTAG) { 3477 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3478 txq->vlan_insertion++; 3479 } 3480 3481 /* CPL header */ 3482 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3483 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3484 cpl->pack = 0; 3485 cpl->len = htobe16(pktlen); 3486 cpl->ctrl1 = htobe64(ctrl1); 3487 3488 /* Software descriptor */ 3489 txsd = &txq->sdesc[eq->pidx]; 3490 txsd->desc_used = ndesc; 3491 3492 eq->pending += ndesc; 3493 eq->avail -= ndesc; 3494 eq->pidx += ndesc; 3495 if (eq->pidx >= eq->cap) 3496 eq->pidx -= eq->cap; 3497 3498 /* SGL */ 3499 dst = (void *)(cpl + 1); 3500 if (sgl->nsegs > 0) { 3501 txsd->credits = 1; 3502 txq->sgl_wrs++; 3503 write_sgl_to_txd(eq, sgl, &dst); 3504 } else { 3505 txsd->credits = 0; 3506 txq->imm_wrs++; 3507 for (; m; m = m->m_next) { 3508 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3509#ifdef INVARIANTS 3510 pktlen -= m->m_len; 3511#endif 3512 } 3513#ifdef INVARIANTS 3514 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3515#endif 3516 3517 } 3518 3519 txq->txpkt_wrs++; 3520 return (0); 3521} 3522 3523/* 3524 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3525 * request. It has either been folded into txpkts or txpkts was flushed and m 3526 * has started a new coalesced work request (as the first frame in a fresh 3527 * txpkts). 3528 * 3529 * Returns non-zero to indicate a failure - caller is responsible for 3530 * transmitting m, if there was anything in txpkts it has been flushed. 3531 */ 3532static int 3533add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3534 struct mbuf *m, struct sgl *sgl) 3535{ 3536 struct sge_eq *eq = &txq->eq; 3537 int can_coalesce; 3538 struct tx_sdesc *txsd; 3539 int flits; 3540 3541 TXQ_LOCK_ASSERT_OWNED(txq); 3542 3543 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3544 3545 if (txpkts->npkt > 0) { 3546 flits = TXPKTS_PKT_HDR + sgl->nflits; 3547 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3548 txpkts->nflits + flits <= TX_WR_FLITS && 3549 txpkts->nflits + flits <= eq->avail * 8 && 3550 txpkts->plen + m->m_pkthdr.len < 65536; 3551 3552 if (can_coalesce) { 3553 txpkts->npkt++; 3554 txpkts->nflits += flits; 3555 txpkts->plen += m->m_pkthdr.len; 3556 3557 txsd = &txq->sdesc[eq->pidx]; 3558 txsd->credits++; 3559 3560 return (0); 3561 } 3562 3563 /* 3564 * Couldn't coalesce m into txpkts. The first order of business 3565 * is to send txpkts on its way. Then we'll revisit m. 3566 */ 3567 write_txpkts_wr(txq, txpkts); 3568 } 3569 3570 /* 3571 * Check if we can start a new coalesced tx work request with m as 3572 * the first packet in it. 3573 */ 3574 3575 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3576 3577 flits = TXPKTS_WR_HDR + sgl->nflits; 3578 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3579 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3580 3581 if (can_coalesce == 0) 3582 return (EINVAL); 3583 3584 /* 3585 * Start a fresh coalesced tx WR with m as the first frame in it. 3586 */ 3587 txpkts->npkt = 1; 3588 txpkts->nflits = flits; 3589 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3590 txpkts->plen = m->m_pkthdr.len; 3591 3592 txsd = &txq->sdesc[eq->pidx]; 3593 txsd->credits = 1; 3594 3595 return (0); 3596} 3597 3598/* 3599 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3600 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3601 * coalescing only if sufficient hardware descriptors are available. 3602 */ 3603static void 3604write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3605{ 3606 struct sge_eq *eq = &txq->eq; 3607 struct fw_eth_tx_pkts_wr *wr; 3608 struct tx_sdesc *txsd; 3609 uint32_t ctrl; 3610 int ndesc; 3611 3612 TXQ_LOCK_ASSERT_OWNED(txq); 3613 3614 ndesc = howmany(txpkts->nflits, 8); 3615 3616 wr = (void *)&eq->desc[eq->pidx]; 3617 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3618 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3619 if (eq->avail == ndesc) { 3620 if (!(eq->flags & EQ_CRFLUSHED)) { 3621 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3622 eq->flags |= EQ_CRFLUSHED; 3623 } 3624 eq->flags |= EQ_STALLED; 3625 } 3626 wr->equiq_to_len16 = htobe32(ctrl); 3627 wr->plen = htobe16(txpkts->plen); 3628 wr->npkt = txpkts->npkt; 3629 wr->r3 = wr->type = 0; 3630 3631 /* Everything else already written */ 3632 3633 txsd = &txq->sdesc[eq->pidx]; 3634 txsd->desc_used = ndesc; 3635 3636 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3637 3638 eq->pending += ndesc; 3639 eq->avail -= ndesc; 3640 eq->pidx += ndesc; 3641 if (eq->pidx >= eq->cap) 3642 eq->pidx -= eq->cap; 3643 3644 txq->txpkts_pkts += txpkts->npkt; 3645 txq->txpkts_wrs++; 3646 txpkts->npkt = 0; /* emptied */ 3647} 3648 3649static inline void 3650write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3651 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3652{ 3653 struct ulp_txpkt *ulpmc; 3654 struct ulptx_idata *ulpsc; 3655 struct cpl_tx_pkt_core *cpl; 3656 struct sge_eq *eq = &txq->eq; 3657 uintptr_t flitp, start, end; 3658 uint64_t ctrl; 3659 caddr_t dst; 3660 3661 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3662 3663 start = (uintptr_t)eq->desc; 3664 end = (uintptr_t)eq->spg; 3665 3666 /* Checksum offload */ 3667 ctrl = 0; 3668 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3669 ctrl |= F_TXPKT_IPCSUM_DIS; 3670 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3671 CSUM_TCP_IPV6 | CSUM_TSO))) 3672 ctrl |= F_TXPKT_L4CSUM_DIS; 3673 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3674 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3675 txq->txcsum++; /* some hardware assistance provided */ 3676 3677 /* VLAN tag insertion */ 3678 if (m->m_flags & M_VLANTAG) { 3679 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3680 txq->vlan_insertion++; 3681 } 3682 3683 /* 3684 * The previous packet's SGL must have ended at a 16 byte boundary (this 3685 * is required by the firmware/hardware). It follows that flitp cannot 3686 * wrap around between the ULPTX master command and ULPTX subcommand (8 3687 * bytes each), and that it can not wrap around in the middle of the 3688 * cpl_tx_pkt_core either. 3689 */ 3690 flitp = (uintptr_t)txpkts->flitp; 3691 KASSERT((flitp & 0xf) == 0, 3692 ("%s: last SGL did not end at 16 byte boundary: %p", 3693 __func__, txpkts->flitp)); 3694 3695 /* ULP master command */ 3696 ulpmc = (void *)flitp; 3697 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3698 V_ULP_TXPKT_FID(eq->iqid)); 3699 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3700 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3701 3702 /* ULP subcommand */ 3703 ulpsc = (void *)(ulpmc + 1); 3704 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3705 F_ULP_TX_SC_MORE); 3706 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3707 3708 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3709 if (flitp == end) 3710 flitp = start; 3711 3712 /* CPL_TX_PKT */ 3713 cpl = (void *)flitp; 3714 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3715 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3716 cpl->pack = 0; 3717 cpl->len = htobe16(m->m_pkthdr.len); 3718 cpl->ctrl1 = htobe64(ctrl); 3719 3720 flitp += sizeof(*cpl); 3721 if (flitp == end) 3722 flitp = start; 3723 3724 /* SGL for this frame */ 3725 dst = (caddr_t)flitp; 3726 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3727 txpkts->flitp = (void *)dst; 3728 3729 KASSERT(((uintptr_t)dst & 0xf) == 0, 3730 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3731} 3732 3733/* 3734 * If the SGL ends on an address that is not 16 byte aligned, this function will 3735 * add a 0 filled flit at the end. It returns 1 in that case. 3736 */ 3737static int 3738write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3739{ 3740 __be64 *flitp, *end; 3741 struct ulptx_sgl *usgl; 3742 bus_dma_segment_t *seg; 3743 int i, padded; 3744 3745 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3746 ("%s: bad SGL - nsegs=%d, nflits=%d", 3747 __func__, sgl->nsegs, sgl->nflits)); 3748 3749 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3750 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3751 3752 flitp = (__be64 *)(*to); 3753 end = flitp + sgl->nflits; 3754 seg = &sgl->seg[0]; 3755 usgl = (void *)flitp; 3756 3757 /* 3758 * We start at a 16 byte boundary somewhere inside the tx descriptor 3759 * ring, so we're at least 16 bytes away from the status page. There is 3760 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3761 */ 3762 3763 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3764 V_ULPTX_NSGE(sgl->nsegs)); 3765 usgl->len0 = htobe32(seg->ds_len); 3766 usgl->addr0 = htobe64(seg->ds_addr); 3767 seg++; 3768 3769 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3770 3771 /* Won't wrap around at all */ 3772 3773 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3774 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3775 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3776 } 3777 if (i & 1) 3778 usgl->sge[i / 2].len[1] = htobe32(0); 3779 } else { 3780 3781 /* Will wrap somewhere in the rest of the SGL */ 3782 3783 /* 2 flits already written, write the rest flit by flit */ 3784 flitp = (void *)(usgl + 1); 3785 for (i = 0; i < sgl->nflits - 2; i++) { 3786 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 3787 flitp = (void *)eq->desc; 3788 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 3789 } 3790 end = flitp; 3791 } 3792 3793 if ((uintptr_t)end & 0xf) { 3794 *(uint64_t *)end = 0; 3795 end++; 3796 padded = 1; 3797 } else 3798 padded = 0; 3799 3800 if ((uintptr_t)end == (uintptr_t)eq->spg) 3801 *to = (void *)eq->desc; 3802 else 3803 *to = (void *)end; 3804 3805 return (padded); 3806} 3807 3808static inline void 3809copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 3810{ 3811 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 3812 bcopy(from, *to, len); 3813 (*to) += len; 3814 } else { 3815 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 3816 3817 bcopy(from, *to, portion); 3818 from += portion; 3819 portion = len - portion; /* remaining */ 3820 bcopy(from, (void *)eq->desc, portion); 3821 (*to) = (caddr_t)eq->desc + portion; 3822 } 3823} 3824 3825static inline void 3826ring_eq_db(struct adapter *sc, struct sge_eq *eq) 3827{ 3828 u_int db, pending; 3829 3830 db = eq->doorbells; 3831 pending = eq->pending; 3832 if (pending > 1) 3833 clrbit(&db, DOORBELL_WCWR); 3834 eq->pending = 0; 3835 wmb(); 3836 3837 switch (ffs(db) - 1) { 3838 case DOORBELL_UDB: 3839 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3840 return; 3841 3842 case DOORBELL_WCWR: { 3843 volatile uint64_t *dst, *src; 3844 int i; 3845 3846 /* 3847 * Queues whose 128B doorbell segment fits in the page do not 3848 * use relative qid (udb_qid is always 0). Only queues with 3849 * doorbell segments can do WCWR. 3850 */ 3851 KASSERT(eq->udb_qid == 0 && pending == 1, 3852 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 3853 __func__, eq->doorbells, pending, eq->pidx, eq)); 3854 3855 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 3856 UDBS_DB_OFFSET); 3857 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 3858 src = (void *)&eq->desc[i]; 3859 while (src != (void *)&eq->desc[i + 1]) 3860 *dst++ = *src++; 3861 wmb(); 3862 return; 3863 } 3864 3865 case DOORBELL_UDBWC: 3866 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3867 wmb(); 3868 return; 3869 3870 case DOORBELL_KDB: 3871 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 3872 V_QID(eq->cntxt_id) | V_PIDX(pending)); 3873 return; 3874 } 3875} 3876 3877static inline int 3878reclaimable(struct sge_eq *eq) 3879{ 3880 unsigned int cidx; 3881 3882 cidx = eq->spg->cidx; /* stable snapshot */ 3883 cidx = be16toh(cidx); 3884 3885 if (cidx >= eq->cidx) 3886 return (cidx - eq->cidx); 3887 else 3888 return (cidx + eq->cap - eq->cidx); 3889} 3890 3891/* 3892 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 3893 * many as possible but stop when there are around "n" mbufs to free. 3894 * 3895 * The actual number reclaimed is provided as the return value. 3896 */ 3897static int 3898reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 3899{ 3900 struct tx_sdesc *txsd; 3901 struct tx_maps *txmaps; 3902 struct tx_map *txm; 3903 unsigned int reclaimed, maps; 3904 struct sge_eq *eq = &txq->eq; 3905 3906 TXQ_LOCK_ASSERT_OWNED(txq); 3907 3908 if (can_reclaim == 0) 3909 can_reclaim = reclaimable(eq); 3910 3911 maps = reclaimed = 0; 3912 while (can_reclaim && maps < n) { 3913 int ndesc; 3914 3915 txsd = &txq->sdesc[eq->cidx]; 3916 ndesc = txsd->desc_used; 3917 3918 /* Firmware doesn't return "partial" credits. */ 3919 KASSERT(can_reclaim >= ndesc, 3920 ("%s: unexpected number of credits: %d, %d", 3921 __func__, can_reclaim, ndesc)); 3922 3923 maps += txsd->credits; 3924 3925 reclaimed += ndesc; 3926 can_reclaim -= ndesc; 3927 3928 eq->cidx += ndesc; 3929 if (__predict_false(eq->cidx >= eq->cap)) 3930 eq->cidx -= eq->cap; 3931 } 3932 3933 txmaps = &txq->txmaps; 3934 txm = &txmaps->maps[txmaps->map_cidx]; 3935 if (maps) 3936 prefetch(txm->m); 3937 3938 eq->avail += reclaimed; 3939 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 3940 ("%s: too many descriptors available", __func__)); 3941 3942 txmaps->map_avail += maps; 3943 KASSERT(txmaps->map_avail <= txmaps->map_total, 3944 ("%s: too many maps available", __func__)); 3945 3946 while (maps--) { 3947 struct tx_map *next; 3948 3949 next = txm + 1; 3950 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 3951 next = txmaps->maps; 3952 prefetch(next->m); 3953 3954 bus_dmamap_unload(txq->tx_tag, txm->map); 3955 m_freem(txm->m); 3956 txm->m = NULL; 3957 3958 txm = next; 3959 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 3960 txmaps->map_cidx = 0; 3961 } 3962 3963 return (reclaimed); 3964} 3965 3966static void 3967write_eqflush_wr(struct sge_eq *eq) 3968{ 3969 struct fw_eq_flush_wr *wr; 3970 3971 EQ_LOCK_ASSERT_OWNED(eq); 3972 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 3973 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 3974 3975 wr = (void *)&eq->desc[eq->pidx]; 3976 bzero(wr, sizeof(*wr)); 3977 wr->opcode = FW_EQ_FLUSH_WR; 3978 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 3979 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3980 3981 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 3982 eq->pending++; 3983 eq->avail--; 3984 if (++eq->pidx == eq->cap) 3985 eq->pidx = 0; 3986} 3987 3988static __be64 3989get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 3990{ 3991 int i = (idx / 3) * 2; 3992 3993 switch (idx % 3) { 3994 case 0: { 3995 __be64 rc; 3996 3997 rc = htobe32(sgl[i].ds_len); 3998 if (i + 1 < nsegs) 3999 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4000 4001 return (rc); 4002 } 4003 case 1: 4004 return htobe64(sgl[i].ds_addr); 4005 case 2: 4006 return htobe64(sgl[i + 1].ds_addr); 4007 } 4008 4009 return (0); 4010} 4011 4012static void 4013find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4014{ 4015 int8_t zidx, hwidx, idx; 4016 uint16_t region1, region3; 4017 int spare, spare_needed, n; 4018 struct sw_zone_info *swz; 4019 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4020 4021 /* 4022 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4023 * large enough for the max payload and cluster metadata. Otherwise 4024 * settle for the largest bufsize that leaves enough room in the cluster 4025 * for metadata. 4026 * 4027 * Without buffer packing: Look for the smallest zone which has a 4028 * bufsize large enough for the max payload. Settle for the largest 4029 * bufsize available if there's nothing big enough for max payload. 4030 */ 4031 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4032 swz = &sc->sge.sw_zone_info[0]; 4033 hwidx = -1; 4034 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4035 if (swz->size > largest_rx_cluster) { 4036 if (__predict_true(hwidx != -1)) 4037 break; 4038 4039 /* 4040 * This is a misconfiguration. largest_rx_cluster is 4041 * preventing us from finding a refill source. See 4042 * dev.t5nex.<n>.buffer_sizes to figure out why. 4043 */ 4044 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4045 " refill source for fl %p (dma %u). Ignored.\n", 4046 largest_rx_cluster, fl, maxp); 4047 } 4048 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4049 hwb = &hwb_list[idx]; 4050 spare = swz->size - hwb->size; 4051 if (spare < spare_needed) 4052 continue; 4053 4054 hwidx = idx; /* best option so far */ 4055 if (hwb->size >= maxp) { 4056 4057 if ((fl->flags & FL_BUF_PACKING) == 0) 4058 goto done; /* stop looking (not packing) */ 4059 4060 if (swz->size >= safest_rx_cluster) 4061 goto done; /* stop looking (packing) */ 4062 } 4063 break; /* keep looking, next zone */ 4064 } 4065 } 4066done: 4067 /* A usable hwidx has been located. */ 4068 MPASS(hwidx != -1); 4069 hwb = &hwb_list[hwidx]; 4070 zidx = hwb->zidx; 4071 swz = &sc->sge.sw_zone_info[zidx]; 4072 region1 = 0; 4073 region3 = swz->size - hwb->size; 4074 4075 /* 4076 * Stay within this zone and see if there is a better match when mbuf 4077 * inlining is allowed. Remember that the hwidx's are sorted in 4078 * decreasing order of size (so in increasing order of spare area). 4079 */ 4080 for (idx = hwidx; idx != -1; idx = hwb->next) { 4081 hwb = &hwb_list[idx]; 4082 spare = swz->size - hwb->size; 4083 4084 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4085 break; 4086 if (spare < CL_METADATA_SIZE + MSIZE) 4087 continue; 4088 n = (spare - CL_METADATA_SIZE) / MSIZE; 4089 if (n > howmany(hwb->size, maxp)) 4090 break; 4091 4092 hwidx = idx; 4093 if (fl->flags & FL_BUF_PACKING) { 4094 region1 = n * MSIZE; 4095 region3 = spare - region1; 4096 } else { 4097 region1 = MSIZE; 4098 region3 = spare - region1; 4099 break; 4100 } 4101 } 4102 4103 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4104 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4105 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4106 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4107 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4108 sc->sge.sw_zone_info[zidx].size, 4109 ("%s: bad buffer layout for fl %p, maxp %d. " 4110 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4111 sc->sge.sw_zone_info[zidx].size, region1, 4112 sc->sge.hw_buf_info[hwidx].size, region3)); 4113 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4114 KASSERT(region3 >= CL_METADATA_SIZE, 4115 ("%s: no room for metadata. fl %p, maxp %d; " 4116 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4117 sc->sge.sw_zone_info[zidx].size, region1, 4118 sc->sge.hw_buf_info[hwidx].size, region3)); 4119 KASSERT(region1 % MSIZE == 0, 4120 ("%s: bad mbuf region for fl %p, maxp %d. " 4121 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4122 sc->sge.sw_zone_info[zidx].size, region1, 4123 sc->sge.hw_buf_info[hwidx].size, region3)); 4124 } 4125 4126 fl->cll_def.zidx = zidx; 4127 fl->cll_def.hwidx = hwidx; 4128 fl->cll_def.region1 = region1; 4129 fl->cll_def.region3 = region3; 4130} 4131 4132static void 4133find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4134{ 4135 struct sge *s = &sc->sge; 4136 struct hw_buf_info *hwb; 4137 struct sw_zone_info *swz; 4138 int spare; 4139 int8_t hwidx; 4140 4141 if (fl->flags & FL_BUF_PACKING) 4142 hwidx = s->safe_hwidx2; /* with room for metadata */ 4143 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4144 hwidx = s->safe_hwidx2; 4145 hwb = &s->hw_buf_info[hwidx]; 4146 swz = &s->sw_zone_info[hwb->zidx]; 4147 spare = swz->size - hwb->size; 4148 4149 /* no good if there isn't room for an mbuf as well */ 4150 if (spare < CL_METADATA_SIZE + MSIZE) 4151 hwidx = s->safe_hwidx1; 4152 } else 4153 hwidx = s->safe_hwidx1; 4154 4155 if (hwidx == -1) { 4156 /* No fallback source */ 4157 fl->cll_alt.hwidx = -1; 4158 fl->cll_alt.zidx = -1; 4159 4160 return; 4161 } 4162 4163 hwb = &s->hw_buf_info[hwidx]; 4164 swz = &s->sw_zone_info[hwb->zidx]; 4165 spare = swz->size - hwb->size; 4166 fl->cll_alt.hwidx = hwidx; 4167 fl->cll_alt.zidx = hwb->zidx; 4168 if (allow_mbufs_in_cluster) 4169 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4170 else 4171 fl->cll_alt.region1 = 0; 4172 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4173} 4174 4175static void 4176add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4177{ 4178 mtx_lock(&sc->sfl_lock); 4179 FL_LOCK(fl); 4180 if ((fl->flags & FL_DOOMED) == 0) { 4181 fl->flags |= FL_STARVING; 4182 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4183 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4184 } 4185 FL_UNLOCK(fl); 4186 mtx_unlock(&sc->sfl_lock); 4187} 4188 4189static int 4190handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4191 struct mbuf *m) 4192{ 4193 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4194 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4195 struct adapter *sc = iq->adapter; 4196 struct sge *s = &sc->sge; 4197 struct sge_eq *eq; 4198 4199 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4200 rss->opcode)); 4201 4202 eq = s->eqmap[qid - s->eq_start]; 4203 EQ_LOCK(eq); 4204 KASSERT(eq->flags & EQ_CRFLUSHED, 4205 ("%s: unsolicited egress update", __func__)); 4206 eq->flags &= ~EQ_CRFLUSHED; 4207 eq->egr_update++; 4208 4209 if (__predict_false(eq->flags & EQ_DOOMED)) 4210 wakeup_one(eq); 4211 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4212 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4213 EQ_UNLOCK(eq); 4214 4215 return (0); 4216} 4217 4218/* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4219CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4220 offsetof(struct cpl_fw6_msg, data)); 4221 4222static int 4223handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4224{ 4225 struct adapter *sc = iq->adapter; 4226 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4227 4228 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4229 rss->opcode)); 4230 4231 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4232 const struct rss_header *rss2; 4233 4234 rss2 = (const struct rss_header *)&cpl->data[0]; 4235 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4236 } 4237 4238 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4239} 4240 4241static int 4242sysctl_uint16(SYSCTL_HANDLER_ARGS) 4243{ 4244 uint16_t *id = arg1; 4245 int i = *id; 4246 4247 return sysctl_handle_int(oidp, &i, 0, req); 4248} 4249 4250static int 4251sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4252{ 4253 struct sge *s = arg1; 4254 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4255 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4256 int i, rc; 4257 struct sbuf sb; 4258 char c; 4259 4260 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4261 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4262 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4263 c = '*'; 4264 else 4265 c = '\0'; 4266 4267 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4268 } 4269 sbuf_trim(&sb); 4270 sbuf_finish(&sb); 4271 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4272 sbuf_delete(&sb); 4273 return (rc); 4274} 4275