1/*- 2 * Copyright (c) 2012-2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76}; 77 78/****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89}; 90 91/****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, 110 FW_RI_RES_WR = 0x0c, 111 FW_RI_RDMA_WRITE_WR = 0x14, 112 FW_RI_SEND_WR = 0x15, 113 FW_RI_RDMA_READ_WR = 0x16, 114 FW_RI_RECV_WR = 0x17, 115 FW_RI_BIND_MW_WR = 0x18, 116 FW_RI_FR_NSMR_WR = 0x19, 117 FW_RI_INV_LSTAG_WR = 0x1a, 118 FW_RI_SEND_IMMEDIATE_WR = 0x15, 119 FW_RI_ATOMIC_WR = 0x16, 120 FW_RI_WR = 0x0d, 121 FW_CHNET_IFCONF_WR = 0x6b, 122 FW_RDEV_WR = 0x38, 123 FW_FOISCSI_NODE_WR = 0x60, 124 FW_FOISCSI_CTRL_WR = 0x6a, 125 FW_FOISCSI_CHAP_WR = 0x6c, 126 FW_FCOE_ELS_CT_WR = 0x30, 127 FW_SCSI_WRITE_WR = 0x31, 128 FW_SCSI_READ_WR = 0x32, 129 FW_SCSI_CMD_WR = 0x33, 130 FW_SCSI_ABRT_CLS_WR = 0x34, 131 FW_SCSI_TGT_ACC_WR = 0x35, 132 FW_SCSI_TGT_XMIT_WR = 0x36, 133 FW_SCSI_TGT_RSP_WR = 0x37, 134 FW_POFCOE_TCB_WR = 0x42, 135 FW_POFCOE_ULPTX_WR = 0x43, 136 FW_LASTC2E_WR = 0x70 137}; 138 139/* 140 * Generic work request header flit0 141 */ 142struct fw_wr_hdr { 143 __be32 hi; 144 __be32 lo; 145}; 146 147/* work request opcode (hi) 148 */ 149#define S_FW_WR_OP 24 150#define M_FW_WR_OP 0xff 151#define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 152#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 153 154/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 155 */ 156#define S_FW_WR_ATOMIC 23 157#define M_FW_WR_ATOMIC 0x1 158#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 159#define G_FW_WR_ATOMIC(x) \ 160 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 161#define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 162 163/* flush flag (hi) - firmware flushes flushable work request buffered 164 * in the flow context. 165 */ 166#define S_FW_WR_FLUSH 22 167#define M_FW_WR_FLUSH 0x1 168#define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 169#define G_FW_WR_FLUSH(x) \ 170 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 171#define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 172 173/* completion flag (hi) - firmware generates a cpl_fw6_ack 174 */ 175#define S_FW_WR_COMPL 21 176#define M_FW_WR_COMPL 0x1 177#define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 178#define G_FW_WR_COMPL(x) \ 179 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 180#define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 181 182 183/* work request immediate data lengh (hi) 184 */ 185#define S_FW_WR_IMMDLEN 0 186#define M_FW_WR_IMMDLEN 0xff 187#define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 188#define G_FW_WR_IMMDLEN(x) \ 189 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 190 191/* egress queue status update to associated ingress queue entry (lo) 192 */ 193#define S_FW_WR_EQUIQ 31 194#define M_FW_WR_EQUIQ 0x1 195#define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 196#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 197#define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 198 199/* egress queue status update to egress queue status entry (lo) 200 */ 201#define S_FW_WR_EQUEQ 30 202#define M_FW_WR_EQUEQ 0x1 203#define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 204#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 205#define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 206 207/* flow context identifier (lo) 208 */ 209#define S_FW_WR_FLOWID 8 210#define M_FW_WR_FLOWID 0xfffff 211#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 212#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 213 214/* length in units of 16-bytes (lo) 215 */ 216#define S_FW_WR_LEN16 0 217#define M_FW_WR_LEN16 0xff 218#define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 219#define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 220 221struct fw_frag_wr { 222 __be32 op_to_fragoff16; 223 __be32 flowid_len16; 224 __be64 r4; 225}; 226 227#define S_FW_FRAG_WR_EOF 15 228#define M_FW_FRAG_WR_EOF 0x1 229#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 230#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 231#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 232 233#define S_FW_FRAG_WR_FRAGOFF16 8 234#define M_FW_FRAG_WR_FRAGOFF16 0x7f 235#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 236#define G_FW_FRAG_WR_FRAGOFF16(x) \ 237 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 238 239/* valid filter configurations for compressed tuple 240 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 241 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 242 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 243 * OV - Outer VLAN/VNIC_ID, 244*/ 245#define HW_TPL_FR_MT_M_E_P_FC 0x3C3 246#define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 247#define HW_TPL_FR_MT_M_IV_P_FC 0x38B 248#define HW_TPL_FR_MT_M_OV_P_FC 0x387 249#define HW_TPL_FR_MT_E_PR_T 0x370 250#define HW_TPL_FR_MT_E_PR_P_FC 0X363 251#define HW_TPL_FR_MT_E_T_P_FC 0X353 252#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 253#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 254#define HW_TPL_FR_MT_T_IV_P_FC 0X31B 255#define HW_TPL_FR_MT_T_OV_P_FC 0X317 256#define HW_TPL_FR_M_E_PR_FC 0X2E1 257#define HW_TPL_FR_M_E_T_FC 0X2D1 258#define HW_TPL_FR_M_PR_IV_FC 0X2A9 259#define HW_TPL_FR_M_PR_OV_FC 0X2A5 260#define HW_TPL_FR_M_T_IV_FC 0X299 261#define HW_TPL_FR_M_T_OV_FC 0X295 262#define HW_TPL_FR_E_PR_T_P 0X272 263#define HW_TPL_FR_E_PR_T_FC 0X271 264#define HW_TPL_FR_E_IV_FC 0X249 265#define HW_TPL_FR_E_OV_FC 0X245 266#define HW_TPL_FR_PR_T_IV_FC 0X239 267#define HW_TPL_FR_PR_T_OV_FC 0X235 268#define HW_TPL_FR_IV_OV_FC 0X20D 269#define HW_TPL_MT_M_E_PR 0X1E0 270#define HW_TPL_MT_M_E_T 0X1D0 271#define HW_TPL_MT_E_PR_T_FC 0X171 272#define HW_TPL_MT_E_IV 0X148 273#define HW_TPL_MT_E_OV 0X144 274#define HW_TPL_MT_PR_T_IV 0X138 275#define HW_TPL_MT_PR_T_OV 0X134 276#define HW_TPL_M_E_PR_P 0X0E2 277#define HW_TPL_M_E_T_P 0X0D2 278#define HW_TPL_E_PR_T_P_FC 0X073 279#define HW_TPL_E_IV_P 0X04A 280#define HW_TPL_E_OV_P 0X046 281#define HW_TPL_PR_T_IV_P 0X03A 282#define HW_TPL_PR_T_OV_P 0X036 283 284/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 285enum fw_filter_wr_cookie { 286 FW_FILTER_WR_SUCCESS, 287 FW_FILTER_WR_FLT_ADDED, 288 FW_FILTER_WR_FLT_DELETED, 289 FW_FILTER_WR_SMT_TBL_FULL, 290 FW_FILTER_WR_EINVAL, 291}; 292 293struct fw_filter_wr { 294 __be32 op_pkd; 295 __be32 len16_pkd; 296 __be64 r3; 297 __be32 tid_to_iq; 298 __be32 del_filter_to_l2tix; 299 __be16 ethtype; 300 __be16 ethtypem; 301 __u8 frag_to_ovlan_vldm; 302 __u8 smac_sel; 303 __be16 rx_chan_rx_rpl_iq; 304 __be32 maci_to_matchtypem; 305 __u8 ptcl; 306 __u8 ptclm; 307 __u8 ttyp; 308 __u8 ttypm; 309 __be16 ivlan; 310 __be16 ivlanm; 311 __be16 ovlan; 312 __be16 ovlanm; 313 __u8 lip[16]; 314 __u8 lipm[16]; 315 __u8 fip[16]; 316 __u8 fipm[16]; 317 __be16 lp; 318 __be16 lpm; 319 __be16 fp; 320 __be16 fpm; 321 __be16 r7; 322 __u8 sma[6]; 323}; 324 325#define S_FW_FILTER_WR_TID 12 326#define M_FW_FILTER_WR_TID 0xfffff 327#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 328#define G_FW_FILTER_WR_TID(x) \ 329 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 330 331#define S_FW_FILTER_WR_RQTYPE 11 332#define M_FW_FILTER_WR_RQTYPE 0x1 333#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 334#define G_FW_FILTER_WR_RQTYPE(x) \ 335 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 336#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 337 338#define S_FW_FILTER_WR_NOREPLY 10 339#define M_FW_FILTER_WR_NOREPLY 0x1 340#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 341#define G_FW_FILTER_WR_NOREPLY(x) \ 342 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 343#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 344 345#define S_FW_FILTER_WR_IQ 0 346#define M_FW_FILTER_WR_IQ 0x3ff 347#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 348#define G_FW_FILTER_WR_IQ(x) \ 349 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 350 351#define S_FW_FILTER_WR_DEL_FILTER 31 352#define M_FW_FILTER_WR_DEL_FILTER 0x1 353#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 354#define G_FW_FILTER_WR_DEL_FILTER(x) \ 355 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 356#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 357 358#define S_FW_FILTER_WR_RPTTID 25 359#define M_FW_FILTER_WR_RPTTID 0x1 360#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 361#define G_FW_FILTER_WR_RPTTID(x) \ 362 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 363#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 364 365#define S_FW_FILTER_WR_DROP 24 366#define M_FW_FILTER_WR_DROP 0x1 367#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 368#define G_FW_FILTER_WR_DROP(x) \ 369 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 370#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 371 372#define S_FW_FILTER_WR_DIRSTEER 23 373#define M_FW_FILTER_WR_DIRSTEER 0x1 374#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 375#define G_FW_FILTER_WR_DIRSTEER(x) \ 376 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 377#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 378 379#define S_FW_FILTER_WR_MASKHASH 22 380#define M_FW_FILTER_WR_MASKHASH 0x1 381#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 382#define G_FW_FILTER_WR_MASKHASH(x) \ 383 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 384#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 385 386#define S_FW_FILTER_WR_DIRSTEERHASH 21 387#define M_FW_FILTER_WR_DIRSTEERHASH 0x1 388#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 389#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 390 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 391#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 392 393#define S_FW_FILTER_WR_LPBK 20 394#define M_FW_FILTER_WR_LPBK 0x1 395#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 396#define G_FW_FILTER_WR_LPBK(x) \ 397 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 398#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 399 400#define S_FW_FILTER_WR_DMAC 19 401#define M_FW_FILTER_WR_DMAC 0x1 402#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 403#define G_FW_FILTER_WR_DMAC(x) \ 404 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 405#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 406 407#define S_FW_FILTER_WR_SMAC 18 408#define M_FW_FILTER_WR_SMAC 0x1 409#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 410#define G_FW_FILTER_WR_SMAC(x) \ 411 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 412#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 413 414#define S_FW_FILTER_WR_INSVLAN 17 415#define M_FW_FILTER_WR_INSVLAN 0x1 416#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 417#define G_FW_FILTER_WR_INSVLAN(x) \ 418 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 419#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 420 421#define S_FW_FILTER_WR_RMVLAN 16 422#define M_FW_FILTER_WR_RMVLAN 0x1 423#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 424#define G_FW_FILTER_WR_RMVLAN(x) \ 425 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 426#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 427 428#define S_FW_FILTER_WR_HITCNTS 15 429#define M_FW_FILTER_WR_HITCNTS 0x1 430#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 431#define G_FW_FILTER_WR_HITCNTS(x) \ 432 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 433#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 434 435#define S_FW_FILTER_WR_TXCHAN 13 436#define M_FW_FILTER_WR_TXCHAN 0x3 437#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 438#define G_FW_FILTER_WR_TXCHAN(x) \ 439 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 440 441#define S_FW_FILTER_WR_PRIO 12 442#define M_FW_FILTER_WR_PRIO 0x1 443#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 444#define G_FW_FILTER_WR_PRIO(x) \ 445 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 446#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 447 448#define S_FW_FILTER_WR_L2TIX 0 449#define M_FW_FILTER_WR_L2TIX 0xfff 450#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 451#define G_FW_FILTER_WR_L2TIX(x) \ 452 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 453 454#define S_FW_FILTER_WR_FRAG 7 455#define M_FW_FILTER_WR_FRAG 0x1 456#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 457#define G_FW_FILTER_WR_FRAG(x) \ 458 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 459#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 460 461#define S_FW_FILTER_WR_FRAGM 6 462#define M_FW_FILTER_WR_FRAGM 0x1 463#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 464#define G_FW_FILTER_WR_FRAGM(x) \ 465 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 466#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 467 468#define S_FW_FILTER_WR_IVLAN_VLD 5 469#define M_FW_FILTER_WR_IVLAN_VLD 0x1 470#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 471#define G_FW_FILTER_WR_IVLAN_VLD(x) \ 472 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 473#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 474 475#define S_FW_FILTER_WR_OVLAN_VLD 4 476#define M_FW_FILTER_WR_OVLAN_VLD 0x1 477#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 478#define G_FW_FILTER_WR_OVLAN_VLD(x) \ 479 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 480#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 481 482#define S_FW_FILTER_WR_IVLAN_VLDM 3 483#define M_FW_FILTER_WR_IVLAN_VLDM 0x1 484#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 485#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 486 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 487#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 488 489#define S_FW_FILTER_WR_OVLAN_VLDM 2 490#define M_FW_FILTER_WR_OVLAN_VLDM 0x1 491#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 492#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 493 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 494#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 495 496#define S_FW_FILTER_WR_RX_CHAN 15 497#define M_FW_FILTER_WR_RX_CHAN 0x1 498#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 499#define G_FW_FILTER_WR_RX_CHAN(x) \ 500 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 501#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 502 503#define S_FW_FILTER_WR_RX_RPL_IQ 0 504#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 505#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 506#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 507 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 508 509#define S_FW_FILTER_WR_MACI 23 510#define M_FW_FILTER_WR_MACI 0x1ff 511#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 512#define G_FW_FILTER_WR_MACI(x) \ 513 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 514 515#define S_FW_FILTER_WR_MACIM 14 516#define M_FW_FILTER_WR_MACIM 0x1ff 517#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 518#define G_FW_FILTER_WR_MACIM(x) \ 519 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 520 521#define S_FW_FILTER_WR_FCOE 13 522#define M_FW_FILTER_WR_FCOE 0x1 523#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 524#define G_FW_FILTER_WR_FCOE(x) \ 525 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 526#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 527 528#define S_FW_FILTER_WR_FCOEM 12 529#define M_FW_FILTER_WR_FCOEM 0x1 530#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 531#define G_FW_FILTER_WR_FCOEM(x) \ 532 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 533#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 534 535#define S_FW_FILTER_WR_PORT 9 536#define M_FW_FILTER_WR_PORT 0x7 537#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 538#define G_FW_FILTER_WR_PORT(x) \ 539 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 540 541#define S_FW_FILTER_WR_PORTM 6 542#define M_FW_FILTER_WR_PORTM 0x7 543#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 544#define G_FW_FILTER_WR_PORTM(x) \ 545 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 546 547#define S_FW_FILTER_WR_MATCHTYPE 3 548#define M_FW_FILTER_WR_MATCHTYPE 0x7 549#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 550#define G_FW_FILTER_WR_MATCHTYPE(x) \ 551 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 552 553#define S_FW_FILTER_WR_MATCHTYPEM 0 554#define M_FW_FILTER_WR_MATCHTYPEM 0x7 555#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 556#define G_FW_FILTER_WR_MATCHTYPEM(x) \ 557 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 558 559struct fw_ulptx_wr { 560 __be32 op_to_compl; 561 __be32 flowid_len16; 562 __u64 cookie; 563}; 564 565struct fw_tp_wr { 566 __be32 op_to_immdlen; 567 __be32 flowid_len16; 568 __u64 cookie; 569}; 570 571struct fw_eth_tx_pkt_wr { 572 __be32 op_immdlen; 573 __be32 equiq_to_len16; 574 __be64 r3; 575}; 576 577#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 578#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 579#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 580#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 581 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 582 583struct fw_eth_tx_pkt2_wr { 584 __be32 op_immdlen; 585 __be32 equiq_to_len16; 586 __be32 r3; 587 __be32 L4ChkDisable_to_IpHdrLen; 588}; 589 590#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 591#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 592#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 593#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 594 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 595 596#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 597#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 598#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 599 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 600#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 601 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 602 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 603#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 604 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 605 606#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 607#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 608#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 609 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 610#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 611 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 612 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 613#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 614 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 615 616#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 617#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 618#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 619#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 620 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 621#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 622 623#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 624#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 625#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 626#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 627 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 628 629#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 630#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 631#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 632#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 633 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 634 635#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 636#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 637#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 638#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 639 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 640 641struct fw_eth_tx_pkts_wr { 642 __be32 op_pkd; 643 __be32 equiq_to_len16; 644 __be32 r3; 645 __be16 plen; 646 __u8 npkt; 647 __u8 type; 648}; 649 650enum fw_eth_tx_eo_type { 651 FW_ETH_TX_EO_TYPE_UDPSEG, 652 FW_ETH_TX_EO_TYPE_TCPSEG, 653 FW_ETH_TX_EO_TYPE_NVGRESEG, 654}; 655 656struct fw_eth_tx_eo_wr { 657 __be32 op_immdlen; 658 __be32 equiq_to_len16; 659 __be64 r3; 660 union fw_eth_tx_eo { 661 struct fw_eth_tx_eo_udpseg { 662 __u8 type; 663 __u8 ethlen; 664 __be16 iplen; 665 __u8 udplen; 666 __u8 rtplen; 667 __be16 r4; 668 __be16 mss; 669 __be16 schedpktsize; 670 __be32 plen; 671 } udpseg; 672 struct fw_eth_tx_eo_tcpseg { 673 __u8 type; 674 __u8 ethlen; 675 __be16 iplen; 676 __u8 tcplen; 677 __u8 tsclk_tsoff; 678 __be16 r4; 679 __be16 mss; 680 __be16 r5; 681 __be32 plen; 682 } tcpseg; 683 struct fw_eth_tx_eo_nvgreseg { 684 __u8 type; 685 __u8 iphdroffout; 686 __be16 grehdroff; 687 __be16 iphdroffin; 688 __be16 tcphdroffin; 689 __be16 mss; 690 __be16 r4; 691 __be32 plen; 692 } nvgreseg; 693 } u; 694}; 695 696#define S_FW_ETH_TX_EO_WR_IMMDLEN 0 697#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 698#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 699#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 700 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 701 702#define S_FW_ETH_TX_EO_WR_TSCLK 6 703#define M_FW_ETH_TX_EO_WR_TSCLK 0x3 704#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 705#define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 706 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 707 708#define S_FW_ETH_TX_EO_WR_TSOFF 0 709#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 710#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 711#define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 712 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 713 714struct fw_eq_flush_wr { 715 __u8 opcode; 716 __u8 r1[3]; 717 __be32 equiq_to_len16; 718 __be64 r3; 719}; 720 721struct fw_ofld_connection_wr { 722 __be32 op_compl; 723 __be32 len16_pkd; 724 __u64 cookie; 725 __be64 r2; 726 __be64 r3; 727 struct fw_ofld_connection_le { 728 __be32 version_cpl; 729 __be32 filter; 730 __be32 r1; 731 __be16 lport; 732 __be16 pport; 733 union fw_ofld_connection_leip { 734 struct fw_ofld_connection_le_ipv4 { 735 __be32 pip; 736 __be32 lip; 737 __be64 r0; 738 __be64 r1; 739 __be64 r2; 740 } ipv4; 741 struct fw_ofld_connection_le_ipv6 { 742 __be64 pip_hi; 743 __be64 pip_lo; 744 __be64 lip_hi; 745 __be64 lip_lo; 746 } ipv6; 747 } u; 748 } le; 749 struct fw_ofld_connection_tcb { 750 __be32 t_state_to_astid; 751 __be16 cplrxdataack_cplpassacceptrpl; 752 __be16 rcv_adv; 753 __be32 rcv_nxt; 754 __be32 tx_max; 755 __be64 opt0; 756 __be32 opt2; 757 __be32 r1; 758 __be64 r2; 759 __be64 r3; 760 } tcb; 761}; 762 763#define S_FW_OFLD_CONNECTION_WR_VERSION 31 764#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 765#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 766 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 767#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 768 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 769 M_FW_OFLD_CONNECTION_WR_VERSION) 770#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 771 772#define S_FW_OFLD_CONNECTION_WR_CPL 30 773#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 774#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 775#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 776 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 777#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 778 779#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 780#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 781#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 782 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 783#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 784 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 785 M_FW_OFLD_CONNECTION_WR_T_STATE) 786 787#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 788#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 789#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 790 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 791#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 792 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 793 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 794 795#define S_FW_OFLD_CONNECTION_WR_ASTID 0 796#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 797#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 798 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 799#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 800 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 801 802#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 803#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 804#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 805 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 806#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 807 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 808 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 809#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 810 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 811 812#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 813#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 814#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 815 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 816#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 817 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 818 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 819#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 820 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 821 822enum fw_flowc_mnem_tcpstate { 823 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 824 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 825 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 826 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 827 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 828 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 829 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 830 * will resend FIN - equiv ESTAB 831 */ 832 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 833 * will resend FIN but have 834 * received FIN 835 */ 836 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 837 * will resend FIN but have 838 * received FIN 839 */ 840 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 841 * waiting for FIN 842 */ 843 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 844}; 845 846enum fw_flowc_mnem_eostate { 847 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 848 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 849 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 850 * outstanding payload 851 */ 852 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 853 * discarding outstanding payload 854 */ 855}; 856 857enum fw_flowc_mnem { 858 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 859 FW_FLOWC_MNEM_CH = 1, 860 FW_FLOWC_MNEM_PORT = 2, 861 FW_FLOWC_MNEM_IQID = 3, 862 FW_FLOWC_MNEM_SNDNXT = 4, 863 FW_FLOWC_MNEM_RCVNXT = 5, 864 FW_FLOWC_MNEM_SNDBUF = 6, 865 FW_FLOWC_MNEM_MSS = 7, 866 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 867 FW_FLOWC_MNEM_TCPSTATE = 9, 868 FW_FLOWC_MNEM_EOSTATE = 10, 869 FW_FLOWC_MNEM_SCHEDCLASS = 11, 870 FW_FLOWC_MNEM_DCBPRIO = 12, 871}; 872 873struct fw_flowc_mnemval { 874 __u8 mnemonic; 875 __u8 r4[3]; 876 __be32 val; 877}; 878 879struct fw_flowc_wr { 880 __be32 op_to_nparams; 881 __be32 flowid_len16; 882#ifndef C99_NOT_SUPPORTED 883 struct fw_flowc_mnemval mnemval[0]; 884#endif 885}; 886 887#define S_FW_FLOWC_WR_NPARAMS 0 888#define M_FW_FLOWC_WR_NPARAMS 0xff 889#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 890#define G_FW_FLOWC_WR_NPARAMS(x) \ 891 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 892 893struct fw_ofld_tx_data_wr { 894 __be32 op_to_immdlen; 895 __be32 flowid_len16; 896 __be32 plen; 897 __be32 lsodisable_to_proxy; 898}; 899 900#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 901#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 902#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 903 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 904#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 905 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 906 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 907#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 908 909#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 910#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 911#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 912 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 913#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 914 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 915#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 916 917#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 918#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 919#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 920 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 921#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 922 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 923 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 924#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 925 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 926 927#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 928#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 929#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 930#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 931 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 932#define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 933 934#define S_FW_OFLD_TX_DATA_WR_SAVE 18 935#define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 936#define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 937#define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 938 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 939#define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 940 941#define S_FW_OFLD_TX_DATA_WR_FLUSH 17 942#define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 943#define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 944#define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 945 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 946#define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 947 948#define S_FW_OFLD_TX_DATA_WR_URGENT 16 949#define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 950#define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 951#define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 952 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 953#define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 954 955#define S_FW_OFLD_TX_DATA_WR_MORE 15 956#define M_FW_OFLD_TX_DATA_WR_MORE 0x1 957#define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 958#define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 959 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 960#define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 961 962#define S_FW_OFLD_TX_DATA_WR_SHOVE 14 963#define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 964#define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 965#define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 966 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 967#define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 968 969#define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 970#define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 971#define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 972#define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 973 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 974 975#define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 976#define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 977#define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 978 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 979#define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 980 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 981 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 982 983#define S_FW_OFLD_TX_DATA_WR_PROXY 5 984#define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 985#define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 986#define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 987 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 988#define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 989 990struct fw_cmd_wr { 991 __be32 op_dma; 992 __be32 len16_pkd; 993 __be64 cookie_daddr; 994}; 995 996#define S_FW_CMD_WR_DMA 17 997#define M_FW_CMD_WR_DMA 0x1 998#define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 999#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1000#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1001 1002struct fw_eth_tx_pkt_vm_wr { 1003 __be32 op_immdlen; 1004 __be32 equiq_to_len16; 1005 __be32 r3[2]; 1006 __u8 ethmacdst[6]; 1007 __u8 ethmacsrc[6]; 1008 __be16 ethtype; 1009 __be16 vlantci; 1010}; 1011 1012/****************************************************************************** 1013 * R I W O R K R E Q U E S T s 1014 **************************************/ 1015 1016enum fw_ri_wr_opcode { 1017 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1018 FW_RI_READ_REQ = 0x1, 1019 FW_RI_READ_RESP = 0x2, 1020 FW_RI_SEND = 0x3, 1021 FW_RI_SEND_WITH_INV = 0x4, 1022 FW_RI_SEND_WITH_SE = 0x5, 1023 FW_RI_SEND_WITH_SE_INV = 0x6, 1024 FW_RI_TERMINATE = 0x7, 1025 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1026 FW_RI_BIND_MW = 0x9, 1027 FW_RI_FAST_REGISTER = 0xa, 1028 FW_RI_LOCAL_INV = 0xb, 1029 FW_RI_QP_MODIFY = 0xc, 1030 FW_RI_BYPASS = 0xd, 1031 FW_RI_RECEIVE = 0xe, 1032#if 0 1033 FW_RI_SEND_IMMEDIATE = 0x8, 1034 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1035 FW_RI_ATOMIC_REQUEST = 0xa, 1036 FW_RI_ATOMIC_RESPONSE = 0xb, 1037 1038 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1039 FW_RI_FAST_REGISTER = 0xd, 1040 FW_RI_LOCAL_INV = 0xe, 1041#endif 1042 FW_RI_SGE_EC_CR_RETURN = 0xf 1043}; 1044 1045enum fw_ri_wr_flags { 1046 FW_RI_COMPLETION_FLAG = 0x01, 1047 FW_RI_NOTIFICATION_FLAG = 0x02, 1048 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1049 FW_RI_READ_FENCE_FLAG = 0x08, 1050 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1051 FW_RI_RDMA_READ_INVALIDATE = 0x20 1052}; 1053 1054enum fw_ri_mpa_attrs { 1055 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1056 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1057 FW_RI_MPA_CRC_ENABLE = 0x04, 1058 FW_RI_MPA_IETF_ENABLE = 0x08 1059}; 1060 1061enum fw_ri_qp_caps { 1062 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1063 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1064 FW_RI_QP_BIND_ENABLE = 0x04, 1065 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1066 FW_RI_QP_STAG0_ENABLE = 0x10, 1067 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1068}; 1069 1070enum fw_ri_addr_type { 1071 FW_RI_ZERO_BASED_TO = 0x00, 1072 FW_RI_VA_BASED_TO = 0x01 1073}; 1074 1075enum fw_ri_mem_perms { 1076 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1077 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1078 FW_RI_MEM_ACCESS_REM = 0x03, 1079 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1080 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1081 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1082}; 1083 1084enum fw_ri_stag_type { 1085 FW_RI_STAG_NSMR = 0x00, 1086 FW_RI_STAG_SMR = 0x01, 1087 FW_RI_STAG_MW = 0x02, 1088 FW_RI_STAG_MW_RELAXED = 0x03 1089}; 1090 1091enum fw_ri_data_op { 1092 FW_RI_DATA_IMMD = 0x81, 1093 FW_RI_DATA_DSGL = 0x82, 1094 FW_RI_DATA_ISGL = 0x83 1095}; 1096 1097enum fw_ri_sgl_depth { 1098 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1099 FW_RI_SGL_DEPTH_MAX_RQ = 4 1100}; 1101 1102enum fw_ri_cqe_err { 1103 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1104 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1105 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1106 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1107 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1108 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1109 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1110 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1111 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1112 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1113 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1114 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1115 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1116 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1117 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1118 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1119 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1120 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1121 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1122 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1123 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1124 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1125 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1126 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1127 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1128 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1129 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1130 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1131 1132}; 1133 1134struct fw_ri_dsge_pair { 1135 __be32 len[2]; 1136 __be64 addr[2]; 1137}; 1138 1139struct fw_ri_dsgl { 1140 __u8 op; 1141 __u8 r1; 1142 __be16 nsge; 1143 __be32 len0; 1144 __be64 addr0; 1145#ifndef C99_NOT_SUPPORTED 1146 struct fw_ri_dsge_pair sge[0]; 1147#endif 1148}; 1149 1150struct fw_ri_sge { 1151 __be32 stag; 1152 __be32 len; 1153 __be64 to; 1154}; 1155 1156struct fw_ri_isgl { 1157 __u8 op; 1158 __u8 r1; 1159 __be16 nsge; 1160 __be32 r2; 1161#ifndef C99_NOT_SUPPORTED 1162 struct fw_ri_sge sge[0]; 1163#endif 1164}; 1165 1166struct fw_ri_immd { 1167 __u8 op; 1168 __u8 r1; 1169 __be16 r2; 1170 __be32 immdlen; 1171#ifndef C99_NOT_SUPPORTED 1172 __u8 data[0]; 1173#endif 1174}; 1175 1176struct fw_ri_tpte { 1177 __be32 valid_to_pdid; 1178 __be32 locread_to_qpid; 1179 __be32 nosnoop_pbladdr; 1180 __be32 len_lo; 1181 __be32 va_hi; 1182 __be32 va_lo_fbo; 1183 __be32 dca_mwbcnt_pstag; 1184 __be32 len_hi; 1185}; 1186 1187#define S_FW_RI_TPTE_VALID 31 1188#define M_FW_RI_TPTE_VALID 0x1 1189#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1190#define G_FW_RI_TPTE_VALID(x) \ 1191 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1192#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1193 1194#define S_FW_RI_TPTE_STAGKEY 23 1195#define M_FW_RI_TPTE_STAGKEY 0xff 1196#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1197#define G_FW_RI_TPTE_STAGKEY(x) \ 1198 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1199 1200#define S_FW_RI_TPTE_STAGSTATE 22 1201#define M_FW_RI_TPTE_STAGSTATE 0x1 1202#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1203#define G_FW_RI_TPTE_STAGSTATE(x) \ 1204 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1205#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1206 1207#define S_FW_RI_TPTE_STAGTYPE 20 1208#define M_FW_RI_TPTE_STAGTYPE 0x3 1209#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1210#define G_FW_RI_TPTE_STAGTYPE(x) \ 1211 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1212 1213#define S_FW_RI_TPTE_PDID 0 1214#define M_FW_RI_TPTE_PDID 0xfffff 1215#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1216#define G_FW_RI_TPTE_PDID(x) \ 1217 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1218 1219#define S_FW_RI_TPTE_PERM 28 1220#define M_FW_RI_TPTE_PERM 0xf 1221#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1222#define G_FW_RI_TPTE_PERM(x) \ 1223 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1224 1225#define S_FW_RI_TPTE_REMINVDIS 27 1226#define M_FW_RI_TPTE_REMINVDIS 0x1 1227#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1228#define G_FW_RI_TPTE_REMINVDIS(x) \ 1229 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1230#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1231 1232#define S_FW_RI_TPTE_ADDRTYPE 26 1233#define M_FW_RI_TPTE_ADDRTYPE 1 1234#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1235#define G_FW_RI_TPTE_ADDRTYPE(x) \ 1236 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1237#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1238 1239#define S_FW_RI_TPTE_MWBINDEN 25 1240#define M_FW_RI_TPTE_MWBINDEN 0x1 1241#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1242#define G_FW_RI_TPTE_MWBINDEN(x) \ 1243 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1244#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1245 1246#define S_FW_RI_TPTE_PS 20 1247#define M_FW_RI_TPTE_PS 0x1f 1248#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1249#define G_FW_RI_TPTE_PS(x) \ 1250 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1251 1252#define S_FW_RI_TPTE_QPID 0 1253#define M_FW_RI_TPTE_QPID 0xfffff 1254#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1255#define G_FW_RI_TPTE_QPID(x) \ 1256 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1257 1258#define S_FW_RI_TPTE_NOSNOOP 31 1259#define M_FW_RI_TPTE_NOSNOOP 0x1 1260#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1261#define G_FW_RI_TPTE_NOSNOOP(x) \ 1262 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1263#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1264 1265#define S_FW_RI_TPTE_PBLADDR 0 1266#define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1267#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1268#define G_FW_RI_TPTE_PBLADDR(x) \ 1269 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1270 1271#define S_FW_RI_TPTE_DCA 24 1272#define M_FW_RI_TPTE_DCA 0x1f 1273#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1274#define G_FW_RI_TPTE_DCA(x) \ 1275 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1276 1277#define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1278#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1279#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1280 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1281#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1282 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1283 1284enum fw_ri_cqe_rxtx { 1285 FW_RI_CQE_RXTX_RX = 0x0, 1286 FW_RI_CQE_RXTX_TX = 0x1, 1287}; 1288 1289struct fw_ri_cqe { 1290 union fw_ri_rxtx { 1291 struct fw_ri_scqe { 1292 __be32 qpid_n_stat_rxtx_type; 1293 __be32 plen; 1294 __be32 reserved; 1295 __be32 wrid; 1296 } scqe; 1297 struct fw_ri_rcqe { 1298 __be32 qpid_n_stat_rxtx_type; 1299 __be32 plen; 1300 __be32 stag; 1301 __be32 msn; 1302 } rcqe; 1303 } u; 1304}; 1305 1306#define S_FW_RI_CQE_QPID 12 1307#define M_FW_RI_CQE_QPID 0xfffff 1308#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1309#define G_FW_RI_CQE_QPID(x) \ 1310 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1311 1312#define S_FW_RI_CQE_NOTIFY 10 1313#define M_FW_RI_CQE_NOTIFY 0x1 1314#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1315#define G_FW_RI_CQE_NOTIFY(x) \ 1316 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1317 1318#define S_FW_RI_CQE_STATUS 5 1319#define M_FW_RI_CQE_STATUS 0x1f 1320#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1321#define G_FW_RI_CQE_STATUS(x) \ 1322 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1323 1324 1325#define S_FW_RI_CQE_RXTX 4 1326#define M_FW_RI_CQE_RXTX 0x1 1327#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1328#define G_FW_RI_CQE_RXTX(x) \ 1329 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1330 1331#define S_FW_RI_CQE_TYPE 0 1332#define M_FW_RI_CQE_TYPE 0xf 1333#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1334#define G_FW_RI_CQE_TYPE(x) \ 1335 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1336 1337enum fw_ri_res_type { 1338 FW_RI_RES_TYPE_SQ, 1339 FW_RI_RES_TYPE_RQ, 1340 FW_RI_RES_TYPE_CQ, 1341}; 1342 1343enum fw_ri_res_op { 1344 FW_RI_RES_OP_WRITE, 1345 FW_RI_RES_OP_RESET, 1346}; 1347 1348struct fw_ri_res { 1349 union fw_ri_restype { 1350 struct fw_ri_res_sqrq { 1351 __u8 restype; 1352 __u8 op; 1353 __be16 r3; 1354 __be32 eqid; 1355 __be32 r4[2]; 1356 __be32 fetchszm_to_iqid; 1357 __be32 dcaen_to_eqsize; 1358 __be64 eqaddr; 1359 } sqrq; 1360 struct fw_ri_res_cq { 1361 __u8 restype; 1362 __u8 op; 1363 __be16 r3; 1364 __be32 iqid; 1365 __be32 r4[2]; 1366 __be32 iqandst_to_iqandstindex; 1367 __be16 iqdroprss_to_iqesize; 1368 __be16 iqsize; 1369 __be64 iqaddr; 1370 __be32 iqns_iqro; 1371 __be32 r6_lo; 1372 __be64 r7; 1373 } cq; 1374 } u; 1375}; 1376 1377struct fw_ri_res_wr { 1378 __be32 op_nres; 1379 __be32 len16_pkd; 1380 __u64 cookie; 1381#ifndef C99_NOT_SUPPORTED 1382 struct fw_ri_res res[0]; 1383#endif 1384}; 1385 1386#define S_FW_RI_RES_WR_NRES 0 1387#define M_FW_RI_RES_WR_NRES 0xff 1388#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1389#define G_FW_RI_RES_WR_NRES(x) \ 1390 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1391 1392#define S_FW_RI_RES_WR_FETCHSZM 26 1393#define M_FW_RI_RES_WR_FETCHSZM 0x1 1394#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1395#define G_FW_RI_RES_WR_FETCHSZM(x) \ 1396 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1397#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1398 1399#define S_FW_RI_RES_WR_STATUSPGNS 25 1400#define M_FW_RI_RES_WR_STATUSPGNS 0x1 1401#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1402#define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1403 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1404#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1405 1406#define S_FW_RI_RES_WR_STATUSPGRO 24 1407#define M_FW_RI_RES_WR_STATUSPGRO 0x1 1408#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1409#define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1410 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1411#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1412 1413#define S_FW_RI_RES_WR_FETCHNS 23 1414#define M_FW_RI_RES_WR_FETCHNS 0x1 1415#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1416#define G_FW_RI_RES_WR_FETCHNS(x) \ 1417 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1418#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1419 1420#define S_FW_RI_RES_WR_FETCHRO 22 1421#define M_FW_RI_RES_WR_FETCHRO 0x1 1422#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1423#define G_FW_RI_RES_WR_FETCHRO(x) \ 1424 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1425#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1426 1427#define S_FW_RI_RES_WR_HOSTFCMODE 20 1428#define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1429#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1430#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1431 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1432 1433#define S_FW_RI_RES_WR_CPRIO 19 1434#define M_FW_RI_RES_WR_CPRIO 0x1 1435#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1436#define G_FW_RI_RES_WR_CPRIO(x) \ 1437 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1438#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1439 1440#define S_FW_RI_RES_WR_ONCHIP 18 1441#define M_FW_RI_RES_WR_ONCHIP 0x1 1442#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1443#define G_FW_RI_RES_WR_ONCHIP(x) \ 1444 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1445#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1446 1447#define S_FW_RI_RES_WR_PCIECHN 16 1448#define M_FW_RI_RES_WR_PCIECHN 0x3 1449#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1450#define G_FW_RI_RES_WR_PCIECHN(x) \ 1451 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1452 1453#define S_FW_RI_RES_WR_IQID 0 1454#define M_FW_RI_RES_WR_IQID 0xffff 1455#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1456#define G_FW_RI_RES_WR_IQID(x) \ 1457 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1458 1459#define S_FW_RI_RES_WR_DCAEN 31 1460#define M_FW_RI_RES_WR_DCAEN 0x1 1461#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1462#define G_FW_RI_RES_WR_DCAEN(x) \ 1463 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1464#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1465 1466#define S_FW_RI_RES_WR_DCACPU 26 1467#define M_FW_RI_RES_WR_DCACPU 0x1f 1468#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1469#define G_FW_RI_RES_WR_DCACPU(x) \ 1470 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1471 1472#define S_FW_RI_RES_WR_FBMIN 23 1473#define M_FW_RI_RES_WR_FBMIN 0x7 1474#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1475#define G_FW_RI_RES_WR_FBMIN(x) \ 1476 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1477 1478#define S_FW_RI_RES_WR_FBMAX 20 1479#define M_FW_RI_RES_WR_FBMAX 0x7 1480#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1481#define G_FW_RI_RES_WR_FBMAX(x) \ 1482 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1483 1484#define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1485#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1486#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1487#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1488 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1489#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1490 1491#define S_FW_RI_RES_WR_CIDXFTHRESH 16 1492#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1493#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1494#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1495 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1496 1497#define S_FW_RI_RES_WR_EQSIZE 0 1498#define M_FW_RI_RES_WR_EQSIZE 0xffff 1499#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1500#define G_FW_RI_RES_WR_EQSIZE(x) \ 1501 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1502 1503#define S_FW_RI_RES_WR_IQANDST 15 1504#define M_FW_RI_RES_WR_IQANDST 0x1 1505#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1506#define G_FW_RI_RES_WR_IQANDST(x) \ 1507 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1508#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1509 1510#define S_FW_RI_RES_WR_IQANUS 14 1511#define M_FW_RI_RES_WR_IQANUS 0x1 1512#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1513#define G_FW_RI_RES_WR_IQANUS(x) \ 1514 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1515#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1516 1517#define S_FW_RI_RES_WR_IQANUD 12 1518#define M_FW_RI_RES_WR_IQANUD 0x3 1519#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1520#define G_FW_RI_RES_WR_IQANUD(x) \ 1521 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1522 1523#define S_FW_RI_RES_WR_IQANDSTINDEX 0 1524#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1525#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1526#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1527 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1528 1529#define S_FW_RI_RES_WR_IQDROPRSS 15 1530#define M_FW_RI_RES_WR_IQDROPRSS 0x1 1531#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1532#define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1533 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1534#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1535 1536#define S_FW_RI_RES_WR_IQGTSMODE 14 1537#define M_FW_RI_RES_WR_IQGTSMODE 0x1 1538#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1539#define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1540 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1541#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1542 1543#define S_FW_RI_RES_WR_IQPCIECH 12 1544#define M_FW_RI_RES_WR_IQPCIECH 0x3 1545#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1546#define G_FW_RI_RES_WR_IQPCIECH(x) \ 1547 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1548 1549#define S_FW_RI_RES_WR_IQDCAEN 11 1550#define M_FW_RI_RES_WR_IQDCAEN 0x1 1551#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1552#define G_FW_RI_RES_WR_IQDCAEN(x) \ 1553 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1554#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1555 1556#define S_FW_RI_RES_WR_IQDCACPU 6 1557#define M_FW_RI_RES_WR_IQDCACPU 0x1f 1558#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1559#define G_FW_RI_RES_WR_IQDCACPU(x) \ 1560 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1561 1562#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1563#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1564#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1565 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1566#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1567 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1568 1569#define S_FW_RI_RES_WR_IQO 3 1570#define M_FW_RI_RES_WR_IQO 0x1 1571#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1572#define G_FW_RI_RES_WR_IQO(x) \ 1573 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1574#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1575 1576#define S_FW_RI_RES_WR_IQCPRIO 2 1577#define M_FW_RI_RES_WR_IQCPRIO 0x1 1578#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1579#define G_FW_RI_RES_WR_IQCPRIO(x) \ 1580 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1581#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1582 1583#define S_FW_RI_RES_WR_IQESIZE 0 1584#define M_FW_RI_RES_WR_IQESIZE 0x3 1585#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1586#define G_FW_RI_RES_WR_IQESIZE(x) \ 1587 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1588 1589#define S_FW_RI_RES_WR_IQNS 31 1590#define M_FW_RI_RES_WR_IQNS 0x1 1591#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1592#define G_FW_RI_RES_WR_IQNS(x) \ 1593 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1594#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1595 1596#define S_FW_RI_RES_WR_IQRO 30 1597#define M_FW_RI_RES_WR_IQRO 0x1 1598#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1599#define G_FW_RI_RES_WR_IQRO(x) \ 1600 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1601#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1602 1603struct fw_ri_rdma_write_wr { 1604 __u8 opcode; 1605 __u8 flags; 1606 __u16 wrid; 1607 __u8 r1[3]; 1608 __u8 len16; 1609 __be64 r2; 1610 __be32 plen; 1611 __be32 stag_sink; 1612 __be64 to_sink; 1613#ifndef C99_NOT_SUPPORTED 1614 union { 1615 struct fw_ri_immd immd_src[0]; 1616 struct fw_ri_isgl isgl_src[0]; 1617 } u; 1618#endif 1619}; 1620 1621struct fw_ri_send_wr { 1622 __u8 opcode; 1623 __u8 flags; 1624 __u16 wrid; 1625 __u8 r1[3]; 1626 __u8 len16; 1627 __be32 sendop_pkd; 1628 __be32 stag_inv; 1629 __be32 plen; 1630 __be32 r3; 1631 __be64 r4; 1632#ifndef C99_NOT_SUPPORTED 1633 union { 1634 struct fw_ri_immd immd_src[0]; 1635 struct fw_ri_isgl isgl_src[0]; 1636 } u; 1637#endif 1638}; 1639 1640#define S_FW_RI_SEND_WR_SENDOP 0 1641#define M_FW_RI_SEND_WR_SENDOP 0xf 1642#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1643#define G_FW_RI_SEND_WR_SENDOP(x) \ 1644 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1645 1646struct fw_ri_rdma_read_wr { 1647 __u8 opcode; 1648 __u8 flags; 1649 __u16 wrid; 1650 __u8 r1[3]; 1651 __u8 len16; 1652 __be64 r2; 1653 __be32 stag_sink; 1654 __be32 to_sink_hi; 1655 __be32 to_sink_lo; 1656 __be32 plen; 1657 __be32 stag_src; 1658 __be32 to_src_hi; 1659 __be32 to_src_lo; 1660 __be32 r5; 1661}; 1662 1663struct fw_ri_recv_wr { 1664 __u8 opcode; 1665 __u8 r1; 1666 __u16 wrid; 1667 __u8 r2[3]; 1668 __u8 len16; 1669 struct fw_ri_isgl isgl; 1670}; 1671 1672struct fw_ri_bind_mw_wr { 1673 __u8 opcode; 1674 __u8 flags; 1675 __u16 wrid; 1676 __u8 r1[3]; 1677 __u8 len16; 1678 __u8 qpbinde_to_dcacpu; 1679 __u8 pgsz_shift; 1680 __u8 addr_type; 1681 __u8 mem_perms; 1682 __be32 stag_mr; 1683 __be32 stag_mw; 1684 __be32 r3; 1685 __be64 len_mw; 1686 __be64 va_fbo; 1687 __be64 r4; 1688}; 1689 1690#define S_FW_RI_BIND_MW_WR_QPBINDE 6 1691#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1692#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1693#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1694 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1695#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1696 1697#define S_FW_RI_BIND_MW_WR_NS 5 1698#define M_FW_RI_BIND_MW_WR_NS 0x1 1699#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1700#define G_FW_RI_BIND_MW_WR_NS(x) \ 1701 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1702#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1703 1704#define S_FW_RI_BIND_MW_WR_DCACPU 0 1705#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1706#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1707#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1708 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1709 1710struct fw_ri_fr_nsmr_wr { 1711 __u8 opcode; 1712 __u8 flags; 1713 __u16 wrid; 1714 __u8 r1[3]; 1715 __u8 len16; 1716 __u8 qpbinde_to_dcacpu; 1717 __u8 pgsz_shift; 1718 __u8 addr_type; 1719 __u8 mem_perms; 1720 __be32 stag; 1721 __be32 len_hi; 1722 __be32 len_lo; 1723 __be32 va_hi; 1724 __be32 va_lo_fbo; 1725}; 1726 1727#define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1728#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1729#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1730#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1731 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1732#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1733 1734#define S_FW_RI_FR_NSMR_WR_NS 5 1735#define M_FW_RI_FR_NSMR_WR_NS 0x1 1736#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1737#define G_FW_RI_FR_NSMR_WR_NS(x) \ 1738 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1739#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1740 1741#define S_FW_RI_FR_NSMR_WR_DCACPU 0 1742#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1743#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1744#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1745 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1746 1747struct fw_ri_inv_lstag_wr { 1748 __u8 opcode; 1749 __u8 flags; 1750 __u16 wrid; 1751 __u8 r1[3]; 1752 __u8 len16; 1753 __be32 r2; 1754 __be32 stag_inv; 1755}; 1756 1757struct fw_ri_send_immediate_wr { 1758 __u8 opcode; 1759 __u8 flags; 1760 __u16 wrid; 1761 __u8 r1[3]; 1762 __u8 len16; 1763 __be32 sendimmop_pkd; 1764 __be32 r3; 1765 __be32 plen; 1766 __be32 r4; 1767 __be64 r5; 1768#ifndef C99_NOT_SUPPORTED 1769 struct fw_ri_immd immd_src[0]; 1770#endif 1771}; 1772 1773#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1774#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1775#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1776 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1777#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1778 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1779 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1780 1781enum fw_ri_atomic_op { 1782 FW_RI_ATOMIC_OP_FETCHADD, 1783 FW_RI_ATOMIC_OP_SWAP, 1784 FW_RI_ATOMIC_OP_CMDSWAP, 1785}; 1786 1787struct fw_ri_atomic_wr { 1788 __u8 opcode; 1789 __u8 flags; 1790 __u16 wrid; 1791 __u8 r1[3]; 1792 __u8 len16; 1793 __be32 atomicop_pkd; 1794 __be64 r3; 1795 __be32 aopcode_pkd; 1796 __be32 reqid; 1797 __be32 stag; 1798 __be32 to_hi; 1799 __be32 to_lo; 1800 __be32 addswap_data_hi; 1801 __be32 addswap_data_lo; 1802 __be32 addswap_mask_hi; 1803 __be32 addswap_mask_lo; 1804 __be32 compare_data_hi; 1805 __be32 compare_data_lo; 1806 __be32 compare_mask_hi; 1807 __be32 compare_mask_lo; 1808 __be32 r5; 1809}; 1810 1811#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1812#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1813#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1814#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1815 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1816 1817#define S_FW_RI_ATOMIC_WR_AOPCODE 0 1818#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1819#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1820#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1821 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1822 1823enum fw_ri_type { 1824 FW_RI_TYPE_INIT, 1825 FW_RI_TYPE_FINI, 1826 FW_RI_TYPE_TERMINATE 1827}; 1828 1829enum fw_ri_init_p2ptype { 1830 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1831 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1832 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1833 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1834 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1835 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1836 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1837}; 1838 1839struct fw_ri_wr { 1840 __be32 op_compl; 1841 __be32 flowid_len16; 1842 __u64 cookie; 1843 union fw_ri { 1844 struct fw_ri_init { 1845 __u8 type; 1846 __u8 mpareqbit_p2ptype; 1847 __u8 r4[2]; 1848 __u8 mpa_attrs; 1849 __u8 qp_caps; 1850 __be16 nrqe; 1851 __be32 pdid; 1852 __be32 qpid; 1853 __be32 sq_eqid; 1854 __be32 rq_eqid; 1855 __be32 scqid; 1856 __be32 rcqid; 1857 __be32 ord_max; 1858 __be32 ird_max; 1859 __be32 iss; 1860 __be32 irs; 1861 __be32 hwrqsize; 1862 __be32 hwrqaddr; 1863 __be64 r5; 1864 union fw_ri_init_p2p { 1865 struct fw_ri_rdma_write_wr write; 1866 struct fw_ri_rdma_read_wr read; 1867 struct fw_ri_send_wr send; 1868 } u; 1869 } init; 1870 struct fw_ri_fini { 1871 __u8 type; 1872 __u8 r3[7]; 1873 __be64 r4; 1874 } fini; 1875 struct fw_ri_terminate { 1876 __u8 type; 1877 __u8 r3[3]; 1878 __be32 immdlen; 1879 __u8 termmsg[40]; 1880 } terminate; 1881 } u; 1882}; 1883 1884#define S_FW_RI_WR_MPAREQBIT 7 1885#define M_FW_RI_WR_MPAREQBIT 0x1 1886#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1887#define G_FW_RI_WR_MPAREQBIT(x) \ 1888 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1889#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1890 1891#define S_FW_RI_WR_0BRRBIT 6 1892#define M_FW_RI_WR_0BRRBIT 0x1 1893#define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1894#define G_FW_RI_WR_0BRRBIT(x) \ 1895 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1896#define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1897 1898#define S_FW_RI_WR_P2PTYPE 0 1899#define M_FW_RI_WR_P2PTYPE 0xf 1900#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1901#define G_FW_RI_WR_P2PTYPE(x) \ 1902 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1903 1904/****************************************************************************** 1905 * F O i S C S I W O R K R E Q U E S T s 1906 *********************************************/ 1907 1908#define FW_FOISCSI_NAME_MAX_LEN 224 1909#define FW_FOISCSI_ALIAS_MAX_LEN 224 1910#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1911#define FW_FOISCSI_INIT_NODE_MAX 8 1912 1913enum fw_chnet_ifconf_wr_subop { 1914 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1915 1916 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1917 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1918 1919 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1920 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1921 1922 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1923 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1924 1925 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1926 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1927 1928 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1929 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1930 1931 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1932 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1933 1934 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1935}; 1936 1937struct fw_chnet_ifconf_wr { 1938 __be32 op_compl; 1939 __be32 flowid_len16; 1940 __be64 cookie; 1941 __be32 if_flowid; 1942 __u8 idx; 1943 __u8 subop; 1944 __u8 retval; 1945 __u8 r2; 1946 __be64 r3; 1947 struct fw_chnet_ifconf_params { 1948 __be32 r0; 1949 __be16 vlanid; 1950 __be16 mtu; 1951 union fw_chnet_ifconf_addr_type { 1952 struct fw_chnet_ifconf_ipv4 { 1953 __be32 addr; 1954 __be32 mask; 1955 __be32 router; 1956 __be32 r0; 1957 __be64 r1; 1958 } ipv4; 1959 struct fw_chnet_ifconf_ipv6 { 1960 __be64 linklocal_lo; 1961 __be64 linklocal_hi; 1962 __be64 router_hi; 1963 __be64 router_lo; 1964 __be64 aconf_hi; 1965 __be64 aconf_lo; 1966 __be64 linklocal_aconf_hi; 1967 __be64 linklocal_aconf_lo; 1968 __be64 router_aconf_hi; 1969 __be64 router_aconf_lo; 1970 __be64 r0; 1971 } ipv6; 1972 } in_attr; 1973 } param; 1974}; 1975 1976enum fw_foiscsi_node_type { 1977 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1978 FW_FOISCSI_NODE_TYPE_TARGET, 1979}; 1980 1981enum fw_foiscsi_session_type { 1982 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1983 FW_FOISCSI_SESSION_TYPE_NORMAL, 1984}; 1985 1986enum fw_foiscsi_auth_policy { 1987 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1988 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1989}; 1990 1991enum fw_foiscsi_auth_method { 1992 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1993 FW_FOISCSI_AUTH_METHOD_CHAP, 1994 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1995 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1996}; 1997 1998enum fw_foiscsi_digest_type { 1999 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2000 FW_FOISCSI_DIGEST_TYPE_CRC32, 2001 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2002 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2003}; 2004 2005enum fw_foiscsi_wr_subop { 2006 FW_FOISCSI_WR_SUBOP_ADD = 1, 2007 FW_FOISCSI_WR_SUBOP_DEL = 2, 2008 FW_FOISCSI_WR_SUBOP_MOD = 4, 2009}; 2010 2011enum fw_foiscsi_ctrl_state { 2012 FW_FOISCSI_CTRL_STATE_FREE = 0, 2013 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2014 FW_FOISCSI_CTRL_STATE_FAILED, 2015 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2016 FW_FOISCSI_CTRL_STATE_REDIRECT, 2017}; 2018 2019struct fw_rdev_wr { 2020 __be32 op_to_immdlen; 2021 __be32 alloc_to_len16; 2022 __be64 cookie; 2023 __u8 protocol; 2024 __u8 event_cause; 2025 __u8 cur_state; 2026 __u8 prev_state; 2027 __be32 flags_to_assoc_flowid; 2028 union rdev_entry { 2029 struct fcoe_rdev_entry { 2030 __be32 flowid; 2031 __u8 protocol; 2032 __u8 event_cause; 2033 __u8 flags; 2034 __u8 rjt_reason; 2035 __u8 cur_login_st; 2036 __u8 prev_login_st; 2037 __be16 rcv_fr_sz; 2038 __u8 rd_xfer_rdy_to_rport_type; 2039 __u8 vft_to_qos; 2040 __u8 org_proc_assoc_to_acc_rsp_code; 2041 __u8 enh_disc_to_tgt; 2042 __u8 wwnn[8]; 2043 __u8 wwpn[8]; 2044 __be16 iqid; 2045 __u8 fc_oui[3]; 2046 __u8 r_id[3]; 2047 } fcoe_rdev; 2048 struct iscsi_rdev_entry { 2049 __be32 flowid; 2050 __u8 protocol; 2051 __u8 event_cause; 2052 __u8 flags; 2053 __u8 r3; 2054 __be16 iscsi_opts; 2055 __be16 tcp_opts; 2056 __be16 ip_opts; 2057 __be16 max_rcv_len; 2058 __be16 max_snd_len; 2059 __be16 first_brst_len; 2060 __be16 max_brst_len; 2061 __be16 r4; 2062 __be16 def_time2wait; 2063 __be16 def_time2ret; 2064 __be16 nop_out_intrvl; 2065 __be16 non_scsi_to; 2066 __be16 isid; 2067 __be16 tsid; 2068 __be16 port; 2069 __be16 tpgt; 2070 __u8 r5[6]; 2071 __be16 iqid; 2072 } iscsi_rdev; 2073 } u; 2074}; 2075 2076#define S_FW_RDEV_WR_IMMDLEN 0 2077#define M_FW_RDEV_WR_IMMDLEN 0xff 2078#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2079#define G_FW_RDEV_WR_IMMDLEN(x) \ 2080 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2081 2082#define S_FW_RDEV_WR_ALLOC 31 2083#define M_FW_RDEV_WR_ALLOC 0x1 2084#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2085#define G_FW_RDEV_WR_ALLOC(x) \ 2086 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2087#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2088 2089#define S_FW_RDEV_WR_FREE 30 2090#define M_FW_RDEV_WR_FREE 0x1 2091#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2092#define G_FW_RDEV_WR_FREE(x) \ 2093 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2094#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2095 2096#define S_FW_RDEV_WR_MODIFY 29 2097#define M_FW_RDEV_WR_MODIFY 0x1 2098#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2099#define G_FW_RDEV_WR_MODIFY(x) \ 2100 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2101#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2102 2103#define S_FW_RDEV_WR_FLOWID 8 2104#define M_FW_RDEV_WR_FLOWID 0xfffff 2105#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2106#define G_FW_RDEV_WR_FLOWID(x) \ 2107 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2108 2109#define S_FW_RDEV_WR_LEN16 0 2110#define M_FW_RDEV_WR_LEN16 0xff 2111#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2112#define G_FW_RDEV_WR_LEN16(x) \ 2113 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2114 2115#define S_FW_RDEV_WR_FLAGS 24 2116#define M_FW_RDEV_WR_FLAGS 0xff 2117#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2118#define G_FW_RDEV_WR_FLAGS(x) \ 2119 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2120 2121#define S_FW_RDEV_WR_GET_NEXT 20 2122#define M_FW_RDEV_WR_GET_NEXT 0xf 2123#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2124#define G_FW_RDEV_WR_GET_NEXT(x) \ 2125 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2126 2127#define S_FW_RDEV_WR_ASSOC_FLOWID 0 2128#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2129#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2130#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2131 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2132 2133#define S_FW_RDEV_WR_RJT 7 2134#define M_FW_RDEV_WR_RJT 0x1 2135#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2136#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2137#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2138 2139#define S_FW_RDEV_WR_REASON 0 2140#define M_FW_RDEV_WR_REASON 0x7f 2141#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2142#define G_FW_RDEV_WR_REASON(x) \ 2143 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2144 2145#define S_FW_RDEV_WR_RD_XFER_RDY 7 2146#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2147#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2148#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2149 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2150#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2151 2152#define S_FW_RDEV_WR_WR_XFER_RDY 6 2153#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2154#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2155#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2156 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2157#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2158 2159#define S_FW_RDEV_WR_FC_SP 5 2160#define M_FW_RDEV_WR_FC_SP 0x1 2161#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2162#define G_FW_RDEV_WR_FC_SP(x) \ 2163 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2164#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2165 2166#define S_FW_RDEV_WR_RPORT_TYPE 0 2167#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2168#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2169#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2170 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2171 2172#define S_FW_RDEV_WR_VFT 7 2173#define M_FW_RDEV_WR_VFT 0x1 2174#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2175#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2176#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2177 2178#define S_FW_RDEV_WR_NPIV 6 2179#define M_FW_RDEV_WR_NPIV 0x1 2180#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2181#define G_FW_RDEV_WR_NPIV(x) \ 2182 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2183#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2184 2185#define S_FW_RDEV_WR_CLASS 4 2186#define M_FW_RDEV_WR_CLASS 0x3 2187#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2188#define G_FW_RDEV_WR_CLASS(x) \ 2189 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2190 2191#define S_FW_RDEV_WR_SEQ_DEL 3 2192#define M_FW_RDEV_WR_SEQ_DEL 0x1 2193#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2194#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2195 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2196#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2197 2198#define S_FW_RDEV_WR_PRIO_PREEMP 2 2199#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2200#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2201#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2202 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2203#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2204 2205#define S_FW_RDEV_WR_PREF 1 2206#define M_FW_RDEV_WR_PREF 0x1 2207#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2208#define G_FW_RDEV_WR_PREF(x) \ 2209 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2210#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2211 2212#define S_FW_RDEV_WR_QOS 0 2213#define M_FW_RDEV_WR_QOS 0x1 2214#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2215#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2216#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2217 2218#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2219#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2220#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2221#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2222 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2223#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2224 2225#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2226#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2227#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2228#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2229 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2230#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2231 2232#define S_FW_RDEV_WR_IMAGE_PAIR 5 2233#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2234#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2235#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2236 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2237#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2238 2239#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2240#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2241#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2242#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2243 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2244 2245#define S_FW_RDEV_WR_ENH_DISC 7 2246#define M_FW_RDEV_WR_ENH_DISC 0x1 2247#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2248#define G_FW_RDEV_WR_ENH_DISC(x) \ 2249 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2250#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2251 2252#define S_FW_RDEV_WR_REC 6 2253#define M_FW_RDEV_WR_REC 0x1 2254#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2255#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2256#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2257 2258#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2259#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2260#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2261#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2262 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2263#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2264 2265#define S_FW_RDEV_WR_RETRY 4 2266#define M_FW_RDEV_WR_RETRY 0x1 2267#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2268#define G_FW_RDEV_WR_RETRY(x) \ 2269 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2270#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2271 2272#define S_FW_RDEV_WR_CONF_CMPL 3 2273#define M_FW_RDEV_WR_CONF_CMPL 0x1 2274#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2275#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2276 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2277#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2278 2279#define S_FW_RDEV_WR_DATA_OVLY 2 2280#define M_FW_RDEV_WR_DATA_OVLY 0x1 2281#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2282#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2283 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2284#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2285 2286#define S_FW_RDEV_WR_INI 1 2287#define M_FW_RDEV_WR_INI 0x1 2288#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2289#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2290#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2291 2292#define S_FW_RDEV_WR_TGT 0 2293#define M_FW_RDEV_WR_TGT 0x1 2294#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2295#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2296#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2297 2298struct fw_foiscsi_node_wr { 2299 __be32 op_to_immdlen; 2300 __be32 flowid_len16; 2301 __u64 cookie; 2302 __u8 subop; 2303 __u8 status; 2304 __u8 alias_len; 2305 __u8 iqn_len; 2306 __be32 node_flowid; 2307 __be16 nodeid; 2308 __be16 login_retry; 2309 __be16 retry_timeout; 2310 __be16 r3; 2311 __u8 iqn[224]; 2312 __u8 alias[224]; 2313}; 2314 2315#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2316#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2317#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2318#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2319 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2320 2321struct fw_foiscsi_ctrl_wr { 2322 __be32 op_compl; 2323 __be32 flowid_len16; 2324 __u64 cookie; 2325 __u8 subop; 2326 __u8 status; 2327 __u8 ctrl_state; 2328 __u8 io_state; 2329 __be32 node_id; 2330 __be32 ctrl_id; 2331 __be32 io_id; 2332 struct fw_foiscsi_sess_attr { 2333 __be32 sess_type_to_erl; 2334 __be16 max_conn; 2335 __be16 max_r2t; 2336 __be16 time2wait; 2337 __be16 time2retain; 2338 __be32 max_burst; 2339 __be32 first_burst; 2340 __be32 r1; 2341 } sess_attr; 2342 struct fw_foiscsi_conn_attr { 2343 __be32 hdigest_to_ddp_pgsz; 2344 __be32 max_rcv_dsl; 2345 __be32 ping_tmo; 2346 __be16 dst_port; 2347 __be16 src_port; 2348 union fw_foiscsi_conn_attr_addr { 2349 struct fw_foiscsi_conn_attr_ipv6 { 2350 __be64 dst_addr[2]; 2351 __be64 src_addr[2]; 2352 } ipv6_addr; 2353 struct fw_foiscsi_conn_attr_ipv4 { 2354 __be32 dst_addr; 2355 __be32 src_addr; 2356 } ipv4_addr; 2357 } u; 2358 } conn_attr; 2359 __u8 tgt_name_len; 2360 __u8 r3[7]; 2361 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2362}; 2363 2364#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2365#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2366#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2367 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2368#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2369 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2370 2371#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2372#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2373#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2374 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2375#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2376 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2377 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2378#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2379 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2380 2381#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2382#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2383#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2384 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2385#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2386 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2387 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2388#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2389 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2390 2391#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2392#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2393#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2394 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2395#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2396 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2397 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2398#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2399 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2400 2401#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2402#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2403#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2404 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2405#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2406 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2407 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2408#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2409 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2410 2411#define S_FW_FOISCSI_CTRL_WR_ERL 24 2412#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2413#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2414#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2415 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2416 2417#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2418#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2419#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2420#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2421 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2422 2423#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2424#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2425#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2426#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2427 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2428 2429#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2430#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2431#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2432 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2433#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2434 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2435 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2436 2437#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2438#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2439#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2440 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2441#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2442 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2443 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2444 2445#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2446#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2447#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2448 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2449#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2450 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2451 2452struct fw_foiscsi_chap_wr { 2453 __be32 op_compl; 2454 __be32 flowid_len16; 2455 __u64 cookie; 2456 __u8 status; 2457 __u8 id_len; 2458 __u8 sec_len; 2459 __u8 node_type; 2460 __be16 node_id; 2461 __u8 r3[2]; 2462 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2463 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2464}; 2465 2466/****************************************************************************** 2467 * F O F C O E W O R K R E Q U E S T s 2468 *******************************************/ 2469 2470struct fw_fcoe_els_ct_wr { 2471 __be32 op_immdlen; 2472 __be32 flowid_len16; 2473 __be64 cookie; 2474 __be16 iqid; 2475 __u8 tmo_val; 2476 __u8 els_ct_type; 2477 __u8 ctl_pri; 2478 __u8 cp_en_class; 2479 __be16 xfer_cnt; 2480 __u8 fl_to_sp; 2481 __u8 l_id[3]; 2482 __u8 r5; 2483 __u8 r_id[3]; 2484 __be64 rsp_dmaaddr; 2485 __be32 rsp_dmalen; 2486 __be32 r6; 2487}; 2488 2489#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2490#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2491#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2492#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2493 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2494 2495#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2496#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2497#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2498#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2499 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2500 2501#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2502#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2503#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2504#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2505 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2506 2507#define S_FW_FCOE_ELS_CT_WR_LEN16 0 2508#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2509#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2510#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2511 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2512 2513#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2514#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2515#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2516#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2517 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2518 2519#define S_FW_FCOE_ELS_CT_WR_CLASS 4 2520#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2521#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2522#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2523 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2524 2525#define S_FW_FCOE_ELS_CT_WR_FL 2 2526#define M_FW_FCOE_ELS_CT_WR_FL 0x1 2527#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2528#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2529 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2530#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2531 2532#define S_FW_FCOE_ELS_CT_WR_NPIV 1 2533#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2534#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2535#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2536 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2537#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2538 2539#define S_FW_FCOE_ELS_CT_WR_SP 0 2540#define M_FW_FCOE_ELS_CT_WR_SP 0x1 2541#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2542#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2543 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2544#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2545 2546/****************************************************************************** 2547 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2548 *****************************************************************************/ 2549 2550struct fw_scsi_write_wr { 2551 __be32 op_immdlen; 2552 __be32 flowid_len16; 2553 __be64 cookie; 2554 __be16 iqid; 2555 __u8 tmo_val; 2556 __u8 use_xfer_cnt; 2557 union fw_scsi_write_priv { 2558 struct fcoe_write_priv { 2559 __u8 ctl_pri; 2560 __u8 cp_en_class; 2561 __u8 r3_lo[2]; 2562 } fcoe; 2563 struct iscsi_write_priv { 2564 __u8 r3[4]; 2565 } iscsi; 2566 } u; 2567 __be32 xfer_cnt; 2568 __be32 ini_xfer_cnt; 2569 __be64 rsp_dmaaddr; 2570 __be32 rsp_dmalen; 2571 __be32 r4; 2572}; 2573 2574#define S_FW_SCSI_WRITE_WR_OPCODE 24 2575#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2576#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2577#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2578 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2579 2580#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2581#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2582#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2583#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2584 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2585 2586#define S_FW_SCSI_WRITE_WR_FLOWID 8 2587#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2588#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2589#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2590 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2591 2592#define S_FW_SCSI_WRITE_WR_LEN16 0 2593#define M_FW_SCSI_WRITE_WR_LEN16 0xff 2594#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2595#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2596 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2597 2598#define S_FW_SCSI_WRITE_WR_CP_EN 6 2599#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2600#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2601#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2602 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2603 2604#define S_FW_SCSI_WRITE_WR_CLASS 4 2605#define M_FW_SCSI_WRITE_WR_CLASS 0x3 2606#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2607#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2608 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2609 2610struct fw_scsi_read_wr { 2611 __be32 op_immdlen; 2612 __be32 flowid_len16; 2613 __be64 cookie; 2614 __be16 iqid; 2615 __u8 tmo_val; 2616 __u8 use_xfer_cnt; 2617 union fw_scsi_read_priv { 2618 struct fcoe_read_priv { 2619 __u8 ctl_pri; 2620 __u8 cp_en_class; 2621 __u8 r3_lo[2]; 2622 } fcoe; 2623 struct iscsi_read_priv { 2624 __u8 r3[4]; 2625 } iscsi; 2626 } u; 2627 __be32 xfer_cnt; 2628 __be32 ini_xfer_cnt; 2629 __be64 rsp_dmaaddr; 2630 __be32 rsp_dmalen; 2631 __be32 r4; 2632}; 2633 2634#define S_FW_SCSI_READ_WR_OPCODE 24 2635#define M_FW_SCSI_READ_WR_OPCODE 0xff 2636#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2637#define G_FW_SCSI_READ_WR_OPCODE(x) \ 2638 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2639 2640#define S_FW_SCSI_READ_WR_IMMDLEN 0 2641#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2642#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2643#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2644 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2645 2646#define S_FW_SCSI_READ_WR_FLOWID 8 2647#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2648#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2649#define G_FW_SCSI_READ_WR_FLOWID(x) \ 2650 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2651 2652#define S_FW_SCSI_READ_WR_LEN16 0 2653#define M_FW_SCSI_READ_WR_LEN16 0xff 2654#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2655#define G_FW_SCSI_READ_WR_LEN16(x) \ 2656 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2657 2658#define S_FW_SCSI_READ_WR_CP_EN 6 2659#define M_FW_SCSI_READ_WR_CP_EN 0x3 2660#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2661#define G_FW_SCSI_READ_WR_CP_EN(x) \ 2662 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2663 2664#define S_FW_SCSI_READ_WR_CLASS 4 2665#define M_FW_SCSI_READ_WR_CLASS 0x3 2666#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2667#define G_FW_SCSI_READ_WR_CLASS(x) \ 2668 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2669 2670struct fw_scsi_cmd_wr { 2671 __be32 op_immdlen; 2672 __be32 flowid_len16; 2673 __be64 cookie; 2674 __be16 iqid; 2675 __u8 tmo_val; 2676 __u8 r3; 2677 union fw_scsi_cmd_priv { 2678 struct fcoe_cmd_priv { 2679 __u8 ctl_pri; 2680 __u8 cp_en_class; 2681 __u8 r4_lo[2]; 2682 } fcoe; 2683 struct iscsi_cmd_priv { 2684 __u8 r4[4]; 2685 } iscsi; 2686 } u; 2687 __u8 r5[8]; 2688 __be64 rsp_dmaaddr; 2689 __be32 rsp_dmalen; 2690 __be32 r6; 2691}; 2692 2693#define S_FW_SCSI_CMD_WR_OPCODE 24 2694#define M_FW_SCSI_CMD_WR_OPCODE 0xff 2695#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2696#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2697 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2698 2699#define S_FW_SCSI_CMD_WR_IMMDLEN 0 2700#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2701#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2702#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2703 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2704 2705#define S_FW_SCSI_CMD_WR_FLOWID 8 2706#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2707#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2708#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2709 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2710 2711#define S_FW_SCSI_CMD_WR_LEN16 0 2712#define M_FW_SCSI_CMD_WR_LEN16 0xff 2713#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2714#define G_FW_SCSI_CMD_WR_LEN16(x) \ 2715 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2716 2717#define S_FW_SCSI_CMD_WR_CP_EN 6 2718#define M_FW_SCSI_CMD_WR_CP_EN 0x3 2719#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2720#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2721 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2722 2723#define S_FW_SCSI_CMD_WR_CLASS 4 2724#define M_FW_SCSI_CMD_WR_CLASS 0x3 2725#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2726#define G_FW_SCSI_CMD_WR_CLASS(x) \ 2727 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2728 2729struct fw_scsi_abrt_cls_wr { 2730 __be32 op_immdlen; 2731 __be32 flowid_len16; 2732 __be64 cookie; 2733 __be16 iqid; 2734 __u8 tmo_val; 2735 __u8 sub_opcode_to_chk_all_io; 2736 __u8 r3[4]; 2737 __be64 t_cookie; 2738}; 2739 2740#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2741#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2742#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2743#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2744 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2745 2746#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2747#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2748#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2749 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2750#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2751 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2752 2753#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2754#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2755#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2756#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2757 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2758 2759#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2760#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2761#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2762#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2763 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2764 2765#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2766#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2767#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2768 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2769#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2770 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2771 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2772 2773#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2774#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2775#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2776#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2777 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2778#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2779 2780#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2781#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2782#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2783 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2784#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2785 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2786 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2787#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2788 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2789 2790struct fw_scsi_tgt_acc_wr { 2791 __be32 op_immdlen; 2792 __be32 flowid_len16; 2793 __be64 cookie; 2794 __be16 iqid; 2795 __u8 r3; 2796 __u8 use_burst_len; 2797 union fw_scsi_tgt_acc_priv { 2798 struct fcoe_tgt_acc_priv { 2799 __u8 ctl_pri; 2800 __u8 cp_en_class; 2801 __u8 r4_lo[2]; 2802 } fcoe; 2803 struct iscsi_tgt_acc_priv { 2804 __u8 r4[4]; 2805 } iscsi; 2806 } u; 2807 __be32 burst_len; 2808 __be32 rel_off; 2809 __be64 r5; 2810 __be32 r6; 2811 __be32 tot_xfer_len; 2812}; 2813 2814#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2815#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2816#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2817#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2818 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2819 2820#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2821#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2822#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2823#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2824 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2825 2826#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2827#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2828#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2829#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2830 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2831 2832#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2833#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2834#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2835#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2836 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2837 2838#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2839#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2840#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2841#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2842 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2843 2844#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2845#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2846#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2847#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2848 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2849 2850struct fw_scsi_tgt_xmit_wr { 2851 __be32 op_immdlen; 2852 __be32 flowid_len16; 2853 __be64 cookie; 2854 __be16 iqid; 2855 __u8 auto_rsp; 2856 __u8 use_xfer_cnt; 2857 union fw_scsi_tgt_xmit_priv { 2858 struct fcoe_tgt_xmit_priv { 2859 __u8 ctl_pri; 2860 __u8 cp_en_class; 2861 __u8 r3_lo[2]; 2862 } fcoe; 2863 struct iscsi_tgt_xmit_priv { 2864 __u8 r3[4]; 2865 } iscsi; 2866 } u; 2867 __be32 xfer_cnt; 2868 __be32 r4; 2869 __be64 r5; 2870 __be32 r6; 2871 __be32 tot_xfer_len; 2872}; 2873 2874#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2875#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2876#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2877#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2878 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2879 2880#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2881#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2882#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2883 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2884#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2885 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2886 2887#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2888#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2889#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2890#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2891 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2892 2893#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2894#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2895#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2896#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2897 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2898 2899#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2900#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2901#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2902#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2903 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2904 2905#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2906#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2907#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2908#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2909 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2910 2911struct fw_scsi_tgt_rsp_wr { 2912 __be32 op_immdlen; 2913 __be32 flowid_len16; 2914 __be64 cookie; 2915 __be16 iqid; 2916 __u8 r3[2]; 2917 union fw_scsi_tgt_rsp_priv { 2918 struct fcoe_tgt_rsp_priv { 2919 __u8 ctl_pri; 2920 __u8 cp_en_class; 2921 __u8 r4_lo[2]; 2922 } fcoe; 2923 struct iscsi_tgt_rsp_priv { 2924 __u8 r4[4]; 2925 } iscsi; 2926 } u; 2927 __u8 r5[8]; 2928}; 2929 2930#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2931#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2932#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2933#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2934 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2935 2936#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2937#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2938#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2939#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2940 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2941 2942#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2943#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2944#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2945#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2946 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2947 2948#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2949#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2950#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2951#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2952 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2953 2954#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2955#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2956#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2957#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2958 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2959 2960#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2961#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2962#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2963#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2964 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2965 2966struct fw_pofcoe_tcb_wr { 2967 __be32 op_compl; 2968 __be32 equiq_to_len16; 2969 __be64 cookie; 2970 __be32 tid_to_port; 2971 __be16 x_id; 2972 __be16 vlan_id; 2973 __be32 s_id; 2974 __be32 d_id; 2975 __be32 tag; 2976 __be32 xfer_len; 2977 __be32 r4; 2978 __be16 r5; 2979 __be16 iqid; 2980}; 2981 2982#define S_FW_POFCOE_TCB_WR_TID 12 2983#define M_FW_POFCOE_TCB_WR_TID 0xfffff 2984#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2985#define G_FW_POFCOE_TCB_WR_TID(x) \ 2986 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2987 2988#define S_FW_POFCOE_TCB_WR_ALLOC 4 2989#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2990#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2991#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2992 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2993#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2994 2995#define S_FW_POFCOE_TCB_WR_FREE 3 2996#define M_FW_POFCOE_TCB_WR_FREE 0x1 2997#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2998#define G_FW_POFCOE_TCB_WR_FREE(x) \ 2999 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3000#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3001 3002#define S_FW_POFCOE_TCB_WR_PORT 0 3003#define M_FW_POFCOE_TCB_WR_PORT 0x7 3004#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3005#define G_FW_POFCOE_TCB_WR_PORT(x) \ 3006 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3007 3008struct fw_pofcoe_ulptx_wr { 3009 __be32 op_pkd; 3010 __be32 equiq_to_len16; 3011 __u64 cookie; 3012}; 3013 3014 3015/****************************************************************************** 3016 * C O M M A N D s 3017 *********************/ 3018 3019/* 3020 * The maximum length of time, in miliseconds, that we expect any firmware 3021 * command to take to execute and return a reply to the host. The RESET 3022 * and INITIALIZE commands can take a fair amount of time to execute but 3023 * most execute in far less time than this maximum. This constant is used 3024 * by host software to determine how long to wait for a firmware command 3025 * reply before declaring the firmware as dead/unreachable ... 3026 */ 3027#define FW_CMD_MAX_TIMEOUT 10000 3028 3029/* 3030 * If a host driver does a HELLO and discovers that there's already a MASTER 3031 * selected, we may have to wait for that MASTER to finish issuing RESET, 3032 * configuration and INITIALIZE commands. Also, there's a possibility that 3033 * our own HELLO may get lost if it happens right as the MASTER is issuign a 3034 * RESET command, so we need to be willing to make a few retries of our HELLO. 3035 */ 3036#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 3037#define FW_CMD_HELLO_RETRIES 3 3038 3039enum fw_cmd_opcodes { 3040 FW_LDST_CMD = 0x01, 3041 FW_RESET_CMD = 0x03, 3042 FW_HELLO_CMD = 0x04, 3043 FW_BYE_CMD = 0x05, 3044 FW_INITIALIZE_CMD = 0x06, 3045 FW_CAPS_CONFIG_CMD = 0x07, 3046 FW_PARAMS_CMD = 0x08, 3047 FW_PFVF_CMD = 0x09, 3048 FW_IQ_CMD = 0x10, 3049 FW_EQ_MNGT_CMD = 0x11, 3050 FW_EQ_ETH_CMD = 0x12, 3051 FW_EQ_CTRL_CMD = 0x13, 3052 FW_EQ_OFLD_CMD = 0x21, 3053 FW_VI_CMD = 0x14, 3054 FW_VI_MAC_CMD = 0x15, 3055 FW_VI_RXMODE_CMD = 0x16, 3056 FW_VI_ENABLE_CMD = 0x17, 3057 FW_VI_STATS_CMD = 0x1a, 3058 FW_ACL_MAC_CMD = 0x18, 3059 FW_ACL_VLAN_CMD = 0x19, 3060 FW_PORT_CMD = 0x1b, 3061 FW_PORT_STATS_CMD = 0x1c, 3062 FW_PORT_LB_STATS_CMD = 0x1d, 3063 FW_PORT_TRACE_CMD = 0x1e, 3064 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3065 FW_RSS_IND_TBL_CMD = 0x20, 3066 FW_RSS_GLB_CONFIG_CMD = 0x22, 3067 FW_RSS_VI_CONFIG_CMD = 0x23, 3068 FW_SCHED_CMD = 0x24, 3069 FW_DEVLOG_CMD = 0x25, 3070 FW_WATCHDOG_CMD = 0x27, 3071 FW_CLIP_CMD = 0x28, 3072 FW_CHNET_IFACE_CMD = 0x26, 3073 FW_FCOE_RES_INFO_CMD = 0x31, 3074 FW_FCOE_LINK_CMD = 0x32, 3075 FW_FCOE_VNP_CMD = 0x33, 3076 FW_FCOE_SPARAMS_CMD = 0x35, 3077 FW_FCOE_STATS_CMD = 0x37, 3078 FW_FCOE_FCF_CMD = 0x38, 3079 FW_LASTC2E_CMD = 0x40, 3080 FW_ERROR_CMD = 0x80, 3081 FW_DEBUG_CMD = 0x81, 3082}; 3083 3084enum fw_cmd_cap { 3085 FW_CMD_CAP_PF = 0x01, 3086 FW_CMD_CAP_DMAQ = 0x02, 3087 FW_CMD_CAP_PORT = 0x04, 3088 FW_CMD_CAP_PORTPROMISC = 0x08, 3089 FW_CMD_CAP_PORTSTATS = 0x10, 3090 FW_CMD_CAP_VF = 0x80, 3091}; 3092 3093/* 3094 * Generic command header flit0 3095 */ 3096struct fw_cmd_hdr { 3097 __be32 hi; 3098 __be32 lo; 3099}; 3100 3101#define S_FW_CMD_OP 24 3102#define M_FW_CMD_OP 0xff 3103#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 3104#define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 3105 3106#define S_FW_CMD_REQUEST 23 3107#define M_FW_CMD_REQUEST 0x1 3108#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 3109#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 3110#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 3111 3112#define S_FW_CMD_READ 22 3113#define M_FW_CMD_READ 0x1 3114#define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3115#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3116#define F_FW_CMD_READ V_FW_CMD_READ(1U) 3117 3118#define S_FW_CMD_WRITE 21 3119#define M_FW_CMD_WRITE 0x1 3120#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3121#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3122#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3123 3124#define S_FW_CMD_EXEC 20 3125#define M_FW_CMD_EXEC 0x1 3126#define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3127#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3128#define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3129 3130#define S_FW_CMD_RAMASK 20 3131#define M_FW_CMD_RAMASK 0xf 3132#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3133#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3134 3135#define S_FW_CMD_RETVAL 8 3136#define M_FW_CMD_RETVAL 0xff 3137#define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3138#define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3139 3140#define S_FW_CMD_LEN16 0 3141#define M_FW_CMD_LEN16 0xff 3142#define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3143#define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3144 3145#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 3146 3147/* 3148 * address spaces 3149 */ 3150enum fw_ldst_addrspc { 3151 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3152 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3153 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3154 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3155 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3156 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3157 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3158 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3159 FW_LDST_ADDRSPC_MDIO = 0x0018, 3160 FW_LDST_ADDRSPC_MPS = 0x0020, 3161 FW_LDST_ADDRSPC_FUNC = 0x0028, 3162 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3163 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3164 FW_LDST_ADDRSPC_LE = 0x0030, 3165 FW_LDST_ADDRSPC_I2C = 0x0038, 3166 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3167 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3168 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3169}; 3170 3171/* 3172 * MDIO VSC8634 register access control field 3173 */ 3174enum fw_ldst_mdio_vsc8634_aid { 3175 FW_LDST_MDIO_VS_STANDARD, 3176 FW_LDST_MDIO_VS_EXTENDED, 3177 FW_LDST_MDIO_VS_GPIO 3178}; 3179 3180enum fw_ldst_mps_fid { 3181 FW_LDST_MPS_ATRB, 3182 FW_LDST_MPS_RPLC 3183}; 3184 3185enum fw_ldst_func_access_ctl { 3186 FW_LDST_FUNC_ACC_CTL_VIID, 3187 FW_LDST_FUNC_ACC_CTL_FID 3188}; 3189 3190enum fw_ldst_func_mod_index { 3191 FW_LDST_FUNC_MPS 3192}; 3193 3194struct fw_ldst_cmd { 3195 __be32 op_to_addrspace; 3196 __be32 cycles_to_len16; 3197 union fw_ldst { 3198 struct fw_ldst_addrval { 3199 __be32 addr; 3200 __be32 val; 3201 } addrval; 3202 struct fw_ldst_idctxt { 3203 __be32 physid; 3204 __be32 msg_ctxtflush; 3205 __be32 ctxt_data7; 3206 __be32 ctxt_data6; 3207 __be32 ctxt_data5; 3208 __be32 ctxt_data4; 3209 __be32 ctxt_data3; 3210 __be32 ctxt_data2; 3211 __be32 ctxt_data1; 3212 __be32 ctxt_data0; 3213 } idctxt; 3214 struct fw_ldst_mdio { 3215 __be16 paddr_mmd; 3216 __be16 raddr; 3217 __be16 vctl; 3218 __be16 rval; 3219 } mdio; 3220 struct fw_ldst_mps { 3221 __be16 fid_ctl; 3222 __be16 rplcpf_pkd; 3223 __be32 rplc127_96; 3224 __be32 rplc95_64; 3225 __be32 rplc63_32; 3226 __be32 rplc31_0; 3227 __be32 atrb; 3228 __be16 vlan[16]; 3229 } mps; 3230 struct fw_ldst_func { 3231 __u8 access_ctl; 3232 __u8 mod_index; 3233 __be16 ctl_id; 3234 __be32 offset; 3235 __be64 data0; 3236 __be64 data1; 3237 } func; 3238 struct fw_ldst_pcie { 3239 __u8 ctrl_to_fn; 3240 __u8 bnum; 3241 __u8 r; 3242 __u8 ext_r; 3243 __u8 select_naccess; 3244 __u8 pcie_fn; 3245 __be16 nset_pkd; 3246 __be32 data[12]; 3247 } pcie; 3248 struct fw_ldst_i2c_deprecated { 3249 __u8 pid_pkd; 3250 __u8 base; 3251 __u8 boffset; 3252 __u8 data; 3253 __be32 r9; 3254 } i2c_deprecated; 3255 struct fw_ldst_i2c { 3256 __u8 pid; 3257 __u8 did; 3258 __u8 boffset; 3259 __u8 blen; 3260 __be32 r9; 3261 __u8 data[48]; 3262 } i2c; 3263 struct fw_ldst_le { 3264 __be32 index; 3265 __be32 r9; 3266 __u8 val[33]; 3267 __u8 r11[7]; 3268 } le; 3269 } u; 3270}; 3271 3272#define S_FW_LDST_CMD_ADDRSPACE 0 3273#define M_FW_LDST_CMD_ADDRSPACE 0xff 3274#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3275#define G_FW_LDST_CMD_ADDRSPACE(x) \ 3276 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3277 3278#define S_FW_LDST_CMD_CYCLES 16 3279#define M_FW_LDST_CMD_CYCLES 0xffff 3280#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3281#define G_FW_LDST_CMD_CYCLES(x) \ 3282 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3283 3284#define S_FW_LDST_CMD_MSG 31 3285#define M_FW_LDST_CMD_MSG 0x1 3286#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3287#define G_FW_LDST_CMD_MSG(x) \ 3288 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3289#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3290 3291#define S_FW_LDST_CMD_CTXTFLUSH 30 3292#define M_FW_LDST_CMD_CTXTFLUSH 0x1 3293#define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3294#define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3295 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3296#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3297 3298#define S_FW_LDST_CMD_PADDR 8 3299#define M_FW_LDST_CMD_PADDR 0x1f 3300#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3301#define G_FW_LDST_CMD_PADDR(x) \ 3302 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3303 3304#define S_FW_LDST_CMD_MMD 0 3305#define M_FW_LDST_CMD_MMD 0x1f 3306#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3307#define G_FW_LDST_CMD_MMD(x) \ 3308 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3309 3310#define S_FW_LDST_CMD_FID 15 3311#define M_FW_LDST_CMD_FID 0x1 3312#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3313#define G_FW_LDST_CMD_FID(x) \ 3314 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3315#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3316 3317#define S_FW_LDST_CMD_CTL 0 3318#define M_FW_LDST_CMD_CTL 0x7fff 3319#define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3320#define G_FW_LDST_CMD_CTL(x) \ 3321 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3322 3323#define S_FW_LDST_CMD_RPLCPF 0 3324#define M_FW_LDST_CMD_RPLCPF 0xff 3325#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3326#define G_FW_LDST_CMD_RPLCPF(x) \ 3327 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3328 3329#define S_FW_LDST_CMD_CTRL 7 3330#define M_FW_LDST_CMD_CTRL 0x1 3331#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3332#define G_FW_LDST_CMD_CTRL(x) \ 3333 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3334#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3335 3336#define S_FW_LDST_CMD_LC 4 3337#define M_FW_LDST_CMD_LC 0x1 3338#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3339#define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3340#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3341 3342#define S_FW_LDST_CMD_AI 3 3343#define M_FW_LDST_CMD_AI 0x1 3344#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3345#define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3346#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3347 3348#define S_FW_LDST_CMD_FN 0 3349#define M_FW_LDST_CMD_FN 0x7 3350#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3351#define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3352 3353#define S_FW_LDST_CMD_SELECT 4 3354#define M_FW_LDST_CMD_SELECT 0xf 3355#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3356#define G_FW_LDST_CMD_SELECT(x) \ 3357 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3358 3359#define S_FW_LDST_CMD_NACCESS 0 3360#define M_FW_LDST_CMD_NACCESS 0xf 3361#define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3362#define G_FW_LDST_CMD_NACCESS(x) \ 3363 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3364 3365#define S_FW_LDST_CMD_NSET 14 3366#define M_FW_LDST_CMD_NSET 0x3 3367#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3368#define G_FW_LDST_CMD_NSET(x) \ 3369 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3370 3371#define S_FW_LDST_CMD_PID 6 3372#define M_FW_LDST_CMD_PID 0x3 3373#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3374#define G_FW_LDST_CMD_PID(x) \ 3375 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3376 3377struct fw_reset_cmd { 3378 __be32 op_to_write; 3379 __be32 retval_len16; 3380 __be32 val; 3381 __be32 halt_pkd; 3382}; 3383 3384#define S_FW_RESET_CMD_HALT 31 3385#define M_FW_RESET_CMD_HALT 0x1 3386#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3387#define G_FW_RESET_CMD_HALT(x) \ 3388 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3389#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3390 3391enum { 3392 FW_HELLO_CMD_STAGE_OS = 0, 3393 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3394 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3395 FW_HELLO_CMD_STAGE_POSTOS = 3, 3396}; 3397 3398struct fw_hello_cmd { 3399 __be32 op_to_write; 3400 __be32 retval_len16; 3401 __be32 err_to_clearinit; 3402 __be32 fwrev; 3403}; 3404 3405#define S_FW_HELLO_CMD_ERR 31 3406#define M_FW_HELLO_CMD_ERR 0x1 3407#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3408#define G_FW_HELLO_CMD_ERR(x) \ 3409 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3410#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3411 3412#define S_FW_HELLO_CMD_INIT 30 3413#define M_FW_HELLO_CMD_INIT 0x1 3414#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3415#define G_FW_HELLO_CMD_INIT(x) \ 3416 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3417#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3418 3419#define S_FW_HELLO_CMD_MASTERDIS 29 3420#define M_FW_HELLO_CMD_MASTERDIS 0x1 3421#define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3422#define G_FW_HELLO_CMD_MASTERDIS(x) \ 3423 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3424#define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3425 3426#define S_FW_HELLO_CMD_MASTERFORCE 28 3427#define M_FW_HELLO_CMD_MASTERFORCE 0x1 3428#define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3429#define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3430 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3431#define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3432 3433#define S_FW_HELLO_CMD_MBMASTER 24 3434#define M_FW_HELLO_CMD_MBMASTER 0xf 3435#define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3436#define G_FW_HELLO_CMD_MBMASTER(x) \ 3437 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3438 3439#define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3440#define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3441#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3442#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3443 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3444#define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3445 3446#define S_FW_HELLO_CMD_MBASYNCNOT 20 3447#define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3448#define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3449#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3450 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3451 3452#define S_FW_HELLO_CMD_STAGE 17 3453#define M_FW_HELLO_CMD_STAGE 0x7 3454#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3455#define G_FW_HELLO_CMD_STAGE(x) \ 3456 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3457 3458#define S_FW_HELLO_CMD_CLEARINIT 16 3459#define M_FW_HELLO_CMD_CLEARINIT 0x1 3460#define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3461#define G_FW_HELLO_CMD_CLEARINIT(x) \ 3462 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3463#define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3464 3465struct fw_bye_cmd { 3466 __be32 op_to_write; 3467 __be32 retval_len16; 3468 __be64 r3; 3469}; 3470 3471struct fw_initialize_cmd { 3472 __be32 op_to_write; 3473 __be32 retval_len16; 3474 __be64 r3; 3475}; 3476 3477enum fw_caps_config_hm { 3478 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3479 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3480 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3481 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3482 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3483 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3484 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3485 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3486 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3487 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3488 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3489 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3490 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3491 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3492 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3493 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3494 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3495 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3496 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3497 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3498 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3499 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3500 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3501 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3502}; 3503 3504/* 3505 * The VF Register Map. 3506 * 3507 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3508 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3509 * the Slice to Module Map Table (see below) in the Physical Function Register 3510 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3511 * and Offset registers in the PF Register Map. The MBDATA base address is 3512 * quite constrained as it determines the Mailbox Data addresses for both PFs 3513 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3514 * overlapping other registers. 3515 */ 3516#define FW_T4VF_SGE_BASE_ADDR 0x0000 3517#define FW_T4VF_MPS_BASE_ADDR 0x0100 3518#define FW_T4VF_PL_BASE_ADDR 0x0200 3519#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3520#define FW_T4VF_CIM_BASE_ADDR 0x0300 3521 3522#define FW_T4VF_REGMAP_START 0x0000 3523#define FW_T4VF_REGMAP_SIZE 0x0400 3524 3525enum fw_caps_config_nbm { 3526 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3527 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3528}; 3529 3530enum fw_caps_config_link { 3531 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3532 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3533 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3534}; 3535 3536enum fw_caps_config_switch { 3537 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3538 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3539}; 3540 3541enum fw_caps_config_nic { 3542 FW_CAPS_CONFIG_NIC = 0x00000001, 3543 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3544 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3545 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3546 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3547 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 3548 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 3549}; 3550 3551enum fw_caps_config_toe { 3552 FW_CAPS_CONFIG_TOE = 0x00000001, 3553}; 3554 3555enum fw_caps_config_rdma { 3556 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3557 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3558}; 3559 3560enum fw_caps_config_iscsi { 3561 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3562 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3563 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3564 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3565 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3566 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3567}; 3568 3569enum fw_caps_config_fcoe { 3570 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3571 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3572 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3573 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3574 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3575}; 3576 3577enum fw_memtype_cf { 3578 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 3579 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 3580 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 3581 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 3582 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 3583 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 3584}; 3585 3586struct fw_caps_config_cmd { 3587 __be32 op_to_write; 3588 __be32 cfvalid_to_len16; 3589 __be32 r2; 3590 __be32 hwmbitmap; 3591 __be16 nbmcaps; 3592 __be16 linkcaps; 3593 __be16 switchcaps; 3594 __be16 r3; 3595 __be16 niccaps; 3596 __be16 toecaps; 3597 __be16 rdmacaps; 3598 __be16 r4; 3599 __be16 iscsicaps; 3600 __be16 fcoecaps; 3601 __be32 cfcsum; 3602 __be32 finiver; 3603 __be32 finicsum; 3604}; 3605 3606#define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3607#define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3608#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3609#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3610 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3611#define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3612 3613#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3614#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3615#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3616 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3617#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3618 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3619 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3620 3621#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3622#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3623#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3624 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3625#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3626 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3627 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3628 3629/* 3630 * params command mnemonics 3631 */ 3632enum fw_params_mnem { 3633 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3634 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3635 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3636 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3637 FW_PARAMS_MNEM_LAST 3638}; 3639 3640/* 3641 * device parameters 3642 */ 3643enum fw_params_param_dev { 3644 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3645 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3646 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3647 * allocated by the device's 3648 * Lookup Engine 3649 */ 3650 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3651 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3652 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3653 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3654 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3655 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3656 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3657 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3658 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3659 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3660 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3661 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3662 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3663 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3664 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3665 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3666 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3667 */ 3668 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3669 */ 3670 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3671 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3672 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 3673 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 3674}; 3675 3676/* 3677 * physical and virtual function parameters 3678 */ 3679enum fw_params_param_pfvf { 3680 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3681 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3682 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3683 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3684 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3685 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3686 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3687 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3688 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3689 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3690 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3691 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3692 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3693 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3694 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3695 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3696 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3697 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3698 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3699 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3700 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3701 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3702 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3703 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3704 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3705 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3706 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3707 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3708 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3709 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3710 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3711 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3712 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3713 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3714 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3715 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3716 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3717 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3718 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3719 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3720}; 3721 3722/* 3723 * dma queue parameters 3724 */ 3725enum fw_params_param_dmaq { 3726 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3727 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3728 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3729 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3730 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3731 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3732 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 3733 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 3734}; 3735 3736/* 3737 * dev bypass parameters; actions and modes 3738 */ 3739enum fw_params_param_dev_bypass { 3740 3741 /* actions 3742 */ 3743 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3744 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3745 3746 /* modes 3747 */ 3748 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3749 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3750 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3751}; 3752 3753enum fw_params_param_dev_phyfw { 3754 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 3755 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 3756}; 3757 3758enum fw_params_param_dev_diag { 3759 FW_PARAM_DEV_DIAG_TMP = 0x00, 3760 FW_PARAM_DEV_DIAG_VDD = 0x01, 3761}; 3762 3763enum fw_params_param_dev_fwcache { 3764 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 3765 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 3766}; 3767 3768#define S_FW_PARAMS_MNEM 24 3769#define M_FW_PARAMS_MNEM 0xff 3770#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3771#define G_FW_PARAMS_MNEM(x) \ 3772 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3773 3774#define S_FW_PARAMS_PARAM_X 16 3775#define M_FW_PARAMS_PARAM_X 0xff 3776#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3777#define G_FW_PARAMS_PARAM_X(x) \ 3778 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3779 3780#define S_FW_PARAMS_PARAM_Y 8 3781#define M_FW_PARAMS_PARAM_Y 0xff 3782#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3783#define G_FW_PARAMS_PARAM_Y(x) \ 3784 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3785 3786#define S_FW_PARAMS_PARAM_Z 0 3787#define M_FW_PARAMS_PARAM_Z 0xff 3788#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3789#define G_FW_PARAMS_PARAM_Z(x) \ 3790 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3791 3792#define S_FW_PARAMS_PARAM_XYZ 0 3793#define M_FW_PARAMS_PARAM_XYZ 0xffffff 3794#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3795#define G_FW_PARAMS_PARAM_XYZ(x) \ 3796 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3797 3798#define S_FW_PARAMS_PARAM_YZ 0 3799#define M_FW_PARAMS_PARAM_YZ 0xffff 3800#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3801#define G_FW_PARAMS_PARAM_YZ(x) \ 3802 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3803 3804struct fw_params_cmd { 3805 __be32 op_to_vfn; 3806 __be32 retval_len16; 3807 struct fw_params_param { 3808 __be32 mnem; 3809 __be32 val; 3810 } param[7]; 3811}; 3812 3813#define S_FW_PARAMS_CMD_PFN 8 3814#define M_FW_PARAMS_CMD_PFN 0x7 3815#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3816#define G_FW_PARAMS_CMD_PFN(x) \ 3817 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3818 3819#define S_FW_PARAMS_CMD_VFN 0 3820#define M_FW_PARAMS_CMD_VFN 0xff 3821#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3822#define G_FW_PARAMS_CMD_VFN(x) \ 3823 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3824 3825struct fw_pfvf_cmd { 3826 __be32 op_to_vfn; 3827 __be32 retval_len16; 3828 __be32 niqflint_niq; 3829 __be32 type_to_neq; 3830 __be32 tc_to_nexactf; 3831 __be32 r_caps_to_nethctrl; 3832 __be16 nricq; 3833 __be16 nriqp; 3834 __be32 r4; 3835}; 3836 3837#define S_FW_PFVF_CMD_PFN 8 3838#define M_FW_PFVF_CMD_PFN 0x7 3839#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3840#define G_FW_PFVF_CMD_PFN(x) \ 3841 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3842 3843#define S_FW_PFVF_CMD_VFN 0 3844#define M_FW_PFVF_CMD_VFN 0xff 3845#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3846#define G_FW_PFVF_CMD_VFN(x) \ 3847 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3848 3849#define S_FW_PFVF_CMD_NIQFLINT 20 3850#define M_FW_PFVF_CMD_NIQFLINT 0xfff 3851#define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3852#define G_FW_PFVF_CMD_NIQFLINT(x) \ 3853 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3854 3855#define S_FW_PFVF_CMD_NIQ 0 3856#define M_FW_PFVF_CMD_NIQ 0xfffff 3857#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3858#define G_FW_PFVF_CMD_NIQ(x) \ 3859 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3860 3861#define S_FW_PFVF_CMD_TYPE 31 3862#define M_FW_PFVF_CMD_TYPE 0x1 3863#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3864#define G_FW_PFVF_CMD_TYPE(x) \ 3865 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3866#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3867 3868#define S_FW_PFVF_CMD_CMASK 24 3869#define M_FW_PFVF_CMD_CMASK 0xf 3870#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3871#define G_FW_PFVF_CMD_CMASK(x) \ 3872 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3873 3874#define S_FW_PFVF_CMD_PMASK 20 3875#define M_FW_PFVF_CMD_PMASK 0xf 3876#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3877#define G_FW_PFVF_CMD_PMASK(x) \ 3878 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3879 3880#define S_FW_PFVF_CMD_NEQ 0 3881#define M_FW_PFVF_CMD_NEQ 0xfffff 3882#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3883#define G_FW_PFVF_CMD_NEQ(x) \ 3884 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3885 3886#define S_FW_PFVF_CMD_TC 24 3887#define M_FW_PFVF_CMD_TC 0xff 3888#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3889#define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3890 3891#define S_FW_PFVF_CMD_NVI 16 3892#define M_FW_PFVF_CMD_NVI 0xff 3893#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3894#define G_FW_PFVF_CMD_NVI(x) \ 3895 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3896 3897#define S_FW_PFVF_CMD_NEXACTF 0 3898#define M_FW_PFVF_CMD_NEXACTF 0xffff 3899#define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3900#define G_FW_PFVF_CMD_NEXACTF(x) \ 3901 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3902 3903#define S_FW_PFVF_CMD_R_CAPS 24 3904#define M_FW_PFVF_CMD_R_CAPS 0xff 3905#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3906#define G_FW_PFVF_CMD_R_CAPS(x) \ 3907 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3908 3909#define S_FW_PFVF_CMD_WX_CAPS 16 3910#define M_FW_PFVF_CMD_WX_CAPS 0xff 3911#define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3912#define G_FW_PFVF_CMD_WX_CAPS(x) \ 3913 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3914 3915#define S_FW_PFVF_CMD_NETHCTRL 0 3916#define M_FW_PFVF_CMD_NETHCTRL 0xffff 3917#define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3918#define G_FW_PFVF_CMD_NETHCTRL(x) \ 3919 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3920 3921/* 3922 * ingress queue type; the first 1K ingress queues can have associated 0, 3923 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3924 * capabilities 3925 */ 3926enum fw_iq_type { 3927 FW_IQ_TYPE_FL_INT_CAP, 3928 FW_IQ_TYPE_NO_FL_INT_CAP 3929}; 3930 3931struct fw_iq_cmd { 3932 __be32 op_to_vfn; 3933 __be32 alloc_to_len16; 3934 __be16 physiqid; 3935 __be16 iqid; 3936 __be16 fl0id; 3937 __be16 fl1id; 3938 __be32 type_to_iqandstindex; 3939 __be16 iqdroprss_to_iqesize; 3940 __be16 iqsize; 3941 __be64 iqaddr; 3942 __be32 iqns_to_fl0congen; 3943 __be16 fl0dcaen_to_fl0cidxfthresh; 3944 __be16 fl0size; 3945 __be64 fl0addr; 3946 __be32 fl1cngchmap_to_fl1congen; 3947 __be16 fl1dcaen_to_fl1cidxfthresh; 3948 __be16 fl1size; 3949 __be64 fl1addr; 3950}; 3951 3952#define S_FW_IQ_CMD_PFN 8 3953#define M_FW_IQ_CMD_PFN 0x7 3954#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3955#define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3956 3957#define S_FW_IQ_CMD_VFN 0 3958#define M_FW_IQ_CMD_VFN 0xff 3959#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3960#define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3961 3962#define S_FW_IQ_CMD_ALLOC 31 3963#define M_FW_IQ_CMD_ALLOC 0x1 3964#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3965#define G_FW_IQ_CMD_ALLOC(x) \ 3966 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3967#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3968 3969#define S_FW_IQ_CMD_FREE 30 3970#define M_FW_IQ_CMD_FREE 0x1 3971#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3972#define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3973#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3974 3975#define S_FW_IQ_CMD_MODIFY 29 3976#define M_FW_IQ_CMD_MODIFY 0x1 3977#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3978#define G_FW_IQ_CMD_MODIFY(x) \ 3979 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3980#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3981 3982#define S_FW_IQ_CMD_IQSTART 28 3983#define M_FW_IQ_CMD_IQSTART 0x1 3984#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3985#define G_FW_IQ_CMD_IQSTART(x) \ 3986 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3987#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3988 3989#define S_FW_IQ_CMD_IQSTOP 27 3990#define M_FW_IQ_CMD_IQSTOP 0x1 3991#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3992#define G_FW_IQ_CMD_IQSTOP(x) \ 3993 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3994#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3995 3996#define S_FW_IQ_CMD_TYPE 29 3997#define M_FW_IQ_CMD_TYPE 0x7 3998#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3999#define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 4000 4001#define S_FW_IQ_CMD_IQASYNCH 28 4002#define M_FW_IQ_CMD_IQASYNCH 0x1 4003#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 4004#define G_FW_IQ_CMD_IQASYNCH(x) \ 4005 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 4006#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 4007 4008#define S_FW_IQ_CMD_VIID 16 4009#define M_FW_IQ_CMD_VIID 0xfff 4010#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 4011#define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 4012 4013#define S_FW_IQ_CMD_IQANDST 15 4014#define M_FW_IQ_CMD_IQANDST 0x1 4015#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 4016#define G_FW_IQ_CMD_IQANDST(x) \ 4017 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 4018#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 4019 4020#define S_FW_IQ_CMD_IQANUS 14 4021#define M_FW_IQ_CMD_IQANUS 0x1 4022#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 4023#define G_FW_IQ_CMD_IQANUS(x) \ 4024 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 4025#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 4026 4027#define S_FW_IQ_CMD_IQANUD 12 4028#define M_FW_IQ_CMD_IQANUD 0x3 4029#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 4030#define G_FW_IQ_CMD_IQANUD(x) \ 4031 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 4032 4033#define S_FW_IQ_CMD_IQANDSTINDEX 0 4034#define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 4035#define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 4036#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 4037 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 4038 4039#define S_FW_IQ_CMD_IQDROPRSS 15 4040#define M_FW_IQ_CMD_IQDROPRSS 0x1 4041#define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 4042#define G_FW_IQ_CMD_IQDROPRSS(x) \ 4043 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 4044#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 4045 4046#define S_FW_IQ_CMD_IQGTSMODE 14 4047#define M_FW_IQ_CMD_IQGTSMODE 0x1 4048#define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 4049#define G_FW_IQ_CMD_IQGTSMODE(x) \ 4050 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 4051#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 4052 4053#define S_FW_IQ_CMD_IQPCIECH 12 4054#define M_FW_IQ_CMD_IQPCIECH 0x3 4055#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 4056#define G_FW_IQ_CMD_IQPCIECH(x) \ 4057 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 4058 4059#define S_FW_IQ_CMD_IQDCAEN 11 4060#define M_FW_IQ_CMD_IQDCAEN 0x1 4061#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 4062#define G_FW_IQ_CMD_IQDCAEN(x) \ 4063 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 4064#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 4065 4066#define S_FW_IQ_CMD_IQDCACPU 6 4067#define M_FW_IQ_CMD_IQDCACPU 0x1f 4068#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 4069#define G_FW_IQ_CMD_IQDCACPU(x) \ 4070 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 4071 4072#define S_FW_IQ_CMD_IQINTCNTTHRESH 4 4073#define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 4074#define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 4075#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 4076 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 4077 4078#define S_FW_IQ_CMD_IQO 3 4079#define M_FW_IQ_CMD_IQO 0x1 4080#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 4081#define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 4082#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 4083 4084#define S_FW_IQ_CMD_IQCPRIO 2 4085#define M_FW_IQ_CMD_IQCPRIO 0x1 4086#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 4087#define G_FW_IQ_CMD_IQCPRIO(x) \ 4088 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 4089#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 4090 4091#define S_FW_IQ_CMD_IQESIZE 0 4092#define M_FW_IQ_CMD_IQESIZE 0x3 4093#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 4094#define G_FW_IQ_CMD_IQESIZE(x) \ 4095 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 4096 4097#define S_FW_IQ_CMD_IQNS 31 4098#define M_FW_IQ_CMD_IQNS 0x1 4099#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 4100#define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 4101#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 4102 4103#define S_FW_IQ_CMD_IQRO 30 4104#define M_FW_IQ_CMD_IQRO 0x1 4105#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 4106#define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 4107#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 4108 4109#define S_FW_IQ_CMD_IQFLINTIQHSEN 28 4110#define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 4111#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 4112#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 4113 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 4114 4115#define S_FW_IQ_CMD_IQFLINTCONGEN 27 4116#define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 4117#define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 4118#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 4119 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 4120#define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 4121 4122#define S_FW_IQ_CMD_IQFLINTISCSIC 26 4123#define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4124#define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4125#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4126 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4127#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4128 4129#define S_FW_IQ_CMD_FL0CNGCHMAP 20 4130#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4131#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4132#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4133 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4134 4135#define S_FW_IQ_CMD_FL0CACHELOCK 15 4136#define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4137#define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4138#define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4139 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4140#define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4141 4142#define S_FW_IQ_CMD_FL0DBP 14 4143#define M_FW_IQ_CMD_FL0DBP 0x1 4144#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4145#define G_FW_IQ_CMD_FL0DBP(x) \ 4146 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4147#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4148 4149#define S_FW_IQ_CMD_FL0DATANS 13 4150#define M_FW_IQ_CMD_FL0DATANS 0x1 4151#define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4152#define G_FW_IQ_CMD_FL0DATANS(x) \ 4153 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4154#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4155 4156#define S_FW_IQ_CMD_FL0DATARO 12 4157#define M_FW_IQ_CMD_FL0DATARO 0x1 4158#define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4159#define G_FW_IQ_CMD_FL0DATARO(x) \ 4160 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4161#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4162 4163#define S_FW_IQ_CMD_FL0CONGCIF 11 4164#define M_FW_IQ_CMD_FL0CONGCIF 0x1 4165#define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4166#define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4167 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4168#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4169 4170#define S_FW_IQ_CMD_FL0ONCHIP 10 4171#define M_FW_IQ_CMD_FL0ONCHIP 0x1 4172#define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4173#define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4174 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4175#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4176 4177#define S_FW_IQ_CMD_FL0STATUSPGNS 9 4178#define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4179#define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4180#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4181 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4182#define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4183 4184#define S_FW_IQ_CMD_FL0STATUSPGRO 8 4185#define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4186#define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4187#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4188 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4189#define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4190 4191#define S_FW_IQ_CMD_FL0FETCHNS 7 4192#define M_FW_IQ_CMD_FL0FETCHNS 0x1 4193#define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4194#define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4195 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4196#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4197 4198#define S_FW_IQ_CMD_FL0FETCHRO 6 4199#define M_FW_IQ_CMD_FL0FETCHRO 0x1 4200#define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4201#define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4202 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4203#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4204 4205#define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4206#define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4207#define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4208#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4209 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4210 4211#define S_FW_IQ_CMD_FL0CPRIO 3 4212#define M_FW_IQ_CMD_FL0CPRIO 0x1 4213#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4214#define G_FW_IQ_CMD_FL0CPRIO(x) \ 4215 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4216#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4217 4218#define S_FW_IQ_CMD_FL0PADEN 2 4219#define M_FW_IQ_CMD_FL0PADEN 0x1 4220#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4221#define G_FW_IQ_CMD_FL0PADEN(x) \ 4222 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4223#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4224 4225#define S_FW_IQ_CMD_FL0PACKEN 1 4226#define M_FW_IQ_CMD_FL0PACKEN 0x1 4227#define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4228#define G_FW_IQ_CMD_FL0PACKEN(x) \ 4229 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4230#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4231 4232#define S_FW_IQ_CMD_FL0CONGEN 0 4233#define M_FW_IQ_CMD_FL0CONGEN 0x1 4234#define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4235#define G_FW_IQ_CMD_FL0CONGEN(x) \ 4236 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4237#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4238 4239#define S_FW_IQ_CMD_FL0DCAEN 15 4240#define M_FW_IQ_CMD_FL0DCAEN 0x1 4241#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4242#define G_FW_IQ_CMD_FL0DCAEN(x) \ 4243 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4244#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4245 4246#define S_FW_IQ_CMD_FL0DCACPU 10 4247#define M_FW_IQ_CMD_FL0DCACPU 0x1f 4248#define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4249#define G_FW_IQ_CMD_FL0DCACPU(x) \ 4250 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4251 4252#define S_FW_IQ_CMD_FL0FBMIN 7 4253#define M_FW_IQ_CMD_FL0FBMIN 0x7 4254#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4255#define G_FW_IQ_CMD_FL0FBMIN(x) \ 4256 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4257 4258#define S_FW_IQ_CMD_FL0FBMAX 4 4259#define M_FW_IQ_CMD_FL0FBMAX 0x7 4260#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4261#define G_FW_IQ_CMD_FL0FBMAX(x) \ 4262 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4263 4264#define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4265#define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4266#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4267#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4268 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4269#define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4270 4271#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4272#define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4273#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4274#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4275 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4276 4277#define S_FW_IQ_CMD_FL1CNGCHMAP 20 4278#define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4279#define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4280#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4281 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4282 4283#define S_FW_IQ_CMD_FL1CACHELOCK 15 4284#define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4285#define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4286#define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4287 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4288#define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4289 4290#define S_FW_IQ_CMD_FL1DBP 14 4291#define M_FW_IQ_CMD_FL1DBP 0x1 4292#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4293#define G_FW_IQ_CMD_FL1DBP(x) \ 4294 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4295#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4296 4297#define S_FW_IQ_CMD_FL1DATANS 13 4298#define M_FW_IQ_CMD_FL1DATANS 0x1 4299#define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4300#define G_FW_IQ_CMD_FL1DATANS(x) \ 4301 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4302#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4303 4304#define S_FW_IQ_CMD_FL1DATARO 12 4305#define M_FW_IQ_CMD_FL1DATARO 0x1 4306#define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4307#define G_FW_IQ_CMD_FL1DATARO(x) \ 4308 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4309#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4310 4311#define S_FW_IQ_CMD_FL1CONGCIF 11 4312#define M_FW_IQ_CMD_FL1CONGCIF 0x1 4313#define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4314#define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4315 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4316#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4317 4318#define S_FW_IQ_CMD_FL1ONCHIP 10 4319#define M_FW_IQ_CMD_FL1ONCHIP 0x1 4320#define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4321#define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4322 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4323#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4324 4325#define S_FW_IQ_CMD_FL1STATUSPGNS 9 4326#define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4327#define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4328#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4329 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4330#define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4331 4332#define S_FW_IQ_CMD_FL1STATUSPGRO 8 4333#define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4334#define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4335#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4336 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4337#define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4338 4339#define S_FW_IQ_CMD_FL1FETCHNS 7 4340#define M_FW_IQ_CMD_FL1FETCHNS 0x1 4341#define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4342#define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4343 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4344#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4345 4346#define S_FW_IQ_CMD_FL1FETCHRO 6 4347#define M_FW_IQ_CMD_FL1FETCHRO 0x1 4348#define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4349#define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4350 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4351#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4352 4353#define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4354#define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4355#define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4356#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4357 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4358 4359#define S_FW_IQ_CMD_FL1CPRIO 3 4360#define M_FW_IQ_CMD_FL1CPRIO 0x1 4361#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4362#define G_FW_IQ_CMD_FL1CPRIO(x) \ 4363 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4364#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4365 4366#define S_FW_IQ_CMD_FL1PADEN 2 4367#define M_FW_IQ_CMD_FL1PADEN 0x1 4368#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4369#define G_FW_IQ_CMD_FL1PADEN(x) \ 4370 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4371#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4372 4373#define S_FW_IQ_CMD_FL1PACKEN 1 4374#define M_FW_IQ_CMD_FL1PACKEN 0x1 4375#define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4376#define G_FW_IQ_CMD_FL1PACKEN(x) \ 4377 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4378#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4379 4380#define S_FW_IQ_CMD_FL1CONGEN 0 4381#define M_FW_IQ_CMD_FL1CONGEN 0x1 4382#define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4383#define G_FW_IQ_CMD_FL1CONGEN(x) \ 4384 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4385#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4386 4387#define S_FW_IQ_CMD_FL1DCAEN 15 4388#define M_FW_IQ_CMD_FL1DCAEN 0x1 4389#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4390#define G_FW_IQ_CMD_FL1DCAEN(x) \ 4391 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4392#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4393 4394#define S_FW_IQ_CMD_FL1DCACPU 10 4395#define M_FW_IQ_CMD_FL1DCACPU 0x1f 4396#define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4397#define G_FW_IQ_CMD_FL1DCACPU(x) \ 4398 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4399 4400#define S_FW_IQ_CMD_FL1FBMIN 7 4401#define M_FW_IQ_CMD_FL1FBMIN 0x7 4402#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4403#define G_FW_IQ_CMD_FL1FBMIN(x) \ 4404 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4405 4406#define S_FW_IQ_CMD_FL1FBMAX 4 4407#define M_FW_IQ_CMD_FL1FBMAX 0x7 4408#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4409#define G_FW_IQ_CMD_FL1FBMAX(x) \ 4410 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4411 4412#define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4413#define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4414#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4415#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4416 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4417#define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4418 4419#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4420#define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4421#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4422#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4423 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4424 4425struct fw_eq_mngt_cmd { 4426 __be32 op_to_vfn; 4427 __be32 alloc_to_len16; 4428 __be32 cmpliqid_eqid; 4429 __be32 physeqid_pkd; 4430 __be32 fetchszm_to_iqid; 4431 __be32 dcaen_to_eqsize; 4432 __be64 eqaddr; 4433}; 4434 4435#define S_FW_EQ_MNGT_CMD_PFN 8 4436#define M_FW_EQ_MNGT_CMD_PFN 0x7 4437#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4438#define G_FW_EQ_MNGT_CMD_PFN(x) \ 4439 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4440 4441#define S_FW_EQ_MNGT_CMD_VFN 0 4442#define M_FW_EQ_MNGT_CMD_VFN 0xff 4443#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4444#define G_FW_EQ_MNGT_CMD_VFN(x) \ 4445 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4446 4447#define S_FW_EQ_MNGT_CMD_ALLOC 31 4448#define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4449#define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4450#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4451 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4452#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4453 4454#define S_FW_EQ_MNGT_CMD_FREE 30 4455#define M_FW_EQ_MNGT_CMD_FREE 0x1 4456#define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4457#define G_FW_EQ_MNGT_CMD_FREE(x) \ 4458 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4459#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4460 4461#define S_FW_EQ_MNGT_CMD_MODIFY 29 4462#define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4463#define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4464#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4465 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4466#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4467 4468#define S_FW_EQ_MNGT_CMD_EQSTART 28 4469#define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4470#define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4471#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4472 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4473#define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4474 4475#define S_FW_EQ_MNGT_CMD_EQSTOP 27 4476#define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4477#define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4478#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4479 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4480#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4481 4482#define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4483#define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4484#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4485#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4486 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4487 4488#define S_FW_EQ_MNGT_CMD_EQID 0 4489#define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4490#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4491#define G_FW_EQ_MNGT_CMD_EQID(x) \ 4492 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4493 4494#define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4495#define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4496#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4497#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4498 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4499 4500#define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4501#define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4502#define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4503#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4504 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4505#define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4506 4507#define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4508#define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4509#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4510#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4511 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4512#define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4513 4514#define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4515#define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4516#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4517#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4518 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4519#define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4520 4521#define S_FW_EQ_MNGT_CMD_FETCHNS 23 4522#define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4523#define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4524#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4525 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4526#define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4527 4528#define S_FW_EQ_MNGT_CMD_FETCHRO 22 4529#define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4530#define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4531#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4532 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4533#define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4534 4535#define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4536#define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4537#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4538#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4539 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4540 4541#define S_FW_EQ_MNGT_CMD_CPRIO 19 4542#define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4543#define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4544#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4545 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4546#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4547 4548#define S_FW_EQ_MNGT_CMD_ONCHIP 18 4549#define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4550#define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4551#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4552 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4553#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4554 4555#define S_FW_EQ_MNGT_CMD_PCIECHN 16 4556#define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4557#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4558#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4559 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4560 4561#define S_FW_EQ_MNGT_CMD_IQID 0 4562#define M_FW_EQ_MNGT_CMD_IQID 0xffff 4563#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4564#define G_FW_EQ_MNGT_CMD_IQID(x) \ 4565 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4566 4567#define S_FW_EQ_MNGT_CMD_DCAEN 31 4568#define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4569#define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4570#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4571 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4572#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4573 4574#define S_FW_EQ_MNGT_CMD_DCACPU 26 4575#define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4576#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4577#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4578 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4579 4580#define S_FW_EQ_MNGT_CMD_FBMIN 23 4581#define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4582#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4583#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4584 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4585 4586#define S_FW_EQ_MNGT_CMD_FBMAX 20 4587#define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4588#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4589#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4590 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4591 4592#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4593#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4594#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4595 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4596#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4597 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4598#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4599 4600#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4601#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4602#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4603#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4604 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4605 4606#define S_FW_EQ_MNGT_CMD_EQSIZE 0 4607#define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4608#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4609#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4610 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4611 4612struct fw_eq_eth_cmd { 4613 __be32 op_to_vfn; 4614 __be32 alloc_to_len16; 4615 __be32 eqid_pkd; 4616 __be32 physeqid_pkd; 4617 __be32 fetchszm_to_iqid; 4618 __be32 dcaen_to_eqsize; 4619 __be64 eqaddr; 4620 __be32 autoequiqe_to_viid; 4621 __be32 r8_lo; 4622 __be64 r9; 4623}; 4624 4625#define S_FW_EQ_ETH_CMD_PFN 8 4626#define M_FW_EQ_ETH_CMD_PFN 0x7 4627#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4628#define G_FW_EQ_ETH_CMD_PFN(x) \ 4629 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4630 4631#define S_FW_EQ_ETH_CMD_VFN 0 4632#define M_FW_EQ_ETH_CMD_VFN 0xff 4633#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4634#define G_FW_EQ_ETH_CMD_VFN(x) \ 4635 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4636 4637#define S_FW_EQ_ETH_CMD_ALLOC 31 4638#define M_FW_EQ_ETH_CMD_ALLOC 0x1 4639#define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4640#define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4641 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4642#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4643 4644#define S_FW_EQ_ETH_CMD_FREE 30 4645#define M_FW_EQ_ETH_CMD_FREE 0x1 4646#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4647#define G_FW_EQ_ETH_CMD_FREE(x) \ 4648 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4649#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4650 4651#define S_FW_EQ_ETH_CMD_MODIFY 29 4652#define M_FW_EQ_ETH_CMD_MODIFY 0x1 4653#define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4654#define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4655 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4656#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4657 4658#define S_FW_EQ_ETH_CMD_EQSTART 28 4659#define M_FW_EQ_ETH_CMD_EQSTART 0x1 4660#define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4661#define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4662 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4663#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4664 4665#define S_FW_EQ_ETH_CMD_EQSTOP 27 4666#define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4667#define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4668#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4669 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4670#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4671 4672#define S_FW_EQ_ETH_CMD_EQID 0 4673#define M_FW_EQ_ETH_CMD_EQID 0xfffff 4674#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4675#define G_FW_EQ_ETH_CMD_EQID(x) \ 4676 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4677 4678#define S_FW_EQ_ETH_CMD_PHYSEQID 0 4679#define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4680#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4681#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4682 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4683 4684#define S_FW_EQ_ETH_CMD_FETCHSZM 26 4685#define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4686#define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4687#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4688 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4689#define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4690 4691#define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4692#define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4693#define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4694#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4695 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4696#define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4697 4698#define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4699#define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4700#define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4701#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4702 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4703#define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4704 4705#define S_FW_EQ_ETH_CMD_FETCHNS 23 4706#define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4707#define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4708#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4709 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4710#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4711 4712#define S_FW_EQ_ETH_CMD_FETCHRO 22 4713#define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4714#define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4715#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4716 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4717#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4718 4719#define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4720#define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4721#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4722#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4723 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4724 4725#define S_FW_EQ_ETH_CMD_CPRIO 19 4726#define M_FW_EQ_ETH_CMD_CPRIO 0x1 4727#define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4728#define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4729 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4730#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4731 4732#define S_FW_EQ_ETH_CMD_ONCHIP 18 4733#define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4734#define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4735#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4736 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4737#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4738 4739#define S_FW_EQ_ETH_CMD_PCIECHN 16 4740#define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4741#define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4742#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4743 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4744 4745#define S_FW_EQ_ETH_CMD_IQID 0 4746#define M_FW_EQ_ETH_CMD_IQID 0xffff 4747#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4748#define G_FW_EQ_ETH_CMD_IQID(x) \ 4749 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4750 4751#define S_FW_EQ_ETH_CMD_DCAEN 31 4752#define M_FW_EQ_ETH_CMD_DCAEN 0x1 4753#define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4754#define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4755 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4756#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4757 4758#define S_FW_EQ_ETH_CMD_DCACPU 26 4759#define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4760#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4761#define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4762 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4763 4764#define S_FW_EQ_ETH_CMD_FBMIN 23 4765#define M_FW_EQ_ETH_CMD_FBMIN 0x7 4766#define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4767#define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4768 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4769 4770#define S_FW_EQ_ETH_CMD_FBMAX 20 4771#define M_FW_EQ_ETH_CMD_FBMAX 0x7 4772#define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4773#define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4774 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4775 4776#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4777#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4778#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4779#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4780 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4781#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4782 4783#define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4784#define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4785#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4786#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4787 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4788 4789#define S_FW_EQ_ETH_CMD_EQSIZE 0 4790#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4791#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4792#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4793 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4794 4795#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 4796#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 4797#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 4798#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 4799 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 4800#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 4801 4802#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 4803#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 4804#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 4805#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 4806 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 4807#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 4808 4809#define S_FW_EQ_ETH_CMD_VIID 16 4810#define M_FW_EQ_ETH_CMD_VIID 0xfff 4811#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4812#define G_FW_EQ_ETH_CMD_VIID(x) \ 4813 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4814 4815struct fw_eq_ctrl_cmd { 4816 __be32 op_to_vfn; 4817 __be32 alloc_to_len16; 4818 __be32 cmpliqid_eqid; 4819 __be32 physeqid_pkd; 4820 __be32 fetchszm_to_iqid; 4821 __be32 dcaen_to_eqsize; 4822 __be64 eqaddr; 4823}; 4824 4825#define S_FW_EQ_CTRL_CMD_PFN 8 4826#define M_FW_EQ_CTRL_CMD_PFN 0x7 4827#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4828#define G_FW_EQ_CTRL_CMD_PFN(x) \ 4829 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4830 4831#define S_FW_EQ_CTRL_CMD_VFN 0 4832#define M_FW_EQ_CTRL_CMD_VFN 0xff 4833#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4834#define G_FW_EQ_CTRL_CMD_VFN(x) \ 4835 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4836 4837#define S_FW_EQ_CTRL_CMD_ALLOC 31 4838#define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4839#define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4840#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4841 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4842#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4843 4844#define S_FW_EQ_CTRL_CMD_FREE 30 4845#define M_FW_EQ_CTRL_CMD_FREE 0x1 4846#define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4847#define G_FW_EQ_CTRL_CMD_FREE(x) \ 4848 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4849#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4850 4851#define S_FW_EQ_CTRL_CMD_MODIFY 29 4852#define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4853#define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4854#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4855 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4856#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4857 4858#define S_FW_EQ_CTRL_CMD_EQSTART 28 4859#define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4860#define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4861#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4862 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4863#define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4864 4865#define S_FW_EQ_CTRL_CMD_EQSTOP 27 4866#define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4867#define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4868#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4869 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4870#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4871 4872#define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4873#define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4874#define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4875#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4876 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4877 4878#define S_FW_EQ_CTRL_CMD_EQID 0 4879#define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4880#define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4881#define G_FW_EQ_CTRL_CMD_EQID(x) \ 4882 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4883 4884#define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4885#define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4886#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4887#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4888 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4889 4890#define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4891#define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4892#define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4893#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4894 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4895#define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4896 4897#define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4898#define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4899#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4900#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4901 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4902#define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4903 4904#define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4905#define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4906#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4907#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4908 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4909#define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4910 4911#define S_FW_EQ_CTRL_CMD_FETCHNS 23 4912#define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4913#define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4914#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4915 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4916#define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4917 4918#define S_FW_EQ_CTRL_CMD_FETCHRO 22 4919#define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4920#define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4921#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4922 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4923#define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4924 4925#define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4926#define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4927#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4928#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4929 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4930 4931#define S_FW_EQ_CTRL_CMD_CPRIO 19 4932#define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4933#define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4934#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4935 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4936#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4937 4938#define S_FW_EQ_CTRL_CMD_ONCHIP 18 4939#define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4940#define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4941#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4942 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4943#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4944 4945#define S_FW_EQ_CTRL_CMD_PCIECHN 16 4946#define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4947#define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4948#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4949 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4950 4951#define S_FW_EQ_CTRL_CMD_IQID 0 4952#define M_FW_EQ_CTRL_CMD_IQID 0xffff 4953#define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4954#define G_FW_EQ_CTRL_CMD_IQID(x) \ 4955 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4956 4957#define S_FW_EQ_CTRL_CMD_DCAEN 31 4958#define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4959#define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4960#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4961 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4962#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4963 4964#define S_FW_EQ_CTRL_CMD_DCACPU 26 4965#define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4966#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4967#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4968 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4969 4970#define S_FW_EQ_CTRL_CMD_FBMIN 23 4971#define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4972#define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4973#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4974 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4975 4976#define S_FW_EQ_CTRL_CMD_FBMAX 20 4977#define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4978#define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4979#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4980 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4981 4982#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4983#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4984#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4985 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4986#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4987 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4988#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4989 4990#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4991#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4992#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4993#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4994 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4995 4996#define S_FW_EQ_CTRL_CMD_EQSIZE 0 4997#define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4998#define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4999#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 5000 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 5001 5002struct fw_eq_ofld_cmd { 5003 __be32 op_to_vfn; 5004 __be32 alloc_to_len16; 5005 __be32 eqid_pkd; 5006 __be32 physeqid_pkd; 5007 __be32 fetchszm_to_iqid; 5008 __be32 dcaen_to_eqsize; 5009 __be64 eqaddr; 5010}; 5011 5012#define S_FW_EQ_OFLD_CMD_PFN 8 5013#define M_FW_EQ_OFLD_CMD_PFN 0x7 5014#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 5015#define G_FW_EQ_OFLD_CMD_PFN(x) \ 5016 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 5017 5018#define S_FW_EQ_OFLD_CMD_VFN 0 5019#define M_FW_EQ_OFLD_CMD_VFN 0xff 5020#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 5021#define G_FW_EQ_OFLD_CMD_VFN(x) \ 5022 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 5023 5024#define S_FW_EQ_OFLD_CMD_ALLOC 31 5025#define M_FW_EQ_OFLD_CMD_ALLOC 0x1 5026#define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 5027#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 5028 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 5029#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 5030 5031#define S_FW_EQ_OFLD_CMD_FREE 30 5032#define M_FW_EQ_OFLD_CMD_FREE 0x1 5033#define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 5034#define G_FW_EQ_OFLD_CMD_FREE(x) \ 5035 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 5036#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 5037 5038#define S_FW_EQ_OFLD_CMD_MODIFY 29 5039#define M_FW_EQ_OFLD_CMD_MODIFY 0x1 5040#define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 5041#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 5042 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 5043#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 5044 5045#define S_FW_EQ_OFLD_CMD_EQSTART 28 5046#define M_FW_EQ_OFLD_CMD_EQSTART 0x1 5047#define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 5048#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 5049 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 5050#define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 5051 5052#define S_FW_EQ_OFLD_CMD_EQSTOP 27 5053#define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 5054#define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 5055#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 5056 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 5057#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 5058 5059#define S_FW_EQ_OFLD_CMD_EQID 0 5060#define M_FW_EQ_OFLD_CMD_EQID 0xfffff 5061#define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 5062#define G_FW_EQ_OFLD_CMD_EQID(x) \ 5063 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 5064 5065#define S_FW_EQ_OFLD_CMD_PHYSEQID 0 5066#define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 5067#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 5068#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 5069 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 5070 5071#define S_FW_EQ_OFLD_CMD_FETCHSZM 26 5072#define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 5073#define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 5074#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 5075 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 5076#define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 5077 5078#define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 5079#define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 5080#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 5081#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 5082 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 5083#define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 5084 5085#define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 5086#define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 5087#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 5088#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 5089 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 5090#define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 5091 5092#define S_FW_EQ_OFLD_CMD_FETCHNS 23 5093#define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 5094#define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 5095#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 5096 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 5097#define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 5098 5099#define S_FW_EQ_OFLD_CMD_FETCHRO 22 5100#define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 5101#define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 5102#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 5103 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 5104#define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 5105 5106#define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 5107#define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 5108#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 5109#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 5110 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 5111 5112#define S_FW_EQ_OFLD_CMD_CPRIO 19 5113#define M_FW_EQ_OFLD_CMD_CPRIO 0x1 5114#define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 5115#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 5116 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 5117#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 5118 5119#define S_FW_EQ_OFLD_CMD_ONCHIP 18 5120#define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 5121#define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 5122#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 5123 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 5124#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 5125 5126#define S_FW_EQ_OFLD_CMD_PCIECHN 16 5127#define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 5128#define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 5129#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 5130 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 5131 5132#define S_FW_EQ_OFLD_CMD_IQID 0 5133#define M_FW_EQ_OFLD_CMD_IQID 0xffff 5134#define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 5135#define G_FW_EQ_OFLD_CMD_IQID(x) \ 5136 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 5137 5138#define S_FW_EQ_OFLD_CMD_DCAEN 31 5139#define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5140#define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5141#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5142 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5143#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5144 5145#define S_FW_EQ_OFLD_CMD_DCACPU 26 5146#define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5147#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5148#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5149 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5150 5151#define S_FW_EQ_OFLD_CMD_FBMIN 23 5152#define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5153#define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5154#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5155 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5156 5157#define S_FW_EQ_OFLD_CMD_FBMAX 20 5158#define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5159#define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5160#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5161 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5162 5163#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5164#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5165#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5166 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5167#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5168 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5169#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5170 5171#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5172#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5173#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5174#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5175 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5176 5177#define S_FW_EQ_OFLD_CMD_EQSIZE 0 5178#define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5179#define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5180#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5181 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5182 5183/* Macros for VIID parsing: 5184 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5185#define S_FW_VIID_PFN 8 5186#define M_FW_VIID_PFN 0x7 5187#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5188#define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5189 5190#define S_FW_VIID_VIVLD 7 5191#define M_FW_VIID_VIVLD 0x1 5192#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5193#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5194 5195#define S_FW_VIID_VIN 0 5196#define M_FW_VIID_VIN 0x7F 5197#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5198#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5199 5200enum fw_vi_func { 5201 FW_VI_FUNC_ETH, 5202 FW_VI_FUNC_OFLD, 5203 FW_VI_FUNC_IWARP, 5204 FW_VI_FUNC_OPENISCSI, 5205 FW_VI_FUNC_OPENFCOE, 5206 FW_VI_FUNC_FOISCSI, 5207 FW_VI_FUNC_FOFCOE, 5208 FW_VI_FUNC_FW, 5209}; 5210 5211struct fw_vi_cmd { 5212 __be32 op_to_vfn; 5213 __be32 alloc_to_len16; 5214 __be16 type_to_viid; 5215 __u8 mac[6]; 5216 __u8 portid_pkd; 5217 __u8 nmac; 5218 __u8 nmac0[6]; 5219 __be16 norss_rsssize; 5220 __u8 nmac1[6]; 5221 __be16 idsiiq_pkd; 5222 __u8 nmac2[6]; 5223 __be16 idseiq_pkd; 5224 __u8 nmac3[6]; 5225 __be64 r9; 5226 __be64 r10; 5227}; 5228 5229#define S_FW_VI_CMD_PFN 8 5230#define M_FW_VI_CMD_PFN 0x7 5231#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5232#define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5233 5234#define S_FW_VI_CMD_VFN 0 5235#define M_FW_VI_CMD_VFN 0xff 5236#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5237#define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5238 5239#define S_FW_VI_CMD_ALLOC 31 5240#define M_FW_VI_CMD_ALLOC 0x1 5241#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5242#define G_FW_VI_CMD_ALLOC(x) \ 5243 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5244#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5245 5246#define S_FW_VI_CMD_FREE 30 5247#define M_FW_VI_CMD_FREE 0x1 5248#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5249#define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5250#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5251 5252#define S_FW_VI_CMD_TYPE 15 5253#define M_FW_VI_CMD_TYPE 0x1 5254#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5255#define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5256#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5257 5258#define S_FW_VI_CMD_FUNC 12 5259#define M_FW_VI_CMD_FUNC 0x7 5260#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5261#define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5262 5263#define S_FW_VI_CMD_VIID 0 5264#define M_FW_VI_CMD_VIID 0xfff 5265#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5266#define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5267 5268#define S_FW_VI_CMD_PORTID 4 5269#define M_FW_VI_CMD_PORTID 0xf 5270#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5271#define G_FW_VI_CMD_PORTID(x) \ 5272 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5273 5274#define S_FW_VI_CMD_NORSS 11 5275#define M_FW_VI_CMD_NORSS 0x1 5276#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5277#define G_FW_VI_CMD_NORSS(x) \ 5278 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5279#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5280 5281#define S_FW_VI_CMD_RSSSIZE 0 5282#define M_FW_VI_CMD_RSSSIZE 0x7ff 5283#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5284#define G_FW_VI_CMD_RSSSIZE(x) \ 5285 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5286 5287#define S_FW_VI_CMD_IDSIIQ 0 5288#define M_FW_VI_CMD_IDSIIQ 0x3ff 5289#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5290#define G_FW_VI_CMD_IDSIIQ(x) \ 5291 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5292 5293#define S_FW_VI_CMD_IDSEIQ 0 5294#define M_FW_VI_CMD_IDSEIQ 0x3ff 5295#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5296#define G_FW_VI_CMD_IDSEIQ(x) \ 5297 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5298 5299/* Special VI_MAC command index ids */ 5300#define FW_VI_MAC_ADD_MAC 0x3FF 5301#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5302#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5303 5304enum fw_vi_mac_smac { 5305 FW_VI_MAC_MPS_TCAM_ENTRY, 5306 FW_VI_MAC_MPS_TCAM_ONLY, 5307 FW_VI_MAC_SMT_ONLY, 5308 FW_VI_MAC_SMT_AND_MPSTCAM 5309}; 5310 5311enum fw_vi_mac_result { 5312 FW_VI_MAC_R_SUCCESS, 5313 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5314 FW_VI_MAC_R_SMAC_FAIL, 5315 FW_VI_MAC_R_F_ACL_CHECK 5316}; 5317 5318struct fw_vi_mac_cmd { 5319 __be32 op_to_viid; 5320 __be32 freemacs_to_len16; 5321 union fw_vi_mac { 5322 struct fw_vi_mac_exact { 5323 __be16 valid_to_idx; 5324 __u8 macaddr[6]; 5325 } exact[7]; 5326 struct fw_vi_mac_hash { 5327 __be64 hashvec; 5328 } hash; 5329 } u; 5330}; 5331 5332#define S_FW_VI_MAC_CMD_VIID 0 5333#define M_FW_VI_MAC_CMD_VIID 0xfff 5334#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5335#define G_FW_VI_MAC_CMD_VIID(x) \ 5336 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5337 5338#define S_FW_VI_MAC_CMD_FREEMACS 31 5339#define M_FW_VI_MAC_CMD_FREEMACS 0x1 5340#define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5341#define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5342 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5343#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5344 5345#define S_FW_VI_MAC_CMD_HASHVECEN 23 5346#define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5347#define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5348#define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5349 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5350#define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5351 5352#define S_FW_VI_MAC_CMD_HASHUNIEN 22 5353#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5354#define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5355#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5356 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5357#define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5358 5359#define S_FW_VI_MAC_CMD_VALID 15 5360#define M_FW_VI_MAC_CMD_VALID 0x1 5361#define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5362#define G_FW_VI_MAC_CMD_VALID(x) \ 5363 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5364#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5365 5366#define S_FW_VI_MAC_CMD_PRIO 12 5367#define M_FW_VI_MAC_CMD_PRIO 0x7 5368#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5369#define G_FW_VI_MAC_CMD_PRIO(x) \ 5370 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5371 5372#define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5373#define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5374#define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5375#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5376 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5377 5378#define S_FW_VI_MAC_CMD_IDX 0 5379#define M_FW_VI_MAC_CMD_IDX 0x3ff 5380#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5381#define G_FW_VI_MAC_CMD_IDX(x) \ 5382 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5383 5384/* T4 max MTU supported */ 5385#define T4_MAX_MTU_SUPPORTED 9600 5386#define FW_RXMODE_MTU_NO_CHG 65535 5387 5388struct fw_vi_rxmode_cmd { 5389 __be32 op_to_viid; 5390 __be32 retval_len16; 5391 __be32 mtu_to_vlanexen; 5392 __be32 r4_lo; 5393}; 5394 5395#define S_FW_VI_RXMODE_CMD_VIID 0 5396#define M_FW_VI_RXMODE_CMD_VIID 0xfff 5397#define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5398#define G_FW_VI_RXMODE_CMD_VIID(x) \ 5399 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5400 5401#define S_FW_VI_RXMODE_CMD_MTU 16 5402#define M_FW_VI_RXMODE_CMD_MTU 0xffff 5403#define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5404#define G_FW_VI_RXMODE_CMD_MTU(x) \ 5405 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5406 5407#define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5408#define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5409#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5410#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5411 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5412 5413#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5414#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5415#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5416 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5417#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5418 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5419 5420#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5421#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5422#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5423 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5424#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5425 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5426 5427#define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5428#define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5429#define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5430#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5431 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5432 5433struct fw_vi_enable_cmd { 5434 __be32 op_to_viid; 5435 __be32 ien_to_len16; 5436 __be16 blinkdur; 5437 __be16 r3; 5438 __be32 r4; 5439}; 5440 5441#define S_FW_VI_ENABLE_CMD_VIID 0 5442#define M_FW_VI_ENABLE_CMD_VIID 0xfff 5443#define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5444#define G_FW_VI_ENABLE_CMD_VIID(x) \ 5445 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5446 5447#define S_FW_VI_ENABLE_CMD_IEN 31 5448#define M_FW_VI_ENABLE_CMD_IEN 0x1 5449#define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5450#define G_FW_VI_ENABLE_CMD_IEN(x) \ 5451 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5452#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5453 5454#define S_FW_VI_ENABLE_CMD_EEN 30 5455#define M_FW_VI_ENABLE_CMD_EEN 0x1 5456#define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5457#define G_FW_VI_ENABLE_CMD_EEN(x) \ 5458 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5459#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5460 5461#define S_FW_VI_ENABLE_CMD_LED 29 5462#define M_FW_VI_ENABLE_CMD_LED 0x1 5463#define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5464#define G_FW_VI_ENABLE_CMD_LED(x) \ 5465 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5466#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5467 5468#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5469#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5470#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5471#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5472 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5473#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5474 5475/* VI VF stats offset definitions */ 5476#define VI_VF_NUM_STATS 16 5477enum fw_vi_stats_vf_index { 5478 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5479 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5480 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5481 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5482 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5483 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5484 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5485 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5486 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5487 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5488 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5489 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5490 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5491 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5492 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5493 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5494}; 5495 5496/* VI PF stats offset definitions */ 5497#define VI_PF_NUM_STATS 17 5498enum fw_vi_stats_pf_index { 5499 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5500 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5501 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5502 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5503 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5504 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5505 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5506 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5507 FW_VI_PF_STAT_RX_BYTES_IX, 5508 FW_VI_PF_STAT_RX_FRAMES_IX, 5509 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5510 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5511 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5512 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5513 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5514 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5515 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5516}; 5517 5518struct fw_vi_stats_cmd { 5519 __be32 op_to_viid; 5520 __be32 retval_len16; 5521 union fw_vi_stats { 5522 struct fw_vi_stats_ctl { 5523 __be16 nstats_ix; 5524 __be16 r6; 5525 __be32 r7; 5526 __be64 stat0; 5527 __be64 stat1; 5528 __be64 stat2; 5529 __be64 stat3; 5530 __be64 stat4; 5531 __be64 stat5; 5532 } ctl; 5533 struct fw_vi_stats_pf { 5534 __be64 tx_bcast_bytes; 5535 __be64 tx_bcast_frames; 5536 __be64 tx_mcast_bytes; 5537 __be64 tx_mcast_frames; 5538 __be64 tx_ucast_bytes; 5539 __be64 tx_ucast_frames; 5540 __be64 tx_offload_bytes; 5541 __be64 tx_offload_frames; 5542 __be64 rx_pf_bytes; 5543 __be64 rx_pf_frames; 5544 __be64 rx_bcast_bytes; 5545 __be64 rx_bcast_frames; 5546 __be64 rx_mcast_bytes; 5547 __be64 rx_mcast_frames; 5548 __be64 rx_ucast_bytes; 5549 __be64 rx_ucast_frames; 5550 __be64 rx_err_frames; 5551 } pf; 5552 struct fw_vi_stats_vf { 5553 __be64 tx_bcast_bytes; 5554 __be64 tx_bcast_frames; 5555 __be64 tx_mcast_bytes; 5556 __be64 tx_mcast_frames; 5557 __be64 tx_ucast_bytes; 5558 __be64 tx_ucast_frames; 5559 __be64 tx_drop_frames; 5560 __be64 tx_offload_bytes; 5561 __be64 tx_offload_frames; 5562 __be64 rx_bcast_bytes; 5563 __be64 rx_bcast_frames; 5564 __be64 rx_mcast_bytes; 5565 __be64 rx_mcast_frames; 5566 __be64 rx_ucast_bytes; 5567 __be64 rx_ucast_frames; 5568 __be64 rx_err_frames; 5569 } vf; 5570 } u; 5571}; 5572 5573#define S_FW_VI_STATS_CMD_VIID 0 5574#define M_FW_VI_STATS_CMD_VIID 0xfff 5575#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5576#define G_FW_VI_STATS_CMD_VIID(x) \ 5577 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5578 5579#define S_FW_VI_STATS_CMD_NSTATS 12 5580#define M_FW_VI_STATS_CMD_NSTATS 0x7 5581#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5582#define G_FW_VI_STATS_CMD_NSTATS(x) \ 5583 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5584 5585#define S_FW_VI_STATS_CMD_IX 0 5586#define M_FW_VI_STATS_CMD_IX 0x1f 5587#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5588#define G_FW_VI_STATS_CMD_IX(x) \ 5589 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5590 5591struct fw_acl_mac_cmd { 5592 __be32 op_to_vfn; 5593 __be32 en_to_len16; 5594 __u8 nmac; 5595 __u8 r3[7]; 5596 __be16 r4; 5597 __u8 macaddr0[6]; 5598 __be16 r5; 5599 __u8 macaddr1[6]; 5600 __be16 r6; 5601 __u8 macaddr2[6]; 5602 __be16 r7; 5603 __u8 macaddr3[6]; 5604}; 5605 5606#define S_FW_ACL_MAC_CMD_PFN 8 5607#define M_FW_ACL_MAC_CMD_PFN 0x7 5608#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5609#define G_FW_ACL_MAC_CMD_PFN(x) \ 5610 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5611 5612#define S_FW_ACL_MAC_CMD_VFN 0 5613#define M_FW_ACL_MAC_CMD_VFN 0xff 5614#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5615#define G_FW_ACL_MAC_CMD_VFN(x) \ 5616 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5617 5618#define S_FW_ACL_MAC_CMD_EN 31 5619#define M_FW_ACL_MAC_CMD_EN 0x1 5620#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5621#define G_FW_ACL_MAC_CMD_EN(x) \ 5622 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5623#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5624 5625struct fw_acl_vlan_cmd { 5626 __be32 op_to_vfn; 5627 __be32 en_to_len16; 5628 __u8 nvlan; 5629 __u8 dropnovlan_fm; 5630 __u8 r3_lo[6]; 5631 __be16 vlanid[16]; 5632}; 5633 5634#define S_FW_ACL_VLAN_CMD_PFN 8 5635#define M_FW_ACL_VLAN_CMD_PFN 0x7 5636#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5637#define G_FW_ACL_VLAN_CMD_PFN(x) \ 5638 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5639 5640#define S_FW_ACL_VLAN_CMD_VFN 0 5641#define M_FW_ACL_VLAN_CMD_VFN 0xff 5642#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5643#define G_FW_ACL_VLAN_CMD_VFN(x) \ 5644 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5645 5646#define S_FW_ACL_VLAN_CMD_EN 31 5647#define M_FW_ACL_VLAN_CMD_EN 0x1 5648#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5649#define G_FW_ACL_VLAN_CMD_EN(x) \ 5650 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5651#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5652 5653#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5654#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5655#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5656#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5657 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5658#define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5659 5660#define S_FW_ACL_VLAN_CMD_FM 6 5661#define M_FW_ACL_VLAN_CMD_FM 0x1 5662#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5663#define G_FW_ACL_VLAN_CMD_FM(x) \ 5664 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5665#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5666 5667/* port capabilities bitmap */ 5668enum fw_port_cap { 5669 FW_PORT_CAP_SPEED_100M = 0x0001, 5670 FW_PORT_CAP_SPEED_1G = 0x0002, 5671 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5672 FW_PORT_CAP_SPEED_10G = 0x0008, 5673 FW_PORT_CAP_SPEED_40G = 0x0010, 5674 FW_PORT_CAP_SPEED_100G = 0x0020, 5675 FW_PORT_CAP_FC_RX = 0x0040, 5676 FW_PORT_CAP_FC_TX = 0x0080, 5677 FW_PORT_CAP_ANEG = 0x0100, 5678 FW_PORT_CAP_MDIX = 0x0200, 5679 FW_PORT_CAP_MDIAUTO = 0x0400, 5680 FW_PORT_CAP_FEC = 0x0800, 5681 FW_PORT_CAP_TECHKR = 0x1000, 5682 FW_PORT_CAP_TECHKX4 = 0x2000, 5683}; 5684 5685#define S_FW_PORT_AUXLINFO_MDI 3 5686#define M_FW_PORT_AUXLINFO_MDI 0x3 5687#define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5688#define G_FW_PORT_AUXLINFO_MDI(x) \ 5689 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5690 5691#define S_FW_PORT_AUXLINFO_KX4 2 5692#define M_FW_PORT_AUXLINFO_KX4 0x1 5693#define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5694#define G_FW_PORT_AUXLINFO_KX4(x) \ 5695 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5696#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5697 5698#define S_FW_PORT_AUXLINFO_KR 1 5699#define M_FW_PORT_AUXLINFO_KR 0x1 5700#define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5701#define G_FW_PORT_AUXLINFO_KR(x) \ 5702 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5703#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5704 5705#define S_FW_PORT_AUXLINFO_FEC 0 5706#define M_FW_PORT_AUXLINFO_FEC 0x1 5707#define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5708#define G_FW_PORT_AUXLINFO_FEC(x) \ 5709 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5710#define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5711 5712#define S_FW_PORT_RCAP_AUX 11 5713#define M_FW_PORT_RCAP_AUX 0x7 5714#define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5715#define G_FW_PORT_RCAP_AUX(x) \ 5716 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5717 5718#define S_FW_PORT_CAP_SPEED 0 5719#define M_FW_PORT_CAP_SPEED 0x3f 5720#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5721#define G_FW_PORT_CAP_SPEED(x) \ 5722 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5723 5724#define S_FW_PORT_CAP_FC 6 5725#define M_FW_PORT_CAP_FC 0x3 5726#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5727#define G_FW_PORT_CAP_FC(x) \ 5728 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5729 5730#define S_FW_PORT_CAP_ANEG 8 5731#define M_FW_PORT_CAP_ANEG 0x1 5732#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5733#define G_FW_PORT_CAP_ANEG(x) \ 5734 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5735 5736enum fw_port_mdi { 5737 FW_PORT_CAP_MDI_UNCHANGED, 5738 FW_PORT_CAP_MDI_AUTO, 5739 FW_PORT_CAP_MDI_F_STRAIGHT, 5740 FW_PORT_CAP_MDI_F_CROSSOVER 5741}; 5742 5743#define S_FW_PORT_CAP_MDI 9 5744#define M_FW_PORT_CAP_MDI 3 5745#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5746#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5747 5748enum fw_port_action { 5749 FW_PORT_ACTION_L1_CFG = 0x0001, 5750 FW_PORT_ACTION_L2_CFG = 0x0002, 5751 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5752 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5753 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5754 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5755 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5756 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5757 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5758 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5759 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5760 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5761 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 5762 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 5763 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 5764 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 5765 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5766 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 5767 FW_PORT_ACTION_PHY_RESET = 0x0040, 5768 FW_PORT_ACTION_PMA_RESET = 0x0041, 5769 FW_PORT_ACTION_PCS_RESET = 0x0042, 5770 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5771 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5772 FW_PORT_ACTION_AN_RESET = 0x0045, 5773 5774}; 5775 5776enum fw_port_l2cfg_ctlbf { 5777 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5778 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5779 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5780 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5781 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5782 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5783 FW_PORT_L2_CTLBF_MTU = 0x40 5784}; 5785 5786enum fw_dcb_app_tlv_sf { 5787 FW_DCB_APP_SF_ETHERTYPE, 5788 FW_DCB_APP_SF_SOCKET_TCP, 5789 FW_DCB_APP_SF_SOCKET_UDP, 5790 FW_DCB_APP_SF_SOCKET_ALL, 5791}; 5792 5793enum fw_port_dcb_versions { 5794 FW_PORT_DCB_VER_CEE1D0, 5795 FW_PORT_DCB_VER_CEE1D01, 5796 FW_PORT_DCB_VER_IEEE, 5797 FW_PORT_DCB_VER_UNKNOWN=7 5798}; 5799 5800enum fw_port_dcb_cfg { 5801 FW_PORT_DCB_CFG_PG = 0x01, 5802 FW_PORT_DCB_CFG_PFC = 0x02, 5803 FW_PORT_DCB_CFG_APPL = 0x04 5804}; 5805 5806enum fw_port_dcb_cfg_rc { 5807 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5808 FW_PORT_DCB_CFG_ERROR = 0x1 5809}; 5810 5811enum fw_port_dcb_type { 5812 FW_PORT_DCB_TYPE_PGID = 0x00, 5813 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5814 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5815 FW_PORT_DCB_TYPE_PFC = 0x03, 5816 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5817 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5818}; 5819 5820enum fw_port_dcb_feature_state { 5821 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 5822 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 5823 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 5824 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 5825}; 5826 5827enum fw_port_diag_ops { 5828 FW_PORT_DIAGS_TEMP = 0x00, 5829 FW_PORT_DIAGS_TX_POWER = 0x01, 5830 FW_PORT_DIAGS_RX_POWER = 0x02, 5831 FW_PORT_DIAGS_TX_DIS = 0x03, 5832}; 5833 5834struct fw_port_cmd { 5835 __be32 op_to_portid; 5836 __be32 action_to_len16; 5837 union fw_port { 5838 struct fw_port_l1cfg { 5839 __be32 rcap; 5840 __be32 r; 5841 } l1cfg; 5842 struct fw_port_l2cfg { 5843 __u8 ctlbf; 5844 __u8 ovlan3_to_ivlan0; 5845 __be16 ivlantype; 5846 __be16 txipg_force_pinfo; 5847 __be16 mtu; 5848 __be16 ovlan0mask; 5849 __be16 ovlan0type; 5850 __be16 ovlan1mask; 5851 __be16 ovlan1type; 5852 __be16 ovlan2mask; 5853 __be16 ovlan2type; 5854 __be16 ovlan3mask; 5855 __be16 ovlan3type; 5856 } l2cfg; 5857 struct fw_port_info { 5858 __be32 lstatus_to_modtype; 5859 __be16 pcap; 5860 __be16 acap; 5861 __be16 mtu; 5862 __u8 cbllen; 5863 __u8 auxlinfo; 5864 __u8 dcbxdis_pkd; 5865 __u8 r8_lo; 5866 __be16 lpcap; 5867 __be64 r9; 5868 } info; 5869 struct fw_port_diags { 5870 __u8 diagop; 5871 __u8 r[3]; 5872 __be32 diagval; 5873 } diags; 5874 union fw_port_dcb { 5875 struct fw_port_dcb_pgid { 5876 __u8 type; 5877 __u8 apply_pkd; 5878 __u8 r10_lo[2]; 5879 __be32 pgid; 5880 __be64 r11; 5881 } pgid; 5882 struct fw_port_dcb_pgrate { 5883 __u8 type; 5884 __u8 apply_pkd; 5885 __u8 r10_lo[5]; 5886 __u8 num_tcs_supported; 5887 __u8 pgrate[8]; 5888 } pgrate; 5889 struct fw_port_dcb_priorate { 5890 __u8 type; 5891 __u8 apply_pkd; 5892 __u8 r10_lo[6]; 5893 __u8 strict_priorate[8]; 5894 } priorate; 5895 struct fw_port_dcb_pfc { 5896 __u8 type; 5897 __u8 pfcen; 5898 __u8 r10[5]; 5899 __u8 max_pfc_tcs; 5900 __be64 r11; 5901 } pfc; 5902 struct fw_port_app_priority { 5903 __u8 type; 5904 __u8 r10[2]; 5905 __u8 idx; 5906 __u8 user_prio_map; 5907 __u8 sel_field; 5908 __be16 protocolid; 5909 __be64 r12; 5910 } app_priority; 5911 struct fw_port_dcb_control { 5912 __u8 type; 5913 __u8 all_syncd_pkd; 5914 __be16 pfc_state_to_app_state; 5915 __be32 r11; 5916 __be64 r12; 5917 } control; 5918 } dcb; 5919 } u; 5920}; 5921 5922#define S_FW_PORT_CMD_READ 22 5923#define M_FW_PORT_CMD_READ 0x1 5924#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5925#define G_FW_PORT_CMD_READ(x) \ 5926 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5927#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5928 5929#define S_FW_PORT_CMD_PORTID 0 5930#define M_FW_PORT_CMD_PORTID 0xf 5931#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5932#define G_FW_PORT_CMD_PORTID(x) \ 5933 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5934 5935#define S_FW_PORT_CMD_ACTION 16 5936#define M_FW_PORT_CMD_ACTION 0xffff 5937#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5938#define G_FW_PORT_CMD_ACTION(x) \ 5939 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5940 5941#define S_FW_PORT_CMD_OVLAN3 7 5942#define M_FW_PORT_CMD_OVLAN3 0x1 5943#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5944#define G_FW_PORT_CMD_OVLAN3(x) \ 5945 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5946#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5947 5948#define S_FW_PORT_CMD_OVLAN2 6 5949#define M_FW_PORT_CMD_OVLAN2 0x1 5950#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5951#define G_FW_PORT_CMD_OVLAN2(x) \ 5952 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5953#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5954 5955#define S_FW_PORT_CMD_OVLAN1 5 5956#define M_FW_PORT_CMD_OVLAN1 0x1 5957#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5958#define G_FW_PORT_CMD_OVLAN1(x) \ 5959 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5960#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5961 5962#define S_FW_PORT_CMD_OVLAN0 4 5963#define M_FW_PORT_CMD_OVLAN0 0x1 5964#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5965#define G_FW_PORT_CMD_OVLAN0(x) \ 5966 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5967#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5968 5969#define S_FW_PORT_CMD_IVLAN0 3 5970#define M_FW_PORT_CMD_IVLAN0 0x1 5971#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5972#define G_FW_PORT_CMD_IVLAN0(x) \ 5973 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5974#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5975 5976#define S_FW_PORT_CMD_TXIPG 3 5977#define M_FW_PORT_CMD_TXIPG 0x1fff 5978#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5979#define G_FW_PORT_CMD_TXIPG(x) \ 5980 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5981 5982#define S_FW_PORT_CMD_FORCE_PINFO 0 5983#define M_FW_PORT_CMD_FORCE_PINFO 0x1 5984#define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5985#define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5986 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5987#define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5988 5989#define S_FW_PORT_CMD_LSTATUS 31 5990#define M_FW_PORT_CMD_LSTATUS 0x1 5991#define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5992#define G_FW_PORT_CMD_LSTATUS(x) \ 5993 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5994#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5995 5996#define S_FW_PORT_CMD_LSPEED 24 5997#define M_FW_PORT_CMD_LSPEED 0x3f 5998#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5999#define G_FW_PORT_CMD_LSPEED(x) \ 6000 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 6001 6002#define S_FW_PORT_CMD_TXPAUSE 23 6003#define M_FW_PORT_CMD_TXPAUSE 0x1 6004#define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 6005#define G_FW_PORT_CMD_TXPAUSE(x) \ 6006 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 6007#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 6008 6009#define S_FW_PORT_CMD_RXPAUSE 22 6010#define M_FW_PORT_CMD_RXPAUSE 0x1 6011#define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 6012#define G_FW_PORT_CMD_RXPAUSE(x) \ 6013 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 6014#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 6015 6016#define S_FW_PORT_CMD_MDIOCAP 21 6017#define M_FW_PORT_CMD_MDIOCAP 0x1 6018#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 6019#define G_FW_PORT_CMD_MDIOCAP(x) \ 6020 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 6021#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 6022 6023#define S_FW_PORT_CMD_MDIOADDR 16 6024#define M_FW_PORT_CMD_MDIOADDR 0x1f 6025#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 6026#define G_FW_PORT_CMD_MDIOADDR(x) \ 6027 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 6028 6029#define S_FW_PORT_CMD_LPTXPAUSE 15 6030#define M_FW_PORT_CMD_LPTXPAUSE 0x1 6031#define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 6032#define G_FW_PORT_CMD_LPTXPAUSE(x) \ 6033 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 6034#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 6035 6036#define S_FW_PORT_CMD_LPRXPAUSE 14 6037#define M_FW_PORT_CMD_LPRXPAUSE 0x1 6038#define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 6039#define G_FW_PORT_CMD_LPRXPAUSE(x) \ 6040 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 6041#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 6042 6043#define S_FW_PORT_CMD_PTYPE 8 6044#define M_FW_PORT_CMD_PTYPE 0x1f 6045#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 6046#define G_FW_PORT_CMD_PTYPE(x) \ 6047 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 6048 6049#define S_FW_PORT_CMD_LINKDNRC 5 6050#define M_FW_PORT_CMD_LINKDNRC 0x7 6051#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 6052#define G_FW_PORT_CMD_LINKDNRC(x) \ 6053 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 6054 6055#define S_FW_PORT_CMD_MODTYPE 0 6056#define M_FW_PORT_CMD_MODTYPE 0x1f 6057#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 6058#define G_FW_PORT_CMD_MODTYPE(x) \ 6059 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 6060 6061#define S_FW_PORT_CMD_DCBXDIS 7 6062#define M_FW_PORT_CMD_DCBXDIS 0x1 6063#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 6064#define G_FW_PORT_CMD_DCBXDIS(x) \ 6065 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 6066#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 6067 6068#define S_FW_PORT_CMD_APPLY 7 6069#define M_FW_PORT_CMD_APPLY 0x1 6070#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 6071#define G_FW_PORT_CMD_APPLY(x) \ 6072 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 6073#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 6074 6075#define S_FW_PORT_CMD_ALL_SYNCD 7 6076#define M_FW_PORT_CMD_ALL_SYNCD 0x1 6077#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 6078#define G_FW_PORT_CMD_ALL_SYNCD(x) \ 6079 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 6080#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 6081 6082#define S_FW_PORT_CMD_PFC_STATE 8 6083#define M_FW_PORT_CMD_PFC_STATE 0xf 6084#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 6085#define G_FW_PORT_CMD_PFC_STATE(x) \ 6086 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 6087 6088#define S_FW_PORT_CMD_ETS_STATE 4 6089#define M_FW_PORT_CMD_ETS_STATE 0xf 6090#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 6091#define G_FW_PORT_CMD_ETS_STATE(x) \ 6092 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 6093 6094#define S_FW_PORT_CMD_APP_STATE 0 6095#define M_FW_PORT_CMD_APP_STATE 0xf 6096#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 6097#define G_FW_PORT_CMD_APP_STATE(x) \ 6098 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 6099 6100/* 6101 * These are configured into the VPD and hence tools that generate 6102 * VPD may use this enumeration. 6103 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 6104 * 6105 * REMEMBER: 6106 * Update the Common Code t4_hw.c:t4_get_port_type_description() 6107 * with any new Firmware Port Technology Types! 6108 */ 6109enum fw_port_type { 6110 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 6111 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 6112 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 6113 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 6114 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 6115 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 6116 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 6117 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 6118 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 6119 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 6120 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 6121 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 6122 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 6123 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 6124 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 6125 6126 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 6127}; 6128 6129/* These are read from module's EEPROM and determined once the 6130 module is inserted. */ 6131enum fw_port_module_type { 6132 FW_PORT_MOD_TYPE_NA = 0x0, 6133 FW_PORT_MOD_TYPE_LR = 0x1, 6134 FW_PORT_MOD_TYPE_SR = 0x2, 6135 FW_PORT_MOD_TYPE_ER = 0x3, 6136 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 6137 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 6138 FW_PORT_MOD_TYPE_LRM = 0x6, 6139 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 6140 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 6141 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 6142 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 6143}; 6144 6145/* used by FW and tools may use this to generate VPD */ 6146enum fw_port_mod_sub_type { 6147 FW_PORT_MOD_SUB_TYPE_NA, 6148 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6149 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6150 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6151 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6152 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 6153 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 6154 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6155 6156 /* 6157 * The following will never been in the VPD. They are TWINAX cable 6158 * lengths decoded from SFP+ module i2c PROMs. These should almost 6159 * certainly go somewhere else ... 6160 */ 6161 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 6162 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 6163 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 6164 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 6165}; 6166 6167/* link down reason codes (3b) */ 6168enum fw_port_link_dn_rc { 6169 FW_PORT_LINK_DN_RC_NONE, 6170 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 6171 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 6172 FW_PORT_LINK_DN_RESERVED3, 6173 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 6174 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 6175 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 6176 FW_PORT_LINK_DN_RESERVED7 6177}; 6178 6179/* port stats */ 6180#define FW_NUM_PORT_STATS 50 6181#define FW_NUM_PORT_TX_STATS 23 6182#define FW_NUM_PORT_RX_STATS 27 6183 6184enum fw_port_stats_tx_index { 6185 FW_STAT_TX_PORT_BYTES_IX, 6186 FW_STAT_TX_PORT_FRAMES_IX, 6187 FW_STAT_TX_PORT_BCAST_IX, 6188 FW_STAT_TX_PORT_MCAST_IX, 6189 FW_STAT_TX_PORT_UCAST_IX, 6190 FW_STAT_TX_PORT_ERROR_IX, 6191 FW_STAT_TX_PORT_64B_IX, 6192 FW_STAT_TX_PORT_65B_127B_IX, 6193 FW_STAT_TX_PORT_128B_255B_IX, 6194 FW_STAT_TX_PORT_256B_511B_IX, 6195 FW_STAT_TX_PORT_512B_1023B_IX, 6196 FW_STAT_TX_PORT_1024B_1518B_IX, 6197 FW_STAT_TX_PORT_1519B_MAX_IX, 6198 FW_STAT_TX_PORT_DROP_IX, 6199 FW_STAT_TX_PORT_PAUSE_IX, 6200 FW_STAT_TX_PORT_PPP0_IX, 6201 FW_STAT_TX_PORT_PPP1_IX, 6202 FW_STAT_TX_PORT_PPP2_IX, 6203 FW_STAT_TX_PORT_PPP3_IX, 6204 FW_STAT_TX_PORT_PPP4_IX, 6205 FW_STAT_TX_PORT_PPP5_IX, 6206 FW_STAT_TX_PORT_PPP6_IX, 6207 FW_STAT_TX_PORT_PPP7_IX 6208}; 6209 6210enum fw_port_stat_rx_index { 6211 FW_STAT_RX_PORT_BYTES_IX, 6212 FW_STAT_RX_PORT_FRAMES_IX, 6213 FW_STAT_RX_PORT_BCAST_IX, 6214 FW_STAT_RX_PORT_MCAST_IX, 6215 FW_STAT_RX_PORT_UCAST_IX, 6216 FW_STAT_RX_PORT_MTU_ERROR_IX, 6217 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6218 FW_STAT_RX_PORT_CRC_ERROR_IX, 6219 FW_STAT_RX_PORT_LEN_ERROR_IX, 6220 FW_STAT_RX_PORT_SYM_ERROR_IX, 6221 FW_STAT_RX_PORT_64B_IX, 6222 FW_STAT_RX_PORT_65B_127B_IX, 6223 FW_STAT_RX_PORT_128B_255B_IX, 6224 FW_STAT_RX_PORT_256B_511B_IX, 6225 FW_STAT_RX_PORT_512B_1023B_IX, 6226 FW_STAT_RX_PORT_1024B_1518B_IX, 6227 FW_STAT_RX_PORT_1519B_MAX_IX, 6228 FW_STAT_RX_PORT_PAUSE_IX, 6229 FW_STAT_RX_PORT_PPP0_IX, 6230 FW_STAT_RX_PORT_PPP1_IX, 6231 FW_STAT_RX_PORT_PPP2_IX, 6232 FW_STAT_RX_PORT_PPP3_IX, 6233 FW_STAT_RX_PORT_PPP4_IX, 6234 FW_STAT_RX_PORT_PPP5_IX, 6235 FW_STAT_RX_PORT_PPP6_IX, 6236 FW_STAT_RX_PORT_PPP7_IX, 6237 FW_STAT_RX_PORT_LESS_64B_IX 6238}; 6239 6240struct fw_port_stats_cmd { 6241 __be32 op_to_portid; 6242 __be32 retval_len16; 6243 union fw_port_stats { 6244 struct fw_port_stats_ctl { 6245 __u8 nstats_bg_bm; 6246 __u8 tx_ix; 6247 __be16 r6; 6248 __be32 r7; 6249 __be64 stat0; 6250 __be64 stat1; 6251 __be64 stat2; 6252 __be64 stat3; 6253 __be64 stat4; 6254 __be64 stat5; 6255 } ctl; 6256 struct fw_port_stats_all { 6257 __be64 tx_bytes; 6258 __be64 tx_frames; 6259 __be64 tx_bcast; 6260 __be64 tx_mcast; 6261 __be64 tx_ucast; 6262 __be64 tx_error; 6263 __be64 tx_64b; 6264 __be64 tx_65b_127b; 6265 __be64 tx_128b_255b; 6266 __be64 tx_256b_511b; 6267 __be64 tx_512b_1023b; 6268 __be64 tx_1024b_1518b; 6269 __be64 tx_1519b_max; 6270 __be64 tx_drop; 6271 __be64 tx_pause; 6272 __be64 tx_ppp0; 6273 __be64 tx_ppp1; 6274 __be64 tx_ppp2; 6275 __be64 tx_ppp3; 6276 __be64 tx_ppp4; 6277 __be64 tx_ppp5; 6278 __be64 tx_ppp6; 6279 __be64 tx_ppp7; 6280 __be64 rx_bytes; 6281 __be64 rx_frames; 6282 __be64 rx_bcast; 6283 __be64 rx_mcast; 6284 __be64 rx_ucast; 6285 __be64 rx_mtu_error; 6286 __be64 rx_mtu_crc_error; 6287 __be64 rx_crc_error; 6288 __be64 rx_len_error; 6289 __be64 rx_sym_error; 6290 __be64 rx_64b; 6291 __be64 rx_65b_127b; 6292 __be64 rx_128b_255b; 6293 __be64 rx_256b_511b; 6294 __be64 rx_512b_1023b; 6295 __be64 rx_1024b_1518b; 6296 __be64 rx_1519b_max; 6297 __be64 rx_pause; 6298 __be64 rx_ppp0; 6299 __be64 rx_ppp1; 6300 __be64 rx_ppp2; 6301 __be64 rx_ppp3; 6302 __be64 rx_ppp4; 6303 __be64 rx_ppp5; 6304 __be64 rx_ppp6; 6305 __be64 rx_ppp7; 6306 __be64 rx_less_64b; 6307 __be64 rx_bg_drop; 6308 __be64 rx_bg_trunc; 6309 } all; 6310 } u; 6311}; 6312 6313#define S_FW_PORT_STATS_CMD_NSTATS 4 6314#define M_FW_PORT_STATS_CMD_NSTATS 0x7 6315#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6316#define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6317 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6318 6319#define S_FW_PORT_STATS_CMD_BG_BM 0 6320#define M_FW_PORT_STATS_CMD_BG_BM 0x3 6321#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6322#define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6323 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6324 6325#define S_FW_PORT_STATS_CMD_TX 7 6326#define M_FW_PORT_STATS_CMD_TX 0x1 6327#define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6328#define G_FW_PORT_STATS_CMD_TX(x) \ 6329 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6330#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6331 6332#define S_FW_PORT_STATS_CMD_IX 0 6333#define M_FW_PORT_STATS_CMD_IX 0x3f 6334#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6335#define G_FW_PORT_STATS_CMD_IX(x) \ 6336 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6337 6338/* port loopback stats */ 6339#define FW_NUM_LB_STATS 14 6340enum fw_port_lb_stats_index { 6341 FW_STAT_LB_PORT_BYTES_IX, 6342 FW_STAT_LB_PORT_FRAMES_IX, 6343 FW_STAT_LB_PORT_BCAST_IX, 6344 FW_STAT_LB_PORT_MCAST_IX, 6345 FW_STAT_LB_PORT_UCAST_IX, 6346 FW_STAT_LB_PORT_ERROR_IX, 6347 FW_STAT_LB_PORT_64B_IX, 6348 FW_STAT_LB_PORT_65B_127B_IX, 6349 FW_STAT_LB_PORT_128B_255B_IX, 6350 FW_STAT_LB_PORT_256B_511B_IX, 6351 FW_STAT_LB_PORT_512B_1023B_IX, 6352 FW_STAT_LB_PORT_1024B_1518B_IX, 6353 FW_STAT_LB_PORT_1519B_MAX_IX, 6354 FW_STAT_LB_PORT_DROP_FRAMES_IX 6355}; 6356 6357struct fw_port_lb_stats_cmd { 6358 __be32 op_to_lbport; 6359 __be32 retval_len16; 6360 union fw_port_lb_stats { 6361 struct fw_port_lb_stats_ctl { 6362 __u8 nstats_bg_bm; 6363 __u8 ix_pkd; 6364 __be16 r6; 6365 __be32 r7; 6366 __be64 stat0; 6367 __be64 stat1; 6368 __be64 stat2; 6369 __be64 stat3; 6370 __be64 stat4; 6371 __be64 stat5; 6372 } ctl; 6373 struct fw_port_lb_stats_all { 6374 __be64 tx_bytes; 6375 __be64 tx_frames; 6376 __be64 tx_bcast; 6377 __be64 tx_mcast; 6378 __be64 tx_ucast; 6379 __be64 tx_error; 6380 __be64 tx_64b; 6381 __be64 tx_65b_127b; 6382 __be64 tx_128b_255b; 6383 __be64 tx_256b_511b; 6384 __be64 tx_512b_1023b; 6385 __be64 tx_1024b_1518b; 6386 __be64 tx_1519b_max; 6387 __be64 rx_lb_drop; 6388 __be64 rx_lb_trunc; 6389 } all; 6390 } u; 6391}; 6392 6393#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6394#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6395#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6396 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6397#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6398 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6399 6400#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6401#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6402#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6403 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6404#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6405 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6406 6407#define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6408#define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6409#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6410#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6411 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6412 6413#define S_FW_PORT_LB_STATS_CMD_IX 0 6414#define M_FW_PORT_LB_STATS_CMD_IX 0xf 6415#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6416#define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6417 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6418 6419/* Trace related defines */ 6420#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6421#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6422 6423struct fw_port_trace_cmd { 6424 __be32 op_to_portid; 6425 __be32 retval_len16; 6426 __be16 traceen_to_pciech; 6427 __be16 qnum; 6428 __be32 r5; 6429}; 6430 6431#define S_FW_PORT_TRACE_CMD_PORTID 0 6432#define M_FW_PORT_TRACE_CMD_PORTID 0xf 6433#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6434#define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6435 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6436 6437#define S_FW_PORT_TRACE_CMD_TRACEEN 15 6438#define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6439#define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6440#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6441 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6442#define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6443 6444#define S_FW_PORT_TRACE_CMD_FLTMODE 14 6445#define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6446#define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6447#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6448 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6449#define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6450 6451#define S_FW_PORT_TRACE_CMD_DUPLEN 13 6452#define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6453#define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6454#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6455 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6456#define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6457 6458#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6459#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6460#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6461 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6462#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6463 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6464 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6465 6466#define S_FW_PORT_TRACE_CMD_PCIECH 6 6467#define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6468#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6469#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6470 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6471 6472struct fw_port_trace_mmap_cmd { 6473 __be32 op_to_portid; 6474 __be32 retval_len16; 6475 __be32 fid_to_skipoffset; 6476 __be32 minpktsize_capturemax; 6477 __u8 map[224]; 6478}; 6479 6480#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6481#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6482#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6483 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6484#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6485 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6486 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6487 6488#define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6489#define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6490#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6491#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6492 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6493 6494#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6495#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6496#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6497 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6498#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6499 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6500 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6501#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6502 6503#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6504#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6505#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6506 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6507#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6508 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6509 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6510#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6511 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6512 6513#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6514#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6515#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6516 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6517#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6518 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6519 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6520 6521#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6522#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6523#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6524 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6525#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6526 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6527 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6528 6529#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6530#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6531#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6532 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6533#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6534 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6535 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6536 6537#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6538#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6539#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6540 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6541#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6542 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6543 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6544 6545struct fw_rss_ind_tbl_cmd { 6546 __be32 op_to_viid; 6547 __be32 retval_len16; 6548 __be16 niqid; 6549 __be16 startidx; 6550 __be32 r3; 6551 __be32 iq0_to_iq2; 6552 __be32 iq3_to_iq5; 6553 __be32 iq6_to_iq8; 6554 __be32 iq9_to_iq11; 6555 __be32 iq12_to_iq14; 6556 __be32 iq15_to_iq17; 6557 __be32 iq18_to_iq20; 6558 __be32 iq21_to_iq23; 6559 __be32 iq24_to_iq26; 6560 __be32 iq27_to_iq29; 6561 __be32 iq30_iq31; 6562 __be32 r15_lo; 6563}; 6564 6565#define S_FW_RSS_IND_TBL_CMD_VIID 0 6566#define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6567#define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6568#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6569 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6570 6571#define S_FW_RSS_IND_TBL_CMD_IQ0 20 6572#define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6573#define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6574#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6575 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6576 6577#define S_FW_RSS_IND_TBL_CMD_IQ1 10 6578#define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6579#define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6580#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6581 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6582 6583#define S_FW_RSS_IND_TBL_CMD_IQ2 0 6584#define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6585#define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6586#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6587 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6588 6589#define S_FW_RSS_IND_TBL_CMD_IQ3 20 6590#define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6591#define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6592#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6593 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6594 6595#define S_FW_RSS_IND_TBL_CMD_IQ4 10 6596#define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6597#define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6598#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6599 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6600 6601#define S_FW_RSS_IND_TBL_CMD_IQ5 0 6602#define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6603#define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6604#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6605 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6606 6607#define S_FW_RSS_IND_TBL_CMD_IQ6 20 6608#define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6609#define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6610#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6611 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6612 6613#define S_FW_RSS_IND_TBL_CMD_IQ7 10 6614#define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6615#define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6616#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6617 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6618 6619#define S_FW_RSS_IND_TBL_CMD_IQ8 0 6620#define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6621#define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6622#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6623 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6624 6625#define S_FW_RSS_IND_TBL_CMD_IQ9 20 6626#define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6627#define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6628#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6629 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6630 6631#define S_FW_RSS_IND_TBL_CMD_IQ10 10 6632#define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6633#define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6634#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6635 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6636 6637#define S_FW_RSS_IND_TBL_CMD_IQ11 0 6638#define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6639#define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6640#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6641 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6642 6643#define S_FW_RSS_IND_TBL_CMD_IQ12 20 6644#define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6645#define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6646#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6647 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6648 6649#define S_FW_RSS_IND_TBL_CMD_IQ13 10 6650#define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6651#define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6652#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6653 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6654 6655#define S_FW_RSS_IND_TBL_CMD_IQ14 0 6656#define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6657#define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6658#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6659 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6660 6661#define S_FW_RSS_IND_TBL_CMD_IQ15 20 6662#define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6663#define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6664#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6665 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6666 6667#define S_FW_RSS_IND_TBL_CMD_IQ16 10 6668#define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6669#define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6670#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6671 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6672 6673#define S_FW_RSS_IND_TBL_CMD_IQ17 0 6674#define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6675#define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6676#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6677 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6678 6679#define S_FW_RSS_IND_TBL_CMD_IQ18 20 6680#define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6681#define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6682#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6683 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6684 6685#define S_FW_RSS_IND_TBL_CMD_IQ19 10 6686#define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6687#define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6688#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6689 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6690 6691#define S_FW_RSS_IND_TBL_CMD_IQ20 0 6692#define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6693#define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6694#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6695 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6696 6697#define S_FW_RSS_IND_TBL_CMD_IQ21 20 6698#define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6699#define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6700#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6701 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6702 6703#define S_FW_RSS_IND_TBL_CMD_IQ22 10 6704#define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6705#define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6706#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6707 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6708 6709#define S_FW_RSS_IND_TBL_CMD_IQ23 0 6710#define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6711#define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6712#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6713 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6714 6715#define S_FW_RSS_IND_TBL_CMD_IQ24 20 6716#define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6717#define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6718#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6719 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6720 6721#define S_FW_RSS_IND_TBL_CMD_IQ25 10 6722#define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6723#define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6724#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6725 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6726 6727#define S_FW_RSS_IND_TBL_CMD_IQ26 0 6728#define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6729#define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6730#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6731 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6732 6733#define S_FW_RSS_IND_TBL_CMD_IQ27 20 6734#define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6735#define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6736#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6737 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6738 6739#define S_FW_RSS_IND_TBL_CMD_IQ28 10 6740#define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6741#define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6742#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6743 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6744 6745#define S_FW_RSS_IND_TBL_CMD_IQ29 0 6746#define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6747#define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6748#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6749 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6750 6751#define S_FW_RSS_IND_TBL_CMD_IQ30 20 6752#define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6753#define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6754#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6755 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6756 6757#define S_FW_RSS_IND_TBL_CMD_IQ31 10 6758#define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6759#define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6760#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6761 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6762 6763struct fw_rss_glb_config_cmd { 6764 __be32 op_to_write; 6765 __be32 retval_len16; 6766 union fw_rss_glb_config { 6767 struct fw_rss_glb_config_manual { 6768 __be32 mode_pkd; 6769 __be32 r3; 6770 __be64 r4; 6771 __be64 r5; 6772 } manual; 6773 struct fw_rss_glb_config_basicvirtual { 6774 __be32 mode_pkd; 6775 __be32 synmapen_to_hashtoeplitz; 6776 __be64 r8; 6777 __be64 r9; 6778 } basicvirtual; 6779 } u; 6780}; 6781 6782#define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6783#define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6784#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6785#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6786 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6787 6788#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6789#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6790#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6791 6792#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6793#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6794#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6795 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6796#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6797 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6798 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6799#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6800 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6801 6802#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6803#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6804#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6805 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6806#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6807 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6808 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6809#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6810 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6811 6812#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6813#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6814#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6815 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6816#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6817 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6818 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6819#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6820 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6821 6822#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6823#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6824#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6825 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6826#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6827 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6828 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6829#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6830 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6831 6832#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6833#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6834#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6835 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6836#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6837 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6838 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6839#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6840 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6841 6842#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6843#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6844#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6845 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6846#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6847 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6848 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6849#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6850 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6851 6852#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6853#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6854#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6855 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6856#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6857 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6858 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6859#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6860 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6861 6862#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6863#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6864#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6865 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6866#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6867 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6868 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6869#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6870 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6871 6872#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6873#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6874#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6875 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6876#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6877 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6878 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6879#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6880 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6881 6882struct fw_rss_vi_config_cmd { 6883 __be32 op_to_viid; 6884 __be32 retval_len16; 6885 union fw_rss_vi_config { 6886 struct fw_rss_vi_config_manual { 6887 __be64 r3; 6888 __be64 r4; 6889 __be64 r5; 6890 } manual; 6891 struct fw_rss_vi_config_basicvirtual { 6892 __be32 r6; 6893 __be32 defaultq_to_udpen; 6894 __be64 r9; 6895 __be64 r10; 6896 } basicvirtual; 6897 } u; 6898}; 6899 6900#define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6901#define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6902#define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6903#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6904 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6905 6906#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6907#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6908#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6909 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6910#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6911 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6912 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6913 6914#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6915#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6916#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6917 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6918#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6919 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6920 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6921#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6922 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6923 6924#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6925#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6926#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6927 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6928#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6929 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6930 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6931#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6932 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6933 6934#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6935#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6936#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6937 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6938#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6939 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6940 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6941#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6942 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6943 6944#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6945#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6946#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6947 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6948#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6949 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6950 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6951#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6952 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6953 6954#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6955#define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6956#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6957#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6958 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6959#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6960 6961enum fw_sched_sc { 6962 FW_SCHED_SC_CONFIG = 0, 6963 FW_SCHED_SC_PARAMS = 1, 6964}; 6965 6966enum fw_sched_type { 6967 FW_SCHED_TYPE_PKTSCHED = 0, 6968 FW_SCHED_TYPE_STREAMSCHED = 1, 6969}; 6970 6971enum fw_sched_params_level { 6972 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6973 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6974 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6975}; 6976 6977enum fw_sched_params_mode { 6978 FW_SCHED_PARAMS_MODE_CLASS = 0, 6979 FW_SCHED_PARAMS_MODE_FLOW = 1, 6980}; 6981 6982enum fw_sched_params_unit { 6983 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6984 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6985}; 6986 6987enum fw_sched_params_rate { 6988 FW_SCHED_PARAMS_RATE_REL = 0, 6989 FW_SCHED_PARAMS_RATE_ABS = 1, 6990}; 6991 6992struct fw_sched_cmd { 6993 __be32 op_to_write; 6994 __be32 retval_len16; 6995 union fw_sched { 6996 struct fw_sched_config { 6997 __u8 sc; 6998 __u8 type; 6999 __u8 minmaxen; 7000 __u8 r3[5]; 7001 __u8 nclasses[4]; 7002 __be32 r4; 7003 } config; 7004 struct fw_sched_params { 7005 __u8 sc; 7006 __u8 type; 7007 __u8 level; 7008 __u8 mode; 7009 __u8 unit; 7010 __u8 rate; 7011 __u8 ch; 7012 __u8 cl; 7013 __be32 min; 7014 __be32 max; 7015 __be16 weight; 7016 __be16 pktsize; 7017 __be16 burstsize; 7018 __be16 r4; 7019 } params; 7020 } u; 7021}; 7022 7023/* 7024 * length of the formatting string 7025 */ 7026#define FW_DEVLOG_FMT_LEN 192 7027 7028/* 7029 * maximum number of the formatting string parameters 7030 */ 7031#define FW_DEVLOG_FMT_PARAMS_NUM 8 7032 7033/* 7034 * priority levels 7035 */ 7036enum fw_devlog_level { 7037 FW_DEVLOG_LEVEL_EMERG = 0x0, 7038 FW_DEVLOG_LEVEL_CRIT = 0x1, 7039 FW_DEVLOG_LEVEL_ERR = 0x2, 7040 FW_DEVLOG_LEVEL_NOTICE = 0x3, 7041 FW_DEVLOG_LEVEL_INFO = 0x4, 7042 FW_DEVLOG_LEVEL_DEBUG = 0x5, 7043 FW_DEVLOG_LEVEL_MAX = 0x5, 7044}; 7045 7046/* 7047 * facilities that may send a log message 7048 */ 7049enum fw_devlog_facility { 7050 FW_DEVLOG_FACILITY_CORE = 0x00, 7051 FW_DEVLOG_FACILITY_CF = 0x01, 7052 FW_DEVLOG_FACILITY_SCHED = 0x02, 7053 FW_DEVLOG_FACILITY_TIMER = 0x04, 7054 FW_DEVLOG_FACILITY_RES = 0x06, 7055 FW_DEVLOG_FACILITY_HW = 0x08, 7056 FW_DEVLOG_FACILITY_FLR = 0x10, 7057 FW_DEVLOG_FACILITY_DMAQ = 0x12, 7058 FW_DEVLOG_FACILITY_PHY = 0x14, 7059 FW_DEVLOG_FACILITY_MAC = 0x16, 7060 FW_DEVLOG_FACILITY_PORT = 0x18, 7061 FW_DEVLOG_FACILITY_VI = 0x1A, 7062 FW_DEVLOG_FACILITY_FILTER = 0x1C, 7063 FW_DEVLOG_FACILITY_ACL = 0x1E, 7064 FW_DEVLOG_FACILITY_TM = 0x20, 7065 FW_DEVLOG_FACILITY_QFC = 0x22, 7066 FW_DEVLOG_FACILITY_DCB = 0x24, 7067 FW_DEVLOG_FACILITY_ETH = 0x26, 7068 FW_DEVLOG_FACILITY_OFLD = 0x28, 7069 FW_DEVLOG_FACILITY_RI = 0x2A, 7070 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 7071 FW_DEVLOG_FACILITY_FCOE = 0x2E, 7072 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 7073 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 7074 FW_DEVLOG_FACILITY_MAX = 0x32, 7075}; 7076 7077/* 7078 * log message format 7079 */ 7080struct fw_devlog_e { 7081 __be64 timestamp; 7082 __be32 seqno; 7083 __be16 reserved1; 7084 __u8 level; 7085 __u8 facility; 7086 __u8 fmt[FW_DEVLOG_FMT_LEN]; 7087 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 7088 __be32 reserved3[4]; 7089}; 7090 7091struct fw_devlog_cmd { 7092 __be32 op_to_write; 7093 __be32 retval_len16; 7094 __u8 level; 7095 __u8 r2[7]; 7096 __be32 memtype_devlog_memaddr16_devlog; 7097 __be32 memsize_devlog; 7098 __be32 r3[2]; 7099}; 7100 7101#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 7102#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 7103#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7104 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7105#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7106 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7107 7108#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 7109#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 7110#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7111 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7112#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7113 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 7114 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7115 7116enum fw_watchdog_actions { 7117 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 7118 FW_WATCHDOG_ACTION_FLR = 1, 7119 FW_WATCHDOG_ACTION_BYPASS = 2, 7120 FW_WATCHDOG_ACTION_TMPCHK = 3, 7121 7122 FW_WATCHDOG_ACTION_MAX = 4, 7123}; 7124 7125#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 7126 7127struct fw_watchdog_cmd { 7128 __be32 op_to_vfn; 7129 __be32 retval_len16; 7130 __be32 timeout; 7131 __be32 action; 7132}; 7133 7134#define S_FW_WATCHDOG_CMD_PFN 8 7135#define M_FW_WATCHDOG_CMD_PFN 0x7 7136#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 7137#define G_FW_WATCHDOG_CMD_PFN(x) \ 7138 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 7139 7140#define S_FW_WATCHDOG_CMD_VFN 0 7141#define M_FW_WATCHDOG_CMD_VFN 0xff 7142#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 7143#define G_FW_WATCHDOG_CMD_VFN(x) \ 7144 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 7145 7146struct fw_clip_cmd { 7147 __be32 op_to_write; 7148 __be32 alloc_to_len16; 7149 __be64 ip_hi; 7150 __be64 ip_lo; 7151 __be32 r4[2]; 7152}; 7153 7154#define S_FW_CLIP_CMD_ALLOC 31 7155#define M_FW_CLIP_CMD_ALLOC 0x1 7156#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 7157#define G_FW_CLIP_CMD_ALLOC(x) \ 7158 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 7159#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 7160 7161#define S_FW_CLIP_CMD_FREE 30 7162#define M_FW_CLIP_CMD_FREE 0x1 7163#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 7164#define G_FW_CLIP_CMD_FREE(x) \ 7165 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 7166#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 7167 7168/****************************************************************************** 7169 * F O i S C S I C O M M A N D s 7170 **************************************/ 7171 7172#define FW_CHNET_IFACE_ADDR_MAX 3 7173 7174enum fw_chnet_iface_cmd_subop { 7175 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 7176 7177 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 7178 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 7179 7180 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 7181 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 7182 7183 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7184}; 7185 7186struct fw_chnet_iface_cmd { 7187 __be32 op_to_portid; 7188 __be32 retval_len16; 7189 __u8 subop; 7190 __u8 r2[3]; 7191 __be32 ifid_ifstate; 7192 __be16 mtu; 7193 __be16 vlanid; 7194 __be32 r3; 7195 __be16 r4; 7196 __u8 mac[6]; 7197}; 7198 7199#define S_FW_CHNET_IFACE_CMD_PORTID 0 7200#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7201#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7202#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7203 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7204 7205#define S_FW_CHNET_IFACE_CMD_IFID 8 7206#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7207#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7208#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7209 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7210 7211#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7212#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7213#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7214#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7215 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7216 7217/****************************************************************************** 7218 * F O F C O E C O M M A N D s 7219 ************************************/ 7220 7221struct fw_fcoe_res_info_cmd { 7222 __be32 op_to_read; 7223 __be32 retval_len16; 7224 __be16 e_d_tov; 7225 __be16 r_a_tov_seq; 7226 __be16 r_a_tov_els; 7227 __be16 r_r_tov; 7228 __be32 max_xchgs; 7229 __be32 max_ssns; 7230 __be32 used_xchgs; 7231 __be32 used_ssns; 7232 __be32 max_fcfs; 7233 __be32 max_vnps; 7234 __be32 used_fcfs; 7235 __be32 used_vnps; 7236}; 7237 7238struct fw_fcoe_link_cmd { 7239 __be32 op_to_portid; 7240 __be32 retval_len16; 7241 __be32 sub_opcode_fcfi; 7242 __u8 r3; 7243 __u8 lstatus; 7244 __be16 flags; 7245 __u8 r4; 7246 __u8 set_vlan; 7247 __be16 vlan_id; 7248 __be32 vnpi_pkd; 7249 __be16 r6; 7250 __u8 phy_mac[6]; 7251 __u8 vnport_wwnn[8]; 7252 __u8 vnport_wwpn[8]; 7253}; 7254 7255#define S_FW_FCOE_LINK_CMD_PORTID 0 7256#define M_FW_FCOE_LINK_CMD_PORTID 0xf 7257#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7258#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7259 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7260 7261#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7262#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7263#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7264 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7265#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7266 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7267 7268#define S_FW_FCOE_LINK_CMD_FCFI 0 7269#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7270#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7271#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7272 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7273 7274#define S_FW_FCOE_LINK_CMD_VNPI 0 7275#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7276#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7277#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7278 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7279 7280struct fw_fcoe_vnp_cmd { 7281 __be32 op_to_fcfi; 7282 __be32 alloc_to_len16; 7283 __be32 gen_wwn_to_vnpi; 7284 __be32 vf_id; 7285 __be16 iqid; 7286 __u8 vnport_mac[6]; 7287 __u8 vnport_wwnn[8]; 7288 __u8 vnport_wwpn[8]; 7289 __u8 cmn_srv_parms[16]; 7290 __u8 clsp_word_0_1[8]; 7291}; 7292 7293#define S_FW_FCOE_VNP_CMD_FCFI 0 7294#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7295#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7296#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7297 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7298 7299#define S_FW_FCOE_VNP_CMD_ALLOC 31 7300#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7301#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7302#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7303 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7304#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7305 7306#define S_FW_FCOE_VNP_CMD_FREE 30 7307#define M_FW_FCOE_VNP_CMD_FREE 0x1 7308#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7309#define G_FW_FCOE_VNP_CMD_FREE(x) \ 7310 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7311#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7312 7313#define S_FW_FCOE_VNP_CMD_MODIFY 29 7314#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7315#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7316#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7317 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7318#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7319 7320#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7321#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7322#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7323#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7324 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7325#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7326 7327#define S_FW_FCOE_VNP_CMD_PERSIST 21 7328#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7329#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7330#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7331 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7332#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7333 7334#define S_FW_FCOE_VNP_CMD_VFID_EN 20 7335#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7336#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7337#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7338 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7339#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7340 7341#define S_FW_FCOE_VNP_CMD_VNPI 0 7342#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7343#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7344#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7345 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7346 7347struct fw_fcoe_sparams_cmd { 7348 __be32 op_to_portid; 7349 __be32 retval_len16; 7350 __u8 r3[7]; 7351 __u8 cos; 7352 __u8 lport_wwnn[8]; 7353 __u8 lport_wwpn[8]; 7354 __u8 cmn_srv_parms[16]; 7355 __u8 cls_srv_parms[16]; 7356}; 7357 7358#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7359#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7360#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7361#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7362 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7363 7364struct fw_fcoe_stats_cmd { 7365 __be32 op_to_flowid; 7366 __be32 free_to_len16; 7367 union fw_fcoe_stats { 7368 struct fw_fcoe_stats_ctl { 7369 __u8 nstats_port; 7370 __u8 port_valid_ix; 7371 __be16 r6; 7372 __be32 r7; 7373 __be64 stat0; 7374 __be64 stat1; 7375 __be64 stat2; 7376 __be64 stat3; 7377 __be64 stat4; 7378 __be64 stat5; 7379 } ctl; 7380 struct fw_fcoe_port_stats { 7381 __be64 tx_bcast_bytes; 7382 __be64 tx_bcast_frames; 7383 __be64 tx_mcast_bytes; 7384 __be64 tx_mcast_frames; 7385 __be64 tx_ucast_bytes; 7386 __be64 tx_ucast_frames; 7387 __be64 tx_drop_frames; 7388 __be64 tx_offload_bytes; 7389 __be64 tx_offload_frames; 7390 __be64 rx_bcast_bytes; 7391 __be64 rx_bcast_frames; 7392 __be64 rx_mcast_bytes; 7393 __be64 rx_mcast_frames; 7394 __be64 rx_ucast_bytes; 7395 __be64 rx_ucast_frames; 7396 __be64 rx_err_frames; 7397 } port_stats; 7398 struct fw_fcoe_fcf_stats { 7399 __be32 fip_tx_bytes; 7400 __be32 fip_tx_fr; 7401 __be64 fcf_ka; 7402 __be64 mcast_adv_rcvd; 7403 __be16 ucast_adv_rcvd; 7404 __be16 sol_sent; 7405 __be16 vlan_req; 7406 __be16 vlan_rpl; 7407 __be16 clr_vlink; 7408 __be16 link_down; 7409 __be16 link_up; 7410 __be16 logo; 7411 __be16 flogi_req; 7412 __be16 flogi_rpl; 7413 __be16 fdisc_req; 7414 __be16 fdisc_rpl; 7415 __be16 fka_prd_chg; 7416 __be16 fc_map_chg; 7417 __be16 vfid_chg; 7418 __u8 no_fka_req; 7419 __u8 no_vnp; 7420 } fcf_stats; 7421 struct fw_fcoe_pcb_stats { 7422 __be64 tx_bytes; 7423 __be64 tx_frames; 7424 __be64 rx_bytes; 7425 __be64 rx_frames; 7426 __be32 vnp_ka; 7427 __be32 unsol_els_rcvd; 7428 __be64 unsol_cmd_rcvd; 7429 __be16 implicit_logo; 7430 __be16 flogi_inv_sparm; 7431 __be16 fdisc_inv_sparm; 7432 __be16 flogi_rjt; 7433 __be16 fdisc_rjt; 7434 __be16 no_ssn; 7435 __be16 mac_flt_fail; 7436 __be16 inv_fr_rcvd; 7437 } pcb_stats; 7438 struct fw_fcoe_scb_stats { 7439 __be64 tx_bytes; 7440 __be64 tx_frames; 7441 __be64 rx_bytes; 7442 __be64 rx_frames; 7443 __be32 host_abrt_req; 7444 __be32 adap_auto_abrt; 7445 __be32 adap_abrt_rsp; 7446 __be32 host_ios_req; 7447 __be16 ssn_offl_ios; 7448 __be16 ssn_not_rdy_ios; 7449 __u8 rx_data_ddp_err; 7450 __u8 ddp_flt_set_err; 7451 __be16 rx_data_fr_err; 7452 __u8 bad_st_abrt_req; 7453 __u8 no_io_abrt_req; 7454 __u8 abort_tmo; 7455 __u8 abort_tmo_2; 7456 __be32 abort_req; 7457 __u8 no_ppod_res_tmo; 7458 __u8 bp_tmo; 7459 __u8 adap_auto_cls; 7460 __u8 no_io_cls_req; 7461 __be32 host_cls_req; 7462 __be64 unsol_cmd_rcvd; 7463 __be32 plogi_req_rcvd; 7464 __be32 prli_req_rcvd; 7465 __be16 logo_req_rcvd; 7466 __be16 prlo_req_rcvd; 7467 __be16 plogi_rjt_rcvd; 7468 __be16 prli_rjt_rcvd; 7469 __be32 adisc_req_rcvd; 7470 __be32 rscn_rcvd; 7471 __be32 rrq_req_rcvd; 7472 __be32 unsol_els_rcvd; 7473 __u8 adisc_rjt_rcvd; 7474 __u8 scr_rjt; 7475 __u8 ct_rjt; 7476 __u8 inval_bls_rcvd; 7477 __be32 ba_rjt_rcvd; 7478 } scb_stats; 7479 } u; 7480}; 7481 7482#define S_FW_FCOE_STATS_CMD_FLOWID 0 7483#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7484#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7485#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7486 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7487 7488#define S_FW_FCOE_STATS_CMD_FREE 30 7489#define M_FW_FCOE_STATS_CMD_FREE 0x1 7490#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7491#define G_FW_FCOE_STATS_CMD_FREE(x) \ 7492 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7493#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7494 7495#define S_FW_FCOE_STATS_CMD_NSTATS 4 7496#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7497#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7498#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7499 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7500 7501#define S_FW_FCOE_STATS_CMD_PORT 0 7502#define M_FW_FCOE_STATS_CMD_PORT 0x3 7503#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7504#define G_FW_FCOE_STATS_CMD_PORT(x) \ 7505 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7506 7507#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7508#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7509#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7510 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7511#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7512 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7513#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7514 7515#define S_FW_FCOE_STATS_CMD_IX 0 7516#define M_FW_FCOE_STATS_CMD_IX 0x3f 7517#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7518#define G_FW_FCOE_STATS_CMD_IX(x) \ 7519 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7520 7521struct fw_fcoe_fcf_cmd { 7522 __be32 op_to_fcfi; 7523 __be32 retval_len16; 7524 __be16 priority_pkd; 7525 __u8 mac[6]; 7526 __u8 name_id[8]; 7527 __u8 fabric[8]; 7528 __be16 vf_id; 7529 __be16 max_fcoe_size; 7530 __u8 vlan_id; 7531 __u8 fc_map[3]; 7532 __be32 fka_adv; 7533 __be32 r6; 7534 __u8 r7_hi; 7535 __u8 fpma_to_portid; 7536 __u8 spma_mac[6]; 7537 __be64 r8; 7538}; 7539 7540#define S_FW_FCOE_FCF_CMD_FCFI 0 7541#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7542#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7543#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7544 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7545 7546#define S_FW_FCOE_FCF_CMD_PRIORITY 0 7547#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7548#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7549#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7550 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7551 7552#define S_FW_FCOE_FCF_CMD_FPMA 6 7553#define M_FW_FCOE_FCF_CMD_FPMA 0x1 7554#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7555#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7556 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7557#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7558 7559#define S_FW_FCOE_FCF_CMD_SPMA 5 7560#define M_FW_FCOE_FCF_CMD_SPMA 0x1 7561#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7562#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7563 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7564#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7565 7566#define S_FW_FCOE_FCF_CMD_LOGIN 4 7567#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7568#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7569#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7570 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7571#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7572 7573#define S_FW_FCOE_FCF_CMD_PORTID 0 7574#define M_FW_FCOE_FCF_CMD_PORTID 0xf 7575#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7576#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7577 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7578 7579/****************************************************************************** 7580 * E R R O R a n d D E B U G C O M M A N D s 7581 ******************************************************/ 7582 7583enum fw_error_type { 7584 FW_ERROR_TYPE_EXCEPTION = 0x0, 7585 FW_ERROR_TYPE_HWMODULE = 0x1, 7586 FW_ERROR_TYPE_WR = 0x2, 7587 FW_ERROR_TYPE_ACL = 0x3, 7588}; 7589 7590struct fw_error_cmd { 7591 __be32 op_to_type; 7592 __be32 len16_pkd; 7593 union fw_error { 7594 struct fw_error_exception { 7595 __be32 info[6]; 7596 } exception; 7597 struct fw_error_hwmodule { 7598 __be32 regaddr; 7599 __be32 regval; 7600 } hwmodule; 7601 struct fw_error_wr { 7602 __be16 cidx; 7603 __be16 pfn_vfn; 7604 __be32 eqid; 7605 __u8 wrhdr[16]; 7606 } wr; 7607 struct fw_error_acl { 7608 __be16 cidx; 7609 __be16 pfn_vfn; 7610 __be32 eqid; 7611 __be16 mv_pkd; 7612 __u8 val[6]; 7613 __be64 r4; 7614 } acl; 7615 } u; 7616}; 7617 7618#define S_FW_ERROR_CMD_FATAL 4 7619#define M_FW_ERROR_CMD_FATAL 0x1 7620#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7621#define G_FW_ERROR_CMD_FATAL(x) \ 7622 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7623#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7624 7625#define S_FW_ERROR_CMD_TYPE 0 7626#define M_FW_ERROR_CMD_TYPE 0xf 7627#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7628#define G_FW_ERROR_CMD_TYPE(x) \ 7629 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7630 7631#define S_FW_ERROR_CMD_PFN 8 7632#define M_FW_ERROR_CMD_PFN 0x7 7633#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7634#define G_FW_ERROR_CMD_PFN(x) \ 7635 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7636 7637#define S_FW_ERROR_CMD_VFN 0 7638#define M_FW_ERROR_CMD_VFN 0xff 7639#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7640#define G_FW_ERROR_CMD_VFN(x) \ 7641 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7642 7643#define S_FW_ERROR_CMD_PFN 8 7644#define M_FW_ERROR_CMD_PFN 0x7 7645#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7646#define G_FW_ERROR_CMD_PFN(x) \ 7647 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7648 7649#define S_FW_ERROR_CMD_VFN 0 7650#define M_FW_ERROR_CMD_VFN 0xff 7651#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7652#define G_FW_ERROR_CMD_VFN(x) \ 7653 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7654 7655#define S_FW_ERROR_CMD_MV 15 7656#define M_FW_ERROR_CMD_MV 0x1 7657#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7658#define G_FW_ERROR_CMD_MV(x) \ 7659 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7660#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7661 7662struct fw_debug_cmd { 7663 __be32 op_type; 7664 __be32 len16_pkd; 7665 union fw_debug { 7666 struct fw_debug_assert { 7667 __be32 fcid; 7668 __be32 line; 7669 __be32 x; 7670 __be32 y; 7671 __u8 filename_0_7[8]; 7672 __u8 filename_8_15[8]; 7673 __be64 r3; 7674 } assert; 7675 struct fw_debug_prt { 7676 __be16 dprtstridx; 7677 __be16 r3[3]; 7678 __be32 dprtstrparam0; 7679 __be32 dprtstrparam1; 7680 __be32 dprtstrparam2; 7681 __be32 dprtstrparam3; 7682 } prt; 7683 } u; 7684}; 7685 7686#define S_FW_DEBUG_CMD_TYPE 0 7687#define M_FW_DEBUG_CMD_TYPE 0xff 7688#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7689#define G_FW_DEBUG_CMD_TYPE(x) \ 7690 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7691 7692/****************************************************************************** 7693 * P C I E F W R E G I S T E R 7694 **************************************/ 7695 7696enum pcie_fw_eval { 7697 PCIE_FW_EVAL_CRASH = 0, 7698 PCIE_FW_EVAL_PREP = 1, 7699 PCIE_FW_EVAL_CONF = 2, 7700 PCIE_FW_EVAL_INIT = 3, 7701 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7702 PCIE_FW_EVAL_OVERHEAT = 5, 7703 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7704}; 7705 7706/** 7707 * Register definitions for the PCIE_FW register which the firmware uses 7708 * to retain status across RESETs. This register should be considered 7709 * as a READ-ONLY register for Host Software and only to be used to 7710 * track firmware initialization/error state, etc. 7711 */ 7712#define S_PCIE_FW_ERR 31 7713#define M_PCIE_FW_ERR 0x1 7714#define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7715#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7716#define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7717 7718#define S_PCIE_FW_INIT 30 7719#define M_PCIE_FW_INIT 0x1 7720#define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7721#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7722#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7723 7724#define S_PCIE_FW_HALT 29 7725#define M_PCIE_FW_HALT 0x1 7726#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7727#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7728#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7729 7730#define S_PCIE_FW_EVAL 24 7731#define M_PCIE_FW_EVAL 0x7 7732#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7733#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7734 7735#define S_PCIE_FW_STAGE 21 7736#define M_PCIE_FW_STAGE 0x7 7737#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7738#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7739 7740#define S_PCIE_FW_ASYNCNOT_VLD 20 7741#define M_PCIE_FW_ASYNCNOT_VLD 0x1 7742#define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7743 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7744#define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7745 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7746#define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7747 7748#define S_PCIE_FW_ASYNCNOTINT 19 7749#define M_PCIE_FW_ASYNCNOTINT 0x1 7750#define V_PCIE_FW_ASYNCNOTINT(x) \ 7751 ((x) << S_PCIE_FW_ASYNCNOTINT) 7752#define G_PCIE_FW_ASYNCNOTINT(x) \ 7753 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7754#define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7755 7756#define S_PCIE_FW_ASYNCNOT 16 7757#define M_PCIE_FW_ASYNCNOT 0x7 7758#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7759#define G_PCIE_FW_ASYNCNOT(x) \ 7760 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7761 7762#define S_PCIE_FW_MASTER_VLD 15 7763#define M_PCIE_FW_MASTER_VLD 0x1 7764#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7765#define G_PCIE_FW_MASTER_VLD(x) \ 7766 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7767#define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7768 7769#define S_PCIE_FW_MASTER 12 7770#define M_PCIE_FW_MASTER 0x7 7771#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7772#define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7773 7774#define S_PCIE_FW_RESET_VLD 11 7775#define M_PCIE_FW_RESET_VLD 0x1 7776#define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7777#define G_PCIE_FW_RESET_VLD(x) \ 7778 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7779#define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7780 7781#define S_PCIE_FW_RESET 8 7782#define M_PCIE_FW_RESET 0x7 7783#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7784#define G_PCIE_FW_RESET(x) \ 7785 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7786 7787#define S_PCIE_FW_REGISTERED 0 7788#define M_PCIE_FW_REGISTERED 0xff 7789#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7790#define G_PCIE_FW_REGISTERED(x) \ 7791 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7792 7793 7794/****************************************************************************** 7795 * P C I E F W P F 0 R E G I S T E R 7796 **********************************************/ 7797 7798/* 7799 * this register is available as 32-bit of persistent storage (accross 7800 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 7801 * will not write it) 7802 */ 7803 7804 7805/****************************************************************************** 7806 * B I N A R Y H E A D E R F O R M A T 7807 **********************************************/ 7808 7809/* 7810 * firmware binary header format 7811 */ 7812struct fw_hdr { 7813 __u8 ver; 7814 __u8 chip; /* terminator chip family */ 7815 __be16 len512; /* bin length in units of 512-bytes */ 7816 __be32 fw_ver; /* firmware version */ 7817 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7818 __u8 intfver_nic; 7819 __u8 intfver_vnic; 7820 __u8 intfver_ofld; 7821 __u8 intfver_ri; 7822 __u8 intfver_iscsipdu; 7823 __u8 intfver_iscsi; 7824 __u8 intfver_fcoepdu; 7825 __u8 intfver_fcoe; 7826 __u32 reserved2; 7827 __u32 reserved3; 7828 __u32 magic; /* runtime or bootstrap fw */ 7829 __be32 flags; 7830 __be32 reserved6[23]; 7831}; 7832 7833enum fw_hdr_chip { 7834 FW_HDR_CHIP_T4, 7835 FW_HDR_CHIP_T5 7836}; 7837 7838#define S_FW_HDR_FW_VER_MAJOR 24 7839#define M_FW_HDR_FW_VER_MAJOR 0xff 7840#define V_FW_HDR_FW_VER_MAJOR(x) \ 7841 ((x) << S_FW_HDR_FW_VER_MAJOR) 7842#define G_FW_HDR_FW_VER_MAJOR(x) \ 7843 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7844 7845#define S_FW_HDR_FW_VER_MINOR 16 7846#define M_FW_HDR_FW_VER_MINOR 0xff 7847#define V_FW_HDR_FW_VER_MINOR(x) \ 7848 ((x) << S_FW_HDR_FW_VER_MINOR) 7849#define G_FW_HDR_FW_VER_MINOR(x) \ 7850 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7851 7852#define S_FW_HDR_FW_VER_MICRO 8 7853#define M_FW_HDR_FW_VER_MICRO 0xff 7854#define V_FW_HDR_FW_VER_MICRO(x) \ 7855 ((x) << S_FW_HDR_FW_VER_MICRO) 7856#define G_FW_HDR_FW_VER_MICRO(x) \ 7857 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7858 7859#define S_FW_HDR_FW_VER_BUILD 0 7860#define M_FW_HDR_FW_VER_BUILD 0xff 7861#define V_FW_HDR_FW_VER_BUILD(x) \ 7862 ((x) << S_FW_HDR_FW_VER_BUILD) 7863#define G_FW_HDR_FW_VER_BUILD(x) \ 7864 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7865 7866enum { 7867 T4FW_VERSION_MAJOR = 0x01, 7868 T4FW_VERSION_MINOR = 0x0b, 7869 T4FW_VERSION_MICRO = 0x1b, 7870 T4FW_VERSION_BUILD = 0x00, 7871 7872 T5FW_VERSION_MAJOR = 0x01, 7873 T5FW_VERSION_MINOR = 0x0b, 7874 T5FW_VERSION_MICRO = 0x1b, 7875 T5FW_VERSION_BUILD = 0x00, 7876}; 7877 7878enum { 7879 T4FW_HDR_INTFVER_NIC = 0x00, 7880 T4FW_HDR_INTFVER_VNIC = 0x00, 7881 T4FW_HDR_INTFVER_OFLD = 0x00, 7882 T4FW_HDR_INTFVER_RI = 0x00, 7883 T4FW_HDR_INTFVER_ISCSIPDU = 0x00, 7884 T4FW_HDR_INTFVER_ISCSI = 0x00, 7885 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 7886 T4FW_HDR_INTFVER_FCOE = 0x00, 7887 7888 T5FW_HDR_INTFVER_NIC = 0x00, 7889 T5FW_HDR_INTFVER_VNIC = 0x00, 7890 T5FW_HDR_INTFVER_OFLD = 0x00, 7891 T5FW_HDR_INTFVER_RI = 0x00, 7892 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 7893 T5FW_HDR_INTFVER_ISCSI = 0x00, 7894 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 7895 T5FW_HDR_INTFVER_FCOE = 0x00, 7896}; 7897 7898enum { 7899 FW_HDR_MAGIC_RUNTIME = 0x00000000, 7900 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 7901}; 7902 7903enum fw_hdr_flags { 7904 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7905}; 7906 7907#endif /* _T4FW_INTERFACE_H_ */ 7908