1167514Skmacy/************************************************************************** 2167514Skmacy 3167514SkmacyCopyright (c) 2007, Chelsio Inc. 4167514SkmacyAll rights reserved. 5167514Skmacy 6167514SkmacyRedistribution and use in source and binary forms, with or without 7167514Skmacymodification, are permitted provided that the following conditions are met: 8167514Skmacy 9167514Skmacy 1. Redistributions of source code must retain the above copyright notice, 10167514Skmacy this list of conditions and the following disclaimer. 11167514Skmacy 12170076Skmacy 2. Neither the name of the Chelsio Corporation nor the names of its 13167514Skmacy contributors may be used to endorse or promote products derived from 14167514Skmacy this software without specific prior written permission. 15167514Skmacy 16167514SkmacyTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17167514SkmacyAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167514SkmacyIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167514SkmacyARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20167514SkmacyLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21167514SkmacyCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22167514SkmacySUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23167514SkmacyINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24167514SkmacyCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25167514SkmacyARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26167514SkmacyPOSSIBILITY OF SUCH DAMAGE. 27167514Skmacy 28167514Skmacy$FreeBSD$ 29167514Skmacy 30167514Skmacy***************************************************************************/ 31167514Skmacy/* This file is automatically generated --- do not edit */ 32167514Skmacy 33167514Skmacy/* registers for module SGE3 */ 34167514Skmacy#define SGE3_BASE_ADDR 0x0 35167514Skmacy 36167514Skmacy#define A_SG_CONTROL 0x0 37167514Skmacy 38176472Skmacy#define S_CONGMODE 29 39176472Skmacy#define V_CONGMODE(x) ((x) << S_CONGMODE) 40176472Skmacy#define F_CONGMODE V_CONGMODE(1U) 41176472Skmacy 42176472Skmacy#define S_TNLFLMODE 28 43176472Skmacy#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) 44176472Skmacy#define F_TNLFLMODE V_TNLFLMODE(1U) 45176472Skmacy 46176472Skmacy#define S_FATLPERREN 27 47176472Skmacy#define V_FATLPERREN(x) ((x) << S_FATLPERREN) 48176472Skmacy#define F_FATLPERREN V_FATLPERREN(1U) 49176472Skmacy 50176472Skmacy#define S_URGTNL 26 51176472Skmacy#define V_URGTNL(x) ((x) << S_URGTNL) 52176472Skmacy#define F_URGTNL V_URGTNL(1U) 53176472Skmacy 54176472Skmacy#define S_NEWNOTIFY 25 55176472Skmacy#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) 56176472Skmacy#define F_NEWNOTIFY V_NEWNOTIFY(1U) 57176472Skmacy 58176472Skmacy#define S_AVOIDCQOVFL 24 59176472Skmacy#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) 60176472Skmacy#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) 61176472Skmacy 62176472Skmacy#define S_OPTONEINTMULTQ 23 63176472Skmacy#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) 64176472Skmacy#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) 65176472Skmacy 66176472Skmacy#define S_CQCRDTCTRL 22 67176472Skmacy#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) 68176472Skmacy#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) 69176472Skmacy 70167514Skmacy#define S_EGRENUPBP 21 71167514Skmacy#define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) 72167514Skmacy#define F_EGRENUPBP V_EGRENUPBP(1U) 73167514Skmacy 74167514Skmacy#define S_DROPPKT 20 75167514Skmacy#define V_DROPPKT(x) ((x) << S_DROPPKT) 76167514Skmacy#define F_DROPPKT V_DROPPKT(1U) 77167514Skmacy 78167514Skmacy#define S_EGRGENCTRL 19 79167514Skmacy#define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) 80167514Skmacy#define F_EGRGENCTRL V_EGRGENCTRL(1U) 81167514Skmacy 82167514Skmacy#define S_USERSPACESIZE 14 83167514Skmacy#define M_USERSPACESIZE 0x1f 84167514Skmacy#define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) 85167514Skmacy#define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE) 86167514Skmacy 87167514Skmacy#define S_HOSTPAGESIZE 11 88167514Skmacy#define M_HOSTPAGESIZE 0x7 89167514Skmacy#define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) 90167514Skmacy#define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE) 91167514Skmacy 92167514Skmacy#define S_PCIRELAX 10 93167514Skmacy#define V_PCIRELAX(x) ((x) << S_PCIRELAX) 94167514Skmacy#define F_PCIRELAX V_PCIRELAX(1U) 95167514Skmacy 96167514Skmacy#define S_FLMODE 9 97167514Skmacy#define V_FLMODE(x) ((x) << S_FLMODE) 98167514Skmacy#define F_FLMODE V_FLMODE(1U) 99167514Skmacy 100167514Skmacy#define S_PKTSHIFT 6 101167514Skmacy#define M_PKTSHIFT 0x7 102167514Skmacy#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) 103167514Skmacy#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT) 104167514Skmacy 105167514Skmacy#define S_ONEINTMULTQ 5 106167514Skmacy#define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) 107167514Skmacy#define F_ONEINTMULTQ V_ONEINTMULTQ(1U) 108167514Skmacy 109167514Skmacy#define S_FLPICKAVAIL 4 110167514Skmacy#define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL) 111167514Skmacy#define F_FLPICKAVAIL V_FLPICKAVAIL(1U) 112167514Skmacy 113167514Skmacy#define S_BIGENDIANEGRESS 3 114167514Skmacy#define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS) 115167514Skmacy#define F_BIGENDIANEGRESS V_BIGENDIANEGRESS(1U) 116167514Skmacy 117167514Skmacy#define S_BIGENDIANINGRESS 2 118167514Skmacy#define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS) 119167514Skmacy#define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U) 120167514Skmacy 121167514Skmacy#define S_ISCSICOALESCING 1 122167514Skmacy#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) 123167514Skmacy#define F_ISCSICOALESCING V_ISCSICOALESCING(1U) 124167514Skmacy 125167514Skmacy#define S_GLOBALENABLE 0 126167514Skmacy#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 127167514Skmacy#define F_GLOBALENABLE V_GLOBALENABLE(1U) 128167514Skmacy 129167514Skmacy#define A_SG_KDOORBELL 0x4 130167514Skmacy 131167514Skmacy#define S_SELEGRCNTX 31 132167514Skmacy#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) 133167514Skmacy#define F_SELEGRCNTX V_SELEGRCNTX(1U) 134167514Skmacy 135167514Skmacy#define S_EGRCNTX 0 136167514Skmacy#define M_EGRCNTX 0xffff 137167514Skmacy#define V_EGRCNTX(x) ((x) << S_EGRCNTX) 138167514Skmacy#define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX) 139167514Skmacy 140167514Skmacy#define A_SG_GTS 0x8 141167514Skmacy 142167514Skmacy#define S_RSPQ 29 143167514Skmacy#define M_RSPQ 0x7 144167514Skmacy#define V_RSPQ(x) ((x) << S_RSPQ) 145167514Skmacy#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ) 146167514Skmacy 147167514Skmacy#define S_NEWTIMER 16 148167514Skmacy#define M_NEWTIMER 0x1fff 149167514Skmacy#define V_NEWTIMER(x) ((x) << S_NEWTIMER) 150167514Skmacy#define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER) 151167514Skmacy 152167514Skmacy#define S_NEWINDEX 0 153167514Skmacy#define M_NEWINDEX 0xffff 154167514Skmacy#define V_NEWINDEX(x) ((x) << S_NEWINDEX) 155167514Skmacy#define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX) 156167514Skmacy 157167514Skmacy#define A_SG_CONTEXT_CMD 0xc 158167514Skmacy 159167514Skmacy#define S_CONTEXT_CMD_OPCODE 28 160167514Skmacy#define M_CONTEXT_CMD_OPCODE 0xf 161167514Skmacy#define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE) 162167514Skmacy#define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE) 163167514Skmacy 164167514Skmacy#define S_CONTEXT_CMD_BUSY 27 165167514Skmacy#define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY) 166167514Skmacy#define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U) 167167514Skmacy 168167514Skmacy#define S_CQ_CREDIT 20 169167514Skmacy#define M_CQ_CREDIT 0x7f 170167514Skmacy#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) 171167514Skmacy#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) 172167514Skmacy 173167514Skmacy#define S_CQ 19 174167514Skmacy#define V_CQ(x) ((x) << S_CQ) 175167514Skmacy#define F_CQ V_CQ(1U) 176167514Skmacy 177167514Skmacy#define S_RESPONSEQ 18 178167514Skmacy#define V_RESPONSEQ(x) ((x) << S_RESPONSEQ) 179167514Skmacy#define F_RESPONSEQ V_RESPONSEQ(1U) 180167514Skmacy 181167514Skmacy#define S_EGRESS 17 182167514Skmacy#define V_EGRESS(x) ((x) << S_EGRESS) 183167514Skmacy#define F_EGRESS V_EGRESS(1U) 184167514Skmacy 185167514Skmacy#define S_FREELIST 16 186167514Skmacy#define V_FREELIST(x) ((x) << S_FREELIST) 187167514Skmacy#define F_FREELIST V_FREELIST(1U) 188167514Skmacy 189167514Skmacy#define S_CONTEXT 0 190167514Skmacy#define M_CONTEXT 0xffff 191167514Skmacy#define V_CONTEXT(x) ((x) << S_CONTEXT) 192167514Skmacy#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) 193167514Skmacy 194167514Skmacy#define A_SG_CONTEXT_DATA0 0x10 195167514Skmacy#define A_SG_CONTEXT_DATA1 0x14 196167514Skmacy#define A_SG_CONTEXT_DATA2 0x18 197167514Skmacy#define A_SG_CONTEXT_DATA3 0x1c 198167514Skmacy#define A_SG_CONTEXT_MASK0 0x20 199167514Skmacy#define A_SG_CONTEXT_MASK1 0x24 200167514Skmacy#define A_SG_CONTEXT_MASK2 0x28 201167514Skmacy#define A_SG_CONTEXT_MASK3 0x2c 202167514Skmacy#define A_SG_RSPQ_CREDIT_RETURN 0x30 203167514Skmacy 204167514Skmacy#define S_CREDITS 0 205167514Skmacy#define M_CREDITS 0xffff 206167514Skmacy#define V_CREDITS(x) ((x) << S_CREDITS) 207167514Skmacy#define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS) 208167514Skmacy 209167514Skmacy#define A_SG_DATA_INTR 0x34 210167514Skmacy 211167514Skmacy#define S_ERRINTR 31 212167514Skmacy#define V_ERRINTR(x) ((x) << S_ERRINTR) 213167514Skmacy#define F_ERRINTR V_ERRINTR(1U) 214167514Skmacy 215167514Skmacy#define S_DATAINTR 0 216167514Skmacy#define M_DATAINTR 0xff 217167514Skmacy#define V_DATAINTR(x) ((x) << S_DATAINTR) 218167514Skmacy#define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR) 219167514Skmacy 220167514Skmacy#define A_SG_HI_DRB_HI_THRSH 0x38 221167514Skmacy 222167514Skmacy#define S_HIDRBHITHRSH 0 223167514Skmacy#define M_HIDRBHITHRSH 0x3ff 224167514Skmacy#define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH) 225167514Skmacy#define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH) 226167514Skmacy 227167514Skmacy#define A_SG_HI_DRB_LO_THRSH 0x3c 228167514Skmacy 229167514Skmacy#define S_HIDRBLOTHRSH 0 230167514Skmacy#define M_HIDRBLOTHRSH 0x3ff 231167514Skmacy#define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH) 232167514Skmacy#define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH) 233167514Skmacy 234167514Skmacy#define A_SG_LO_DRB_HI_THRSH 0x40 235167514Skmacy 236167514Skmacy#define S_LODRBHITHRSH 0 237167514Skmacy#define M_LODRBHITHRSH 0x3ff 238167514Skmacy#define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH) 239167514Skmacy#define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH) 240167514Skmacy 241167514Skmacy#define A_SG_LO_DRB_LO_THRSH 0x44 242167514Skmacy 243167514Skmacy#define S_LODRBLOTHRSH 0 244167514Skmacy#define M_LODRBLOTHRSH 0x3ff 245167514Skmacy#define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH) 246167514Skmacy#define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH) 247167514Skmacy 248167514Skmacy#define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48 249167514Skmacy#define A_SG_RSPQ_FL_STATUS 0x4c 250167514Skmacy 251167514Skmacy#define S_RSPQ0STARVED 0 252167514Skmacy#define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED) 253167514Skmacy#define F_RSPQ0STARVED V_RSPQ0STARVED(1U) 254167514Skmacy 255167514Skmacy#define S_RSPQ1STARVED 1 256167514Skmacy#define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED) 257167514Skmacy#define F_RSPQ1STARVED V_RSPQ1STARVED(1U) 258167514Skmacy 259167514Skmacy#define S_RSPQ2STARVED 2 260167514Skmacy#define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED) 261167514Skmacy#define F_RSPQ2STARVED V_RSPQ2STARVED(1U) 262167514Skmacy 263167514Skmacy#define S_RSPQ3STARVED 3 264167514Skmacy#define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED) 265167514Skmacy#define F_RSPQ3STARVED V_RSPQ3STARVED(1U) 266167514Skmacy 267167514Skmacy#define S_RSPQ4STARVED 4 268167514Skmacy#define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED) 269167514Skmacy#define F_RSPQ4STARVED V_RSPQ4STARVED(1U) 270167514Skmacy 271167514Skmacy#define S_RSPQ5STARVED 5 272167514Skmacy#define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED) 273167514Skmacy#define F_RSPQ5STARVED V_RSPQ5STARVED(1U) 274167514Skmacy 275167514Skmacy#define S_RSPQ6STARVED 6 276167514Skmacy#define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED) 277167514Skmacy#define F_RSPQ6STARVED V_RSPQ6STARVED(1U) 278167514Skmacy 279167514Skmacy#define S_RSPQ7STARVED 7 280167514Skmacy#define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED) 281167514Skmacy#define F_RSPQ7STARVED V_RSPQ7STARVED(1U) 282167514Skmacy 283197791Snp#define S_RSPQXSTARVED 0 284197791Snp#define M_RSPQXSTARVED 0xff 285197791Snp#define V_RSPQXSTARVED(x) ((x) << S_RSPQXSTARVED) 286197791Snp#define G_RSPQXSTARVED(x) (((x) >> S_RSPQXSTARVED) & M_RSPQXSTARVED) 287197791Snp 288167514Skmacy#define S_RSPQ0DISABLED 8 289167514Skmacy#define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED) 290167514Skmacy#define F_RSPQ0DISABLED V_RSPQ0DISABLED(1U) 291167514Skmacy 292167514Skmacy#define S_RSPQ1DISABLED 9 293167514Skmacy#define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED) 294167514Skmacy#define F_RSPQ1DISABLED V_RSPQ1DISABLED(1U) 295167514Skmacy 296167514Skmacy#define S_RSPQ2DISABLED 10 297167514Skmacy#define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED) 298167514Skmacy#define F_RSPQ2DISABLED V_RSPQ2DISABLED(1U) 299167514Skmacy 300167514Skmacy#define S_RSPQ3DISABLED 11 301167514Skmacy#define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED) 302167514Skmacy#define F_RSPQ3DISABLED V_RSPQ3DISABLED(1U) 303167514Skmacy 304167514Skmacy#define S_RSPQ4DISABLED 12 305167514Skmacy#define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED) 306167514Skmacy#define F_RSPQ4DISABLED V_RSPQ4DISABLED(1U) 307167514Skmacy 308167514Skmacy#define S_RSPQ5DISABLED 13 309167514Skmacy#define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED) 310167514Skmacy#define F_RSPQ5DISABLED V_RSPQ5DISABLED(1U) 311167514Skmacy 312167514Skmacy#define S_RSPQ6DISABLED 14 313167514Skmacy#define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED) 314167514Skmacy#define F_RSPQ6DISABLED V_RSPQ6DISABLED(1U) 315167514Skmacy 316167514Skmacy#define S_RSPQ7DISABLED 15 317167514Skmacy#define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED) 318167514Skmacy#define F_RSPQ7DISABLED V_RSPQ7DISABLED(1U) 319167514Skmacy 320167514Skmacy#define S_FL0EMPTY 16 321167514Skmacy#define V_FL0EMPTY(x) ((x) << S_FL0EMPTY) 322167514Skmacy#define F_FL0EMPTY V_FL0EMPTY(1U) 323167514Skmacy 324167514Skmacy#define S_FL1EMPTY 17 325167514Skmacy#define V_FL1EMPTY(x) ((x) << S_FL1EMPTY) 326167514Skmacy#define F_FL1EMPTY V_FL1EMPTY(1U) 327167514Skmacy 328167514Skmacy#define S_FL2EMPTY 18 329167514Skmacy#define V_FL2EMPTY(x) ((x) << S_FL2EMPTY) 330167514Skmacy#define F_FL2EMPTY V_FL2EMPTY(1U) 331167514Skmacy 332167514Skmacy#define S_FL3EMPTY 19 333167514Skmacy#define V_FL3EMPTY(x) ((x) << S_FL3EMPTY) 334167514Skmacy#define F_FL3EMPTY V_FL3EMPTY(1U) 335167514Skmacy 336167514Skmacy#define S_FL4EMPTY 20 337167514Skmacy#define V_FL4EMPTY(x) ((x) << S_FL4EMPTY) 338167514Skmacy#define F_FL4EMPTY V_FL4EMPTY(1U) 339167514Skmacy 340167514Skmacy#define S_FL5EMPTY 21 341167514Skmacy#define V_FL5EMPTY(x) ((x) << S_FL5EMPTY) 342167514Skmacy#define F_FL5EMPTY V_FL5EMPTY(1U) 343167514Skmacy 344167514Skmacy#define S_FL6EMPTY 22 345167514Skmacy#define V_FL6EMPTY(x) ((x) << S_FL6EMPTY) 346167514Skmacy#define F_FL6EMPTY V_FL6EMPTY(1U) 347167514Skmacy 348167514Skmacy#define S_FL7EMPTY 23 349167514Skmacy#define V_FL7EMPTY(x) ((x) << S_FL7EMPTY) 350167514Skmacy#define F_FL7EMPTY V_FL7EMPTY(1U) 351167514Skmacy 352167514Skmacy#define S_FL8EMPTY 24 353167514Skmacy#define V_FL8EMPTY(x) ((x) << S_FL8EMPTY) 354167514Skmacy#define F_FL8EMPTY V_FL8EMPTY(1U) 355167514Skmacy 356167514Skmacy#define S_FL9EMPTY 25 357167514Skmacy#define V_FL9EMPTY(x) ((x) << S_FL9EMPTY) 358167514Skmacy#define F_FL9EMPTY V_FL9EMPTY(1U) 359167514Skmacy 360167514Skmacy#define S_FL10EMPTY 26 361167514Skmacy#define V_FL10EMPTY(x) ((x) << S_FL10EMPTY) 362167514Skmacy#define F_FL10EMPTY V_FL10EMPTY(1U) 363167514Skmacy 364167514Skmacy#define S_FL11EMPTY 27 365167514Skmacy#define V_FL11EMPTY(x) ((x) << S_FL11EMPTY) 366167514Skmacy#define F_FL11EMPTY V_FL11EMPTY(1U) 367167514Skmacy 368167514Skmacy#define S_FL12EMPTY 28 369167514Skmacy#define V_FL12EMPTY(x) ((x) << S_FL12EMPTY) 370167514Skmacy#define F_FL12EMPTY V_FL12EMPTY(1U) 371167514Skmacy 372167514Skmacy#define S_FL13EMPTY 29 373167514Skmacy#define V_FL13EMPTY(x) ((x) << S_FL13EMPTY) 374167514Skmacy#define F_FL13EMPTY V_FL13EMPTY(1U) 375167514Skmacy 376167514Skmacy#define S_FL14EMPTY 30 377167514Skmacy#define V_FL14EMPTY(x) ((x) << S_FL14EMPTY) 378167514Skmacy#define F_FL14EMPTY V_FL14EMPTY(1U) 379167514Skmacy 380167514Skmacy#define S_FL15EMPTY 31 381167514Skmacy#define V_FL15EMPTY(x) ((x) << S_FL15EMPTY) 382167514Skmacy#define F_FL15EMPTY V_FL15EMPTY(1U) 383167514Skmacy 384197791Snp#define S_FLXEMPTY 16 385197791Snp#define M_FLXEMPTY 0xffff 386197791Snp#define V_FLXEMPTY(x) ((x) << S_FLXEMPTY) 387197791Snp#define G_FLXEMPTY(x) (((x) >> S_FLXEMPTY) & M_FLXEMPTY) 388197791Snp 389167514Skmacy#define A_SG_EGR_PRI_CNT 0x50 390167514Skmacy 391167514Skmacy#define S_EGRERROPCODE 24 392167514Skmacy#define M_EGRERROPCODE 0xff 393167514Skmacy#define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) 394167514Skmacy#define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) 395167514Skmacy 396167514Skmacy#define S_EGRHIOPCODE 16 397167514Skmacy#define M_EGRHIOPCODE 0xff 398167514Skmacy#define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) 399167514Skmacy#define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) 400167514Skmacy 401167514Skmacy#define S_EGRLOOPCODE 8 402167514Skmacy#define M_EGRLOOPCODE 0xff 403167514Skmacy#define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) 404167514Skmacy#define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) 405167514Skmacy 406176472Skmacy#define S_EGRPRICNT 0 407176472Skmacy#define M_EGRPRICNT 0x1f 408176472Skmacy#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) 409176472Skmacy#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) 410176472Skmacy 411167514Skmacy#define A_SG_EGR_RCQ_DRB_THRSH 0x54 412167514Skmacy 413167514Skmacy#define S_HIRCQDRBTHRSH 16 414167514Skmacy#define M_HIRCQDRBTHRSH 0x7ff 415167514Skmacy#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) 416167514Skmacy#define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) 417167514Skmacy 418167514Skmacy#define S_LORCQDRBTHRSH 0 419167514Skmacy#define M_LORCQDRBTHRSH 0x7ff 420167514Skmacy#define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH) 421167514Skmacy#define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH) 422167514Skmacy 423167514Skmacy#define A_SG_EGR_CNTX_BADDR 0x58 424167514Skmacy 425167514Skmacy#define S_EGRCNTXBADDR 5 426167514Skmacy#define M_EGRCNTXBADDR 0x7ffffff 427167514Skmacy#define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) 428167514Skmacy#define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) 429167514Skmacy 430167514Skmacy#define A_SG_INT_CAUSE 0x5c 431167514Skmacy 432176472Skmacy#define S_HIRCQPARITYERROR 31 433176472Skmacy#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR) 434176472Skmacy#define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U) 435176472Skmacy 436176472Skmacy#define S_LORCQPARITYERROR 30 437176472Skmacy#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR) 438176472Skmacy#define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U) 439176472Skmacy 440176472Skmacy#define S_HIDRBPARITYERROR 29 441176472Skmacy#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR) 442176472Skmacy#define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U) 443176472Skmacy 444176472Skmacy#define S_LODRBPARITYERROR 28 445176472Skmacy#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR) 446176472Skmacy#define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U) 447176472Skmacy 448176472Skmacy#define S_FLPARITYERROR 22 449176472Skmacy#define M_FLPARITYERROR 0x3f 450176472Skmacy#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR) 451176472Skmacy#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) 452176472Skmacy 453176472Skmacy#define S_ITPARITYERROR 20 454176472Skmacy#define M_ITPARITYERROR 0x3 455176472Skmacy#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR) 456176472Skmacy#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) 457176472Skmacy 458176472Skmacy#define S_IRPARITYERROR 19 459176472Skmacy#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR) 460176472Skmacy#define F_IRPARITYERROR V_IRPARITYERROR(1U) 461176472Skmacy 462176472Skmacy#define S_RCPARITYERROR 18 463176472Skmacy#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR) 464176472Skmacy#define F_RCPARITYERROR V_RCPARITYERROR(1U) 465176472Skmacy 466176472Skmacy#define S_OCPARITYERROR 17 467176472Skmacy#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR) 468176472Skmacy#define F_OCPARITYERROR V_OCPARITYERROR(1U) 469176472Skmacy 470176472Skmacy#define S_CPPARITYERROR 16 471176472Skmacy#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR) 472176472Skmacy#define F_CPPARITYERROR V_CPPARITYERROR(1U) 473176472Skmacy 474176472Skmacy#define S_R_REQ_FRAMINGERROR 15 475176472Skmacy#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR) 476176472Skmacy#define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U) 477176472Skmacy 478176472Skmacy#define S_UC_REQ_FRAMINGERROR 14 479176472Skmacy#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR) 480176472Skmacy#define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U) 481176472Skmacy 482167514Skmacy#define S_HICTLDRBDROPERR 13 483167514Skmacy#define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) 484167514Skmacy#define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) 485167514Skmacy 486167514Skmacy#define S_LOCTLDRBDROPERR 12 487167514Skmacy#define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) 488167514Skmacy#define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) 489167514Skmacy 490167514Skmacy#define S_HIPIODRBDROPERR 11 491167514Skmacy#define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR) 492167514Skmacy#define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U) 493167514Skmacy 494167514Skmacy#define S_LOPIODRBDROPERR 10 495167514Skmacy#define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR) 496167514Skmacy#define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U) 497167514Skmacy 498167514Skmacy#define S_HICRDTUNDFLOWERR 9 499167514Skmacy#define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR) 500167514Skmacy#define F_HICRDTUNDFLOWERR V_HICRDTUNDFLOWERR(1U) 501167514Skmacy 502167514Skmacy#define S_LOCRDTUNDFLOWERR 8 503167514Skmacy#define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR) 504167514Skmacy#define F_LOCRDTUNDFLOWERR V_LOCRDTUNDFLOWERR(1U) 505167514Skmacy 506167514Skmacy#define S_HIPRIORITYDBFULL 7 507167514Skmacy#define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL) 508167514Skmacy#define F_HIPRIORITYDBFULL V_HIPRIORITYDBFULL(1U) 509167514Skmacy 510167514Skmacy#define S_HIPRIORITYDBEMPTY 6 511167514Skmacy#define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY) 512167514Skmacy#define F_HIPRIORITYDBEMPTY V_HIPRIORITYDBEMPTY(1U) 513167514Skmacy 514167514Skmacy#define S_LOPRIORITYDBFULL 5 515167514Skmacy#define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL) 516167514Skmacy#define F_LOPRIORITYDBFULL V_LOPRIORITYDBFULL(1U) 517167514Skmacy 518167514Skmacy#define S_LOPRIORITYDBEMPTY 4 519167514Skmacy#define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY) 520167514Skmacy#define F_LOPRIORITYDBEMPTY V_LOPRIORITYDBEMPTY(1U) 521167514Skmacy 522167514Skmacy#define S_RSPQDISABLED 3 523167514Skmacy#define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED) 524167514Skmacy#define F_RSPQDISABLED V_RSPQDISABLED(1U) 525167514Skmacy 526167514Skmacy#define S_RSPQCREDITOVERFOW 2 527167514Skmacy#define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW) 528167514Skmacy#define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U) 529167514Skmacy 530167514Skmacy#define S_FLEMPTY 1 531167514Skmacy#define V_FLEMPTY(x) ((x) << S_FLEMPTY) 532167514Skmacy#define F_FLEMPTY V_FLEMPTY(1U) 533167514Skmacy 534167514Skmacy#define S_RSPQSTARVE 0 535167514Skmacy#define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE) 536167514Skmacy#define F_RSPQSTARVE V_RSPQSTARVE(1U) 537167514Skmacy 538167514Skmacy#define A_SG_INT_ENABLE 0x60 539167514Skmacy#define A_SG_CMDQ_CREDIT_TH 0x64 540167514Skmacy 541167514Skmacy#define S_TIMEOUT 8 542167514Skmacy#define M_TIMEOUT 0xffffff 543167514Skmacy#define V_TIMEOUT(x) ((x) << S_TIMEOUT) 544167514Skmacy#define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT) 545167514Skmacy 546167514Skmacy#define S_THRESHOLD 0 547167514Skmacy#define M_THRESHOLD 0xff 548167514Skmacy#define V_THRESHOLD(x) ((x) << S_THRESHOLD) 549167514Skmacy#define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD) 550167514Skmacy 551167514Skmacy#define A_SG_TIMER_TICK 0x68 552167514Skmacy#define A_SG_CQ_CONTEXT_BADDR 0x6c 553167514Skmacy 554167514Skmacy#define S_BASEADDR 5 555167514Skmacy#define M_BASEADDR 0x7ffffff 556167514Skmacy#define V_BASEADDR(x) ((x) << S_BASEADDR) 557167514Skmacy#define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR) 558167514Skmacy 559167514Skmacy#define A_SG_OCO_BASE 0x70 560167514Skmacy 561167514Skmacy#define S_BASE1 16 562167514Skmacy#define M_BASE1 0xffff 563167514Skmacy#define V_BASE1(x) ((x) << S_BASE1) 564167514Skmacy#define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1) 565167514Skmacy 566167514Skmacy#define S_BASE0 0 567167514Skmacy#define M_BASE0 0xffff 568167514Skmacy#define V_BASE0(x) ((x) << S_BASE0) 569167514Skmacy#define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0) 570167514Skmacy 571167514Skmacy#define A_SG_DRB_PRI_THRESH 0x74 572167514Skmacy 573167514Skmacy#define S_DRBPRITHRSH 0 574167514Skmacy#define M_DRBPRITHRSH 0xffff 575167514Skmacy#define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH) 576167514Skmacy#define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH) 577167514Skmacy 578167514Skmacy#define A_SG_DEBUG_INDEX 0x78 579167514Skmacy#define A_SG_DEBUG_DATA 0x7c 580167514Skmacy 581167514Skmacy/* registers for module PCIX1 */ 582167514Skmacy#define PCIX1_BASE_ADDR 0x80 583167514Skmacy 584167514Skmacy#define A_PCIX_INT_ENABLE 0x80 585167514Skmacy 586167514Skmacy#define S_MSIXPARERR 22 587167514Skmacy#define M_MSIXPARERR 0x7 588167514Skmacy#define V_MSIXPARERR(x) ((x) << S_MSIXPARERR) 589167514Skmacy#define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR) 590167514Skmacy 591167514Skmacy#define S_CFPARERR 18 592167514Skmacy#define M_CFPARERR 0xf 593167514Skmacy#define V_CFPARERR(x) ((x) << S_CFPARERR) 594167514Skmacy#define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR) 595167514Skmacy 596167514Skmacy#define S_RFPARERR 14 597167514Skmacy#define M_RFPARERR 0xf 598167514Skmacy#define V_RFPARERR(x) ((x) << S_RFPARERR) 599167514Skmacy#define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR) 600167514Skmacy 601167514Skmacy#define S_WFPARERR 12 602167514Skmacy#define M_WFPARERR 0x3 603167514Skmacy#define V_WFPARERR(x) ((x) << S_WFPARERR) 604167514Skmacy#define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR) 605167514Skmacy 606167514Skmacy#define S_PIOPARERR 11 607167514Skmacy#define V_PIOPARERR(x) ((x) << S_PIOPARERR) 608167514Skmacy#define F_PIOPARERR V_PIOPARERR(1U) 609167514Skmacy 610167514Skmacy#define S_DETUNCECCERR 10 611167514Skmacy#define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR) 612167514Skmacy#define F_DETUNCECCERR V_DETUNCECCERR(1U) 613167514Skmacy 614167514Skmacy#define S_DETCORECCERR 9 615167514Skmacy#define V_DETCORECCERR(x) ((x) << S_DETCORECCERR) 616167514Skmacy#define F_DETCORECCERR V_DETCORECCERR(1U) 617167514Skmacy 618167514Skmacy#define S_RCVSPLCMPERR 8 619167514Skmacy#define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR) 620167514Skmacy#define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U) 621167514Skmacy 622167514Skmacy#define S_UNXSPLCMP 7 623167514Skmacy#define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP) 624167514Skmacy#define F_UNXSPLCMP V_UNXSPLCMP(1U) 625167514Skmacy 626167514Skmacy#define S_SPLCMPDIS 6 627167514Skmacy#define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS) 628167514Skmacy#define F_SPLCMPDIS V_SPLCMPDIS(1U) 629167514Skmacy 630167514Skmacy#define S_DETPARERR 5 631167514Skmacy#define V_DETPARERR(x) ((x) << S_DETPARERR) 632167514Skmacy#define F_DETPARERR V_DETPARERR(1U) 633167514Skmacy 634167514Skmacy#define S_SIGSYSERR 4 635167514Skmacy#define V_SIGSYSERR(x) ((x) << S_SIGSYSERR) 636167514Skmacy#define F_SIGSYSERR V_SIGSYSERR(1U) 637167514Skmacy 638167514Skmacy#define S_RCVMSTABT 3 639167514Skmacy#define V_RCVMSTABT(x) ((x) << S_RCVMSTABT) 640167514Skmacy#define F_RCVMSTABT V_RCVMSTABT(1U) 641167514Skmacy 642167514Skmacy#define S_RCVTARABT 2 643167514Skmacy#define V_RCVTARABT(x) ((x) << S_RCVTARABT) 644167514Skmacy#define F_RCVTARABT V_RCVTARABT(1U) 645167514Skmacy 646167514Skmacy#define S_SIGTARABT 1 647167514Skmacy#define V_SIGTARABT(x) ((x) << S_SIGTARABT) 648167514Skmacy#define F_SIGTARABT V_SIGTARABT(1U) 649167514Skmacy 650167514Skmacy#define S_MSTDETPARERR 0 651167514Skmacy#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) 652167514Skmacy#define F_MSTDETPARERR V_MSTDETPARERR(1U) 653167514Skmacy 654167514Skmacy#define A_PCIX_INT_CAUSE 0x84 655167514Skmacy#define A_PCIX_CFG 0x88 656167514Skmacy 657176472Skmacy#define S_DMASTOPEN 19 658176472Skmacy#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN) 659176472Skmacy#define F_DMASTOPEN V_DMASTOPEN(1U) 660176472Skmacy 661167514Skmacy#define S_CLIDECEN 18 662167514Skmacy#define V_CLIDECEN(x) ((x) << S_CLIDECEN) 663167514Skmacy#define F_CLIDECEN V_CLIDECEN(1U) 664167514Skmacy 665167514Skmacy#define S_LATTMRDIS 17 666167514Skmacy#define V_LATTMRDIS(x) ((x) << S_LATTMRDIS) 667167514Skmacy#define F_LATTMRDIS V_LATTMRDIS(1U) 668167514Skmacy 669167514Skmacy#define S_LOWPWREN 16 670167514Skmacy#define V_LOWPWREN(x) ((x) << S_LOWPWREN) 671167514Skmacy#define F_LOWPWREN V_LOWPWREN(1U) 672167514Skmacy 673167514Skmacy#define S_ASYNCINTVEC 11 674167514Skmacy#define M_ASYNCINTVEC 0x1f 675167514Skmacy#define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC) 676167514Skmacy#define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC) 677167514Skmacy 678167514Skmacy#define S_MAXSPLTRNC 8 679167514Skmacy#define M_MAXSPLTRNC 0x7 680167514Skmacy#define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC) 681167514Skmacy#define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC) 682167514Skmacy 683167514Skmacy#define S_MAXSPLTRNR 5 684167514Skmacy#define M_MAXSPLTRNR 0x7 685167514Skmacy#define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR) 686167514Skmacy#define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR) 687167514Skmacy 688167514Skmacy#define S_MAXWRBYTECNT 3 689167514Skmacy#define M_MAXWRBYTECNT 0x3 690167514Skmacy#define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT) 691167514Skmacy#define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT) 692167514Skmacy 693167514Skmacy#define S_WRREQATOMICEN 2 694167514Skmacy#define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN) 695167514Skmacy#define F_WRREQATOMICEN V_WRREQATOMICEN(1U) 696167514Skmacy 697167514Skmacy#define S_RSTWRMMODE 1 698167514Skmacy#define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE) 699167514Skmacy#define F_RSTWRMMODE V_RSTWRMMODE(1U) 700167514Skmacy 701167514Skmacy#define S_PIOACK64EN 0 702167514Skmacy#define V_PIOACK64EN(x) ((x) << S_PIOACK64EN) 703167514Skmacy#define F_PIOACK64EN V_PIOACK64EN(1U) 704167514Skmacy 705167514Skmacy#define A_PCIX_MODE 0x8c 706167514Skmacy 707167514Skmacy#define S_PCLKRANGE 6 708167514Skmacy#define M_PCLKRANGE 0x3 709167514Skmacy#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE) 710167514Skmacy#define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE) 711167514Skmacy 712167514Skmacy#define S_PCIXINITPAT 2 713167514Skmacy#define M_PCIXINITPAT 0xf 714167514Skmacy#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) 715167514Skmacy#define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT) 716167514Skmacy 717167514Skmacy#define S_66MHZ 1 718167514Skmacy#define V_66MHZ(x) ((x) << S_66MHZ) 719167514Skmacy#define F_66MHZ V_66MHZ(1U) 720167514Skmacy 721167514Skmacy#define S_64BIT 0 722167514Skmacy#define V_64BIT(x) ((x) << S_64BIT) 723167514Skmacy#define F_64BIT V_64BIT(1U) 724167514Skmacy 725167514Skmacy#define A_PCIX_CAL 0x90 726167514Skmacy 727167514Skmacy#define S_BUSY 31 728167514Skmacy#define V_BUSY(x) ((x) << S_BUSY) 729167514Skmacy#define F_BUSY V_BUSY(1U) 730167514Skmacy 731167514Skmacy#define S_PERCALDIV 22 732167514Skmacy#define M_PERCALDIV 0xff 733167514Skmacy#define V_PERCALDIV(x) ((x) << S_PERCALDIV) 734167514Skmacy#define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV) 735167514Skmacy 736167514Skmacy#define S_PERCALEN 21 737167514Skmacy#define V_PERCALEN(x) ((x) << S_PERCALEN) 738167514Skmacy#define F_PERCALEN V_PERCALEN(1U) 739167514Skmacy 740167514Skmacy#define S_SGLCALEN 20 741167514Skmacy#define V_SGLCALEN(x) ((x) << S_SGLCALEN) 742167514Skmacy#define F_SGLCALEN V_SGLCALEN(1U) 743167514Skmacy 744167514Skmacy#define S_ZINUPDMODE 19 745167514Skmacy#define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE) 746167514Skmacy#define F_ZINUPDMODE V_ZINUPDMODE(1U) 747167514Skmacy 748167514Skmacy#define S_ZINSEL 18 749167514Skmacy#define V_ZINSEL(x) ((x) << S_ZINSEL) 750167514Skmacy#define F_ZINSEL V_ZINSEL(1U) 751167514Skmacy 752167514Skmacy#define S_ZPDMAN 15 753167514Skmacy#define M_ZPDMAN 0x7 754167514Skmacy#define V_ZPDMAN(x) ((x) << S_ZPDMAN) 755167514Skmacy#define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN) 756167514Skmacy 757167514Skmacy#define S_ZPUMAN 12 758167514Skmacy#define M_ZPUMAN 0x7 759167514Skmacy#define V_ZPUMAN(x) ((x) << S_ZPUMAN) 760167514Skmacy#define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN) 761167514Skmacy 762167514Skmacy#define S_ZPDOUT 9 763167514Skmacy#define M_ZPDOUT 0x7 764167514Skmacy#define V_ZPDOUT(x) ((x) << S_ZPDOUT) 765167514Skmacy#define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT) 766167514Skmacy 767167514Skmacy#define S_ZPUOUT 6 768167514Skmacy#define M_ZPUOUT 0x7 769167514Skmacy#define V_ZPUOUT(x) ((x) << S_ZPUOUT) 770167514Skmacy#define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT) 771167514Skmacy 772167514Skmacy#define S_ZPDIN 3 773167514Skmacy#define M_ZPDIN 0x7 774167514Skmacy#define V_ZPDIN(x) ((x) << S_ZPDIN) 775167514Skmacy#define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN) 776167514Skmacy 777167514Skmacy#define S_ZPUIN 0 778167514Skmacy#define M_ZPUIN 0x7 779167514Skmacy#define V_ZPUIN(x) ((x) << S_ZPUIN) 780167514Skmacy#define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN) 781167514Skmacy 782167514Skmacy#define A_PCIX_WOL 0x94 783167514Skmacy 784167514Skmacy#define S_WAKEUP1 3 785167514Skmacy#define V_WAKEUP1(x) ((x) << S_WAKEUP1) 786167514Skmacy#define F_WAKEUP1 V_WAKEUP1(1U) 787167514Skmacy 788167514Skmacy#define S_WAKEUP0 2 789167514Skmacy#define V_WAKEUP0(x) ((x) << S_WAKEUP0) 790167514Skmacy#define F_WAKEUP0 V_WAKEUP0(1U) 791167514Skmacy 792167514Skmacy#define S_SLEEPMODE1 1 793167514Skmacy#define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1) 794167514Skmacy#define F_SLEEPMODE1 V_SLEEPMODE1(1U) 795167514Skmacy 796167514Skmacy#define S_SLEEPMODE0 0 797167514Skmacy#define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) 798167514Skmacy#define F_SLEEPMODE0 V_SLEEPMODE0(1U) 799167514Skmacy 800176472Skmacy#define A_PCIX_STAT0 0x98 801176472Skmacy 802176472Skmacy#define S_PIOREQFIFOLEVEL 26 803176472Skmacy#define M_PIOREQFIFOLEVEL 0x3f 804176472Skmacy#define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL) 805176472Skmacy#define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL) 806176472Skmacy 807176472Skmacy#define S_RFINIST 24 808176472Skmacy#define M_RFINIST 0x3 809176472Skmacy#define V_RFINIST(x) ((x) << S_RFINIST) 810176472Skmacy#define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST) 811176472Skmacy 812176472Skmacy#define S_RFRESPRDST 22 813176472Skmacy#define M_RFRESPRDST 0x3 814176472Skmacy#define V_RFRESPRDST(x) ((x) << S_RFRESPRDST) 815176472Skmacy#define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST) 816176472Skmacy 817176472Skmacy#define S_TARCST 19 818176472Skmacy#define M_TARCST 0x7 819176472Skmacy#define V_TARCST(x) ((x) << S_TARCST) 820176472Skmacy#define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST) 821176472Skmacy 822176472Skmacy#define S_TARXST 16 823176472Skmacy#define M_TARXST 0x7 824176472Skmacy#define V_TARXST(x) ((x) << S_TARXST) 825176472Skmacy#define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST) 826176472Skmacy 827176472Skmacy#define S_WFREQWRST 13 828176472Skmacy#define M_WFREQWRST 0x7 829176472Skmacy#define V_WFREQWRST(x) ((x) << S_WFREQWRST) 830176472Skmacy#define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST) 831176472Skmacy 832176472Skmacy#define S_WFRESPFIFOEMPTY 12 833176472Skmacy#define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY) 834176472Skmacy#define F_WFRESPFIFOEMPTY V_WFRESPFIFOEMPTY(1U) 835176472Skmacy 836176472Skmacy#define S_WFREQFIFOEMPTY 11 837176472Skmacy#define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY) 838176472Skmacy#define F_WFREQFIFOEMPTY V_WFREQFIFOEMPTY(1U) 839176472Skmacy 840176472Skmacy#define S_RFRESPFIFOEMPTY 10 841176472Skmacy#define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY) 842176472Skmacy#define F_RFRESPFIFOEMPTY V_RFRESPFIFOEMPTY(1U) 843176472Skmacy 844176472Skmacy#define S_RFREQFIFOEMPTY 9 845176472Skmacy#define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY) 846176472Skmacy#define F_RFREQFIFOEMPTY V_RFREQFIFOEMPTY(1U) 847176472Skmacy 848176472Skmacy#define S_PIORESPFIFOLEVEL 7 849176472Skmacy#define M_PIORESPFIFOLEVEL 0x3 850176472Skmacy#define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL) 851176472Skmacy#define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL) 852176472Skmacy 853176472Skmacy#define S_CFRESPFIFOEMPTY 6 854176472Skmacy#define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY) 855176472Skmacy#define F_CFRESPFIFOEMPTY V_CFRESPFIFOEMPTY(1U) 856176472Skmacy 857176472Skmacy#define S_CFREQFIFOEMPTY 5 858176472Skmacy#define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY) 859176472Skmacy#define F_CFREQFIFOEMPTY V_CFREQFIFOEMPTY(1U) 860176472Skmacy 861176472Skmacy#define S_VPDRESPFIFOEMPTY 4 862176472Skmacy#define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY) 863176472Skmacy#define F_VPDRESPFIFOEMPTY V_VPDRESPFIFOEMPTY(1U) 864176472Skmacy 865176472Skmacy#define S_VPDREQFIFOEMPTY 3 866176472Skmacy#define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY) 867176472Skmacy#define F_VPDREQFIFOEMPTY V_VPDREQFIFOEMPTY(1U) 868176472Skmacy 869176472Skmacy#define S_PIO_RSPPND 2 870176472Skmacy#define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND) 871176472Skmacy#define F_PIO_RSPPND V_PIO_RSPPND(1U) 872176472Skmacy 873176472Skmacy#define S_DLYTRNPND 1 874176472Skmacy#define V_DLYTRNPND(x) ((x) << S_DLYTRNPND) 875176472Skmacy#define F_DLYTRNPND V_DLYTRNPND(1U) 876176472Skmacy 877176472Skmacy#define S_SPLTRNPND 0 878176472Skmacy#define V_SPLTRNPND(x) ((x) << S_SPLTRNPND) 879176472Skmacy#define F_SPLTRNPND V_SPLTRNPND(1U) 880176472Skmacy 881176472Skmacy#define A_PCIX_STAT1 0x9c 882176472Skmacy 883176472Skmacy#define S_WFINIST 26 884176472Skmacy#define M_WFINIST 0xf 885176472Skmacy#define V_WFINIST(x) ((x) << S_WFINIST) 886176472Skmacy#define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST) 887176472Skmacy 888176472Skmacy#define S_ARBST 23 889176472Skmacy#define M_ARBST 0x7 890176472Skmacy#define V_ARBST(x) ((x) << S_ARBST) 891176472Skmacy#define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST) 892176472Skmacy 893176472Skmacy#define S_PMIST 21 894176472Skmacy#define M_PMIST 0x3 895176472Skmacy#define V_PMIST(x) ((x) << S_PMIST) 896176472Skmacy#define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST) 897176472Skmacy 898176472Skmacy#define S_CALST 19 899176472Skmacy#define M_CALST 0x3 900176472Skmacy#define V_CALST(x) ((x) << S_CALST) 901176472Skmacy#define G_CALST(x) (((x) >> S_CALST) & M_CALST) 902176472Skmacy 903176472Skmacy#define S_CFREQRDST 17 904176472Skmacy#define M_CFREQRDST 0x3 905176472Skmacy#define V_CFREQRDST(x) ((x) << S_CFREQRDST) 906176472Skmacy#define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST) 907176472Skmacy 908176472Skmacy#define S_CFINIST 15 909176472Skmacy#define M_CFINIST 0x3 910176472Skmacy#define V_CFINIST(x) ((x) << S_CFINIST) 911176472Skmacy#define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST) 912176472Skmacy 913176472Skmacy#define S_CFRESPRDST 13 914176472Skmacy#define M_CFRESPRDST 0x3 915176472Skmacy#define V_CFRESPRDST(x) ((x) << S_CFRESPRDST) 916176472Skmacy#define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST) 917176472Skmacy 918176472Skmacy#define S_INICST 10 919176472Skmacy#define M_INICST 0x7 920176472Skmacy#define V_INICST(x) ((x) << S_INICST) 921176472Skmacy#define G_INICST(x) (((x) >> S_INICST) & M_INICST) 922176472Skmacy 923176472Skmacy#define S_INIXST 7 924176472Skmacy#define M_INIXST 0x7 925176472Skmacy#define V_INIXST(x) ((x) << S_INIXST) 926176472Skmacy#define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST) 927176472Skmacy 928176472Skmacy#define S_INTST 4 929176472Skmacy#define M_INTST 0x7 930176472Skmacy#define V_INTST(x) ((x) << S_INTST) 931176472Skmacy#define G_INTST(x) (((x) >> S_INTST) & M_INTST) 932176472Skmacy 933176472Skmacy#define S_PIOST 2 934176472Skmacy#define M_PIOST 0x3 935176472Skmacy#define V_PIOST(x) ((x) << S_PIOST) 936176472Skmacy#define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST) 937176472Skmacy 938176472Skmacy#define S_RFREQRDST 0 939176472Skmacy#define M_RFREQRDST 0x3 940176472Skmacy#define V_RFREQRDST(x) ((x) << S_RFREQRDST) 941176472Skmacy#define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST) 942176472Skmacy 943167514Skmacy/* registers for module PCIE0 */ 944167514Skmacy#define PCIE0_BASE_ADDR 0x80 945167514Skmacy 946167514Skmacy#define A_PCIE_INT_ENABLE 0x80 947167514Skmacy 948176472Skmacy#define S_BISTERR 19 949167514Skmacy#define M_BISTERR 0xff 950167514Skmacy#define V_BISTERR(x) ((x) << S_BISTERR) 951167514Skmacy#define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) 952167514Skmacy 953176472Skmacy#define S_TXPARERR 18 954176472Skmacy#define V_TXPARERR(x) ((x) << S_TXPARERR) 955176472Skmacy#define F_TXPARERR V_TXPARERR(1U) 956176472Skmacy 957176472Skmacy#define S_RXPARERR 17 958176472Skmacy#define V_RXPARERR(x) ((x) << S_RXPARERR) 959176472Skmacy#define F_RXPARERR V_RXPARERR(1U) 960176472Skmacy 961176472Skmacy#define S_RETRYLUTPARERR 16 962176472Skmacy#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR) 963176472Skmacy#define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U) 964176472Skmacy 965176472Skmacy#define S_RETRYBUFPARERR 15 966176472Skmacy#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR) 967176472Skmacy#define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U) 968176472Skmacy 969167514Skmacy#define S_PCIE_MSIXPARERR 12 970167514Skmacy#define M_PCIE_MSIXPARERR 0x7 971167514Skmacy#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) 972167514Skmacy#define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) 973167514Skmacy 974167514Skmacy#define S_PCIE_CFPARERR 11 975167514Skmacy#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) 976167514Skmacy#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) 977167514Skmacy 978167514Skmacy#define S_PCIE_RFPARERR 10 979167514Skmacy#define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR) 980167514Skmacy#define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U) 981167514Skmacy 982167514Skmacy#define S_PCIE_WFPARERR 9 983167514Skmacy#define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR) 984167514Skmacy#define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U) 985167514Skmacy 986167514Skmacy#define S_PCIE_PIOPARERR 8 987167514Skmacy#define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR) 988167514Skmacy#define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U) 989167514Skmacy 990167514Skmacy#define S_UNXSPLCPLERRC 7 991167514Skmacy#define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC) 992167514Skmacy#define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U) 993167514Skmacy 994167514Skmacy#define S_UNXSPLCPLERRR 6 995167514Skmacy#define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR) 996167514Skmacy#define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U) 997167514Skmacy 998167514Skmacy#define S_VPDADDRCHNG 5 999167514Skmacy#define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG) 1000167514Skmacy#define F_VPDADDRCHNG V_VPDADDRCHNG(1U) 1001167514Skmacy 1002167514Skmacy#define S_BUSMSTREN 4 1003167514Skmacy#define V_BUSMSTREN(x) ((x) << S_BUSMSTREN) 1004167514Skmacy#define F_BUSMSTREN V_BUSMSTREN(1U) 1005167514Skmacy 1006167514Skmacy#define S_PMSTCHNG 3 1007167514Skmacy#define V_PMSTCHNG(x) ((x) << S_PMSTCHNG) 1008167514Skmacy#define F_PMSTCHNG V_PMSTCHNG(1U) 1009167514Skmacy 1010167514Skmacy#define S_PEXMSG 2 1011167514Skmacy#define V_PEXMSG(x) ((x) << S_PEXMSG) 1012167514Skmacy#define F_PEXMSG V_PEXMSG(1U) 1013167514Skmacy 1014167514Skmacy#define S_ZEROLENRD 1 1015167514Skmacy#define V_ZEROLENRD(x) ((x) << S_ZEROLENRD) 1016167514Skmacy#define F_ZEROLENRD V_ZEROLENRD(1U) 1017167514Skmacy 1018167514Skmacy#define S_PEXERR 0 1019167514Skmacy#define V_PEXERR(x) ((x) << S_PEXERR) 1020167514Skmacy#define F_PEXERR V_PEXERR(1U) 1021167514Skmacy 1022167514Skmacy#define A_PCIE_INT_CAUSE 0x84 1023167514Skmacy#define A_PCIE_CFG 0x88 1024167514Skmacy 1025176472Skmacy#define S_PCIE_DMASTOPEN 24 1026176472Skmacy#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) 1027176472Skmacy#define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) 1028176472Skmacy 1029176472Skmacy#define S_PRIORITYINTA 23 1030176472Skmacy#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) 1031176472Skmacy#define F_PRIORITYINTA V_PRIORITYINTA(1U) 1032176472Skmacy 1033176472Skmacy#define S_INIFULLPKT 22 1034176472Skmacy#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) 1035176472Skmacy#define F_INIFULLPKT V_INIFULLPKT(1U) 1036176472Skmacy 1037167514Skmacy#define S_ENABLELINKDWNDRST 21 1038167514Skmacy#define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) 1039167514Skmacy#define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) 1040167514Skmacy 1041167514Skmacy#define S_ENABLELINKDOWNRST 20 1042167514Skmacy#define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) 1043167514Skmacy#define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) 1044167514Skmacy 1045167514Skmacy#define S_ENABLEHOTRST 19 1046167514Skmacy#define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST) 1047167514Skmacy#define F_ENABLEHOTRST V_ENABLEHOTRST(1U) 1048167514Skmacy 1049167514Skmacy#define S_INIWAITFORGNT 18 1050167514Skmacy#define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT) 1051167514Skmacy#define F_INIWAITFORGNT V_INIWAITFORGNT(1U) 1052167514Skmacy 1053167514Skmacy#define S_INIBEDIS 17 1054167514Skmacy#define V_INIBEDIS(x) ((x) << S_INIBEDIS) 1055167514Skmacy#define F_INIBEDIS V_INIBEDIS(1U) 1056167514Skmacy 1057167514Skmacy#define S_PCIE_CLIDECEN 16 1058167514Skmacy#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) 1059167514Skmacy#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) 1060167514Skmacy 1061167514Skmacy#define S_PCIE_MAXSPLTRNC 7 1062167514Skmacy#define M_PCIE_MAXSPLTRNC 0xf 1063167514Skmacy#define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC) 1064167514Skmacy#define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC) 1065167514Skmacy 1066167514Skmacy#define S_PCIE_MAXSPLTRNR 1 1067167514Skmacy#define M_PCIE_MAXSPLTRNR 0x3f 1068167514Skmacy#define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) 1069167514Skmacy#define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) 1070167514Skmacy 1071167514Skmacy#define S_CRSTWRMMODE 0 1072167514Skmacy#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) 1073167514Skmacy#define F_CRSTWRMMODE V_CRSTWRMMODE(1U) 1074167514Skmacy 1075176472Skmacy#define A_PCIE_MODE 0x8c 1076167514Skmacy 1077176472Skmacy#define S_TAR_STATE 29 1078176472Skmacy#define M_TAR_STATE 0x7 1079176472Skmacy#define V_TAR_STATE(x) ((x) << S_TAR_STATE) 1080176472Skmacy#define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE) 1081167514Skmacy 1082176472Skmacy#define S_RF_STATEINI 26 1083176472Skmacy#define M_RF_STATEINI 0x7 1084176472Skmacy#define V_RF_STATEINI(x) ((x) << S_RF_STATEINI) 1085176472Skmacy#define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI) 1086167514Skmacy 1087176472Skmacy#define S_CF_STATEINI 23 1088176472Skmacy#define M_CF_STATEINI 0x7 1089176472Skmacy#define V_CF_STATEINI(x) ((x) << S_CF_STATEINI) 1090176472Skmacy#define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI) 1091176472Skmacy 1092176472Skmacy#define S_PIO_STATEPL 20 1093176472Skmacy#define M_PIO_STATEPL 0x7 1094176472Skmacy#define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL) 1095176472Skmacy#define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL) 1096176472Skmacy 1097176472Skmacy#define S_PIO_STATEISC 18 1098176472Skmacy#define M_PIO_STATEISC 0x3 1099176472Skmacy#define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC) 1100176472Skmacy#define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC) 1101176472Skmacy 1102176472Skmacy#define S_NUMFSTTRNSEQRX 10 1103176472Skmacy#define M_NUMFSTTRNSEQRX 0xff 1104176472Skmacy#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) 1105176472Skmacy#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) 1106176472Skmacy 1107167514Skmacy#define S_LNKCNTLSTATE 2 1108167514Skmacy#define M_LNKCNTLSTATE 0xff 1109167514Skmacy#define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) 1110167514Skmacy#define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) 1111167514Skmacy 1112167514Skmacy#define S_VC0UP 1 1113167514Skmacy#define V_VC0UP(x) ((x) << S_VC0UP) 1114167514Skmacy#define F_VC0UP V_VC0UP(1U) 1115167514Skmacy 1116167514Skmacy#define S_LNKINITIAL 0 1117167514Skmacy#define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) 1118167514Skmacy#define F_LNKINITIAL V_LNKINITIAL(1U) 1119167514Skmacy 1120176472Skmacy#define A_PCIE_STAT 0x90 1121167514Skmacy 1122176472Skmacy#define S_INI_STATE 28 1123176472Skmacy#define M_INI_STATE 0xf 1124176472Skmacy#define V_INI_STATE(x) ((x) << S_INI_STATE) 1125176472Skmacy#define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE) 1126176472Skmacy 1127176472Skmacy#define S_WF_STATEINI 24 1128176472Skmacy#define M_WF_STATEINI 0xf 1129176472Skmacy#define V_WF_STATEINI(x) ((x) << S_WF_STATEINI) 1130176472Skmacy#define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI) 1131176472Skmacy 1132176472Skmacy#define S_PLM_REQFIFOCNT 22 1133176472Skmacy#define M_PLM_REQFIFOCNT 0x3 1134176472Skmacy#define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT) 1135176472Skmacy#define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT) 1136176472Skmacy 1137176472Skmacy#define S_ER_REQFIFOEMPTY 21 1138176472Skmacy#define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY) 1139176472Skmacy#define F_ER_REQFIFOEMPTY V_ER_REQFIFOEMPTY(1U) 1140176472Skmacy 1141176472Skmacy#define S_WF_RSPFIFOEMPTY 20 1142176472Skmacy#define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY) 1143176472Skmacy#define F_WF_RSPFIFOEMPTY V_WF_RSPFIFOEMPTY(1U) 1144176472Skmacy 1145176472Skmacy#define S_WF_REQFIFOEMPTY 19 1146176472Skmacy#define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY) 1147176472Skmacy#define F_WF_REQFIFOEMPTY V_WF_REQFIFOEMPTY(1U) 1148176472Skmacy 1149176472Skmacy#define S_RF_RSPFIFOEMPTY 18 1150176472Skmacy#define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY) 1151176472Skmacy#define F_RF_RSPFIFOEMPTY V_RF_RSPFIFOEMPTY(1U) 1152176472Skmacy 1153176472Skmacy#define S_RF_REQFIFOEMPTY 17 1154176472Skmacy#define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY) 1155176472Skmacy#define F_RF_REQFIFOEMPTY V_RF_REQFIFOEMPTY(1U) 1156176472Skmacy 1157176472Skmacy#define S_RF_ACTEMPTY 16 1158176472Skmacy#define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY) 1159176472Skmacy#define F_RF_ACTEMPTY V_RF_ACTEMPTY(1U) 1160176472Skmacy 1161176472Skmacy#define S_PIO_RSPFIFOCNT 11 1162176472Skmacy#define M_PIO_RSPFIFOCNT 0x1f 1163176472Skmacy#define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT) 1164176472Skmacy#define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT) 1165176472Skmacy 1166176472Skmacy#define S_PIO_REQFIFOCNT 5 1167176472Skmacy#define M_PIO_REQFIFOCNT 0x3f 1168176472Skmacy#define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT) 1169176472Skmacy#define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT) 1170176472Skmacy 1171176472Skmacy#define S_CF_RSPFIFOEMPTY 4 1172176472Skmacy#define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY) 1173176472Skmacy#define F_CF_RSPFIFOEMPTY V_CF_RSPFIFOEMPTY(1U) 1174176472Skmacy 1175176472Skmacy#define S_CF_REQFIFOEMPTY 3 1176176472Skmacy#define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY) 1177176472Skmacy#define F_CF_REQFIFOEMPTY V_CF_REQFIFOEMPTY(1U) 1178176472Skmacy 1179176472Skmacy#define S_CF_ACTEMPTY 2 1180176472Skmacy#define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY) 1181176472Skmacy#define F_CF_ACTEMPTY V_CF_ACTEMPTY(1U) 1182176472Skmacy 1183176472Skmacy#define S_VPD_RSPFIFOEMPTY 1 1184176472Skmacy#define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY) 1185176472Skmacy#define F_VPD_RSPFIFOEMPTY V_VPD_RSPFIFOEMPTY(1U) 1186176472Skmacy 1187176472Skmacy#define S_VPD_REQFIFOEMPTY 0 1188176472Skmacy#define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY) 1189176472Skmacy#define F_VPD_REQFIFOEMPTY V_VPD_REQFIFOEMPTY(1U) 1190176472Skmacy 1191167514Skmacy#define A_PCIE_CAL 0x90 1192167514Skmacy 1193167514Skmacy#define S_CALBUSY 31 1194167514Skmacy#define V_CALBUSY(x) ((x) << S_CALBUSY) 1195167514Skmacy#define F_CALBUSY V_CALBUSY(1U) 1196167514Skmacy 1197167514Skmacy#define S_CALFAULT 30 1198167514Skmacy#define V_CALFAULT(x) ((x) << S_CALFAULT) 1199167514Skmacy#define F_CALFAULT V_CALFAULT(1U) 1200167514Skmacy 1201167514Skmacy#define S_PCIE_ZINSEL 11 1202167514Skmacy#define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL) 1203167514Skmacy#define F_PCIE_ZINSEL V_PCIE_ZINSEL(1U) 1204167514Skmacy 1205167514Skmacy#define S_ZMAN 8 1206167514Skmacy#define M_ZMAN 0x7 1207167514Skmacy#define V_ZMAN(x) ((x) << S_ZMAN) 1208167514Skmacy#define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN) 1209167514Skmacy 1210167514Skmacy#define S_ZOUT 3 1211167514Skmacy#define M_ZOUT 0x1f 1212167514Skmacy#define V_ZOUT(x) ((x) << S_ZOUT) 1213167514Skmacy#define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) 1214167514Skmacy 1215167514Skmacy#define S_ZIN 0 1216167514Skmacy#define M_ZIN 0x7 1217167514Skmacy#define V_ZIN(x) ((x) << S_ZIN) 1218167514Skmacy#define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) 1219167514Skmacy 1220167514Skmacy#define A_PCIE_WOL 0x94 1221176472Skmacy 1222176472Skmacy#define S_CF_RSPSTATE 12 1223176472Skmacy#define M_CF_RSPSTATE 0x3 1224176472Skmacy#define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE) 1225176472Skmacy#define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE) 1226176472Skmacy 1227176472Skmacy#define S_RF_RSPSTATE 10 1228176472Skmacy#define M_RF_RSPSTATE 0x3 1229176472Skmacy#define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE) 1230176472Skmacy#define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE) 1231176472Skmacy 1232176472Skmacy#define S_PME_STATE 7 1233176472Skmacy#define M_PME_STATE 0x7 1234176472Skmacy#define V_PME_STATE(x) ((x) << S_PME_STATE) 1235176472Skmacy#define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE) 1236176472Skmacy 1237176472Skmacy#define S_INT_STATE 4 1238176472Skmacy#define M_INT_STATE 0x7 1239176472Skmacy#define V_INT_STATE(x) ((x) << S_INT_STATE) 1240176472Skmacy#define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE) 1241176472Skmacy 1242167514Skmacy#define A_PCIE_PEX_CTRL0 0x98 1243167514Skmacy 1244176472Skmacy#define S_CPLTIMEOUTRETRY 31 1245176472Skmacy#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) 1246176472Skmacy#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) 1247176472Skmacy 1248176472Skmacy#define S_STRICTTSMN 30 1249176472Skmacy#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) 1250176472Skmacy#define F_STRICTTSMN V_STRICTTSMN(1U) 1251176472Skmacy 1252167514Skmacy#define S_NUMFSTTRNSEQ 22 1253167514Skmacy#define M_NUMFSTTRNSEQ 0xff 1254167514Skmacy#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) 1255167514Skmacy#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) 1256167514Skmacy 1257167514Skmacy#define S_REPLAYLMT 2 1258167514Skmacy#define M_REPLAYLMT 0xfffff 1259167514Skmacy#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) 1260167514Skmacy#define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) 1261167514Skmacy 1262167514Skmacy#define S_TXPNDCHKEN 1 1263167514Skmacy#define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN) 1264167514Skmacy#define F_TXPNDCHKEN V_TXPNDCHKEN(1U) 1265167514Skmacy 1266167514Skmacy#define S_CPLPNDCHKEN 0 1267167514Skmacy#define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) 1268167514Skmacy#define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) 1269167514Skmacy 1270167514Skmacy#define A_PCIE_PEX_CTRL1 0x9c 1271167514Skmacy 1272167514Skmacy#define S_RXPHYERREN 31 1273167514Skmacy#define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) 1274167514Skmacy#define F_RXPHYERREN V_RXPHYERREN(1U) 1275167514Skmacy 1276167514Skmacy#define S_DLLPTIMEOUTLMT 13 1277167514Skmacy#define M_DLLPTIMEOUTLMT 0x3ffff 1278167514Skmacy#define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) 1279167514Skmacy#define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) 1280167514Skmacy 1281167514Skmacy#define S_ACKLAT 0 1282167514Skmacy#define M_ACKLAT 0x1fff 1283167514Skmacy#define V_ACKLAT(x) ((x) << S_ACKLAT) 1284167514Skmacy#define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) 1285167514Skmacy 1286176472Skmacy#define S_T3A_DLLPTIMEOUTLMT 11 1287176472Skmacy#define M_T3A_DLLPTIMEOUTLMT 0xfffff 1288176472Skmacy#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) 1289176472Skmacy#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) 1290176472Skmacy 1291176472Skmacy#define S_T3A_ACKLAT 0 1292176472Skmacy#define M_T3A_ACKLAT 0x7ff 1293176472Skmacy#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) 1294176472Skmacy#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) 1295176472Skmacy 1296167514Skmacy#define A_PCIE_PEX_CTRL2 0xa0 1297167514Skmacy 1298176472Skmacy#define S_LNKCNTLDETDIR 30 1299176472Skmacy#define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) 1300176472Skmacy#define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) 1301176472Skmacy 1302176472Skmacy#define S_ENTERL1REN 29 1303176472Skmacy#define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) 1304176472Skmacy#define F_ENTERL1REN V_ENTERL1REN(1U) 1305176472Skmacy 1306176472Skmacy#define S_PMEXITL1REQ 28 1307167514Skmacy#define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) 1308167514Skmacy#define F_PMEXITL1REQ V_PMEXITL1REQ(1U) 1309167514Skmacy 1310176472Skmacy#define S_PMTXIDLE 27 1311167514Skmacy#define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) 1312167514Skmacy#define F_PMTXIDLE V_PMTXIDLE(1U) 1313167514Skmacy 1314176472Skmacy#define S_PCIMODELOOP 26 1315167514Skmacy#define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) 1316167514Skmacy#define F_PCIMODELOOP V_PCIMODELOOP(1U) 1317167514Skmacy 1318176472Skmacy#define S_L1ASPMTXRXL0STIME 14 1319167514Skmacy#define M_L1ASPMTXRXL0STIME 0xfff 1320167514Skmacy#define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) 1321167514Skmacy#define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) 1322167514Skmacy 1323176472Skmacy#define S_L0SIDLETIME 3 1324167514Skmacy#define M_L0SIDLETIME 0x7ff 1325167514Skmacy#define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) 1326167514Skmacy#define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) 1327167514Skmacy 1328167514Skmacy#define S_ENTERL1ASPMEN 2 1329167514Skmacy#define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN) 1330167514Skmacy#define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U) 1331167514Skmacy 1332167514Skmacy#define S_ENTERL1EN 1 1333167514Skmacy#define V_ENTERL1EN(x) ((x) << S_ENTERL1EN) 1334167514Skmacy#define F_ENTERL1EN V_ENTERL1EN(1U) 1335167514Skmacy 1336167514Skmacy#define S_ENTERL0SEN 0 1337167514Skmacy#define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN) 1338167514Skmacy#define F_ENTERL0SEN V_ENTERL0SEN(1U) 1339167514Skmacy 1340176472Skmacy#define S_ENTERL23 3 1341176472Skmacy#define V_ENTERL23(x) ((x) << S_ENTERL23) 1342176472Skmacy#define F_ENTERL23 V_ENTERL23(1U) 1343167514Skmacy 1344167514Skmacy#define A_PCIE_PEX_ERR 0xa4 1345167514Skmacy 1346176472Skmacy#define S_CPLTIMEOUTID 18 1347176472Skmacy#define M_CPLTIMEOUTID 0x7f 1348176472Skmacy#define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) 1349176472Skmacy#define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) 1350176472Skmacy 1351167514Skmacy#define S_FLOWCTLOFLOWERR 17 1352167514Skmacy#define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR) 1353167514Skmacy#define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U) 1354167514Skmacy 1355167514Skmacy#define S_REPLAYTIMEOUT 16 1356167514Skmacy#define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT) 1357167514Skmacy#define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U) 1358167514Skmacy 1359167514Skmacy#define S_REPLAYROLLOVER 15 1360167514Skmacy#define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER) 1361167514Skmacy#define F_REPLAYROLLOVER V_REPLAYROLLOVER(1U) 1362167514Skmacy 1363167514Skmacy#define S_BADDLLP 14 1364167514Skmacy#define V_BADDLLP(x) ((x) << S_BADDLLP) 1365167514Skmacy#define F_BADDLLP V_BADDLLP(1U) 1366167514Skmacy 1367167514Skmacy#define S_DLLPERR 13 1368167514Skmacy#define V_DLLPERR(x) ((x) << S_DLLPERR) 1369167514Skmacy#define F_DLLPERR V_DLLPERR(1U) 1370167514Skmacy 1371167514Skmacy#define S_FLOWCTLPROTERR 12 1372167514Skmacy#define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR) 1373167514Skmacy#define F_FLOWCTLPROTERR V_FLOWCTLPROTERR(1U) 1374167514Skmacy 1375167514Skmacy#define S_CPLTIMEOUT 11 1376167514Skmacy#define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT) 1377167514Skmacy#define F_CPLTIMEOUT V_CPLTIMEOUT(1U) 1378167514Skmacy 1379167514Skmacy#define S_PHYRCVERR 10 1380167514Skmacy#define V_PHYRCVERR(x) ((x) << S_PHYRCVERR) 1381167514Skmacy#define F_PHYRCVERR V_PHYRCVERR(1U) 1382167514Skmacy 1383167514Skmacy#define S_DISTLP 9 1384167514Skmacy#define V_DISTLP(x) ((x) << S_DISTLP) 1385167514Skmacy#define F_DISTLP V_DISTLP(1U) 1386167514Skmacy 1387167514Skmacy#define S_BADECRC 8 1388167514Skmacy#define V_BADECRC(x) ((x) << S_BADECRC) 1389167514Skmacy#define F_BADECRC V_BADECRC(1U) 1390167514Skmacy 1391167514Skmacy#define S_BADTLP 7 1392167514Skmacy#define V_BADTLP(x) ((x) << S_BADTLP) 1393167514Skmacy#define F_BADTLP V_BADTLP(1U) 1394167514Skmacy 1395167514Skmacy#define S_MALTLP 6 1396167514Skmacy#define V_MALTLP(x) ((x) << S_MALTLP) 1397167514Skmacy#define F_MALTLP V_MALTLP(1U) 1398167514Skmacy 1399167514Skmacy#define S_UNXCPL 5 1400167514Skmacy#define V_UNXCPL(x) ((x) << S_UNXCPL) 1401167514Skmacy#define F_UNXCPL V_UNXCPL(1U) 1402167514Skmacy 1403167514Skmacy#define S_UNSREQ 4 1404167514Skmacy#define V_UNSREQ(x) ((x) << S_UNSREQ) 1405167514Skmacy#define F_UNSREQ V_UNSREQ(1U) 1406167514Skmacy 1407167514Skmacy#define S_PSNREQ 3 1408167514Skmacy#define V_PSNREQ(x) ((x) << S_PSNREQ) 1409167514Skmacy#define F_PSNREQ V_PSNREQ(1U) 1410167514Skmacy 1411167514Skmacy#define S_UNSCPL 2 1412167514Skmacy#define V_UNSCPL(x) ((x) << S_UNSCPL) 1413167514Skmacy#define F_UNSCPL V_UNSCPL(1U) 1414167514Skmacy 1415167514Skmacy#define S_CPLABT 1 1416167514Skmacy#define V_CPLABT(x) ((x) << S_CPLABT) 1417167514Skmacy#define F_CPLABT V_CPLABT(1U) 1418167514Skmacy 1419167514Skmacy#define S_PSNCPL 0 1420167514Skmacy#define V_PSNCPL(x) ((x) << S_PSNCPL) 1421167514Skmacy#define F_PSNCPL V_PSNCPL(1U) 1422167514Skmacy 1423176472Skmacy#define A_PCIE_SERDES_CTRL 0xa8 1424167514Skmacy 1425176472Skmacy#define S_PMASEL 3 1426176472Skmacy#define V_PMASEL(x) ((x) << S_PMASEL) 1427176472Skmacy#define F_PMASEL V_PMASEL(1U) 1428176472Skmacy 1429176472Skmacy#define S_LANE 0 1430176472Skmacy#define M_LANE 0x7 1431176472Skmacy#define V_LANE(x) ((x) << S_LANE) 1432176472Skmacy#define G_LANE(x) (((x) >> S_LANE) & M_LANE) 1433176472Skmacy 1434167514Skmacy#define A_PCIE_PIPE_CTRL 0xa8 1435167514Skmacy 1436167514Skmacy#define S_RECDETUSEC 19 1437167514Skmacy#define M_RECDETUSEC 0x7 1438167514Skmacy#define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) 1439167514Skmacy#define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) 1440167514Skmacy 1441167514Skmacy#define S_PLLLCKCYC 6 1442167514Skmacy#define M_PLLLCKCYC 0x1fff 1443167514Skmacy#define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC) 1444167514Skmacy#define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC) 1445167514Skmacy 1446167514Skmacy#define S_ELECIDLEDETCYC 3 1447167514Skmacy#define M_ELECIDLEDETCYC 0x7 1448167514Skmacy#define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC) 1449167514Skmacy#define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC) 1450167514Skmacy 1451167514Skmacy#define S_USECDRLOS 2 1452167514Skmacy#define V_USECDRLOS(x) ((x) << S_USECDRLOS) 1453167514Skmacy#define F_USECDRLOS V_USECDRLOS(1U) 1454167514Skmacy 1455167514Skmacy#define S_PCLKREQINP1 1 1456167514Skmacy#define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1) 1457167514Skmacy#define F_PCLKREQINP1 V_PCLKREQINP1(1U) 1458167514Skmacy 1459167514Skmacy#define S_PCLKOFFINP1 0 1460167514Skmacy#define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1) 1461167514Skmacy#define F_PCLKOFFINP1 V_PCLKOFFINP1(1U) 1462167514Skmacy 1463176472Skmacy#define A_PCIE_SERDES_QUAD_CTRL0 0xac 1464167514Skmacy 1465176472Skmacy#define S_TESTSIG 10 1466176472Skmacy#define M_TESTSIG 0x7ffff 1467176472Skmacy#define V_TESTSIG(x) ((x) << S_TESTSIG) 1468176472Skmacy#define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) 1469167514Skmacy 1470176472Skmacy#define S_OFFSET 2 1471176472Skmacy#define M_OFFSET 0xff 1472176472Skmacy#define V_OFFSET(x) ((x) << S_OFFSET) 1473176472Skmacy#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) 1474167514Skmacy 1475176472Skmacy#define S_OFFSETEN 1 1476176472Skmacy#define V_OFFSETEN(x) ((x) << S_OFFSETEN) 1477176472Skmacy#define F_OFFSETEN V_OFFSETEN(1U) 1478176472Skmacy 1479176472Skmacy#define S_IDDQB 0 1480176472Skmacy#define V_IDDQB(x) ((x) << S_IDDQB) 1481176472Skmacy#define F_IDDQB V_IDDQB(1U) 1482176472Skmacy 1483167514Skmacy#define S_MANMODE 31 1484167514Skmacy#define V_MANMODE(x) ((x) << S_MANMODE) 1485167514Skmacy#define F_MANMODE V_MANMODE(1U) 1486167514Skmacy 1487167514Skmacy#define S_MANLPBKEN 29 1488167514Skmacy#define M_MANLPBKEN 0x3 1489167514Skmacy#define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) 1490167514Skmacy#define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) 1491167514Skmacy 1492167514Skmacy#define S_MANTXRECDETEN 28 1493167514Skmacy#define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN) 1494167514Skmacy#define F_MANTXRECDETEN V_MANTXRECDETEN(1U) 1495167514Skmacy 1496167514Skmacy#define S_MANTXBEACON 27 1497167514Skmacy#define V_MANTXBEACON(x) ((x) << S_MANTXBEACON) 1498167514Skmacy#define F_MANTXBEACON V_MANTXBEACON(1U) 1499167514Skmacy 1500167514Skmacy#define S_MANTXEI 26 1501167514Skmacy#define V_MANTXEI(x) ((x) << S_MANTXEI) 1502167514Skmacy#define F_MANTXEI V_MANTXEI(1U) 1503167514Skmacy 1504167514Skmacy#define S_MANRXPOLARITY 25 1505167514Skmacy#define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY) 1506167514Skmacy#define F_MANRXPOLARITY V_MANRXPOLARITY(1U) 1507167514Skmacy 1508167514Skmacy#define S_MANTXRST 24 1509167514Skmacy#define V_MANTXRST(x) ((x) << S_MANTXRST) 1510167514Skmacy#define F_MANTXRST V_MANTXRST(1U) 1511167514Skmacy 1512167514Skmacy#define S_MANRXRST 23 1513167514Skmacy#define V_MANRXRST(x) ((x) << S_MANRXRST) 1514167514Skmacy#define F_MANRXRST V_MANRXRST(1U) 1515167514Skmacy 1516167514Skmacy#define S_MANTXEN 22 1517167514Skmacy#define V_MANTXEN(x) ((x) << S_MANTXEN) 1518167514Skmacy#define F_MANTXEN V_MANTXEN(1U) 1519167514Skmacy 1520167514Skmacy#define S_MANRXEN 21 1521167514Skmacy#define V_MANRXEN(x) ((x) << S_MANRXEN) 1522167514Skmacy#define F_MANRXEN V_MANRXEN(1U) 1523167514Skmacy 1524167514Skmacy#define S_MANEN 20 1525167514Skmacy#define V_MANEN(x) ((x) << S_MANEN) 1526167514Skmacy#define F_MANEN V_MANEN(1U) 1527167514Skmacy 1528167514Skmacy#define S_PCIE_CMURANGE 17 1529167514Skmacy#define M_PCIE_CMURANGE 0x7 1530167514Skmacy#define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE) 1531167514Skmacy#define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE) 1532167514Skmacy 1533167514Skmacy#define S_PCIE_BGENB 16 1534167514Skmacy#define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB) 1535167514Skmacy#define F_PCIE_BGENB V_PCIE_BGENB(1U) 1536167514Skmacy 1537167514Skmacy#define S_PCIE_ENSKPDROP 15 1538167514Skmacy#define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP) 1539167514Skmacy#define F_PCIE_ENSKPDROP V_PCIE_ENSKPDROP(1U) 1540167514Skmacy 1541167514Skmacy#define S_PCIE_ENCOMMA 14 1542167514Skmacy#define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA) 1543167514Skmacy#define F_PCIE_ENCOMMA V_PCIE_ENCOMMA(1U) 1544167514Skmacy 1545167514Skmacy#define S_PCIE_EN8B10B 13 1546167514Skmacy#define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B) 1547167514Skmacy#define F_PCIE_EN8B10B V_PCIE_EN8B10B(1U) 1548167514Skmacy 1549167514Skmacy#define S_PCIE_ENELBUF 12 1550167514Skmacy#define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF) 1551167514Skmacy#define F_PCIE_ENELBUF V_PCIE_ENELBUF(1U) 1552167514Skmacy 1553167514Skmacy#define S_PCIE_GAIN 7 1554167514Skmacy#define M_PCIE_GAIN 0x1f 1555167514Skmacy#define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN) 1556167514Skmacy#define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN) 1557167514Skmacy 1558167514Skmacy#define S_PCIE_BANDGAP 3 1559167514Skmacy#define M_PCIE_BANDGAP 0xf 1560167514Skmacy#define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP) 1561167514Skmacy#define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP) 1562167514Skmacy 1563167514Skmacy#define S_RXCOMADJ 2 1564167514Skmacy#define V_RXCOMADJ(x) ((x) << S_RXCOMADJ) 1565167514Skmacy#define F_RXCOMADJ V_RXCOMADJ(1U) 1566167514Skmacy 1567167514Skmacy#define S_PREEMPH 0 1568167514Skmacy#define M_PREEMPH 0x3 1569167514Skmacy#define V_PREEMPH(x) ((x) << S_PREEMPH) 1570167514Skmacy#define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) 1571167514Skmacy 1572167514Skmacy#define A_PCIE_SERDES_QUAD_CTRL1 0xb0 1573167514Skmacy 1574167514Skmacy#define S_FASTINIT 28 1575167514Skmacy#define V_FASTINIT(x) ((x) << S_FASTINIT) 1576167514Skmacy#define F_FASTINIT V_FASTINIT(1U) 1577167514Skmacy 1578167514Skmacy#define S_CTCDISABLE 27 1579167514Skmacy#define V_CTCDISABLE(x) ((x) << S_CTCDISABLE) 1580167514Skmacy#define F_CTCDISABLE V_CTCDISABLE(1U) 1581167514Skmacy 1582167514Skmacy#define S_MANRESETPLL 26 1583167514Skmacy#define V_MANRESETPLL(x) ((x) << S_MANRESETPLL) 1584167514Skmacy#define F_MANRESETPLL V_MANRESETPLL(1U) 1585167514Skmacy 1586167514Skmacy#define S_MANL2PWRDN 25 1587167514Skmacy#define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN) 1588167514Skmacy#define F_MANL2PWRDN V_MANL2PWRDN(1U) 1589167514Skmacy 1590167514Skmacy#define S_MANQUADEN 24 1591167514Skmacy#define V_MANQUADEN(x) ((x) << S_MANQUADEN) 1592167514Skmacy#define F_MANQUADEN V_MANQUADEN(1U) 1593167514Skmacy 1594167514Skmacy#define S_RXEQCTL 22 1595167514Skmacy#define M_RXEQCTL 0x3 1596167514Skmacy#define V_RXEQCTL(x) ((x) << S_RXEQCTL) 1597167514Skmacy#define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL) 1598167514Skmacy 1599167514Skmacy#define S_HIVMODE 21 1600167514Skmacy#define V_HIVMODE(x) ((x) << S_HIVMODE) 1601167514Skmacy#define F_HIVMODE V_HIVMODE(1U) 1602167514Skmacy 1603167514Skmacy#define S_REFSEL 19 1604167514Skmacy#define M_REFSEL 0x3 1605167514Skmacy#define V_REFSEL(x) ((x) << S_REFSEL) 1606167514Skmacy#define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL) 1607167514Skmacy 1608167514Skmacy#define S_RXTERMADJ 17 1609167514Skmacy#define M_RXTERMADJ 0x3 1610167514Skmacy#define V_RXTERMADJ(x) ((x) << S_RXTERMADJ) 1611167514Skmacy#define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ) 1612167514Skmacy 1613167514Skmacy#define S_TXTERMADJ 15 1614167514Skmacy#define M_TXTERMADJ 0x3 1615167514Skmacy#define V_TXTERMADJ(x) ((x) << S_TXTERMADJ) 1616167514Skmacy#define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ) 1617167514Skmacy 1618167514Skmacy#define S_DEQ 11 1619167514Skmacy#define M_DEQ 0xf 1620167514Skmacy#define V_DEQ(x) ((x) << S_DEQ) 1621167514Skmacy#define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ) 1622167514Skmacy 1623167514Skmacy#define S_DTX 7 1624167514Skmacy#define M_DTX 0xf 1625167514Skmacy#define V_DTX(x) ((x) << S_DTX) 1626167514Skmacy#define G_DTX(x) (((x) >> S_DTX) & M_DTX) 1627167514Skmacy 1628167514Skmacy#define S_LODRV 6 1629167514Skmacy#define V_LODRV(x) ((x) << S_LODRV) 1630167514Skmacy#define F_LODRV V_LODRV(1U) 1631167514Skmacy 1632167514Skmacy#define S_HIDRV 5 1633167514Skmacy#define V_HIDRV(x) ((x) << S_HIDRV) 1634167514Skmacy#define F_HIDRV V_HIDRV(1U) 1635167514Skmacy 1636167514Skmacy#define S_INTPARRESET 4 1637167514Skmacy#define V_INTPARRESET(x) ((x) << S_INTPARRESET) 1638167514Skmacy#define F_INTPARRESET V_INTPARRESET(1U) 1639167514Skmacy 1640167514Skmacy#define S_INTPARLPBK 3 1641167514Skmacy#define V_INTPARLPBK(x) ((x) << S_INTPARLPBK) 1642167514Skmacy#define F_INTPARLPBK V_INTPARLPBK(1U) 1643167514Skmacy 1644167514Skmacy#define S_INTSERLPBKWDRV 2 1645167514Skmacy#define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV) 1646167514Skmacy#define F_INTSERLPBKWDRV V_INTSERLPBKWDRV(1U) 1647167514Skmacy 1648167514Skmacy#define S_PW 1 1649167514Skmacy#define V_PW(x) ((x) << S_PW) 1650167514Skmacy#define F_PW V_PW(1U) 1651167514Skmacy 1652167514Skmacy#define S_PCLKDETECT 0 1653167514Skmacy#define V_PCLKDETECT(x) ((x) << S_PCLKDETECT) 1654167514Skmacy#define F_PCLKDETECT V_PCLKDETECT(1U) 1655167514Skmacy 1656176472Skmacy#define A_PCIE_SERDES_STATUS0 0xb0 1657176472Skmacy 1658176472Skmacy#define S_RXERRLANE7 21 1659176472Skmacy#define M_RXERRLANE7 0x7 1660176472Skmacy#define V_RXERRLANE7(x) ((x) << S_RXERRLANE7) 1661176472Skmacy#define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7) 1662176472Skmacy 1663176472Skmacy#define S_RXERRLANE6 18 1664176472Skmacy#define M_RXERRLANE6 0x7 1665176472Skmacy#define V_RXERRLANE6(x) ((x) << S_RXERRLANE6) 1666176472Skmacy#define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6) 1667176472Skmacy 1668176472Skmacy#define S_RXERRLANE5 15 1669176472Skmacy#define M_RXERRLANE5 0x7 1670176472Skmacy#define V_RXERRLANE5(x) ((x) << S_RXERRLANE5) 1671176472Skmacy#define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5) 1672176472Skmacy 1673176472Skmacy#define S_RXERRLANE4 12 1674176472Skmacy#define M_RXERRLANE4 0x7 1675176472Skmacy#define V_RXERRLANE4(x) ((x) << S_RXERRLANE4) 1676176472Skmacy#define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4) 1677176472Skmacy 1678176472Skmacy#define S_PCIE_RXERRLANE3 9 1679176472Skmacy#define M_PCIE_RXERRLANE3 0x7 1680176472Skmacy#define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3) 1681176472Skmacy#define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3) 1682176472Skmacy 1683176472Skmacy#define S_PCIE_RXERRLANE2 6 1684176472Skmacy#define M_PCIE_RXERRLANE2 0x7 1685176472Skmacy#define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2) 1686176472Skmacy#define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2) 1687176472Skmacy 1688176472Skmacy#define S_PCIE_RXERRLANE1 3 1689176472Skmacy#define M_PCIE_RXERRLANE1 0x7 1690176472Skmacy#define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1) 1691176472Skmacy#define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1) 1692176472Skmacy 1693176472Skmacy#define S_PCIE_RXERRLANE0 0 1694176472Skmacy#define M_PCIE_RXERRLANE0 0x7 1695176472Skmacy#define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0) 1696176472Skmacy#define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0) 1697176472Skmacy 1698176472Skmacy#define A_PCIE_SERDES_LANE_CTRL 0xb4 1699176472Skmacy 1700176472Skmacy#define S_EXTBISTCHKERRCLR 22 1701176472Skmacy#define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR) 1702176472Skmacy#define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U) 1703176472Skmacy 1704176472Skmacy#define S_EXTBISTCHKEN 21 1705176472Skmacy#define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN) 1706176472Skmacy#define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U) 1707176472Skmacy 1708176472Skmacy#define S_EXTBISTGENEN 20 1709176472Skmacy#define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN) 1710176472Skmacy#define F_EXTBISTGENEN V_EXTBISTGENEN(1U) 1711176472Skmacy 1712176472Skmacy#define S_EXTBISTPAT 17 1713176472Skmacy#define M_EXTBISTPAT 0x7 1714176472Skmacy#define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) 1715176472Skmacy#define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) 1716176472Skmacy 1717176472Skmacy#define S_EXTPARRESET 16 1718176472Skmacy#define V_EXTPARRESET(x) ((x) << S_EXTPARRESET) 1719176472Skmacy#define F_EXTPARRESET V_EXTPARRESET(1U) 1720176472Skmacy 1721176472Skmacy#define S_EXTPARLPBK 15 1722176472Skmacy#define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK) 1723176472Skmacy#define F_EXTPARLPBK V_EXTPARLPBK(1U) 1724176472Skmacy 1725176472Skmacy#define S_MANRXTERMEN 14 1726176472Skmacy#define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN) 1727176472Skmacy#define F_MANRXTERMEN V_MANRXTERMEN(1U) 1728176472Skmacy 1729176472Skmacy#define S_MANBEACONTXEN 13 1730176472Skmacy#define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN) 1731176472Skmacy#define F_MANBEACONTXEN V_MANBEACONTXEN(1U) 1732176472Skmacy 1733176472Skmacy#define S_MANRXDETECTEN 12 1734176472Skmacy#define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN) 1735176472Skmacy#define F_MANRXDETECTEN V_MANRXDETECTEN(1U) 1736176472Skmacy 1737176472Skmacy#define S_MANTXIDLEEN 11 1738176472Skmacy#define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN) 1739176472Skmacy#define F_MANTXIDLEEN V_MANTXIDLEEN(1U) 1740176472Skmacy 1741176472Skmacy#define S_MANRXIDLEEN 10 1742176472Skmacy#define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN) 1743176472Skmacy#define F_MANRXIDLEEN V_MANRXIDLEEN(1U) 1744176472Skmacy 1745176472Skmacy#define S_MANL1PWRDN 9 1746176472Skmacy#define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN) 1747176472Skmacy#define F_MANL1PWRDN V_MANL1PWRDN(1U) 1748176472Skmacy 1749176472Skmacy#define S_MANRESET 8 1750176472Skmacy#define V_MANRESET(x) ((x) << S_MANRESET) 1751176472Skmacy#define F_MANRESET V_MANRESET(1U) 1752176472Skmacy 1753176472Skmacy#define S_MANFMOFFSET 3 1754176472Skmacy#define M_MANFMOFFSET 0x1f 1755176472Skmacy#define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) 1756176472Skmacy#define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) 1757176472Skmacy 1758176472Skmacy#define S_MANFMOFFSETEN 2 1759176472Skmacy#define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN) 1760176472Skmacy#define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U) 1761176472Skmacy 1762176472Skmacy#define S_MANLANEEN 1 1763176472Skmacy#define V_MANLANEEN(x) ((x) << S_MANLANEEN) 1764176472Skmacy#define F_MANLANEEN V_MANLANEEN(1U) 1765176472Skmacy 1766176472Skmacy#define S_INTSERLPBK 0 1767176472Skmacy#define V_INTSERLPBK(x) ((x) << S_INTSERLPBK) 1768176472Skmacy#define F_INTSERLPBK V_INTSERLPBK(1U) 1769176472Skmacy 1770167514Skmacy#define A_PCIE_SERDES_STATUS1 0xb4 1771167514Skmacy 1772167514Skmacy#define S_CMULOCK 31 1773167514Skmacy#define V_CMULOCK(x) ((x) << S_CMULOCK) 1774167514Skmacy#define F_CMULOCK V_CMULOCK(1U) 1775167514Skmacy 1776167514Skmacy#define S_RXKLOCKLANE7 23 1777167514Skmacy#define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7) 1778167514Skmacy#define F_RXKLOCKLANE7 V_RXKLOCKLANE7(1U) 1779167514Skmacy 1780167514Skmacy#define S_RXKLOCKLANE6 22 1781167514Skmacy#define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6) 1782167514Skmacy#define F_RXKLOCKLANE6 V_RXKLOCKLANE6(1U) 1783167514Skmacy 1784167514Skmacy#define S_RXKLOCKLANE5 21 1785167514Skmacy#define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5) 1786167514Skmacy#define F_RXKLOCKLANE5 V_RXKLOCKLANE5(1U) 1787167514Skmacy 1788167514Skmacy#define S_RXKLOCKLANE4 20 1789167514Skmacy#define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4) 1790167514Skmacy#define F_RXKLOCKLANE4 V_RXKLOCKLANE4(1U) 1791167514Skmacy 1792167514Skmacy#define S_PCIE_RXKLOCKLANE3 19 1793167514Skmacy#define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3) 1794167514Skmacy#define F_PCIE_RXKLOCKLANE3 V_PCIE_RXKLOCKLANE3(1U) 1795167514Skmacy 1796167514Skmacy#define S_PCIE_RXKLOCKLANE2 18 1797167514Skmacy#define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2) 1798167514Skmacy#define F_PCIE_RXKLOCKLANE2 V_PCIE_RXKLOCKLANE2(1U) 1799167514Skmacy 1800167514Skmacy#define S_PCIE_RXKLOCKLANE1 17 1801167514Skmacy#define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1) 1802167514Skmacy#define F_PCIE_RXKLOCKLANE1 V_PCIE_RXKLOCKLANE1(1U) 1803167514Skmacy 1804167514Skmacy#define S_PCIE_RXKLOCKLANE0 16 1805167514Skmacy#define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0) 1806167514Skmacy#define F_PCIE_RXKLOCKLANE0 V_PCIE_RXKLOCKLANE0(1U) 1807167514Skmacy 1808167514Skmacy#define S_RXUFLOWLANE7 15 1809167514Skmacy#define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7) 1810167514Skmacy#define F_RXUFLOWLANE7 V_RXUFLOWLANE7(1U) 1811167514Skmacy 1812167514Skmacy#define S_RXUFLOWLANE6 14 1813167514Skmacy#define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6) 1814167514Skmacy#define F_RXUFLOWLANE6 V_RXUFLOWLANE6(1U) 1815167514Skmacy 1816167514Skmacy#define S_RXUFLOWLANE5 13 1817167514Skmacy#define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5) 1818167514Skmacy#define F_RXUFLOWLANE5 V_RXUFLOWLANE5(1U) 1819167514Skmacy 1820167514Skmacy#define S_RXUFLOWLANE4 12 1821167514Skmacy#define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4) 1822167514Skmacy#define F_RXUFLOWLANE4 V_RXUFLOWLANE4(1U) 1823167514Skmacy 1824167514Skmacy#define S_PCIE_RXUFLOWLANE3 11 1825167514Skmacy#define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3) 1826167514Skmacy#define F_PCIE_RXUFLOWLANE3 V_PCIE_RXUFLOWLANE3(1U) 1827167514Skmacy 1828167514Skmacy#define S_PCIE_RXUFLOWLANE2 10 1829167514Skmacy#define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2) 1830167514Skmacy#define F_PCIE_RXUFLOWLANE2 V_PCIE_RXUFLOWLANE2(1U) 1831167514Skmacy 1832167514Skmacy#define S_PCIE_RXUFLOWLANE1 9 1833167514Skmacy#define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1) 1834167514Skmacy#define F_PCIE_RXUFLOWLANE1 V_PCIE_RXUFLOWLANE1(1U) 1835167514Skmacy 1836167514Skmacy#define S_PCIE_RXUFLOWLANE0 8 1837167514Skmacy#define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0) 1838167514Skmacy#define F_PCIE_RXUFLOWLANE0 V_PCIE_RXUFLOWLANE0(1U) 1839167514Skmacy 1840167514Skmacy#define S_RXOFLOWLANE7 7 1841167514Skmacy#define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7) 1842167514Skmacy#define F_RXOFLOWLANE7 V_RXOFLOWLANE7(1U) 1843167514Skmacy 1844167514Skmacy#define S_RXOFLOWLANE6 6 1845167514Skmacy#define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6) 1846167514Skmacy#define F_RXOFLOWLANE6 V_RXOFLOWLANE6(1U) 1847167514Skmacy 1848167514Skmacy#define S_RXOFLOWLANE5 5 1849167514Skmacy#define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5) 1850167514Skmacy#define F_RXOFLOWLANE5 V_RXOFLOWLANE5(1U) 1851167514Skmacy 1852167514Skmacy#define S_RXOFLOWLANE4 4 1853167514Skmacy#define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4) 1854167514Skmacy#define F_RXOFLOWLANE4 V_RXOFLOWLANE4(1U) 1855167514Skmacy 1856167514Skmacy#define S_PCIE_RXOFLOWLANE3 3 1857167514Skmacy#define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3) 1858167514Skmacy#define F_PCIE_RXOFLOWLANE3 V_PCIE_RXOFLOWLANE3(1U) 1859167514Skmacy 1860167514Skmacy#define S_PCIE_RXOFLOWLANE2 2 1861167514Skmacy#define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2) 1862167514Skmacy#define F_PCIE_RXOFLOWLANE2 V_PCIE_RXOFLOWLANE2(1U) 1863167514Skmacy 1864167514Skmacy#define S_PCIE_RXOFLOWLANE1 1 1865167514Skmacy#define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1) 1866167514Skmacy#define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U) 1867167514Skmacy 1868167514Skmacy#define S_PCIE_RXOFLOWLANE0 0 1869167514Skmacy#define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0) 1870167514Skmacy#define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U) 1871167514Skmacy 1872176472Skmacy#define A_PCIE_SERDES_LANE_STAT 0xb8 1873167514Skmacy 1874176472Skmacy#define S_EXTBISTCHKERRCNT 8 1875176472Skmacy#define M_EXTBISTCHKERRCNT 0xffffff 1876176472Skmacy#define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) 1877176472Skmacy#define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) 1878167514Skmacy 1879176472Skmacy#define S_EXTBISTCHKFMD 7 1880176472Skmacy#define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD) 1881176472Skmacy#define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U) 1882167514Skmacy 1883176472Skmacy#define S_BEACONDETECTCHG 6 1884176472Skmacy#define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG) 1885176472Skmacy#define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U) 1886167514Skmacy 1887176472Skmacy#define S_RXDETECTCHG 5 1888176472Skmacy#define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG) 1889176472Skmacy#define F_RXDETECTCHG V_RXDETECTCHG(1U) 1890167514Skmacy 1891176472Skmacy#define S_TXIDLEDETECTCHG 4 1892176472Skmacy#define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG) 1893176472Skmacy#define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U) 1894167514Skmacy 1895176472Skmacy#define S_BEACONDETECT 2 1896176472Skmacy#define V_BEACONDETECT(x) ((x) << S_BEACONDETECT) 1897176472Skmacy#define F_BEACONDETECT V_BEACONDETECT(1U) 1898167514Skmacy 1899176472Skmacy#define S_RXDETECT 1 1900176472Skmacy#define V_RXDETECT(x) ((x) << S_RXDETECT) 1901176472Skmacy#define F_RXDETECT V_RXDETECT(1U) 1902167514Skmacy 1903176472Skmacy#define S_TXIDLEDETECT 0 1904176472Skmacy#define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT) 1905176472Skmacy#define F_TXIDLEDETECT V_TXIDLEDETECT(1U) 1906167514Skmacy 1907167514Skmacy#define A_PCIE_SERDES_STATUS2 0xb8 1908167514Skmacy 1909167514Skmacy#define S_TXRECDETLANE7 31 1910167514Skmacy#define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7) 1911167514Skmacy#define F_TXRECDETLANE7 V_TXRECDETLANE7(1U) 1912167514Skmacy 1913167514Skmacy#define S_TXRECDETLANE6 30 1914167514Skmacy#define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6) 1915167514Skmacy#define F_TXRECDETLANE6 V_TXRECDETLANE6(1U) 1916167514Skmacy 1917167514Skmacy#define S_TXRECDETLANE5 29 1918167514Skmacy#define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5) 1919167514Skmacy#define F_TXRECDETLANE5 V_TXRECDETLANE5(1U) 1920167514Skmacy 1921167514Skmacy#define S_TXRECDETLANE4 28 1922167514Skmacy#define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4) 1923167514Skmacy#define F_TXRECDETLANE4 V_TXRECDETLANE4(1U) 1924167514Skmacy 1925167514Skmacy#define S_TXRECDETLANE3 27 1926167514Skmacy#define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3) 1927167514Skmacy#define F_TXRECDETLANE3 V_TXRECDETLANE3(1U) 1928167514Skmacy 1929167514Skmacy#define S_TXRECDETLANE2 26 1930167514Skmacy#define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2) 1931167514Skmacy#define F_TXRECDETLANE2 V_TXRECDETLANE2(1U) 1932167514Skmacy 1933167514Skmacy#define S_TXRECDETLANE1 25 1934167514Skmacy#define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1) 1935167514Skmacy#define F_TXRECDETLANE1 V_TXRECDETLANE1(1U) 1936167514Skmacy 1937167514Skmacy#define S_TXRECDETLANE0 24 1938167514Skmacy#define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0) 1939167514Skmacy#define F_TXRECDETLANE0 V_TXRECDETLANE0(1U) 1940167514Skmacy 1941167514Skmacy#define S_RXEIDLANE7 23 1942167514Skmacy#define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7) 1943167514Skmacy#define F_RXEIDLANE7 V_RXEIDLANE7(1U) 1944167514Skmacy 1945167514Skmacy#define S_RXEIDLANE6 22 1946167514Skmacy#define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6) 1947167514Skmacy#define F_RXEIDLANE6 V_RXEIDLANE6(1U) 1948167514Skmacy 1949167514Skmacy#define S_RXEIDLANE5 21 1950167514Skmacy#define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5) 1951167514Skmacy#define F_RXEIDLANE5 V_RXEIDLANE5(1U) 1952167514Skmacy 1953167514Skmacy#define S_RXEIDLANE4 20 1954167514Skmacy#define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4) 1955167514Skmacy#define F_RXEIDLANE4 V_RXEIDLANE4(1U) 1956167514Skmacy 1957167514Skmacy#define S_RXEIDLANE3 19 1958167514Skmacy#define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3) 1959167514Skmacy#define F_RXEIDLANE3 V_RXEIDLANE3(1U) 1960167514Skmacy 1961167514Skmacy#define S_RXEIDLANE2 18 1962167514Skmacy#define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2) 1963167514Skmacy#define F_RXEIDLANE2 V_RXEIDLANE2(1U) 1964167514Skmacy 1965167514Skmacy#define S_RXEIDLANE1 17 1966167514Skmacy#define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1) 1967167514Skmacy#define F_RXEIDLANE1 V_RXEIDLANE1(1U) 1968167514Skmacy 1969167514Skmacy#define S_RXEIDLANE0 16 1970167514Skmacy#define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0) 1971167514Skmacy#define F_RXEIDLANE0 V_RXEIDLANE0(1U) 1972167514Skmacy 1973167514Skmacy#define S_RXREMSKIPLANE7 15 1974167514Skmacy#define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7) 1975167514Skmacy#define F_RXREMSKIPLANE7 V_RXREMSKIPLANE7(1U) 1976167514Skmacy 1977167514Skmacy#define S_RXREMSKIPLANE6 14 1978167514Skmacy#define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6) 1979167514Skmacy#define F_RXREMSKIPLANE6 V_RXREMSKIPLANE6(1U) 1980167514Skmacy 1981167514Skmacy#define S_RXREMSKIPLANE5 13 1982167514Skmacy#define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5) 1983167514Skmacy#define F_RXREMSKIPLANE5 V_RXREMSKIPLANE5(1U) 1984167514Skmacy 1985167514Skmacy#define S_RXREMSKIPLANE4 12 1986167514Skmacy#define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4) 1987167514Skmacy#define F_RXREMSKIPLANE4 V_RXREMSKIPLANE4(1U) 1988167514Skmacy 1989167514Skmacy#define S_PCIE_RXREMSKIPLANE3 11 1990167514Skmacy#define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3) 1991167514Skmacy#define F_PCIE_RXREMSKIPLANE3 V_PCIE_RXREMSKIPLANE3(1U) 1992167514Skmacy 1993167514Skmacy#define S_PCIE_RXREMSKIPLANE2 10 1994167514Skmacy#define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2) 1995167514Skmacy#define F_PCIE_RXREMSKIPLANE2 V_PCIE_RXREMSKIPLANE2(1U) 1996167514Skmacy 1997167514Skmacy#define S_PCIE_RXREMSKIPLANE1 9 1998167514Skmacy#define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1) 1999167514Skmacy#define F_PCIE_RXREMSKIPLANE1 V_PCIE_RXREMSKIPLANE1(1U) 2000167514Skmacy 2001167514Skmacy#define S_PCIE_RXREMSKIPLANE0 8 2002167514Skmacy#define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0) 2003167514Skmacy#define F_PCIE_RXREMSKIPLANE0 V_PCIE_RXREMSKIPLANE0(1U) 2004167514Skmacy 2005167514Skmacy#define S_RXADDSKIPLANE7 7 2006167514Skmacy#define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7) 2007167514Skmacy#define F_RXADDSKIPLANE7 V_RXADDSKIPLANE7(1U) 2008167514Skmacy 2009167514Skmacy#define S_RXADDSKIPLANE6 6 2010167514Skmacy#define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6) 2011167514Skmacy#define F_RXADDSKIPLANE6 V_RXADDSKIPLANE6(1U) 2012167514Skmacy 2013167514Skmacy#define S_RXADDSKIPLANE5 5 2014167514Skmacy#define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5) 2015167514Skmacy#define F_RXADDSKIPLANE5 V_RXADDSKIPLANE5(1U) 2016167514Skmacy 2017167514Skmacy#define S_RXADDSKIPLANE4 4 2018167514Skmacy#define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4) 2019167514Skmacy#define F_RXADDSKIPLANE4 V_RXADDSKIPLANE4(1U) 2020167514Skmacy 2021167514Skmacy#define S_PCIE_RXADDSKIPLANE3 3 2022167514Skmacy#define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3) 2023167514Skmacy#define F_PCIE_RXADDSKIPLANE3 V_PCIE_RXADDSKIPLANE3(1U) 2024167514Skmacy 2025167514Skmacy#define S_PCIE_RXADDSKIPLANE2 2 2026167514Skmacy#define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2) 2027167514Skmacy#define F_PCIE_RXADDSKIPLANE2 V_PCIE_RXADDSKIPLANE2(1U) 2028167514Skmacy 2029167514Skmacy#define S_PCIE_RXADDSKIPLANE1 1 2030167514Skmacy#define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1) 2031167514Skmacy#define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U) 2032167514Skmacy 2033167514Skmacy#define S_PCIE_RXADDSKIPLANE0 0 2034167514Skmacy#define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0) 2035167514Skmacy#define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U) 2036167514Skmacy 2037176472Skmacy#define A_PCIE_PEX_WMARK 0xbc 2038167514Skmacy 2039176472Skmacy#define S_P_WMARK 18 2040176472Skmacy#define M_P_WMARK 0x7ff 2041176472Skmacy#define V_P_WMARK(x) ((x) << S_P_WMARK) 2042176472Skmacy#define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK) 2043167514Skmacy 2044176472Skmacy#define S_NP_WMARK 11 2045176472Skmacy#define M_NP_WMARK 0x7f 2046176472Skmacy#define V_NP_WMARK(x) ((x) << S_NP_WMARK) 2047176472Skmacy#define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK) 2048167514Skmacy 2049176472Skmacy#define S_CPL_WMARK 0 2050176472Skmacy#define M_CPL_WMARK 0x7ff 2051176472Skmacy#define V_CPL_WMARK(x) ((x) << S_CPL_WMARK) 2052176472Skmacy#define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK) 2053167514Skmacy 2054167514Skmacy#define A_PCIE_SERDES_BIST 0xbc 2055167514Skmacy 2056167514Skmacy#define S_PCIE_BISTDONE 24 2057167514Skmacy#define M_PCIE_BISTDONE 0xff 2058167514Skmacy#define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) 2059167514Skmacy#define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) 2060167514Skmacy 2061167514Skmacy#define S_PCIE_BISTCYCLETHRESH 3 2062167514Skmacy#define M_PCIE_BISTCYCLETHRESH 0xffff 2063167514Skmacy#define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH) 2064167514Skmacy#define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH) 2065167514Skmacy 2066167514Skmacy#define S_BISTMODE 0 2067167514Skmacy#define M_BISTMODE 0x7 2068167514Skmacy#define V_BISTMODE(x) ((x) << S_BISTMODE) 2069167514Skmacy#define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE) 2070167514Skmacy 2071167514Skmacy/* registers for module T3DBG */ 2072167514Skmacy#define T3DBG_BASE_ADDR 0xc0 2073167514Skmacy 2074167514Skmacy#define A_T3DBG_DBG0_CFG 0xc0 2075167514Skmacy 2076167514Skmacy#define S_REGSELECT 9 2077167514Skmacy#define M_REGSELECT 0xff 2078167514Skmacy#define V_REGSELECT(x) ((x) << S_REGSELECT) 2079167514Skmacy#define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT) 2080167514Skmacy 2081167514Skmacy#define S_MODULESELECT 4 2082167514Skmacy#define M_MODULESELECT 0x1f 2083167514Skmacy#define V_MODULESELECT(x) ((x) << S_MODULESELECT) 2084167514Skmacy#define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT) 2085167514Skmacy 2086167514Skmacy#define S_CLKSELECT 0 2087167514Skmacy#define M_CLKSELECT 0xf 2088167514Skmacy#define V_CLKSELECT(x) ((x) << S_CLKSELECT) 2089167514Skmacy#define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT) 2090167514Skmacy 2091167514Skmacy#define A_T3DBG_DBG0_EN 0xc4 2092167514Skmacy 2093167514Skmacy#define S_SDRBYTE0 8 2094167514Skmacy#define V_SDRBYTE0(x) ((x) << S_SDRBYTE0) 2095167514Skmacy#define F_SDRBYTE0 V_SDRBYTE0(1U) 2096167514Skmacy 2097167514Skmacy#define S_DDREN 4 2098167514Skmacy#define V_DDREN(x) ((x) << S_DDREN) 2099167514Skmacy#define F_DDREN V_DDREN(1U) 2100167514Skmacy 2101167514Skmacy#define S_PORTEN 0 2102167514Skmacy#define V_PORTEN(x) ((x) << S_PORTEN) 2103167514Skmacy#define F_PORTEN V_PORTEN(1U) 2104167514Skmacy 2105167514Skmacy#define A_T3DBG_DBG1_CFG 0xc8 2106167514Skmacy#define A_T3DBG_DBG1_EN 0xcc 2107167514Skmacy#define A_T3DBG_GPIO_EN 0xd0 2108167514Skmacy 2109167514Skmacy#define S_GPIO11_OEN 27 2110167514Skmacy#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN) 2111167514Skmacy#define F_GPIO11_OEN V_GPIO11_OEN(1U) 2112167514Skmacy 2113167514Skmacy#define S_GPIO10_OEN 26 2114167514Skmacy#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) 2115167514Skmacy#define F_GPIO10_OEN V_GPIO10_OEN(1U) 2116167514Skmacy 2117167514Skmacy#define S_GPIO9_OEN 25 2118167514Skmacy#define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN) 2119167514Skmacy#define F_GPIO9_OEN V_GPIO9_OEN(1U) 2120167514Skmacy 2121167514Skmacy#define S_GPIO8_OEN 24 2122167514Skmacy#define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN) 2123167514Skmacy#define F_GPIO8_OEN V_GPIO8_OEN(1U) 2124167514Skmacy 2125167514Skmacy#define S_GPIO7_OEN 23 2126167514Skmacy#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) 2127167514Skmacy#define F_GPIO7_OEN V_GPIO7_OEN(1U) 2128167514Skmacy 2129167514Skmacy#define S_GPIO6_OEN 22 2130167514Skmacy#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN) 2131167514Skmacy#define F_GPIO6_OEN V_GPIO6_OEN(1U) 2132167514Skmacy 2133167514Skmacy#define S_GPIO5_OEN 21 2134167514Skmacy#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN) 2135167514Skmacy#define F_GPIO5_OEN V_GPIO5_OEN(1U) 2136167514Skmacy 2137167514Skmacy#define S_GPIO4_OEN 20 2138167514Skmacy#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) 2139167514Skmacy#define F_GPIO4_OEN V_GPIO4_OEN(1U) 2140167514Skmacy 2141167514Skmacy#define S_GPIO3_OEN 19 2142167514Skmacy#define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN) 2143167514Skmacy#define F_GPIO3_OEN V_GPIO3_OEN(1U) 2144167514Skmacy 2145167514Skmacy#define S_GPIO2_OEN 18 2146167514Skmacy#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) 2147167514Skmacy#define F_GPIO2_OEN V_GPIO2_OEN(1U) 2148167514Skmacy 2149167514Skmacy#define S_GPIO1_OEN 17 2150167514Skmacy#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN) 2151167514Skmacy#define F_GPIO1_OEN V_GPIO1_OEN(1U) 2152167514Skmacy 2153167514Skmacy#define S_GPIO0_OEN 16 2154167514Skmacy#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) 2155167514Skmacy#define F_GPIO0_OEN V_GPIO0_OEN(1U) 2156167514Skmacy 2157167514Skmacy#define S_GPIO11_OUT_VAL 11 2158167514Skmacy#define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL) 2159167514Skmacy#define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U) 2160167514Skmacy 2161167514Skmacy#define S_GPIO10_OUT_VAL 10 2162167514Skmacy#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) 2163167514Skmacy#define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) 2164167514Skmacy 2165167514Skmacy#define S_GPIO9_OUT_VAL 9 2166167514Skmacy#define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL) 2167167514Skmacy#define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U) 2168167514Skmacy 2169167514Skmacy#define S_GPIO8_OUT_VAL 8 2170167514Skmacy#define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL) 2171167514Skmacy#define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U) 2172167514Skmacy 2173167514Skmacy#define S_GPIO7_OUT_VAL 7 2174167514Skmacy#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) 2175167514Skmacy#define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) 2176167514Skmacy 2177167514Skmacy#define S_GPIO6_OUT_VAL 6 2178167514Skmacy#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL) 2179167514Skmacy#define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U) 2180167514Skmacy 2181167514Skmacy#define S_GPIO5_OUT_VAL 5 2182167514Skmacy#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL) 2183167514Skmacy#define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U) 2184167514Skmacy 2185167514Skmacy#define S_GPIO4_OUT_VAL 4 2186167514Skmacy#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) 2187167514Skmacy#define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) 2188167514Skmacy 2189167514Skmacy#define S_GPIO3_OUT_VAL 3 2190167514Skmacy#define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL) 2191167514Skmacy#define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U) 2192167514Skmacy 2193167514Skmacy#define S_GPIO2_OUT_VAL 2 2194167514Skmacy#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) 2195167514Skmacy#define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) 2196167514Skmacy 2197167514Skmacy#define S_GPIO1_OUT_VAL 1 2198167514Skmacy#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL) 2199167514Skmacy#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 2200167514Skmacy 2201167514Skmacy#define S_GPIO0_OUT_VAL 0 2202167514Skmacy#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 2203167514Skmacy#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 2204167514Skmacy 2205167514Skmacy#define A_T3DBG_GPIO_IN 0xd4 2206167514Skmacy 2207176472Skmacy#define S_GPIO11_CHG_DET 27 2208176472Skmacy#define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET) 2209176472Skmacy#define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U) 2210176472Skmacy 2211176472Skmacy#define S_GPIO10_CHG_DET 26 2212176472Skmacy#define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET) 2213176472Skmacy#define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U) 2214176472Skmacy 2215176472Skmacy#define S_GPIO9_CHG_DET 25 2216176472Skmacy#define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET) 2217176472Skmacy#define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U) 2218176472Skmacy 2219176472Skmacy#define S_GPIO8_CHG_DET 24 2220176472Skmacy#define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET) 2221176472Skmacy#define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U) 2222176472Skmacy 2223176472Skmacy#define S_GPIO7_CHG_DET 23 2224176472Skmacy#define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET) 2225176472Skmacy#define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U) 2226176472Skmacy 2227176472Skmacy#define S_GPIO6_CHG_DET 22 2228176472Skmacy#define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET) 2229176472Skmacy#define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U) 2230176472Skmacy 2231176472Skmacy#define S_GPIO5_CHG_DET 21 2232176472Skmacy#define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET) 2233176472Skmacy#define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U) 2234176472Skmacy 2235176472Skmacy#define S_GPIO4_CHG_DET 20 2236176472Skmacy#define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET) 2237176472Skmacy#define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U) 2238176472Skmacy 2239176472Skmacy#define S_GPIO3_CHG_DET 19 2240176472Skmacy#define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET) 2241176472Skmacy#define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U) 2242176472Skmacy 2243176472Skmacy#define S_GPIO2_CHG_DET 18 2244176472Skmacy#define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET) 2245176472Skmacy#define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U) 2246176472Skmacy 2247176472Skmacy#define S_GPIO1_CHG_DET 17 2248176472Skmacy#define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET) 2249176472Skmacy#define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U) 2250176472Skmacy 2251176472Skmacy#define S_GPIO0_CHG_DET 16 2252176472Skmacy#define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET) 2253176472Skmacy#define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U) 2254176472Skmacy 2255167514Skmacy#define S_GPIO11_IN 11 2256167514Skmacy#define V_GPIO11_IN(x) ((x) << S_GPIO11_IN) 2257167514Skmacy#define F_GPIO11_IN V_GPIO11_IN(1U) 2258167514Skmacy 2259167514Skmacy#define S_GPIO10_IN 10 2260167514Skmacy#define V_GPIO10_IN(x) ((x) << S_GPIO10_IN) 2261167514Skmacy#define F_GPIO10_IN V_GPIO10_IN(1U) 2262167514Skmacy 2263167514Skmacy#define S_GPIO9_IN 9 2264167514Skmacy#define V_GPIO9_IN(x) ((x) << S_GPIO9_IN) 2265167514Skmacy#define F_GPIO9_IN V_GPIO9_IN(1U) 2266167514Skmacy 2267167514Skmacy#define S_GPIO8_IN 8 2268167514Skmacy#define V_GPIO8_IN(x) ((x) << S_GPIO8_IN) 2269167514Skmacy#define F_GPIO8_IN V_GPIO8_IN(1U) 2270167514Skmacy 2271167514Skmacy#define S_GPIO7_IN 7 2272167514Skmacy#define V_GPIO7_IN(x) ((x) << S_GPIO7_IN) 2273167514Skmacy#define F_GPIO7_IN V_GPIO7_IN(1U) 2274167514Skmacy 2275167514Skmacy#define S_GPIO6_IN 6 2276167514Skmacy#define V_GPIO6_IN(x) ((x) << S_GPIO6_IN) 2277167514Skmacy#define F_GPIO6_IN V_GPIO6_IN(1U) 2278167514Skmacy 2279167514Skmacy#define S_GPIO5_IN 5 2280167514Skmacy#define V_GPIO5_IN(x) ((x) << S_GPIO5_IN) 2281167514Skmacy#define F_GPIO5_IN V_GPIO5_IN(1U) 2282167514Skmacy 2283167514Skmacy#define S_GPIO4_IN 4 2284167514Skmacy#define V_GPIO4_IN(x) ((x) << S_GPIO4_IN) 2285167514Skmacy#define F_GPIO4_IN V_GPIO4_IN(1U) 2286167514Skmacy 2287167514Skmacy#define S_GPIO3_IN 3 2288167514Skmacy#define V_GPIO3_IN(x) ((x) << S_GPIO3_IN) 2289167514Skmacy#define F_GPIO3_IN V_GPIO3_IN(1U) 2290167514Skmacy 2291167514Skmacy#define S_GPIO2_IN 2 2292167514Skmacy#define V_GPIO2_IN(x) ((x) << S_GPIO2_IN) 2293167514Skmacy#define F_GPIO2_IN V_GPIO2_IN(1U) 2294167514Skmacy 2295167514Skmacy#define S_GPIO1_IN 1 2296167514Skmacy#define V_GPIO1_IN(x) ((x) << S_GPIO1_IN) 2297167514Skmacy#define F_GPIO1_IN V_GPIO1_IN(1U) 2298167514Skmacy 2299167514Skmacy#define S_GPIO0_IN 0 2300167514Skmacy#define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) 2301167514Skmacy#define F_GPIO0_IN V_GPIO0_IN(1U) 2302167514Skmacy 2303167514Skmacy#define A_T3DBG_INT_ENABLE 0xd8 2304167514Skmacy 2305167514Skmacy#define S_C_LOCK 21 2306167514Skmacy#define V_C_LOCK(x) ((x) << S_C_LOCK) 2307167514Skmacy#define F_C_LOCK V_C_LOCK(1U) 2308167514Skmacy 2309167514Skmacy#define S_M_LOCK 20 2310167514Skmacy#define V_M_LOCK(x) ((x) << S_M_LOCK) 2311167514Skmacy#define F_M_LOCK V_M_LOCK(1U) 2312167514Skmacy 2313167514Skmacy#define S_U_LOCK 19 2314167514Skmacy#define V_U_LOCK(x) ((x) << S_U_LOCK) 2315167514Skmacy#define F_U_LOCK V_U_LOCK(1U) 2316167514Skmacy 2317167514Skmacy#define S_R_LOCK 18 2318167514Skmacy#define V_R_LOCK(x) ((x) << S_R_LOCK) 2319167514Skmacy#define F_R_LOCK V_R_LOCK(1U) 2320167514Skmacy 2321167514Skmacy#define S_PX_LOCK 17 2322167514Skmacy#define V_PX_LOCK(x) ((x) << S_PX_LOCK) 2323167514Skmacy#define F_PX_LOCK V_PX_LOCK(1U) 2324167514Skmacy 2325167514Skmacy#define S_GPIO11 11 2326167514Skmacy#define V_GPIO11(x) ((x) << S_GPIO11) 2327167514Skmacy#define F_GPIO11 V_GPIO11(1U) 2328167514Skmacy 2329167514Skmacy#define S_GPIO10 10 2330167514Skmacy#define V_GPIO10(x) ((x) << S_GPIO10) 2331167514Skmacy#define F_GPIO10 V_GPIO10(1U) 2332167514Skmacy 2333167514Skmacy#define S_GPIO9 9 2334167514Skmacy#define V_GPIO9(x) ((x) << S_GPIO9) 2335167514Skmacy#define F_GPIO9 V_GPIO9(1U) 2336167514Skmacy 2337167514Skmacy#define S_GPIO8 8 2338167514Skmacy#define V_GPIO8(x) ((x) << S_GPIO8) 2339167514Skmacy#define F_GPIO8 V_GPIO8(1U) 2340167514Skmacy 2341167514Skmacy#define S_GPIO7 7 2342167514Skmacy#define V_GPIO7(x) ((x) << S_GPIO7) 2343167514Skmacy#define F_GPIO7 V_GPIO7(1U) 2344167514Skmacy 2345167514Skmacy#define S_GPIO6 6 2346167514Skmacy#define V_GPIO6(x) ((x) << S_GPIO6) 2347167514Skmacy#define F_GPIO6 V_GPIO6(1U) 2348167514Skmacy 2349167514Skmacy#define S_GPIO5 5 2350167514Skmacy#define V_GPIO5(x) ((x) << S_GPIO5) 2351167514Skmacy#define F_GPIO5 V_GPIO5(1U) 2352167514Skmacy 2353167514Skmacy#define S_GPIO4 4 2354167514Skmacy#define V_GPIO4(x) ((x) << S_GPIO4) 2355167514Skmacy#define F_GPIO4 V_GPIO4(1U) 2356167514Skmacy 2357167514Skmacy#define S_GPIO3 3 2358167514Skmacy#define V_GPIO3(x) ((x) << S_GPIO3) 2359167514Skmacy#define F_GPIO3 V_GPIO3(1U) 2360167514Skmacy 2361167514Skmacy#define S_GPIO2 2 2362167514Skmacy#define V_GPIO2(x) ((x) << S_GPIO2) 2363167514Skmacy#define F_GPIO2 V_GPIO2(1U) 2364167514Skmacy 2365167514Skmacy#define S_GPIO1 1 2366167514Skmacy#define V_GPIO1(x) ((x) << S_GPIO1) 2367167514Skmacy#define F_GPIO1 V_GPIO1(1U) 2368167514Skmacy 2369167514Skmacy#define S_GPIO0 0 2370167514Skmacy#define V_GPIO0(x) ((x) << S_GPIO0) 2371167514Skmacy#define F_GPIO0 V_GPIO0(1U) 2372167514Skmacy 2373176472Skmacy#define S_PE_LOCK 16 2374176472Skmacy#define V_PE_LOCK(x) ((x) << S_PE_LOCK) 2375176472Skmacy#define F_PE_LOCK V_PE_LOCK(1U) 2376176472Skmacy 2377167514Skmacy#define A_T3DBG_INT_CAUSE 0xdc 2378167514Skmacy#define A_T3DBG_DBG0_RST_VALUE 0xe0 2379167514Skmacy 2380167514Skmacy#define S_DEBUGDATA 0 2381176472Skmacy#define M_DEBUGDATA 0xff 2382167514Skmacy#define V_DEBUGDATA(x) ((x) << S_DEBUGDATA) 2383176472Skmacy#define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA) 2384167514Skmacy 2385167514Skmacy#define A_T3DBG_PLL_OCLK_PAD_EN 0xe4 2386167514Skmacy 2387167514Skmacy#define S_PCIE_OCLK_EN 20 2388167514Skmacy#define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN) 2389167514Skmacy#define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U) 2390167514Skmacy 2391176472Skmacy#define S_PCLKTREE_DBG_EN 17 2392176472Skmacy#define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN) 2393176472Skmacy#define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U) 2394176472Skmacy 2395167514Skmacy#define S_PCIX_OCLK_EN 16 2396167514Skmacy#define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN) 2397167514Skmacy#define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U) 2398167514Skmacy 2399167514Skmacy#define S_U_OCLK_EN 12 2400167514Skmacy#define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN) 2401167514Skmacy#define F_U_OCLK_EN V_U_OCLK_EN(1U) 2402167514Skmacy 2403167514Skmacy#define S_R_OCLK_EN 8 2404167514Skmacy#define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN) 2405167514Skmacy#define F_R_OCLK_EN V_R_OCLK_EN(1U) 2406167514Skmacy 2407167514Skmacy#define S_M_OCLK_EN 4 2408167514Skmacy#define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN) 2409167514Skmacy#define F_M_OCLK_EN V_M_OCLK_EN(1U) 2410167514Skmacy 2411167514Skmacy#define S_C_OCLK_EN 0 2412167514Skmacy#define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) 2413167514Skmacy#define F_C_OCLK_EN V_C_OCLK_EN(1U) 2414167514Skmacy 2415167514Skmacy#define A_T3DBG_PLL_LOCK 0xe8 2416167514Skmacy 2417167514Skmacy#define S_PCIX_LOCK 16 2418167514Skmacy#define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK) 2419167514Skmacy#define F_PCIX_LOCK V_PCIX_LOCK(1U) 2420167514Skmacy 2421167514Skmacy#define S_PLL_U_LOCK 12 2422167514Skmacy#define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK) 2423167514Skmacy#define F_PLL_U_LOCK V_PLL_U_LOCK(1U) 2424167514Skmacy 2425167514Skmacy#define S_PLL_R_LOCK 8 2426167514Skmacy#define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK) 2427167514Skmacy#define F_PLL_R_LOCK V_PLL_R_LOCK(1U) 2428167514Skmacy 2429167514Skmacy#define S_PLL_M_LOCK 4 2430167514Skmacy#define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK) 2431167514Skmacy#define F_PLL_M_LOCK V_PLL_M_LOCK(1U) 2432167514Skmacy 2433167514Skmacy#define S_PLL_C_LOCK 0 2434167514Skmacy#define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) 2435167514Skmacy#define F_PLL_C_LOCK V_PLL_C_LOCK(1U) 2436167514Skmacy 2437176472Skmacy#define S_PCIE_LOCK 20 2438176472Skmacy#define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK) 2439176472Skmacy#define F_PCIE_LOCK V_PCIE_LOCK(1U) 2440176472Skmacy 2441167514Skmacy#define A_T3DBG_SERDES_RBC_CFG 0xec 2442167514Skmacy 2443167514Skmacy#define S_X_RBC_LANE_SEL 16 2444176472Skmacy#define M_X_RBC_LANE_SEL 0x3 2445167514Skmacy#define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) 2446176472Skmacy#define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL) 2447167514Skmacy 2448167514Skmacy#define S_X_RBC_DBG_EN 12 2449167514Skmacy#define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN) 2450167514Skmacy#define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U) 2451167514Skmacy 2452167514Skmacy#define S_X_SERDES_SEL 8 2453167514Skmacy#define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL) 2454167514Skmacy#define F_X_SERDES_SEL V_X_SERDES_SEL(1U) 2455167514Skmacy 2456167514Skmacy#define S_PE_RBC_LANE_SEL 4 2457176472Skmacy#define M_PE_RBC_LANE_SEL 0x7 2458167514Skmacy#define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) 2459176472Skmacy#define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL) 2460167514Skmacy 2461167514Skmacy#define S_PE_RBC_DBG_EN 0 2462167514Skmacy#define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN) 2463167514Skmacy#define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U) 2464167514Skmacy 2465167514Skmacy#define A_T3DBG_GPIO_ACT_LOW 0xf0 2466167514Skmacy 2467167514Skmacy#define S_C_LOCK_ACT_LOW 21 2468167514Skmacy#define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW) 2469167514Skmacy#define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U) 2470167514Skmacy 2471167514Skmacy#define S_M_LOCK_ACT_LOW 20 2472167514Skmacy#define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW) 2473167514Skmacy#define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U) 2474167514Skmacy 2475167514Skmacy#define S_U_LOCK_ACT_LOW 19 2476167514Skmacy#define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW) 2477167514Skmacy#define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U) 2478167514Skmacy 2479167514Skmacy#define S_R_LOCK_ACT_LOW 18 2480167514Skmacy#define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW) 2481167514Skmacy#define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U) 2482167514Skmacy 2483167514Skmacy#define S_PX_LOCK_ACT_LOW 17 2484167514Skmacy#define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW) 2485167514Skmacy#define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U) 2486167514Skmacy 2487167514Skmacy#define S_GPIO11_ACT_LOW 11 2488167514Skmacy#define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW) 2489167514Skmacy#define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U) 2490167514Skmacy 2491167514Skmacy#define S_GPIO10_ACT_LOW 10 2492167514Skmacy#define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW) 2493167514Skmacy#define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U) 2494167514Skmacy 2495167514Skmacy#define S_GPIO9_ACT_LOW 9 2496167514Skmacy#define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW) 2497167514Skmacy#define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U) 2498167514Skmacy 2499167514Skmacy#define S_GPIO8_ACT_LOW 8 2500167514Skmacy#define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW) 2501167514Skmacy#define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U) 2502167514Skmacy 2503167514Skmacy#define S_GPIO7_ACT_LOW 7 2504167514Skmacy#define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW) 2505167514Skmacy#define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U) 2506167514Skmacy 2507167514Skmacy#define S_GPIO6_ACT_LOW 6 2508167514Skmacy#define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW) 2509167514Skmacy#define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U) 2510167514Skmacy 2511167514Skmacy#define S_GPIO5_ACT_LOW 5 2512167514Skmacy#define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW) 2513167514Skmacy#define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U) 2514167514Skmacy 2515167514Skmacy#define S_GPIO4_ACT_LOW 4 2516167514Skmacy#define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW) 2517167514Skmacy#define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U) 2518167514Skmacy 2519167514Skmacy#define S_GPIO3_ACT_LOW 3 2520167514Skmacy#define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW) 2521167514Skmacy#define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U) 2522167514Skmacy 2523167514Skmacy#define S_GPIO2_ACT_LOW 2 2524167514Skmacy#define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW) 2525167514Skmacy#define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U) 2526167514Skmacy 2527167514Skmacy#define S_GPIO1_ACT_LOW 1 2528167514Skmacy#define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW) 2529167514Skmacy#define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U) 2530167514Skmacy 2531167514Skmacy#define S_GPIO0_ACT_LOW 0 2532167514Skmacy#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) 2533167514Skmacy#define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) 2534167514Skmacy 2535176472Skmacy#define S_PE_LOCK_ACT_LOW 16 2536176472Skmacy#define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW) 2537176472Skmacy#define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U) 2538176472Skmacy 2539167514Skmacy#define A_T3DBG_PMON_CFG 0xf4 2540167514Skmacy 2541167514Skmacy#define S_PMON_DONE 29 2542167514Skmacy#define V_PMON_DONE(x) ((x) << S_PMON_DONE) 2543167514Skmacy#define F_PMON_DONE V_PMON_DONE(1U) 2544167514Skmacy 2545167514Skmacy#define S_PMON_FAIL 28 2546167514Skmacy#define V_PMON_FAIL(x) ((x) << S_PMON_FAIL) 2547167514Skmacy#define F_PMON_FAIL V_PMON_FAIL(1U) 2548167514Skmacy 2549167514Skmacy#define S_PMON_FDEL_AUTO 22 2550176472Skmacy#define M_PMON_FDEL_AUTO 0x3f 2551167514Skmacy#define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) 2552176472Skmacy#define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO) 2553167514Skmacy 2554167514Skmacy#define S_PMON_CDEL_AUTO 16 2555176472Skmacy#define M_PMON_CDEL_AUTO 0x3f 2556167514Skmacy#define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) 2557176472Skmacy#define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO) 2558167514Skmacy 2559167514Skmacy#define S_PMON_FDEL_MANUAL 10 2560176472Skmacy#define M_PMON_FDEL_MANUAL 0x3f 2561167514Skmacy#define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) 2562176472Skmacy#define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL) 2563167514Skmacy 2564167514Skmacy#define S_PMON_CDEL_MANUAL 4 2565176472Skmacy#define M_PMON_CDEL_MANUAL 0x3f 2566167514Skmacy#define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) 2567176472Skmacy#define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL) 2568167514Skmacy 2569167514Skmacy#define S_PMON_MANUAL 1 2570167514Skmacy#define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL) 2571167514Skmacy#define F_PMON_MANUAL V_PMON_MANUAL(1U) 2572167514Skmacy 2573167514Skmacy#define S_PMON_AUTO 0 2574167514Skmacy#define V_PMON_AUTO(x) ((x) << S_PMON_AUTO) 2575167514Skmacy#define F_PMON_AUTO V_PMON_AUTO(1U) 2576167514Skmacy 2577167514Skmacy#define A_T3DBG_SERDES_REFCLK_CFG 0xf8 2578167514Skmacy 2579167514Skmacy#define S_PE_REFCLK_DBG_EN 12 2580167514Skmacy#define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN) 2581167514Skmacy#define F_PE_REFCLK_DBG_EN V_PE_REFCLK_DBG_EN(1U) 2582167514Skmacy 2583167514Skmacy#define S_X_REFCLK_DBG_EN 8 2584167514Skmacy#define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN) 2585167514Skmacy#define F_X_REFCLK_DBG_EN V_X_REFCLK_DBG_EN(1U) 2586167514Skmacy 2587167514Skmacy#define S_PE_REFCLK_TERMADJ 5 2588167514Skmacy#define M_PE_REFCLK_TERMADJ 0x3 2589167514Skmacy#define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ) 2590167514Skmacy#define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ) 2591167514Skmacy 2592167514Skmacy#define S_PE_REFCLK_PD 4 2593167514Skmacy#define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD) 2594167514Skmacy#define F_PE_REFCLK_PD V_PE_REFCLK_PD(1U) 2595167514Skmacy 2596167514Skmacy#define S_X_REFCLK_TERMADJ 1 2597167514Skmacy#define M_X_REFCLK_TERMADJ 0x3 2598167514Skmacy#define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ) 2599167514Skmacy#define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ) 2600167514Skmacy 2601167514Skmacy#define S_X_REFCLK_PD 0 2602167514Skmacy#define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD) 2603167514Skmacy#define F_X_REFCLK_PD V_X_REFCLK_PD(1U) 2604167514Skmacy 2605167514Skmacy#define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc 2606167514Skmacy 2607167514Skmacy#define S_BSMODEQUAD1 31 2608167514Skmacy#define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1) 2609167514Skmacy#define F_BSMODEQUAD1 V_BSMODEQUAD1(1U) 2610167514Skmacy 2611167514Skmacy#define S_BSINSELLANE7 29 2612167514Skmacy#define M_BSINSELLANE7 0x3 2613167514Skmacy#define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7) 2614167514Skmacy#define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7) 2615167514Skmacy 2616167514Skmacy#define S_BSENLANE7 28 2617167514Skmacy#define V_BSENLANE7(x) ((x) << S_BSENLANE7) 2618167514Skmacy#define F_BSENLANE7 V_BSENLANE7(1U) 2619167514Skmacy 2620167514Skmacy#define S_BSINSELLANE6 25 2621167514Skmacy#define M_BSINSELLANE6 0x3 2622167514Skmacy#define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6) 2623167514Skmacy#define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6) 2624167514Skmacy 2625167514Skmacy#define S_BSENLANE6 24 2626167514Skmacy#define V_BSENLANE6(x) ((x) << S_BSENLANE6) 2627167514Skmacy#define F_BSENLANE6 V_BSENLANE6(1U) 2628167514Skmacy 2629167514Skmacy#define S_BSINSELLANE5 21 2630167514Skmacy#define M_BSINSELLANE5 0x3 2631167514Skmacy#define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5) 2632167514Skmacy#define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5) 2633167514Skmacy 2634167514Skmacy#define S_BSENLANE5 20 2635167514Skmacy#define V_BSENLANE5(x) ((x) << S_BSENLANE5) 2636167514Skmacy#define F_BSENLANE5 V_BSENLANE5(1U) 2637167514Skmacy 2638167514Skmacy#define S_BSINSELLANE4 17 2639167514Skmacy#define M_BSINSELLANE4 0x3 2640167514Skmacy#define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4) 2641167514Skmacy#define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4) 2642167514Skmacy 2643167514Skmacy#define S_BSENLANE4 16 2644167514Skmacy#define V_BSENLANE4(x) ((x) << S_BSENLANE4) 2645167514Skmacy#define F_BSENLANE4 V_BSENLANE4(1U) 2646167514Skmacy 2647167514Skmacy#define S_BSMODEQUAD0 15 2648167514Skmacy#define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0) 2649167514Skmacy#define F_BSMODEQUAD0 V_BSMODEQUAD0(1U) 2650167514Skmacy 2651167514Skmacy#define S_BSINSELLANE3 13 2652167514Skmacy#define M_BSINSELLANE3 0x3 2653167514Skmacy#define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3) 2654167514Skmacy#define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3) 2655167514Skmacy 2656167514Skmacy#define S_BSENLANE3 12 2657167514Skmacy#define V_BSENLANE3(x) ((x) << S_BSENLANE3) 2658167514Skmacy#define F_BSENLANE3 V_BSENLANE3(1U) 2659167514Skmacy 2660167514Skmacy#define S_BSINSELLANE2 9 2661167514Skmacy#define M_BSINSELLANE2 0x3 2662167514Skmacy#define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2) 2663167514Skmacy#define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2) 2664167514Skmacy 2665167514Skmacy#define S_BSENLANE2 8 2666167514Skmacy#define V_BSENLANE2(x) ((x) << S_BSENLANE2) 2667167514Skmacy#define F_BSENLANE2 V_BSENLANE2(1U) 2668167514Skmacy 2669167514Skmacy#define S_BSINSELLANE1 5 2670167514Skmacy#define M_BSINSELLANE1 0x3 2671167514Skmacy#define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1) 2672167514Skmacy#define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1) 2673167514Skmacy 2674167514Skmacy#define S_BSENLANE1 4 2675167514Skmacy#define V_BSENLANE1(x) ((x) << S_BSENLANE1) 2676167514Skmacy#define F_BSENLANE1 V_BSENLANE1(1U) 2677167514Skmacy 2678167514Skmacy#define S_BSINSELLANE0 1 2679167514Skmacy#define M_BSINSELLANE0 0x3 2680167514Skmacy#define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0) 2681167514Skmacy#define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0) 2682167514Skmacy 2683167514Skmacy#define S_BSENLANE0 0 2684167514Skmacy#define V_BSENLANE0(x) ((x) << S_BSENLANE0) 2685167514Skmacy#define F_BSENLANE0 V_BSENLANE0(1U) 2686167514Skmacy 2687167514Skmacy/* registers for module MC7_PMRX */ 2688167514Skmacy#define MC7_PMRX_BASE_ADDR 0x100 2689167514Skmacy 2690167514Skmacy#define A_MC7_CFG 0x100 2691167514Skmacy 2692167514Skmacy#define S_IMPSETUPDATE 14 2693167514Skmacy#define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE) 2694167514Skmacy#define F_IMPSETUPDATE V_IMPSETUPDATE(1U) 2695167514Skmacy 2696167514Skmacy#define S_IFEN 13 2697167514Skmacy#define V_IFEN(x) ((x) << S_IFEN) 2698167514Skmacy#define F_IFEN V_IFEN(1U) 2699167514Skmacy 2700167514Skmacy#define S_TERM300 12 2701167514Skmacy#define V_TERM300(x) ((x) << S_TERM300) 2702167514Skmacy#define F_TERM300 V_TERM300(1U) 2703167514Skmacy 2704167514Skmacy#define S_TERM150 11 2705167514Skmacy#define V_TERM150(x) ((x) << S_TERM150) 2706167514Skmacy#define F_TERM150 V_TERM150(1U) 2707167514Skmacy 2708167514Skmacy#define S_SLOW 10 2709167514Skmacy#define V_SLOW(x) ((x) << S_SLOW) 2710167514Skmacy#define F_SLOW V_SLOW(1U) 2711167514Skmacy 2712167514Skmacy#define S_WIDTH 8 2713167514Skmacy#define M_WIDTH 0x3 2714167514Skmacy#define V_WIDTH(x) ((x) << S_WIDTH) 2715167514Skmacy#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH) 2716167514Skmacy 2717167514Skmacy#define S_ODTEN 7 2718167514Skmacy#define V_ODTEN(x) ((x) << S_ODTEN) 2719167514Skmacy#define F_ODTEN V_ODTEN(1U) 2720167514Skmacy 2721167514Skmacy#define S_BKS 6 2722167514Skmacy#define V_BKS(x) ((x) << S_BKS) 2723167514Skmacy#define F_BKS V_BKS(1U) 2724167514Skmacy 2725167514Skmacy#define S_ORG 5 2726167514Skmacy#define V_ORG(x) ((x) << S_ORG) 2727167514Skmacy#define F_ORG V_ORG(1U) 2728167514Skmacy 2729167514Skmacy#define S_DEN 2 2730167514Skmacy#define M_DEN 0x7 2731167514Skmacy#define V_DEN(x) ((x) << S_DEN) 2732167514Skmacy#define G_DEN(x) (((x) >> S_DEN) & M_DEN) 2733167514Skmacy 2734167514Skmacy#define S_RDY 1 2735167514Skmacy#define V_RDY(x) ((x) << S_RDY) 2736167514Skmacy#define F_RDY V_RDY(1U) 2737167514Skmacy 2738167514Skmacy#define S_CLKEN 0 2739167514Skmacy#define V_CLKEN(x) ((x) << S_CLKEN) 2740167514Skmacy#define F_CLKEN V_CLKEN(1U) 2741167514Skmacy 2742167514Skmacy#define A_MC7_MODE 0x104 2743167514Skmacy 2744167514Skmacy#define S_MODE 0 2745167514Skmacy#define M_MODE 0xffff 2746167514Skmacy#define V_MODE(x) ((x) << S_MODE) 2747167514Skmacy#define G_MODE(x) (((x) >> S_MODE) & M_MODE) 2748167514Skmacy 2749167514Skmacy#define A_MC7_EXT_MODE1 0x108 2750167514Skmacy 2751167514Skmacy#define S_OCDADJUSTMODE 20 2752167514Skmacy#define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE) 2753167514Skmacy#define F_OCDADJUSTMODE V_OCDADJUSTMODE(1U) 2754167514Skmacy 2755167514Skmacy#define S_OCDCODE 16 2756167514Skmacy#define M_OCDCODE 0xf 2757167514Skmacy#define V_OCDCODE(x) ((x) << S_OCDCODE) 2758167514Skmacy#define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE) 2759167514Skmacy 2760167514Skmacy#define S_EXTMODE1 0 2761167514Skmacy#define M_EXTMODE1 0xffff 2762167514Skmacy#define V_EXTMODE1(x) ((x) << S_EXTMODE1) 2763167514Skmacy#define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1) 2764167514Skmacy 2765167514Skmacy#define A_MC7_EXT_MODE2 0x10c 2766167514Skmacy 2767167514Skmacy#define S_EXTMODE2 0 2768167514Skmacy#define M_EXTMODE2 0xffff 2769167514Skmacy#define V_EXTMODE2(x) ((x) << S_EXTMODE2) 2770167514Skmacy#define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2) 2771167514Skmacy 2772167514Skmacy#define A_MC7_EXT_MODE3 0x110 2773167514Skmacy 2774167514Skmacy#define S_EXTMODE3 0 2775167514Skmacy#define M_EXTMODE3 0xffff 2776167514Skmacy#define V_EXTMODE3(x) ((x) << S_EXTMODE3) 2777167514Skmacy#define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3) 2778167514Skmacy 2779167514Skmacy#define A_MC7_PRE 0x114 2780167514Skmacy#define A_MC7_REF 0x118 2781167514Skmacy 2782167514Skmacy#define S_PREREFDIV 1 2783167514Skmacy#define M_PREREFDIV 0x3fff 2784167514Skmacy#define V_PREREFDIV(x) ((x) << S_PREREFDIV) 2785167514Skmacy#define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV) 2786167514Skmacy 2787167514Skmacy#define S_PERREFEN 0 2788167514Skmacy#define V_PERREFEN(x) ((x) << S_PERREFEN) 2789167514Skmacy#define F_PERREFEN V_PERREFEN(1U) 2790167514Skmacy 2791167514Skmacy#define A_MC7_DLL 0x11c 2792167514Skmacy 2793167514Skmacy#define S_DLLLOCK 31 2794167514Skmacy#define V_DLLLOCK(x) ((x) << S_DLLLOCK) 2795167514Skmacy#define F_DLLLOCK V_DLLLOCK(1U) 2796167514Skmacy 2797167514Skmacy#define S_DLLDELTA 24 2798167514Skmacy#define M_DLLDELTA 0x7f 2799167514Skmacy#define V_DLLDELTA(x) ((x) << S_DLLDELTA) 2800167514Skmacy#define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA) 2801167514Skmacy 2802167514Skmacy#define S_MANDELTA 3 2803167514Skmacy#define M_MANDELTA 0x7f 2804167514Skmacy#define V_MANDELTA(x) ((x) << S_MANDELTA) 2805167514Skmacy#define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA) 2806167514Skmacy 2807167514Skmacy#define S_DLLDELTASEL 2 2808167514Skmacy#define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL) 2809167514Skmacy#define F_DLLDELTASEL V_DLLDELTASEL(1U) 2810167514Skmacy 2811167514Skmacy#define S_DLLENB 1 2812167514Skmacy#define V_DLLENB(x) ((x) << S_DLLENB) 2813167514Skmacy#define F_DLLENB V_DLLENB(1U) 2814167514Skmacy 2815167514Skmacy#define S_DLLRST 0 2816167514Skmacy#define V_DLLRST(x) ((x) << S_DLLRST) 2817167514Skmacy#define F_DLLRST V_DLLRST(1U) 2818167514Skmacy 2819167514Skmacy#define A_MC7_PARM 0x120 2820167514Skmacy 2821167514Skmacy#define S_ACTTOPREDLY 26 2822167514Skmacy#define M_ACTTOPREDLY 0xf 2823167514Skmacy#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) 2824167514Skmacy#define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY) 2825167514Skmacy 2826167514Skmacy#define S_ACTTORDWRDLY 23 2827167514Skmacy#define M_ACTTORDWRDLY 0x7 2828167514Skmacy#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) 2829167514Skmacy#define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY) 2830167514Skmacy 2831167514Skmacy#define S_PRECYC 20 2832167514Skmacy#define M_PRECYC 0x7 2833167514Skmacy#define V_PRECYC(x) ((x) << S_PRECYC) 2834167514Skmacy#define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC) 2835167514Skmacy 2836167514Skmacy#define S_REFCYC 13 2837167514Skmacy#define M_REFCYC 0x7f 2838167514Skmacy#define V_REFCYC(x) ((x) << S_REFCYC) 2839167514Skmacy#define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC) 2840167514Skmacy 2841167514Skmacy#define S_BKCYC 8 2842167514Skmacy#define M_BKCYC 0x1f 2843167514Skmacy#define V_BKCYC(x) ((x) << S_BKCYC) 2844167514Skmacy#define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC) 2845167514Skmacy 2846167514Skmacy#define S_WRTORDDLY 4 2847167514Skmacy#define M_WRTORDDLY 0xf 2848167514Skmacy#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) 2849167514Skmacy#define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY) 2850167514Skmacy 2851167514Skmacy#define S_RDTOWRDLY 0 2852167514Skmacy#define M_RDTOWRDLY 0xf 2853167514Skmacy#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) 2854167514Skmacy#define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY) 2855167514Skmacy 2856167514Skmacy#define A_MC7_HWM_WRR 0x124 2857167514Skmacy 2858167514Skmacy#define S_MEM_HWM 26 2859167514Skmacy#define M_MEM_HWM 0x3f 2860167514Skmacy#define V_MEM_HWM(x) ((x) << S_MEM_HWM) 2861167514Skmacy#define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM) 2862167514Skmacy 2863167514Skmacy#define S_ULP_HWM 22 2864167514Skmacy#define M_ULP_HWM 0xf 2865167514Skmacy#define V_ULP_HWM(x) ((x) << S_ULP_HWM) 2866167514Skmacy#define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM) 2867167514Skmacy 2868167514Skmacy#define S_TOT_RLD_WT 14 2869167514Skmacy#define M_TOT_RLD_WT 0xff 2870167514Skmacy#define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT) 2871167514Skmacy#define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT) 2872167514Skmacy 2873167514Skmacy#define S_MEM_RLD_WT 7 2874167514Skmacy#define M_MEM_RLD_WT 0x7f 2875167514Skmacy#define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT) 2876167514Skmacy#define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT) 2877167514Skmacy 2878167514Skmacy#define S_ULP_RLD_WT 0 2879167514Skmacy#define M_ULP_RLD_WT 0x7f 2880167514Skmacy#define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT) 2881167514Skmacy#define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT) 2882167514Skmacy 2883167514Skmacy#define A_MC7_CAL 0x128 2884167514Skmacy 2885167514Skmacy#define S_BUSY 31 2886167514Skmacy#define V_BUSY(x) ((x) << S_BUSY) 2887167514Skmacy#define F_BUSY V_BUSY(1U) 2888167514Skmacy 2889167514Skmacy#define S_CAL_FAULT 30 2890167514Skmacy#define V_CAL_FAULT(x) ((x) << S_CAL_FAULT) 2891167514Skmacy#define F_CAL_FAULT V_CAL_FAULT(1U) 2892167514Skmacy 2893167514Skmacy#define S_PER_CAL_DIV 22 2894167514Skmacy#define M_PER_CAL_DIV 0xff 2895167514Skmacy#define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV) 2896167514Skmacy#define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV) 2897167514Skmacy 2898167514Skmacy#define S_PER_CAL_EN 21 2899167514Skmacy#define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN) 2900167514Skmacy#define F_PER_CAL_EN V_PER_CAL_EN(1U) 2901167514Skmacy 2902167514Skmacy#define S_SGL_CAL_EN 20 2903167514Skmacy#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) 2904167514Skmacy#define F_SGL_CAL_EN V_SGL_CAL_EN(1U) 2905167514Skmacy 2906167514Skmacy#define S_IMP_UPD_MODE 19 2907167514Skmacy#define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) 2908167514Skmacy#define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) 2909167514Skmacy 2910167514Skmacy#define S_IMP_SEL 18 2911167514Skmacy#define V_IMP_SEL(x) ((x) << S_IMP_SEL) 2912167514Skmacy#define F_IMP_SEL V_IMP_SEL(1U) 2913167514Skmacy 2914167514Skmacy#define S_IMP_MAN_PD 15 2915167514Skmacy#define M_IMP_MAN_PD 0x7 2916167514Skmacy#define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD) 2917167514Skmacy#define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD) 2918167514Skmacy 2919167514Skmacy#define S_IMP_MAN_PU 12 2920167514Skmacy#define M_IMP_MAN_PU 0x7 2921167514Skmacy#define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU) 2922167514Skmacy#define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU) 2923167514Skmacy 2924167514Skmacy#define S_IMP_CAL_PD 9 2925167514Skmacy#define M_IMP_CAL_PD 0x7 2926167514Skmacy#define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD) 2927167514Skmacy#define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD) 2928167514Skmacy 2929167514Skmacy#define S_IMP_CAL_PU 6 2930167514Skmacy#define M_IMP_CAL_PU 0x7 2931167514Skmacy#define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU) 2932167514Skmacy#define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU) 2933167514Skmacy 2934167514Skmacy#define S_IMP_SET_PD 3 2935167514Skmacy#define M_IMP_SET_PD 0x7 2936167514Skmacy#define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD) 2937167514Skmacy#define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD) 2938167514Skmacy 2939167514Skmacy#define S_IMP_SET_PU 0 2940167514Skmacy#define M_IMP_SET_PU 0x7 2941167514Skmacy#define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU) 2942167514Skmacy#define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU) 2943167514Skmacy 2944167514Skmacy#define A_MC7_ERR_ADDR 0x12c 2945167514Skmacy 2946167514Skmacy#define S_ERRADDRESS 3 2947167514Skmacy#define M_ERRADDRESS 0x1fffffff 2948167514Skmacy#define V_ERRADDRESS(x) ((x) << S_ERRADDRESS) 2949167514Skmacy#define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS) 2950167514Skmacy 2951167514Skmacy#define S_ERRAGENT 1 2952167514Skmacy#define M_ERRAGENT 0x3 2953167514Skmacy#define V_ERRAGENT(x) ((x) << S_ERRAGENT) 2954167514Skmacy#define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT) 2955167514Skmacy 2956167514Skmacy#define S_ERROP 0 2957167514Skmacy#define V_ERROP(x) ((x) << S_ERROP) 2958167514Skmacy#define F_ERROP V_ERROP(1U) 2959167514Skmacy 2960167514Skmacy#define A_MC7_ECC 0x130 2961167514Skmacy 2962167514Skmacy#define S_UECNT 10 2963167514Skmacy#define M_UECNT 0xff 2964167514Skmacy#define V_UECNT(x) ((x) << S_UECNT) 2965167514Skmacy#define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT) 2966167514Skmacy 2967167514Skmacy#define S_CECNT 2 2968167514Skmacy#define M_CECNT 0xff 2969167514Skmacy#define V_CECNT(x) ((x) << S_CECNT) 2970167514Skmacy#define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT) 2971167514Skmacy 2972167514Skmacy#define S_ECCCHKEN 1 2973167514Skmacy#define V_ECCCHKEN(x) ((x) << S_ECCCHKEN) 2974167514Skmacy#define F_ECCCHKEN V_ECCCHKEN(1U) 2975167514Skmacy 2976167514Skmacy#define S_ECCGENEN 0 2977167514Skmacy#define V_ECCGENEN(x) ((x) << S_ECCGENEN) 2978167514Skmacy#define F_ECCGENEN V_ECCGENEN(1U) 2979167514Skmacy 2980167514Skmacy#define A_MC7_CE_ADDR 0x134 2981167514Skmacy#define A_MC7_CE_DATA0 0x138 2982167514Skmacy#define A_MC7_CE_DATA1 0x13c 2983167514Skmacy#define A_MC7_CE_DATA2 0x140 2984167514Skmacy 2985167514Skmacy#define S_DATA 0 2986167514Skmacy#define M_DATA 0xff 2987167514Skmacy#define V_DATA(x) ((x) << S_DATA) 2988167514Skmacy#define G_DATA(x) (((x) >> S_DATA) & M_DATA) 2989167514Skmacy 2990167514Skmacy#define A_MC7_UE_ADDR 0x144 2991167514Skmacy#define A_MC7_UE_DATA0 0x148 2992167514Skmacy#define A_MC7_UE_DATA1 0x14c 2993167514Skmacy#define A_MC7_UE_DATA2 0x150 2994167514Skmacy#define A_MC7_BD_ADDR 0x154 2995167514Skmacy 2996167514Skmacy#define S_ADDR 3 2997167514Skmacy#define M_ADDR 0x1fffffff 2998167514Skmacy#define V_ADDR(x) ((x) << S_ADDR) 2999167514Skmacy#define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR) 3000167514Skmacy 3001167514Skmacy#define A_MC7_BD_DATA0 0x158 3002167514Skmacy#define A_MC7_BD_DATA1 0x15c 3003167514Skmacy#define A_MC7_BD_DATA2 0x160 3004167514Skmacy#define A_MC7_BD_OP 0x164 3005167514Skmacy 3006167514Skmacy#define S_OP 0 3007167514Skmacy#define V_OP(x) ((x) << S_OP) 3008167514Skmacy#define F_OP V_OP(1U) 3009167514Skmacy 3010167514Skmacy#define A_MC7_BIST_ADDR_BEG 0x168 3011167514Skmacy 3012167514Skmacy#define S_ADDRBEG 5 3013167514Skmacy#define M_ADDRBEG 0x7ffffff 3014167514Skmacy#define V_ADDRBEG(x) ((x) << S_ADDRBEG) 3015167514Skmacy#define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG) 3016167514Skmacy 3017167514Skmacy#define A_MC7_BIST_ADDR_END 0x16c 3018167514Skmacy 3019167514Skmacy#define S_ADDREND 5 3020167514Skmacy#define M_ADDREND 0x7ffffff 3021167514Skmacy#define V_ADDREND(x) ((x) << S_ADDREND) 3022167514Skmacy#define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND) 3023167514Skmacy 3024167514Skmacy#define A_MC7_BIST_DATA 0x170 3025167514Skmacy#define A_MC7_BIST_OP 0x174 3026167514Skmacy 3027167514Skmacy#define S_GAP 4 3028167514Skmacy#define M_GAP 0x1f 3029167514Skmacy#define V_GAP(x) ((x) << S_GAP) 3030167514Skmacy#define G_GAP(x) (((x) >> S_GAP) & M_GAP) 3031167514Skmacy 3032167514Skmacy#define S_CONT 3 3033167514Skmacy#define V_CONT(x) ((x) << S_CONT) 3034167514Skmacy#define F_CONT V_CONT(1U) 3035167514Skmacy 3036167514Skmacy#define S_DATAPAT 1 3037167514Skmacy#define M_DATAPAT 0x3 3038167514Skmacy#define V_DATAPAT(x) ((x) << S_DATAPAT) 3039167514Skmacy#define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT) 3040167514Skmacy 3041167514Skmacy#define A_MC7_INT_ENABLE 0x178 3042167514Skmacy 3043167514Skmacy#define S_AE 17 3044167514Skmacy#define V_AE(x) ((x) << S_AE) 3045167514Skmacy#define F_AE V_AE(1U) 3046167514Skmacy 3047167514Skmacy#define S_PE 2 3048167514Skmacy#define M_PE 0x7fff 3049167514Skmacy#define V_PE(x) ((x) << S_PE) 3050167514Skmacy#define G_PE(x) (((x) >> S_PE) & M_PE) 3051167514Skmacy 3052167514Skmacy#define S_UE 1 3053167514Skmacy#define V_UE(x) ((x) << S_UE) 3054167514Skmacy#define F_UE V_UE(1U) 3055167514Skmacy 3056167514Skmacy#define S_CE 0 3057167514Skmacy#define V_CE(x) ((x) << S_CE) 3058167514Skmacy#define F_CE V_CE(1U) 3059167514Skmacy 3060167514Skmacy#define A_MC7_INT_CAUSE 0x17c 3061167514Skmacy 3062167514Skmacy/* registers for module MC7_PMTX */ 3063167514Skmacy#define MC7_PMTX_BASE_ADDR 0x180 3064167514Skmacy 3065167514Skmacy/* registers for module MC7_CM */ 3066167514Skmacy#define MC7_CM_BASE_ADDR 0x200 3067167514Skmacy 3068167514Skmacy/* registers for module CIM */ 3069167514Skmacy#define CIM_BASE_ADDR 0x280 3070167514Skmacy 3071167514Skmacy#define A_CIM_BOOT_CFG 0x280 3072167514Skmacy 3073167514Skmacy#define S_BOOTADDR 2 3074167514Skmacy#define M_BOOTADDR 0x3fffffff 3075167514Skmacy#define V_BOOTADDR(x) ((x) << S_BOOTADDR) 3076167514Skmacy#define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR) 3077167514Skmacy 3078167514Skmacy#define S_BOOTSDRAM 1 3079167514Skmacy#define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM) 3080167514Skmacy#define F_BOOTSDRAM V_BOOTSDRAM(1U) 3081167514Skmacy 3082167514Skmacy#define S_UPCRST 0 3083167514Skmacy#define V_UPCRST(x) ((x) << S_UPCRST) 3084167514Skmacy#define F_UPCRST V_UPCRST(1U) 3085167514Skmacy 3086167514Skmacy#define A_CIM_FLASH_BASE_ADDR 0x284 3087167514Skmacy 3088167514Skmacy#define S_FLASHBASEADDR 2 3089167514Skmacy#define M_FLASHBASEADDR 0x3fffff 3090167514Skmacy#define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR) 3091167514Skmacy#define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR) 3092167514Skmacy 3093167514Skmacy#define A_CIM_FLASH_ADDR_SIZE 0x288 3094167514Skmacy 3095167514Skmacy#define S_FLASHADDRSIZE 2 3096167514Skmacy#define M_FLASHADDRSIZE 0x3fffff 3097167514Skmacy#define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE) 3098167514Skmacy#define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE) 3099167514Skmacy 3100167514Skmacy#define A_CIM_SDRAM_BASE_ADDR 0x28c 3101167514Skmacy 3102167514Skmacy#define S_SDRAMBASEADDR 2 3103167514Skmacy#define M_SDRAMBASEADDR 0x3fffffff 3104167514Skmacy#define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR) 3105167514Skmacy#define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR) 3106167514Skmacy 3107167514Skmacy#define A_CIM_SDRAM_ADDR_SIZE 0x290 3108167514Skmacy 3109167514Skmacy#define S_SDRAMADDRSIZE 2 3110167514Skmacy#define M_SDRAMADDRSIZE 0x3fffffff 3111167514Skmacy#define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE) 3112167514Skmacy#define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE) 3113167514Skmacy 3114167514Skmacy#define A_CIM_UP_SPARE_INT 0x294 3115167514Skmacy 3116167514Skmacy#define S_UPSPAREINT 0 3117167514Skmacy#define M_UPSPAREINT 0x7 3118167514Skmacy#define V_UPSPAREINT(x) ((x) << S_UPSPAREINT) 3119167514Skmacy#define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT) 3120167514Skmacy 3121167514Skmacy#define A_CIM_HOST_INT_ENABLE 0x298 3122167514Skmacy 3123176472Skmacy#define S_DTAGPARERR 28 3124176472Skmacy#define V_DTAGPARERR(x) ((x) << S_DTAGPARERR) 3125176472Skmacy#define F_DTAGPARERR V_DTAGPARERR(1U) 3126176472Skmacy 3127176472Skmacy#define S_ITAGPARERR 27 3128176472Skmacy#define V_ITAGPARERR(x) ((x) << S_ITAGPARERR) 3129176472Skmacy#define F_ITAGPARERR V_ITAGPARERR(1U) 3130176472Skmacy 3131176472Skmacy#define S_IBQTPPARERR 26 3132176472Skmacy#define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR) 3133176472Skmacy#define F_IBQTPPARERR V_IBQTPPARERR(1U) 3134176472Skmacy 3135176472Skmacy#define S_IBQULPPARERR 25 3136176472Skmacy#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR) 3137176472Skmacy#define F_IBQULPPARERR V_IBQULPPARERR(1U) 3138176472Skmacy 3139176472Skmacy#define S_IBQSGEHIPARERR 24 3140176472Skmacy#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR) 3141176472Skmacy#define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U) 3142176472Skmacy 3143176472Skmacy#define S_IBQSGELOPARERR 23 3144176472Skmacy#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR) 3145176472Skmacy#define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U) 3146176472Skmacy 3147176472Skmacy#define S_OBQULPLOPARERR 22 3148176472Skmacy#define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR) 3149176472Skmacy#define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U) 3150176472Skmacy 3151176472Skmacy#define S_OBQULPHIPARERR 21 3152176472Skmacy#define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR) 3153176472Skmacy#define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U) 3154176472Skmacy 3155176472Skmacy#define S_OBQSGEPARERR 20 3156176472Skmacy#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR) 3157176472Skmacy#define F_OBQSGEPARERR V_OBQSGEPARERR(1U) 3158176472Skmacy 3159176472Skmacy#define S_DCACHEPARERR 19 3160176472Skmacy#define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR) 3161176472Skmacy#define F_DCACHEPARERR V_DCACHEPARERR(1U) 3162176472Skmacy 3163176472Skmacy#define S_ICACHEPARERR 18 3164176472Skmacy#define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR) 3165176472Skmacy#define F_ICACHEPARERR V_ICACHEPARERR(1U) 3166176472Skmacy 3167176472Skmacy#define S_DRAMPARERR 17 3168176472Skmacy#define V_DRAMPARERR(x) ((x) << S_DRAMPARERR) 3169176472Skmacy#define F_DRAMPARERR V_DRAMPARERR(1U) 3170176472Skmacy 3171167514Skmacy#define S_TIMER1INTEN 15 3172167514Skmacy#define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN) 3173167514Skmacy#define F_TIMER1INTEN V_TIMER1INTEN(1U) 3174167514Skmacy 3175167514Skmacy#define S_TIMER0INTEN 14 3176167514Skmacy#define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN) 3177167514Skmacy#define F_TIMER0INTEN V_TIMER0INTEN(1U) 3178167514Skmacy 3179167514Skmacy#define S_PREFDROPINTEN 13 3180167514Skmacy#define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN) 3181167514Skmacy#define F_PREFDROPINTEN V_PREFDROPINTEN(1U) 3182167514Skmacy 3183167514Skmacy#define S_BLKWRPLINTEN 12 3184167514Skmacy#define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN) 3185167514Skmacy#define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U) 3186167514Skmacy 3187167514Skmacy#define S_BLKRDPLINTEN 11 3188167514Skmacy#define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN) 3189167514Skmacy#define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U) 3190167514Skmacy 3191167514Skmacy#define S_BLKWRCTLINTEN 10 3192167514Skmacy#define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN) 3193167514Skmacy#define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U) 3194167514Skmacy 3195167514Skmacy#define S_BLKRDCTLINTEN 9 3196167514Skmacy#define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN) 3197167514Skmacy#define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U) 3198167514Skmacy 3199167514Skmacy#define S_BLKWRFLASHINTEN 8 3200167514Skmacy#define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN) 3201167514Skmacy#define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U) 3202167514Skmacy 3203167514Skmacy#define S_BLKRDFLASHINTEN 7 3204167514Skmacy#define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN) 3205167514Skmacy#define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U) 3206167514Skmacy 3207167514Skmacy#define S_SGLWRFLASHINTEN 6 3208167514Skmacy#define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN) 3209167514Skmacy#define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U) 3210167514Skmacy 3211167514Skmacy#define S_WRBLKFLASHINTEN 5 3212167514Skmacy#define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN) 3213167514Skmacy#define F_WRBLKFLASHINTEN V_WRBLKFLASHINTEN(1U) 3214167514Skmacy 3215167514Skmacy#define S_BLKWRBOOTINTEN 4 3216167514Skmacy#define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN) 3217167514Skmacy#define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U) 3218167514Skmacy 3219167514Skmacy#define S_BLKRDBOOTINTEN 3 3220167514Skmacy#define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN) 3221167514Skmacy#define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U) 3222167514Skmacy 3223167514Skmacy#define S_FLASHRANGEINTEN 2 3224167514Skmacy#define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN) 3225167514Skmacy#define F_FLASHRANGEINTEN V_FLASHRANGEINTEN(1U) 3226167514Skmacy 3227167514Skmacy#define S_SDRAMRANGEINTEN 1 3228167514Skmacy#define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN) 3229167514Skmacy#define F_SDRAMRANGEINTEN V_SDRAMRANGEINTEN(1U) 3230167514Skmacy 3231167514Skmacy#define S_RSVDSPACEINTEN 0 3232167514Skmacy#define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN) 3233167514Skmacy#define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U) 3234167514Skmacy 3235167514Skmacy#define A_CIM_HOST_INT_CAUSE 0x29c 3236167514Skmacy 3237167514Skmacy#define S_TIMER1INT 15 3238167514Skmacy#define V_TIMER1INT(x) ((x) << S_TIMER1INT) 3239167514Skmacy#define F_TIMER1INT V_TIMER1INT(1U) 3240167514Skmacy 3241167514Skmacy#define S_TIMER0INT 14 3242167514Skmacy#define V_TIMER0INT(x) ((x) << S_TIMER0INT) 3243167514Skmacy#define F_TIMER0INT V_TIMER0INT(1U) 3244167514Skmacy 3245167514Skmacy#define S_PREFDROPINT 13 3246167514Skmacy#define V_PREFDROPINT(x) ((x) << S_PREFDROPINT) 3247167514Skmacy#define F_PREFDROPINT V_PREFDROPINT(1U) 3248167514Skmacy 3249167514Skmacy#define S_BLKWRPLINT 12 3250167514Skmacy#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) 3251167514Skmacy#define F_BLKWRPLINT V_BLKWRPLINT(1U) 3252167514Skmacy 3253167514Skmacy#define S_BLKRDPLINT 11 3254167514Skmacy#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT) 3255167514Skmacy#define F_BLKRDPLINT V_BLKRDPLINT(1U) 3256167514Skmacy 3257167514Skmacy#define S_BLKWRCTLINT 10 3258167514Skmacy#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT) 3259167514Skmacy#define F_BLKWRCTLINT V_BLKWRCTLINT(1U) 3260167514Skmacy 3261167514Skmacy#define S_BLKRDCTLINT 9 3262167514Skmacy#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT) 3263167514Skmacy#define F_BLKRDCTLINT V_BLKRDCTLINT(1U) 3264167514Skmacy 3265167514Skmacy#define S_BLKWRFLASHINT 8 3266167514Skmacy#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT) 3267167514Skmacy#define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U) 3268167514Skmacy 3269167514Skmacy#define S_BLKRDFLASHINT 7 3270167514Skmacy#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT) 3271167514Skmacy#define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U) 3272167514Skmacy 3273167514Skmacy#define S_SGLWRFLASHINT 6 3274167514Skmacy#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT) 3275167514Skmacy#define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U) 3276167514Skmacy 3277167514Skmacy#define S_WRBLKFLASHINT 5 3278167514Skmacy#define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT) 3279167514Skmacy#define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U) 3280167514Skmacy 3281167514Skmacy#define S_BLKWRBOOTINT 4 3282167514Skmacy#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) 3283167514Skmacy#define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) 3284167514Skmacy 3285167514Skmacy#define S_BLKRDBOOTINT 3 3286167514Skmacy#define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT) 3287167514Skmacy#define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U) 3288167514Skmacy 3289167514Skmacy#define S_FLASHRANGEINT 2 3290167514Skmacy#define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT) 3291167514Skmacy#define F_FLASHRANGEINT V_FLASHRANGEINT(1U) 3292167514Skmacy 3293167514Skmacy#define S_SDRAMRANGEINT 1 3294167514Skmacy#define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT) 3295167514Skmacy#define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U) 3296167514Skmacy 3297167514Skmacy#define S_RSVDSPACEINT 0 3298167514Skmacy#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) 3299167514Skmacy#define F_RSVDSPACEINT V_RSVDSPACEINT(1U) 3300167514Skmacy 3301167514Skmacy#define A_CIM_UP_INT_ENABLE 0x2a0 3302167514Skmacy 3303167514Skmacy#define S_MSTPLINTEN 16 3304167514Skmacy#define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN) 3305167514Skmacy#define F_MSTPLINTEN V_MSTPLINTEN(1U) 3306167514Skmacy 3307167514Skmacy#define A_CIM_UP_INT_CAUSE 0x2a4 3308167514Skmacy 3309167514Skmacy#define S_MSTPLINT 16 3310167514Skmacy#define V_MSTPLINT(x) ((x) << S_MSTPLINT) 3311167514Skmacy#define F_MSTPLINT V_MSTPLINT(1U) 3312167514Skmacy 3313167514Skmacy#define A_CIM_IBQ_FULLA_THRSH 0x2a8 3314167514Skmacy 3315167514Skmacy#define S_IBQ0FULLTHRSH 0 3316167514Skmacy#define M_IBQ0FULLTHRSH 0x1ff 3317167514Skmacy#define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH) 3318167514Skmacy#define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH) 3319167514Skmacy 3320167514Skmacy#define S_IBQ1FULLTHRSH 16 3321167514Skmacy#define M_IBQ1FULLTHRSH 0x1ff 3322167514Skmacy#define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH) 3323167514Skmacy#define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH) 3324167514Skmacy 3325167514Skmacy#define A_CIM_IBQ_FULLB_THRSH 0x2ac 3326167514Skmacy 3327167514Skmacy#define S_IBQ2FULLTHRSH 0 3328167514Skmacy#define M_IBQ2FULLTHRSH 0x1ff 3329167514Skmacy#define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH) 3330167514Skmacy#define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH) 3331167514Skmacy 3332167514Skmacy#define S_IBQ3FULLTHRSH 16 3333167514Skmacy#define M_IBQ3FULLTHRSH 0x1ff 3334167514Skmacy#define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH) 3335167514Skmacy#define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH) 3336167514Skmacy 3337167514Skmacy#define A_CIM_HOST_ACC_CTRL 0x2b0 3338167514Skmacy 3339167514Skmacy#define S_HOSTBUSY 17 3340167514Skmacy#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) 3341167514Skmacy#define F_HOSTBUSY V_HOSTBUSY(1U) 3342167514Skmacy 3343167514Skmacy#define S_HOSTWRITE 16 3344167514Skmacy#define V_HOSTWRITE(x) ((x) << S_HOSTWRITE) 3345167514Skmacy#define F_HOSTWRITE V_HOSTWRITE(1U) 3346167514Skmacy 3347167514Skmacy#define S_HOSTADDR 0 3348167514Skmacy#define M_HOSTADDR 0xffff 3349167514Skmacy#define V_HOSTADDR(x) ((x) << S_HOSTADDR) 3350167514Skmacy#define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR) 3351167514Skmacy 3352167514Skmacy#define A_CIM_HOST_ACC_DATA 0x2b4 3353167514Skmacy#define A_CIM_IBQ_DBG_CFG 0x2c0 3354167514Skmacy 3355167514Skmacy#define S_IBQDBGADDR 16 3356167514Skmacy#define M_IBQDBGADDR 0x1ff 3357167514Skmacy#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR) 3358167514Skmacy#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR) 3359167514Skmacy 3360167514Skmacy#define S_IBQDBGQID 3 3361167514Skmacy#define M_IBQDBGQID 0x3 3362167514Skmacy#define V_IBQDBGQID(x) ((x) << S_IBQDBGQID) 3363167514Skmacy#define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID) 3364167514Skmacy 3365167514Skmacy#define S_IBQDBGWR 2 3366167514Skmacy#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR) 3367167514Skmacy#define F_IBQDBGWR V_IBQDBGWR(1U) 3368167514Skmacy 3369167514Skmacy#define S_IBQDBGBUSY 1 3370167514Skmacy#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY) 3371167514Skmacy#define F_IBQDBGBUSY V_IBQDBGBUSY(1U) 3372167514Skmacy 3373167514Skmacy#define S_IBQDBGEN 0 3374167514Skmacy#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) 3375167514Skmacy#define F_IBQDBGEN V_IBQDBGEN(1U) 3376167514Skmacy 3377167514Skmacy#define A_CIM_OBQ_DBG_CFG 0x2c4 3378167514Skmacy 3379167514Skmacy#define S_OBQDBGADDR 16 3380167514Skmacy#define M_OBQDBGADDR 0x1ff 3381167514Skmacy#define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR) 3382167514Skmacy#define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR) 3383167514Skmacy 3384167514Skmacy#define S_OBQDBGQID 3 3385167514Skmacy#define M_OBQDBGQID 0x3 3386167514Skmacy#define V_OBQDBGQID(x) ((x) << S_OBQDBGQID) 3387167514Skmacy#define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID) 3388167514Skmacy 3389167514Skmacy#define S_OBQDBGWR 2 3390167514Skmacy#define V_OBQDBGWR(x) ((x) << S_OBQDBGWR) 3391167514Skmacy#define F_OBQDBGWR V_OBQDBGWR(1U) 3392167514Skmacy 3393167514Skmacy#define S_OBQDBGBUSY 1 3394167514Skmacy#define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY) 3395167514Skmacy#define F_OBQDBGBUSY V_OBQDBGBUSY(1U) 3396167514Skmacy 3397167514Skmacy#define S_OBQDBGEN 0 3398167514Skmacy#define V_OBQDBGEN(x) ((x) << S_OBQDBGEN) 3399167514Skmacy#define F_OBQDBGEN V_OBQDBGEN(1U) 3400167514Skmacy 3401167514Skmacy#define A_CIM_IBQ_DBG_DATA 0x2c8 3402167514Skmacy#define A_CIM_OBQ_DBG_DATA 0x2cc 3403167514Skmacy#define A_CIM_CDEBUGDATA 0x2d0 3404167514Skmacy 3405167514Skmacy#define S_CDEBUGDATAH 16 3406167514Skmacy#define M_CDEBUGDATAH 0xffff 3407167514Skmacy#define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH) 3408167514Skmacy#define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH) 3409167514Skmacy 3410167514Skmacy#define S_CDEBUGDATAL 0 3411167514Skmacy#define M_CDEBUGDATAL 0xffff 3412167514Skmacy#define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL) 3413167514Skmacy#define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL) 3414167514Skmacy 3415167514Skmacy#define A_CIM_DEBUGCFG 0x2e0 3416167514Skmacy 3417167514Skmacy#define S_POLADBGRDPTR 23 3418167514Skmacy#define M_POLADBGRDPTR 0x1ff 3419167514Skmacy#define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR) 3420167514Skmacy#define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR) 3421167514Skmacy 3422167514Skmacy#define S_PILADBGRDPTR 14 3423167514Skmacy#define M_PILADBGRDPTR 0x1ff 3424167514Skmacy#define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR) 3425167514Skmacy#define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR) 3426167514Skmacy 3427167514Skmacy#define S_CIM_LADBGEN 12 3428167514Skmacy#define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN) 3429167514Skmacy#define F_CIM_LADBGEN V_CIM_LADBGEN(1U) 3430167514Skmacy 3431167514Skmacy#define S_DEBUGSELHI 5 3432167514Skmacy#define M_DEBUGSELHI 0x1f 3433167514Skmacy#define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI) 3434167514Skmacy#define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI) 3435167514Skmacy 3436167514Skmacy#define S_DEBUGSELLO 0 3437167514Skmacy#define M_DEBUGSELLO 0x1f 3438167514Skmacy#define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO) 3439167514Skmacy#define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO) 3440167514Skmacy 3441167514Skmacy#define A_CIM_DEBUGSTS 0x2e4 3442167514Skmacy 3443167514Skmacy#define S_POLADBGWRPTR 16 3444167514Skmacy#define M_POLADBGWRPTR 0x1ff 3445167514Skmacy#define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR) 3446167514Skmacy#define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR) 3447167514Skmacy 3448167514Skmacy#define S_PILADBGWRPTR 0 3449167514Skmacy#define M_PILADBGWRPTR 0x1ff 3450167514Skmacy#define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR) 3451167514Skmacy#define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR) 3452167514Skmacy 3453167514Skmacy#define A_CIM_PO_LA_DEBUGDATA 0x2e8 3454167514Skmacy#define A_CIM_PI_LA_DEBUGDATA 0x2ec 3455167514Skmacy 3456167514Skmacy/* registers for module TP1 */ 3457167514Skmacy#define TP1_BASE_ADDR 0x300 3458167514Skmacy 3459167514Skmacy#define A_TP_IN_CONFIG 0x300 3460167514Skmacy 3461167514Skmacy#define S_RXFBARBPRIO 25 3462167514Skmacy#define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO) 3463167514Skmacy#define F_RXFBARBPRIO V_RXFBARBPRIO(1U) 3464167514Skmacy 3465167514Skmacy#define S_TXFBARBPRIO 24 3466167514Skmacy#define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) 3467167514Skmacy#define F_TXFBARBPRIO V_TXFBARBPRIO(1U) 3468167514Skmacy 3469167514Skmacy#define S_DBMAXOPCNT 16 3470167514Skmacy#define M_DBMAXOPCNT 0xff 3471167514Skmacy#define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT) 3472167514Skmacy#define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT) 3473167514Skmacy 3474176472Skmacy#define S_IPV6ENABLE 15 3475176472Skmacy#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) 3476176472Skmacy#define F_IPV6ENABLE V_IPV6ENABLE(1U) 3477176472Skmacy 3478167514Skmacy#define S_NICMODE 14 3479167514Skmacy#define V_NICMODE(x) ((x) << S_NICMODE) 3480167514Skmacy#define F_NICMODE V_NICMODE(1U) 3481167514Skmacy 3482167514Skmacy#define S_ECHECKSUMCHECKTCP 13 3483167514Skmacy#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) 3484167514Skmacy#define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) 3485167514Skmacy 3486167514Skmacy#define S_ECHECKSUMCHECKIP 12 3487167514Skmacy#define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP) 3488167514Skmacy#define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U) 3489167514Skmacy 3490167514Skmacy#define S_ECPL 10 3491167514Skmacy#define V_ECPL(x) ((x) << S_ECPL) 3492167514Skmacy#define F_ECPL V_ECPL(1U) 3493167514Skmacy 3494167514Skmacy#define S_EETHERNET 8 3495167514Skmacy#define V_EETHERNET(x) ((x) << S_EETHERNET) 3496167514Skmacy#define F_EETHERNET V_EETHERNET(1U) 3497167514Skmacy 3498167514Skmacy#define S_ETUNNEL 7 3499167514Skmacy#define V_ETUNNEL(x) ((x) << S_ETUNNEL) 3500167514Skmacy#define F_ETUNNEL V_ETUNNEL(1U) 3501167514Skmacy 3502167514Skmacy#define S_CCHECKSUMCHECKTCP 6 3503167514Skmacy#define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP) 3504167514Skmacy#define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U) 3505167514Skmacy 3506167514Skmacy#define S_CCHECKSUMCHECKIP 5 3507167514Skmacy#define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP) 3508167514Skmacy#define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U) 3509167514Skmacy 3510167514Skmacy#define S_CCPL 3 3511167514Skmacy#define V_CCPL(x) ((x) << S_CCPL) 3512167514Skmacy#define F_CCPL V_CCPL(1U) 3513167514Skmacy 3514167514Skmacy#define S_CETHERNET 1 3515167514Skmacy#define V_CETHERNET(x) ((x) << S_CETHERNET) 3516167514Skmacy#define F_CETHERNET V_CETHERNET(1U) 3517167514Skmacy 3518167514Skmacy#define S_CTUNNEL 0 3519167514Skmacy#define V_CTUNNEL(x) ((x) << S_CTUNNEL) 3520167514Skmacy#define F_CTUNNEL V_CTUNNEL(1U) 3521167514Skmacy 3522167514Skmacy#define A_TP_OUT_CONFIG 0x304 3523167514Skmacy 3524176472Skmacy#define S_IPIDSPLITMODE 16 3525176472Skmacy#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) 3526176472Skmacy#define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) 3527176472Skmacy 3528176472Skmacy#define S_VLANEXTRACTIONENABLE2NDPORT 13 3529176472Skmacy#define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT) 3530176472Skmacy#define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U) 3531176472Skmacy 3532167514Skmacy#define S_VLANEXTRACTIONENABLE 12 3533167514Skmacy#define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE) 3534167514Skmacy#define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U) 3535167514Skmacy 3536167514Skmacy#define S_ECHECKSUMGENERATETCP 11 3537167514Skmacy#define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP) 3538167514Skmacy#define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U) 3539167514Skmacy 3540167514Skmacy#define S_ECHECKSUMGENERATEIP 10 3541167514Skmacy#define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP) 3542167514Skmacy#define F_ECHECKSUMGENERATEIP V_ECHECKSUMGENERATEIP(1U) 3543167514Skmacy 3544167514Skmacy#define S_OUT_ECPL 8 3545167514Skmacy#define V_OUT_ECPL(x) ((x) << S_OUT_ECPL) 3546167514Skmacy#define F_OUT_ECPL V_OUT_ECPL(1U) 3547167514Skmacy 3548167514Skmacy#define S_OUT_EETHERNET 6 3549167514Skmacy#define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET) 3550167514Skmacy#define F_OUT_EETHERNET V_OUT_EETHERNET(1U) 3551167514Skmacy 3552167514Skmacy#define S_CCHECKSUMGENERATETCP 5 3553167514Skmacy#define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP) 3554167514Skmacy#define F_CCHECKSUMGENERATETCP V_CCHECKSUMGENERATETCP(1U) 3555167514Skmacy 3556167514Skmacy#define S_CCHECKSUMGENERATEIP 4 3557167514Skmacy#define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP) 3558167514Skmacy#define F_CCHECKSUMGENERATEIP V_CCHECKSUMGENERATEIP(1U) 3559167514Skmacy 3560167514Skmacy#define S_OUT_CCPL 2 3561167514Skmacy#define V_OUT_CCPL(x) ((x) << S_OUT_CCPL) 3562167514Skmacy#define F_OUT_CCPL V_OUT_CCPL(1U) 3563167514Skmacy 3564167514Skmacy#define S_OUT_CETHERNET 0 3565167514Skmacy#define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET) 3566167514Skmacy#define F_OUT_CETHERNET V_OUT_CETHERNET(1U) 3567167514Skmacy 3568176472Skmacy#define A_TP_GLOBAL_CONFIG 0x308 3569167514Skmacy 3570176472Skmacy#define S_SYNCOOKIEPARAMS 26 3571176472Skmacy#define M_SYNCOOKIEPARAMS 0x3f 3572176472Skmacy#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) 3573176472Skmacy#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) 3574167514Skmacy 3575167514Skmacy#define S_RXFLOWCONTROLDISABLE 25 3576167514Skmacy#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) 3577167514Skmacy#define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) 3578167514Skmacy 3579167514Skmacy#define S_TXPACINGENABLE 24 3580167514Skmacy#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 3581167514Skmacy#define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 3582167514Skmacy 3583167514Skmacy#define S_ATTACKFILTERENABLE 23 3584167514Skmacy#define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE) 3585167514Skmacy#define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U) 3586167514Skmacy 3587167514Skmacy#define S_SYNCOOKIENOOPTIONS 22 3588167514Skmacy#define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS) 3589167514Skmacy#define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U) 3590167514Skmacy 3591167514Skmacy#define S_PROTECTEDMODE 21 3592167514Skmacy#define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE) 3593167514Skmacy#define F_PROTECTEDMODE V_PROTECTEDMODE(1U) 3594167514Skmacy 3595167514Skmacy#define S_PINGDROP 20 3596167514Skmacy#define V_PINGDROP(x) ((x) << S_PINGDROP) 3597167514Skmacy#define F_PINGDROP V_PINGDROP(1U) 3598167514Skmacy 3599167514Skmacy#define S_FRAGMENTDROP 19 3600167514Skmacy#define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP) 3601167514Skmacy#define F_FRAGMENTDROP V_FRAGMENTDROP(1U) 3602167514Skmacy 3603167514Skmacy#define S_FIVETUPLELOOKUP 17 3604167514Skmacy#define M_FIVETUPLELOOKUP 0x3 3605167514Skmacy#define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP) 3606167514Skmacy#define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP) 3607167514Skmacy 3608167514Skmacy#define S_PATHMTU 15 3609167514Skmacy#define V_PATHMTU(x) ((x) << S_PATHMTU) 3610167514Skmacy#define F_PATHMTU V_PATHMTU(1U) 3611167514Skmacy 3612167514Skmacy#define S_IPIDENTSPLIT 14 3613167514Skmacy#define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT) 3614167514Skmacy#define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U) 3615167514Skmacy 3616167514Skmacy#define S_IPCHECKSUMOFFLOAD 13 3617167514Skmacy#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) 3618167514Skmacy#define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) 3619167514Skmacy 3620167514Skmacy#define S_UDPCHECKSUMOFFLOAD 12 3621167514Skmacy#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD) 3622167514Skmacy#define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U) 3623167514Skmacy 3624167514Skmacy#define S_TCPCHECKSUMOFFLOAD 11 3625167514Skmacy#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) 3626167514Skmacy#define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) 3627167514Skmacy 3628167514Skmacy#define S_QOSMAPPING 10 3629167514Skmacy#define V_QOSMAPPING(x) ((x) << S_QOSMAPPING) 3630167514Skmacy#define F_QOSMAPPING V_QOSMAPPING(1U) 3631167514Skmacy 3632167514Skmacy#define S_TCAMSERVERUSE 8 3633167514Skmacy#define M_TCAMSERVERUSE 0x3 3634167514Skmacy#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) 3635167514Skmacy#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) 3636167514Skmacy 3637167514Skmacy#define S_IPTTL 0 3638167514Skmacy#define M_IPTTL 0xff 3639167514Skmacy#define V_IPTTL(x) ((x) << S_IPTTL) 3640167514Skmacy#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) 3641167514Skmacy 3642167514Skmacy#define A_TP_GLOBAL_RX_CREDIT 0x30c 3643167514Skmacy#define A_TP_CMM_SIZE 0x310 3644167514Skmacy 3645167514Skmacy#define S_CMMEMMGRSIZE 0 3646167514Skmacy#define M_CMMEMMGRSIZE 0xfffffff 3647167514Skmacy#define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) 3648167514Skmacy#define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) 3649167514Skmacy 3650167514Skmacy#define A_TP_CMM_MM_BASE 0x314 3651167514Skmacy 3652167514Skmacy#define S_CMMEMMGRBASE 0 3653167514Skmacy#define M_CMMEMMGRBASE 0xfffffff 3654167514Skmacy#define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) 3655167514Skmacy#define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) 3656167514Skmacy 3657167514Skmacy#define A_TP_CMM_TIMER_BASE 0x318 3658167514Skmacy 3659176472Skmacy#define S_CMTIMERMAXNUM 28 3660176472Skmacy#define M_CMTIMERMAXNUM 0x3 3661176472Skmacy#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) 3662176472Skmacy#define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM) 3663176472Skmacy 3664167514Skmacy#define S_CMTIMERBASE 0 3665167514Skmacy#define M_CMTIMERBASE 0xfffffff 3666167514Skmacy#define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) 3667167514Skmacy#define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) 3668167514Skmacy 3669167514Skmacy#define A_TP_PMM_SIZE 0x31c 3670167514Skmacy 3671167514Skmacy#define S_PMSIZE 0 3672167514Skmacy#define M_PMSIZE 0xfffffff 3673167514Skmacy#define V_PMSIZE(x) ((x) << S_PMSIZE) 3674167514Skmacy#define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) 3675167514Skmacy 3676167514Skmacy#define A_TP_PMM_TX_BASE 0x320 3677167514Skmacy#define A_TP_PMM_DEFRAG_BASE 0x324 3678167514Skmacy#define A_TP_PMM_RX_BASE 0x328 3679167514Skmacy#define A_TP_PMM_RX_PAGE_SIZE 0x32c 3680167514Skmacy#define A_TP_PMM_RX_MAX_PAGE 0x330 3681167514Skmacy 3682167514Skmacy#define S_PMRXMAXPAGE 0 3683167514Skmacy#define M_PMRXMAXPAGE 0x1fffff 3684167514Skmacy#define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE) 3685167514Skmacy#define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE) 3686167514Skmacy 3687167514Skmacy#define A_TP_PMM_TX_PAGE_SIZE 0x334 3688167514Skmacy#define A_TP_PMM_TX_MAX_PAGE 0x338 3689167514Skmacy 3690167514Skmacy#define S_PMTXMAXPAGE 0 3691167514Skmacy#define M_PMTXMAXPAGE 0x1fffff 3692167514Skmacy#define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE) 3693167514Skmacy#define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE) 3694167514Skmacy 3695167514Skmacy#define A_TP_TCP_OPTIONS 0x340 3696167514Skmacy 3697167514Skmacy#define S_MTUDEFAULT 16 3698167514Skmacy#define M_MTUDEFAULT 0xffff 3699167514Skmacy#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT) 3700167514Skmacy#define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT) 3701167514Skmacy 3702167514Skmacy#define S_MTUENABLE 10 3703167514Skmacy#define V_MTUENABLE(x) ((x) << S_MTUENABLE) 3704167514Skmacy#define F_MTUENABLE V_MTUENABLE(1U) 3705167514Skmacy 3706167514Skmacy#define S_SACKTX 9 3707167514Skmacy#define V_SACKTX(x) ((x) << S_SACKTX) 3708167514Skmacy#define F_SACKTX V_SACKTX(1U) 3709167514Skmacy 3710167514Skmacy#define S_SACKRX 8 3711167514Skmacy#define V_SACKRX(x) ((x) << S_SACKRX) 3712167514Skmacy#define F_SACKRX V_SACKRX(1U) 3713167514Skmacy 3714167514Skmacy#define S_SACKMODE 4 3715167514Skmacy#define M_SACKMODE 0x3 3716167514Skmacy#define V_SACKMODE(x) ((x) << S_SACKMODE) 3717167514Skmacy#define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE) 3718167514Skmacy 3719167514Skmacy#define S_WINDOWSCALEMODE 2 3720167514Skmacy#define M_WINDOWSCALEMODE 0x3 3721167514Skmacy#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE) 3722167514Skmacy#define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE) 3723167514Skmacy 3724167514Skmacy#define S_TIMESTAMPSMODE 0 3725167514Skmacy#define M_TIMESTAMPSMODE 0x3 3726167514Skmacy#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE) 3727167514Skmacy#define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE) 3728167514Skmacy 3729167514Skmacy#define A_TP_DACK_CONFIG 0x344 3730167514Skmacy 3731167514Skmacy#define S_AUTOSTATE3 30 3732167514Skmacy#define M_AUTOSTATE3 0x3 3733167514Skmacy#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) 3734167514Skmacy#define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3) 3735167514Skmacy 3736167514Skmacy#define S_AUTOSTATE2 28 3737167514Skmacy#define M_AUTOSTATE2 0x3 3738167514Skmacy#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) 3739167514Skmacy#define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2) 3740167514Skmacy 3741167514Skmacy#define S_AUTOSTATE1 26 3742167514Skmacy#define M_AUTOSTATE1 0x3 3743167514Skmacy#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) 3744167514Skmacy#define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1) 3745167514Skmacy 3746167514Skmacy#define S_BYTETHRESHOLD 5 3747167514Skmacy#define M_BYTETHRESHOLD 0xfffff 3748167514Skmacy#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) 3749167514Skmacy#define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD) 3750167514Skmacy 3751167514Skmacy#define S_MSSTHRESHOLD 3 3752167514Skmacy#define M_MSSTHRESHOLD 0x3 3753167514Skmacy#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) 3754167514Skmacy#define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD) 3755167514Skmacy 3756167514Skmacy#define S_AUTOCAREFUL 2 3757167514Skmacy#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL) 3758167514Skmacy#define F_AUTOCAREFUL V_AUTOCAREFUL(1U) 3759167514Skmacy 3760167514Skmacy#define S_AUTOENABLE 1 3761167514Skmacy#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE) 3762167514Skmacy#define F_AUTOENABLE V_AUTOENABLE(1U) 3763167514Skmacy 3764167514Skmacy#define S_DACK_MODE 0 3765167514Skmacy#define V_DACK_MODE(x) ((x) << S_DACK_MODE) 3766167514Skmacy#define F_DACK_MODE V_DACK_MODE(1U) 3767167514Skmacy 3768167514Skmacy#define A_TP_PC_CONFIG 0x348 3769167514Skmacy 3770176472Skmacy#define S_CMCACHEDISABLE 31 3771176472Skmacy#define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE) 3772176472Skmacy#define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U) 3773176472Skmacy 3774176472Skmacy#define S_ENABLEOCSPIFULL 30 3775176472Skmacy#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) 3776176472Skmacy#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) 3777176472Skmacy 3778176472Skmacy#define S_ENABLEFLMERRORDDP 29 3779176472Skmacy#define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP) 3780176472Skmacy#define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U) 3781176472Skmacy 3782176472Skmacy#define S_LOCKTID 28 3783176472Skmacy#define V_LOCKTID(x) ((x) << S_LOCKTID) 3784176472Skmacy#define F_LOCKTID V_LOCKTID(1U) 3785176472Skmacy 3786176472Skmacy#define S_FIXRCVWND 27 3787176472Skmacy#define V_FIXRCVWND(x) ((x) << S_FIXRCVWND) 3788176472Skmacy#define F_FIXRCVWND V_FIXRCVWND(1U) 3789176472Skmacy 3790167514Skmacy#define S_TXTOSQUEUEMAPMODE 26 3791167514Skmacy#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) 3792167514Skmacy#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) 3793167514Skmacy 3794167514Skmacy#define S_RDDPCONGEN 25 3795167514Skmacy#define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN) 3796167514Skmacy#define F_RDDPCONGEN V_RDDPCONGEN(1U) 3797167514Skmacy 3798167514Skmacy#define S_ENABLEONFLYPDU 24 3799167514Skmacy#define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU) 3800167514Skmacy#define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U) 3801167514Skmacy 3802167514Skmacy#define S_ENABLEEPCMDAFULL 23 3803167514Skmacy#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL) 3804167514Skmacy#define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U) 3805167514Skmacy 3806167514Skmacy#define S_MODULATEUNIONMODE 22 3807167514Skmacy#define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE) 3808167514Skmacy#define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U) 3809167514Skmacy 3810167514Skmacy#define S_TXDATAACKRATEENABLE 21 3811167514Skmacy#define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE) 3812167514Skmacy#define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U) 3813167514Skmacy 3814167514Skmacy#define S_TXDEFERENABLE 20 3815167514Skmacy#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE) 3816167514Skmacy#define F_TXDEFERENABLE V_TXDEFERENABLE(1U) 3817167514Skmacy 3818167514Skmacy#define S_RXCONGESTIONMODE 19 3819167514Skmacy#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE) 3820167514Skmacy#define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U) 3821167514Skmacy 3822167514Skmacy#define S_HEARBEATONCEDACK 18 3823167514Skmacy#define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK) 3824167514Skmacy#define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U) 3825167514Skmacy 3826167514Skmacy#define S_HEARBEATONCEHEAP 17 3827167514Skmacy#define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP) 3828167514Skmacy#define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U) 3829167514Skmacy 3830167514Skmacy#define S_HEARBEATDACK 16 3831167514Skmacy#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK) 3832167514Skmacy#define F_HEARBEATDACK V_HEARBEATDACK(1U) 3833167514Skmacy 3834167514Skmacy#define S_TXCONGESTIONMODE 15 3835167514Skmacy#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE) 3836167514Skmacy#define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U) 3837167514Skmacy 3838167514Skmacy#define S_ACCEPTLATESTRCVADV 14 3839167514Skmacy#define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV) 3840167514Skmacy#define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U) 3841167514Skmacy 3842167514Skmacy#define S_DISABLESYNDATA 13 3843167514Skmacy#define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA) 3844167514Skmacy#define F_DISABLESYNDATA V_DISABLESYNDATA(1U) 3845167514Skmacy 3846167514Skmacy#define S_DISABLEWINDOWPSH 12 3847167514Skmacy#define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH) 3848167514Skmacy#define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U) 3849167514Skmacy 3850167514Skmacy#define S_DISABLEFINOLDDATA 11 3851167514Skmacy#define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA) 3852167514Skmacy#define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U) 3853167514Skmacy 3854167514Skmacy#define S_ENABLEFLMERROR 10 3855167514Skmacy#define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR) 3856167514Skmacy#define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U) 3857167514Skmacy 3858167514Skmacy#define S_DISABLENEXTMTU 9 3859167514Skmacy#define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU) 3860167514Skmacy#define F_DISABLENEXTMTU V_DISABLENEXTMTU(1U) 3861167514Skmacy 3862167514Skmacy#define S_FILTERPEERFIN 8 3863167514Skmacy#define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN) 3864167514Skmacy#define F_FILTERPEERFIN V_FILTERPEERFIN(1U) 3865167514Skmacy 3866167514Skmacy#define S_ENABLEFEEDBACKSEND 7 3867167514Skmacy#define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND) 3868167514Skmacy#define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U) 3869167514Skmacy 3870167514Skmacy#define S_ENABLERDMAERROR 6 3871167514Skmacy#define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR) 3872167514Skmacy#define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U) 3873167514Skmacy 3874167514Skmacy#define S_ENABLEDDPFLOWCONTROL 5 3875167514Skmacy#define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL) 3876167514Skmacy#define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U) 3877167514Skmacy 3878167514Skmacy#define S_DISABLEHELDFIN 4 3879167514Skmacy#define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN) 3880167514Skmacy#define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U) 3881167514Skmacy 3882167514Skmacy#define S_TABLELATENCYDELTA 0 3883167514Skmacy#define M_TABLELATENCYDELTA 0xf 3884167514Skmacy#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) 3885167514Skmacy#define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) 3886167514Skmacy 3887176472Skmacy#define A_TP_PC_CONFIG2 0x34c 3888167514Skmacy 3889176472Skmacy#define S_DISBLEDAPARBIT0 15 3890176472Skmacy#define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0) 3891176472Skmacy#define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U) 3892167514Skmacy 3893176472Skmacy#define S_ENABLEARPMISS 13 3894176472Skmacy#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS) 3895176472Skmacy#define F_ENABLEARPMISS V_ENABLEARPMISS(1U) 3896167514Skmacy 3897176472Skmacy#define S_ENABLENONOFDTNLSYN 12 3898176472Skmacy#define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN) 3899176472Skmacy#define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U) 3900167514Skmacy 3901176472Skmacy#define S_ENABLEIPV6RSS 11 3902176472Skmacy#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS) 3903176472Skmacy#define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U) 3904167514Skmacy 3905167514Skmacy#define S_ENABLEDROPRQEMPTYPKT 10 3906167514Skmacy#define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT) 3907167514Skmacy#define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U) 3908167514Skmacy 3909167514Skmacy#define S_ENABLETXPORTFROMDA2 9 3910167514Skmacy#define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2) 3911167514Skmacy#define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U) 3912167514Skmacy 3913167514Skmacy#define S_ENABLERXPKTTMSTPRSS 8 3914167514Skmacy#define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS) 3915167514Skmacy#define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U) 3916167514Skmacy 3917167514Skmacy#define S_ENABLESNDUNAINRXDATA 7 3918167514Skmacy#define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA) 3919167514Skmacy#define F_ENABLESNDUNAINRXDATA V_ENABLESNDUNAINRXDATA(1U) 3920167514Skmacy 3921167514Skmacy#define S_ENABLERXPORTFROMADDR 6 3922167514Skmacy#define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR) 3923167514Skmacy#define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U) 3924167514Skmacy 3925167514Skmacy#define S_ENABLETXPORTFROMDA 5 3926167514Skmacy#define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA) 3927167514Skmacy#define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U) 3928167514Skmacy 3929176472Skmacy#define S_ENABLECHDRAFULL 4 3930176472Skmacy#define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL) 3931176472Skmacy#define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U) 3932167514Skmacy 3933167514Skmacy#define S_ENABLENONOFDSCBBIT 3 3934167514Skmacy#define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT) 3935167514Skmacy#define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U) 3936167514Skmacy 3937167514Skmacy#define S_ENABLENONOFDTIDRSS 2 3938167514Skmacy#define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS) 3939167514Skmacy#define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U) 3940167514Skmacy 3941167514Skmacy#define S_ENABLENONOFDTCBRSS 1 3942167514Skmacy#define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS) 3943167514Skmacy#define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U) 3944167514Skmacy 3945167514Skmacy#define S_ENABLEOLDRXFORWARD 0 3946167514Skmacy#define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD) 3947167514Skmacy#define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U) 3948167514Skmacy 3949176472Skmacy#define S_CHDRAFULL 4 3950176472Skmacy#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) 3951176472Skmacy#define F_CHDRAFULL V_CHDRAFULL(1U) 3952176472Skmacy 3953167514Skmacy#define A_TP_TCP_BACKOFF_REG0 0x350 3954167514Skmacy 3955167514Skmacy#define S_TIMERBACKOFFINDEX3 24 3956167514Skmacy#define M_TIMERBACKOFFINDEX3 0xff 3957167514Skmacy#define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3) 3958167514Skmacy#define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3) 3959167514Skmacy 3960167514Skmacy#define S_TIMERBACKOFFINDEX2 16 3961167514Skmacy#define M_TIMERBACKOFFINDEX2 0xff 3962167514Skmacy#define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2) 3963167514Skmacy#define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2) 3964167514Skmacy 3965167514Skmacy#define S_TIMERBACKOFFINDEX1 8 3966167514Skmacy#define M_TIMERBACKOFFINDEX1 0xff 3967167514Skmacy#define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1) 3968167514Skmacy#define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1) 3969167514Skmacy 3970167514Skmacy#define S_TIMERBACKOFFINDEX0 0 3971167514Skmacy#define M_TIMERBACKOFFINDEX0 0xff 3972167514Skmacy#define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0) 3973167514Skmacy#define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0) 3974167514Skmacy 3975167514Skmacy#define A_TP_TCP_BACKOFF_REG1 0x354 3976167514Skmacy 3977167514Skmacy#define S_TIMERBACKOFFINDEX7 24 3978167514Skmacy#define M_TIMERBACKOFFINDEX7 0xff 3979167514Skmacy#define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7) 3980167514Skmacy#define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7) 3981167514Skmacy 3982167514Skmacy#define S_TIMERBACKOFFINDEX6 16 3983167514Skmacy#define M_TIMERBACKOFFINDEX6 0xff 3984167514Skmacy#define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6) 3985167514Skmacy#define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6) 3986167514Skmacy 3987167514Skmacy#define S_TIMERBACKOFFINDEX5 8 3988167514Skmacy#define M_TIMERBACKOFFINDEX5 0xff 3989167514Skmacy#define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5) 3990167514Skmacy#define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5) 3991167514Skmacy 3992167514Skmacy#define S_TIMERBACKOFFINDEX4 0 3993167514Skmacy#define M_TIMERBACKOFFINDEX4 0xff 3994167514Skmacy#define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4) 3995167514Skmacy#define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4) 3996167514Skmacy 3997167514Skmacy#define A_TP_TCP_BACKOFF_REG2 0x358 3998167514Skmacy 3999167514Skmacy#define S_TIMERBACKOFFINDEX11 24 4000167514Skmacy#define M_TIMERBACKOFFINDEX11 0xff 4001167514Skmacy#define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11) 4002167514Skmacy#define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11) 4003167514Skmacy 4004167514Skmacy#define S_TIMERBACKOFFINDEX10 16 4005167514Skmacy#define M_TIMERBACKOFFINDEX10 0xff 4006167514Skmacy#define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10) 4007167514Skmacy#define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10) 4008167514Skmacy 4009167514Skmacy#define S_TIMERBACKOFFINDEX9 8 4010167514Skmacy#define M_TIMERBACKOFFINDEX9 0xff 4011167514Skmacy#define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9) 4012167514Skmacy#define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9) 4013167514Skmacy 4014167514Skmacy#define S_TIMERBACKOFFINDEX8 0 4015167514Skmacy#define M_TIMERBACKOFFINDEX8 0xff 4016167514Skmacy#define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8) 4017167514Skmacy#define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8) 4018167514Skmacy 4019167514Skmacy#define A_TP_TCP_BACKOFF_REG3 0x35c 4020167514Skmacy 4021167514Skmacy#define S_TIMERBACKOFFINDEX15 24 4022167514Skmacy#define M_TIMERBACKOFFINDEX15 0xff 4023167514Skmacy#define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15) 4024167514Skmacy#define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15) 4025167514Skmacy 4026167514Skmacy#define S_TIMERBACKOFFINDEX14 16 4027167514Skmacy#define M_TIMERBACKOFFINDEX14 0xff 4028167514Skmacy#define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14) 4029167514Skmacy#define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14) 4030167514Skmacy 4031167514Skmacy#define S_TIMERBACKOFFINDEX13 8 4032167514Skmacy#define M_TIMERBACKOFFINDEX13 0xff 4033167514Skmacy#define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13) 4034167514Skmacy#define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13) 4035167514Skmacy 4036167514Skmacy#define S_TIMERBACKOFFINDEX12 0 4037167514Skmacy#define M_TIMERBACKOFFINDEX12 0xff 4038167514Skmacy#define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12) 4039167514Skmacy#define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12) 4040167514Skmacy 4041167514Skmacy#define A_TP_PARA_REG0 0x360 4042167514Skmacy 4043167514Skmacy#define S_INITCWND 24 4044167514Skmacy#define M_INITCWND 0x7 4045167514Skmacy#define V_INITCWND(x) ((x) << S_INITCWND) 4046167514Skmacy#define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND) 4047167514Skmacy 4048167514Skmacy#define S_DUPACKTHRESH 20 4049167514Skmacy#define M_DUPACKTHRESH 0xf 4050167514Skmacy#define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH) 4051167514Skmacy#define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH) 4052167514Skmacy 4053167514Skmacy#define A_TP_PARA_REG1 0x364 4054167514Skmacy 4055167514Skmacy#define S_INITRWND 16 4056167514Skmacy#define M_INITRWND 0xffff 4057167514Skmacy#define V_INITRWND(x) ((x) << S_INITRWND) 4058167514Skmacy#define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND) 4059167514Skmacy 4060167514Skmacy#define S_INITIALSSTHRESH 0 4061167514Skmacy#define M_INITIALSSTHRESH 0xffff 4062167514Skmacy#define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH) 4063167514Skmacy#define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH) 4064167514Skmacy 4065167514Skmacy#define A_TP_PARA_REG2 0x368 4066167514Skmacy 4067167514Skmacy#define S_MAXRXDATA 16 4068167514Skmacy#define M_MAXRXDATA 0xffff 4069167514Skmacy#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) 4070167514Skmacy#define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA) 4071167514Skmacy 4072167514Skmacy#define S_RXCOALESCESIZE 0 4073167514Skmacy#define M_RXCOALESCESIZE 0xffff 4074167514Skmacy#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) 4075167514Skmacy#define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE) 4076167514Skmacy 4077167514Skmacy#define A_TP_PARA_REG3 0x36c 4078167514Skmacy 4079167514Skmacy#define S_TUNNELCNGDROP1 21 4080167514Skmacy#define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1) 4081167514Skmacy#define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U) 4082167514Skmacy 4083167514Skmacy#define S_TUNNELCNGDROP0 20 4084167514Skmacy#define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0) 4085167514Skmacy#define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U) 4086167514Skmacy 4087167514Skmacy#define S_TXDATAACKIDX 16 4088167514Skmacy#define M_TXDATAACKIDX 0xf 4089167514Skmacy#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX) 4090167514Skmacy#define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX) 4091167514Skmacy 4092167514Skmacy#define S_RXFRAGENABLE 12 4093167514Skmacy#define M_RXFRAGENABLE 0x7 4094167514Skmacy#define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE) 4095167514Skmacy#define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE) 4096167514Skmacy 4097167514Skmacy#define S_TXPACEFIXEDSTRICT 11 4098167514Skmacy#define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT) 4099167514Skmacy#define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U) 4100167514Skmacy 4101167514Skmacy#define S_TXPACEAUTOSTRICT 10 4102167514Skmacy#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT) 4103167514Skmacy#define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U) 4104167514Skmacy 4105167514Skmacy#define S_TXPACEFIXED 9 4106167514Skmacy#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) 4107167514Skmacy#define F_TXPACEFIXED V_TXPACEFIXED(1U) 4108167514Skmacy 4109167514Skmacy#define S_TXPACEAUTO 8 4110167514Skmacy#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) 4111167514Skmacy#define F_TXPACEAUTO V_TXPACEAUTO(1U) 4112167514Skmacy 4113176472Skmacy#define S_RXURGTUNNEL 6 4114176472Skmacy#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) 4115176472Skmacy#define F_RXURGTUNNEL V_RXURGTUNNEL(1U) 4116176472Skmacy 4117167514Skmacy#define S_RXURGMODE 5 4118167514Skmacy#define V_RXURGMODE(x) ((x) << S_RXURGMODE) 4119167514Skmacy#define F_RXURGMODE V_RXURGMODE(1U) 4120167514Skmacy 4121167514Skmacy#define S_TXURGMODE 4 4122167514Skmacy#define V_TXURGMODE(x) ((x) << S_TXURGMODE) 4123167514Skmacy#define F_TXURGMODE V_TXURGMODE(1U) 4124167514Skmacy 4125167514Skmacy#define S_CNGCTRLMODE 2 4126167514Skmacy#define M_CNGCTRLMODE 0x3 4127167514Skmacy#define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE) 4128167514Skmacy#define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE) 4129167514Skmacy 4130167514Skmacy#define S_RXCOALESCEENABLE 1 4131167514Skmacy#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) 4132167514Skmacy#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) 4133167514Skmacy 4134167514Skmacy#define S_RXCOALESCEPSHEN 0 4135167514Skmacy#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) 4136167514Skmacy#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) 4137167514Skmacy 4138167514Skmacy#define A_TP_PARA_REG4 0x370 4139167514Skmacy 4140167514Skmacy#define S_HIGHSPEEDCFG 24 4141167514Skmacy#define M_HIGHSPEEDCFG 0xff 4142167514Skmacy#define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG) 4143167514Skmacy#define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG) 4144167514Skmacy 4145167514Skmacy#define S_NEWRENOCFG 16 4146167514Skmacy#define M_NEWRENOCFG 0xff 4147167514Skmacy#define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG) 4148167514Skmacy#define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG) 4149167514Skmacy 4150167514Skmacy#define S_TAHOECFG 8 4151167514Skmacy#define M_TAHOECFG 0xff 4152167514Skmacy#define V_TAHOECFG(x) ((x) << S_TAHOECFG) 4153167514Skmacy#define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG) 4154167514Skmacy 4155167514Skmacy#define S_RENOCFG 0 4156167514Skmacy#define M_RENOCFG 0xff 4157167514Skmacy#define V_RENOCFG(x) ((x) << S_RENOCFG) 4158167514Skmacy#define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG) 4159167514Skmacy 4160167514Skmacy#define A_TP_PARA_REG5 0x374 4161167514Skmacy 4162167514Skmacy#define S_INDICATESIZE 16 4163167514Skmacy#define M_INDICATESIZE 0xffff 4164167514Skmacy#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) 4165167514Skmacy#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) 4166167514Skmacy 4167167514Skmacy#define S_SCHDENABLE 8 4168167514Skmacy#define V_SCHDENABLE(x) ((x) << S_SCHDENABLE) 4169167514Skmacy#define F_SCHDENABLE V_SCHDENABLE(1U) 4170167514Skmacy 4171176472Skmacy#define S_RXDDPOFFINIT 3 4172176472Skmacy#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT) 4173176472Skmacy#define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U) 4174176472Skmacy 4175167514Skmacy#define S_ONFLYDDPENABLE 2 4176167514Skmacy#define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE) 4177167514Skmacy#define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U) 4178167514Skmacy 4179167514Skmacy#define S_DACKTIMERSPIN 1 4180167514Skmacy#define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN) 4181167514Skmacy#define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U) 4182167514Skmacy 4183167514Skmacy#define S_PUSHTIMERENABLE 0 4184167514Skmacy#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) 4185167514Skmacy#define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) 4186167514Skmacy 4187167514Skmacy#define A_TP_PARA_REG6 0x378 4188167514Skmacy 4189167514Skmacy#define S_TXPDUSIZEADJ 16 4190167514Skmacy#define M_TXPDUSIZEADJ 0xff 4191167514Skmacy#define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) 4192167514Skmacy#define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) 4193167514Skmacy 4194176472Skmacy#define S_ENABLEDEFERACK 12 4195176472Skmacy#define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK) 4196176472Skmacy#define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U) 4197167514Skmacy 4198176472Skmacy#define S_ENABLEESND 11 4199176472Skmacy#define V_ENABLEESND(x) ((x) << S_ENABLEESND) 4200176472Skmacy#define F_ENABLEESND V_ENABLEESND(1U) 4201167514Skmacy 4202176472Skmacy#define S_ENABLECSND 10 4203176472Skmacy#define V_ENABLECSND(x) ((x) << S_ENABLECSND) 4204176472Skmacy#define F_ENABLECSND V_ENABLECSND(1U) 4205167514Skmacy 4206176472Skmacy#define S_ENABLEPDUE 9 4207176472Skmacy#define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE) 4208176472Skmacy#define F_ENABLEPDUE V_ENABLEPDUE(1U) 4209167514Skmacy 4210167514Skmacy#define S_ENABLEPDUC 8 4211167514Skmacy#define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC) 4212167514Skmacy#define F_ENABLEPDUC V_ENABLEPDUC(1U) 4213167514Skmacy 4214176472Skmacy#define S_ENABLEBUFI 7 4215176472Skmacy#define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI) 4216176472Skmacy#define F_ENABLEBUFI V_ENABLEBUFI(1U) 4217167514Skmacy 4218176472Skmacy#define S_ENABLEBUFE 6 4219176472Skmacy#define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE) 4220176472Skmacy#define F_ENABLEBUFE V_ENABLEBUFE(1U) 4221167514Skmacy 4222167514Skmacy#define S_ENABLEDEFER 5 4223167514Skmacy#define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER) 4224167514Skmacy#define F_ENABLEDEFER V_ENABLEDEFER(1U) 4225167514Skmacy 4226167514Skmacy#define S_ENABLECLEARRXMTOOS 4 4227167514Skmacy#define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS) 4228167514Skmacy#define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U) 4229167514Skmacy 4230167514Skmacy#define S_DISABLEPDUCNG 3 4231167514Skmacy#define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG) 4232167514Skmacy#define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U) 4233167514Skmacy 4234167514Skmacy#define S_DISABLEPDUTIMEOUT 2 4235167514Skmacy#define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT) 4236167514Skmacy#define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U) 4237167514Skmacy 4238167514Skmacy#define S_DISABLEPDURXMT 1 4239167514Skmacy#define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT) 4240167514Skmacy#define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U) 4241167514Skmacy 4242167514Skmacy#define S_DISABLEPDUXMT 0 4243167514Skmacy#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) 4244167514Skmacy#define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) 4245167514Skmacy 4246176472Skmacy#define S_ENABLEEPDU 14 4247176472Skmacy#define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU) 4248176472Skmacy#define F_ENABLEEPDU V_ENABLEEPDU(1U) 4249167514Skmacy 4250176472Skmacy#define S_T3A_ENABLEESND 13 4251176472Skmacy#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) 4252176472Skmacy#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) 4253167514Skmacy 4254176472Skmacy#define S_T3A_ENABLECSND 12 4255176472Skmacy#define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND) 4256176472Skmacy#define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U) 4257167514Skmacy 4258176472Skmacy#define S_T3A_ENABLEDEFERACK 9 4259176472Skmacy#define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK) 4260176472Skmacy#define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U) 4261167514Skmacy 4262176472Skmacy#define S_ENABLEPDUI 7 4263176472Skmacy#define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI) 4264176472Skmacy#define F_ENABLEPDUI V_ENABLEPDUI(1U) 4265167514Skmacy 4266176472Skmacy#define S_T3A_ENABLEPDUE 6 4267176472Skmacy#define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE) 4268176472Skmacy#define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U) 4269167514Skmacy 4270167514Skmacy#define A_TP_PARA_REG7 0x37c 4271167514Skmacy 4272167514Skmacy#define S_PMMAXXFERLEN1 16 4273167514Skmacy#define M_PMMAXXFERLEN1 0xffff 4274167514Skmacy#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) 4275167514Skmacy#define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1) 4276167514Skmacy 4277167514Skmacy#define S_PMMAXXFERLEN0 0 4278167514Skmacy#define M_PMMAXXFERLEN0 0xffff 4279167514Skmacy#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0) 4280167514Skmacy#define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0) 4281167514Skmacy 4282167514Skmacy#define A_TP_TIMER_RESOLUTION 0x390 4283167514Skmacy 4284167514Skmacy#define S_TIMERRESOLUTION 16 4285167514Skmacy#define M_TIMERRESOLUTION 0xff 4286167514Skmacy#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) 4287167514Skmacy#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION) 4288167514Skmacy 4289167514Skmacy#define S_TIMESTAMPRESOLUTION 8 4290167514Skmacy#define M_TIMESTAMPRESOLUTION 0xff 4291167514Skmacy#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) 4292167514Skmacy#define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION) 4293167514Skmacy 4294167514Skmacy#define S_DELAYEDACKRESOLUTION 0 4295167514Skmacy#define M_DELAYEDACKRESOLUTION 0xff 4296167514Skmacy#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) 4297167514Skmacy#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION) 4298167514Skmacy 4299167514Skmacy#define A_TP_MSL 0x394 4300167514Skmacy 4301167514Skmacy#define S_MSL 0 4302167514Skmacy#define M_MSL 0x3fffffff 4303167514Skmacy#define V_MSL(x) ((x) << S_MSL) 4304167514Skmacy#define G_MSL(x) (((x) >> S_MSL) & M_MSL) 4305167514Skmacy 4306167514Skmacy#define A_TP_RXT_MIN 0x398 4307167514Skmacy 4308167514Skmacy#define S_RXTMIN 0 4309167514Skmacy#define M_RXTMIN 0x3fffffff 4310167514Skmacy#define V_RXTMIN(x) ((x) << S_RXTMIN) 4311167514Skmacy#define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN) 4312167514Skmacy 4313167514Skmacy#define A_TP_RXT_MAX 0x39c 4314167514Skmacy 4315167514Skmacy#define S_RXTMAX 0 4316167514Skmacy#define M_RXTMAX 0x3fffffff 4317167514Skmacy#define V_RXTMAX(x) ((x) << S_RXTMAX) 4318167514Skmacy#define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX) 4319167514Skmacy 4320167514Skmacy#define A_TP_PERS_MIN 0x3a0 4321167514Skmacy 4322167514Skmacy#define S_PERSMIN 0 4323167514Skmacy#define M_PERSMIN 0x3fffffff 4324167514Skmacy#define V_PERSMIN(x) ((x) << S_PERSMIN) 4325167514Skmacy#define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN) 4326167514Skmacy 4327167514Skmacy#define A_TP_PERS_MAX 0x3a4 4328167514Skmacy 4329167514Skmacy#define S_PERSMAX 0 4330167514Skmacy#define M_PERSMAX 0x3fffffff 4331167514Skmacy#define V_PERSMAX(x) ((x) << S_PERSMAX) 4332167514Skmacy#define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX) 4333167514Skmacy 4334167514Skmacy#define A_TP_KEEP_IDLE 0x3a8 4335167514Skmacy 4336167514Skmacy#define S_KEEPALIVEIDLE 0 4337167514Skmacy#define M_KEEPALIVEIDLE 0x3fffffff 4338167514Skmacy#define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE) 4339167514Skmacy#define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE) 4340167514Skmacy 4341167514Skmacy#define A_TP_KEEP_INTVL 0x3ac 4342167514Skmacy 4343167514Skmacy#define S_KEEPALIVEINTVL 0 4344167514Skmacy#define M_KEEPALIVEINTVL 0x3fffffff 4345167514Skmacy#define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL) 4346167514Skmacy#define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL) 4347167514Skmacy 4348167514Skmacy#define A_TP_INIT_SRTT 0x3b0 4349167514Skmacy 4350167514Skmacy#define S_INITSRTT 0 4351167514Skmacy#define M_INITSRTT 0xffff 4352167514Skmacy#define V_INITSRTT(x) ((x) << S_INITSRTT) 4353167514Skmacy#define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT) 4354167514Skmacy 4355167514Skmacy#define A_TP_DACK_TIMER 0x3b4 4356167514Skmacy 4357167514Skmacy#define S_DACKTIME 0 4358167514Skmacy#define M_DACKTIME 0xfff 4359167514Skmacy#define V_DACKTIME(x) ((x) << S_DACKTIME) 4360167514Skmacy#define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME) 4361167514Skmacy 4362167514Skmacy#define A_TP_FINWAIT2_TIMER 0x3b8 4363167514Skmacy 4364167514Skmacy#define S_FINWAIT2TIME 0 4365167514Skmacy#define M_FINWAIT2TIME 0x3fffffff 4366167514Skmacy#define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME) 4367167514Skmacy#define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME) 4368167514Skmacy 4369167514Skmacy#define A_TP_FAST_FINWAIT2_TIMER 0x3bc 4370167514Skmacy 4371167514Skmacy#define S_FASTFINWAIT2TIME 0 4372167514Skmacy#define M_FASTFINWAIT2TIME 0x3fffffff 4373167514Skmacy#define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME) 4374167514Skmacy#define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME) 4375167514Skmacy 4376167514Skmacy#define A_TP_SHIFT_CNT 0x3c0 4377167514Skmacy 4378167514Skmacy#define S_SYNSHIFTMAX 24 4379167514Skmacy#define M_SYNSHIFTMAX 0xff 4380167514Skmacy#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) 4381167514Skmacy#define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX) 4382167514Skmacy 4383167514Skmacy#define S_RXTSHIFTMAXR1 20 4384167514Skmacy#define M_RXTSHIFTMAXR1 0xf 4385167514Skmacy#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) 4386167514Skmacy#define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1) 4387167514Skmacy 4388167514Skmacy#define S_RXTSHIFTMAXR2 16 4389167514Skmacy#define M_RXTSHIFTMAXR2 0xf 4390167514Skmacy#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) 4391167514Skmacy#define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2) 4392167514Skmacy 4393167514Skmacy#define S_PERSHIFTBACKOFFMAX 12 4394167514Skmacy#define M_PERSHIFTBACKOFFMAX 0xf 4395167514Skmacy#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) 4396167514Skmacy#define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX) 4397167514Skmacy 4398167514Skmacy#define S_PERSHIFTMAX 8 4399167514Skmacy#define M_PERSHIFTMAX 0xf 4400167514Skmacy#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) 4401167514Skmacy#define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX) 4402167514Skmacy 4403167514Skmacy#define S_KEEPALIVEMAX 0 4404167514Skmacy#define M_KEEPALIVEMAX 0xff 4405167514Skmacy#define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX) 4406167514Skmacy#define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX) 4407167514Skmacy 4408167514Skmacy#define A_TP_TIME_HI 0x3c8 4409167514Skmacy#define A_TP_TIME_LO 0x3cc 4410167514Skmacy#define A_TP_MTU_PORT_TABLE 0x3d0 4411167514Skmacy 4412167514Skmacy#define S_PORT1MTUVALUE 16 4413167514Skmacy#define M_PORT1MTUVALUE 0xffff 4414167514Skmacy#define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE) 4415167514Skmacy#define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE) 4416167514Skmacy 4417167514Skmacy#define S_PORT0MTUVALUE 0 4418167514Skmacy#define M_PORT0MTUVALUE 0xffff 4419167514Skmacy#define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE) 4420167514Skmacy#define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE) 4421167514Skmacy 4422167514Skmacy#define A_TP_ULP_TABLE 0x3d4 4423167514Skmacy 4424167514Skmacy#define S_ULPTYPE7FIELD 28 4425167514Skmacy#define M_ULPTYPE7FIELD 0xf 4426167514Skmacy#define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD) 4427167514Skmacy#define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD) 4428167514Skmacy 4429167514Skmacy#define S_ULPTYPE6FIELD 24 4430167514Skmacy#define M_ULPTYPE6FIELD 0xf 4431167514Skmacy#define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD) 4432167514Skmacy#define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD) 4433167514Skmacy 4434167514Skmacy#define S_ULPTYPE5FIELD 20 4435167514Skmacy#define M_ULPTYPE5FIELD 0xf 4436167514Skmacy#define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD) 4437167514Skmacy#define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD) 4438167514Skmacy 4439167514Skmacy#define S_ULPTYPE4FIELD 16 4440167514Skmacy#define M_ULPTYPE4FIELD 0xf 4441167514Skmacy#define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD) 4442167514Skmacy#define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD) 4443167514Skmacy 4444167514Skmacy#define S_ULPTYPE3FIELD 12 4445167514Skmacy#define M_ULPTYPE3FIELD 0xf 4446167514Skmacy#define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD) 4447167514Skmacy#define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD) 4448167514Skmacy 4449167514Skmacy#define S_ULPTYPE2FIELD 8 4450167514Skmacy#define M_ULPTYPE2FIELD 0xf 4451167514Skmacy#define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD) 4452167514Skmacy#define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD) 4453167514Skmacy 4454167514Skmacy#define S_ULPTYPE1FIELD 4 4455167514Skmacy#define M_ULPTYPE1FIELD 0xf 4456167514Skmacy#define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD) 4457167514Skmacy#define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD) 4458167514Skmacy 4459167514Skmacy#define S_ULPTYPE0FIELD 0 4460167514Skmacy#define M_ULPTYPE0FIELD 0xf 4461167514Skmacy#define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD) 4462167514Skmacy#define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD) 4463167514Skmacy 4464167514Skmacy#define A_TP_PACE_TABLE 0x3d8 4465167514Skmacy#define A_TP_CCTRL_TABLE 0x3dc 4466167514Skmacy#define A_TP_TOS_TABLE 0x3e0 4467167514Skmacy#define A_TP_MTU_TABLE 0x3e4 4468167514Skmacy#define A_TP_RSS_MAP_TABLE 0x3e8 4469167514Skmacy#define A_TP_RSS_LKP_TABLE 0x3ec 4470167514Skmacy#define A_TP_RSS_CONFIG 0x3f0 4471167514Skmacy 4472167514Skmacy#define S_TNL4TUPEN 29 4473167514Skmacy#define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN) 4474167514Skmacy#define F_TNL4TUPEN V_TNL4TUPEN(1U) 4475167514Skmacy 4476167514Skmacy#define S_TNL2TUPEN 28 4477167514Skmacy#define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN) 4478167514Skmacy#define F_TNL2TUPEN V_TNL2TUPEN(1U) 4479167514Skmacy 4480167514Skmacy#define S_TNLPRTEN 26 4481167514Skmacy#define V_TNLPRTEN(x) ((x) << S_TNLPRTEN) 4482167514Skmacy#define F_TNLPRTEN V_TNLPRTEN(1U) 4483167514Skmacy 4484167514Skmacy#define S_TNLMAPEN 25 4485167514Skmacy#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN) 4486167514Skmacy#define F_TNLMAPEN V_TNLMAPEN(1U) 4487167514Skmacy 4488167514Skmacy#define S_TNLLKPEN 24 4489167514Skmacy#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN) 4490167514Skmacy#define F_TNLLKPEN V_TNLLKPEN(1U) 4491167514Skmacy 4492167514Skmacy#define S_OFD4TUPEN 21 4493167514Skmacy#define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN) 4494167514Skmacy#define F_OFD4TUPEN V_OFD4TUPEN(1U) 4495167514Skmacy 4496167514Skmacy#define S_OFD2TUPEN 20 4497167514Skmacy#define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN) 4498167514Skmacy#define F_OFD2TUPEN V_OFD2TUPEN(1U) 4499167514Skmacy 4500167514Skmacy#define S_OFDMAPEN 17 4501167514Skmacy#define V_OFDMAPEN(x) ((x) << S_OFDMAPEN) 4502167514Skmacy#define F_OFDMAPEN V_OFDMAPEN(1U) 4503167514Skmacy 4504167514Skmacy#define S_OFDLKPEN 16 4505167514Skmacy#define V_OFDLKPEN(x) ((x) << S_OFDLKPEN) 4506167514Skmacy#define F_OFDLKPEN V_OFDLKPEN(1U) 4507167514Skmacy 4508167514Skmacy#define S_SYN4TUPEN 13 4509167514Skmacy#define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN) 4510167514Skmacy#define F_SYN4TUPEN V_SYN4TUPEN(1U) 4511167514Skmacy 4512167514Skmacy#define S_SYN2TUPEN 12 4513167514Skmacy#define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN) 4514167514Skmacy#define F_SYN2TUPEN V_SYN2TUPEN(1U) 4515167514Skmacy 4516167514Skmacy#define S_SYNMAPEN 9 4517167514Skmacy#define V_SYNMAPEN(x) ((x) << S_SYNMAPEN) 4518167514Skmacy#define F_SYNMAPEN V_SYNMAPEN(1U) 4519167514Skmacy 4520167514Skmacy#define S_SYNLKPEN 8 4521167514Skmacy#define V_SYNLKPEN(x) ((x) << S_SYNLKPEN) 4522167514Skmacy#define F_SYNLKPEN V_SYNLKPEN(1U) 4523167514Skmacy 4524167514Skmacy#define S_RRCPLMAPEN 7 4525167514Skmacy#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) 4526167514Skmacy#define F_RRCPLMAPEN V_RRCPLMAPEN(1U) 4527167514Skmacy 4528167514Skmacy#define S_RRCPLCPUSIZE 4 4529167514Skmacy#define M_RRCPLCPUSIZE 0x7 4530167514Skmacy#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE) 4531167514Skmacy#define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE) 4532167514Skmacy 4533167514Skmacy#define S_RQFEEDBACKENABLE 3 4534167514Skmacy#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) 4535167514Skmacy#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) 4536167514Skmacy 4537167514Skmacy#define S_HASHTOEPLITZ 2 4538167514Skmacy#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) 4539167514Skmacy#define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) 4540167514Skmacy 4541167514Skmacy#define S_HASHSAVE 1 4542167514Skmacy#define V_HASHSAVE(x) ((x) << S_HASHSAVE) 4543167514Skmacy#define F_HASHSAVE V_HASHSAVE(1U) 4544167514Skmacy 4545167514Skmacy#define S_DISABLE 0 4546167514Skmacy#define V_DISABLE(x) ((x) << S_DISABLE) 4547167514Skmacy#define F_DISABLE V_DISABLE(1U) 4548167514Skmacy 4549167514Skmacy#define A_TP_RSS_CONFIG_TNL 0x3f4 4550167514Skmacy 4551167514Skmacy#define S_MASKSIZE 28 4552167514Skmacy#define M_MASKSIZE 0x7 4553167514Skmacy#define V_MASKSIZE(x) ((x) << S_MASKSIZE) 4554167514Skmacy#define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE) 4555167514Skmacy 4556167514Skmacy#define S_DEFAULTCPUBASE 22 4557167514Skmacy#define M_DEFAULTCPUBASE 0x3f 4558167514Skmacy#define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE) 4559167514Skmacy#define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE) 4560167514Skmacy 4561167514Skmacy#define S_DEFAULTCPU 16 4562167514Skmacy#define M_DEFAULTCPU 0x3f 4563167514Skmacy#define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU) 4564167514Skmacy#define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU) 4565167514Skmacy 4566167514Skmacy#define S_DEFAULTQUEUE 0 4567167514Skmacy#define M_DEFAULTQUEUE 0xffff 4568167514Skmacy#define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE) 4569167514Skmacy#define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE) 4570167514Skmacy 4571167514Skmacy#define A_TP_RSS_CONFIG_OFD 0x3f8 4572167514Skmacy#define A_TP_RSS_CONFIG_SYN 0x3fc 4573167514Skmacy#define A_TP_RSS_SECRET_KEY0 0x400 4574167514Skmacy#define A_TP_RSS_SECRET_KEY1 0x404 4575167514Skmacy#define A_TP_RSS_SECRET_KEY2 0x408 4576167514Skmacy#define A_TP_RSS_SECRET_KEY3 0x40c 4577167514Skmacy#define A_TP_TM_PIO_ADDR 0x418 4578167514Skmacy#define A_TP_TM_PIO_DATA 0x41c 4579167514Skmacy#define A_TP_TX_MOD_QUE_TABLE 0x420 4580167514Skmacy#define A_TP_TX_RESOURCE_LIMIT 0x424 4581167514Skmacy 4582167514Skmacy#define S_TX_RESOURCE_LIMIT_CH1_PC 24 4583167514Skmacy#define M_TX_RESOURCE_LIMIT_CH1_PC 0xff 4584167514Skmacy#define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC) 4585167514Skmacy#define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC) 4586167514Skmacy 4587167514Skmacy#define S_TX_RESOURCE_LIMIT_CH1_NON_PC 16 4588167514Skmacy#define M_TX_RESOURCE_LIMIT_CH1_NON_PC 0xff 4589167514Skmacy#define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC) 4590167514Skmacy#define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC) 4591167514Skmacy 4592167514Skmacy#define S_TX_RESOURCE_LIMIT_CH0_PC 8 4593167514Skmacy#define M_TX_RESOURCE_LIMIT_CH0_PC 0xff 4594167514Skmacy#define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC) 4595167514Skmacy#define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC) 4596167514Skmacy 4597167514Skmacy#define S_TX_RESOURCE_LIMIT_CH0_NON_PC 0 4598167514Skmacy#define M_TX_RESOURCE_LIMIT_CH0_NON_PC 0xff 4599167514Skmacy#define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC) 4600167514Skmacy#define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC) 4601167514Skmacy 4602167514Skmacy#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428 4603167514Skmacy 4604167514Skmacy#define S_RX_MOD_WEIGHT 24 4605167514Skmacy#define M_RX_MOD_WEIGHT 0xff 4606167514Skmacy#define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT) 4607167514Skmacy#define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT) 4608167514Skmacy 4609167514Skmacy#define S_TX_MOD_WEIGHT 16 4610167514Skmacy#define M_TX_MOD_WEIGHT 0xff 4611167514Skmacy#define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT) 4612167514Skmacy#define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT) 4613167514Skmacy 4614167746Skmacy#define S_TX_MOD_TIMER_MODE 8 4615167746Skmacy#define M_TX_MOD_TIMER_MODE 0xff 4616167514Skmacy#define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE) 4617167514Skmacy#define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE) 4618167514Skmacy 4619167514Skmacy#define S_TX_MOD_QUEUE_REQ_MAP 0 4620167514Skmacy#define M_TX_MOD_QUEUE_REQ_MAP 0xff 4621167514Skmacy#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 4622167514Skmacy#define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP) 4623167514Skmacy 4624167514Skmacy#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c 4625167514Skmacy 4626167514Skmacy#define S_TP_TX_MODQ_WGHT7 24 4627167514Skmacy#define M_TP_TX_MODQ_WGHT7 0xff 4628167514Skmacy#define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7) 4629167514Skmacy#define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7) 4630167514Skmacy 4631167514Skmacy#define S_TP_TX_MODQ_WGHT6 16 4632167514Skmacy#define M_TP_TX_MODQ_WGHT6 0xff 4633167514Skmacy#define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6) 4634167514Skmacy#define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6) 4635167514Skmacy 4636167514Skmacy#define S_TP_TX_MODQ_WGHT5 8 4637167514Skmacy#define M_TP_TX_MODQ_WGHT5 0xff 4638167514Skmacy#define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5) 4639167514Skmacy#define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5) 4640167514Skmacy 4641167514Skmacy#define S_TP_TX_MODQ_WGHT4 0 4642167514Skmacy#define M_TP_TX_MODQ_WGHT4 0xff 4643167514Skmacy#define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4) 4644167514Skmacy#define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4) 4645167514Skmacy 4646167514Skmacy#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430 4647167514Skmacy 4648167514Skmacy#define S_TP_TX_MODQ_WGHT3 24 4649167514Skmacy#define M_TP_TX_MODQ_WGHT3 0xff 4650167514Skmacy#define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3) 4651167514Skmacy#define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3) 4652167514Skmacy 4653167514Skmacy#define S_TP_TX_MODQ_WGHT2 16 4654167514Skmacy#define M_TP_TX_MODQ_WGHT2 0xff 4655167514Skmacy#define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2) 4656167514Skmacy#define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2) 4657167514Skmacy 4658167514Skmacy#define S_TP_TX_MODQ_WGHT1 8 4659167514Skmacy#define M_TP_TX_MODQ_WGHT1 0xff 4660167514Skmacy#define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1) 4661167514Skmacy#define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1) 4662167514Skmacy 4663167514Skmacy#define S_TP_TX_MODQ_WGHT0 0 4664167514Skmacy#define M_TP_TX_MODQ_WGHT0 0xff 4665167514Skmacy#define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0) 4666167514Skmacy#define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0) 4667167514Skmacy 4668167514Skmacy#define A_TP_MOD_CHANNEL_WEIGHT 0x434 4669167514Skmacy 4670167514Skmacy#define S_RX_MOD_CHANNEL_WEIGHT1 24 4671167514Skmacy#define M_RX_MOD_CHANNEL_WEIGHT1 0xff 4672167514Skmacy#define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1) 4673167514Skmacy#define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1) 4674167514Skmacy 4675167514Skmacy#define S_RX_MOD_CHANNEL_WEIGHT0 16 4676167514Skmacy#define M_RX_MOD_CHANNEL_WEIGHT0 0xff 4677167514Skmacy#define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0) 4678167514Skmacy#define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0) 4679167514Skmacy 4680167514Skmacy#define S_TX_MOD_CHANNEL_WEIGHT1 8 4681167514Skmacy#define M_TX_MOD_CHANNEL_WEIGHT1 0xff 4682167514Skmacy#define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1) 4683167514Skmacy#define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1) 4684167514Skmacy 4685167514Skmacy#define S_TX_MOD_CHANNEL_WEIGHT0 0 4686167514Skmacy#define M_TX_MOD_CHANNEL_WEIGHT0 0xff 4687167514Skmacy#define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0) 4688167514Skmacy#define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0) 4689167514Skmacy 4690167514Skmacy#define A_TP_MOD_RATE_LIMIT 0x438 4691167514Skmacy 4692167514Skmacy#define S_RX_MOD_RATE_LIMIT_INC 24 4693167514Skmacy#define M_RX_MOD_RATE_LIMIT_INC 0xff 4694167514Skmacy#define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC) 4695167514Skmacy#define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC) 4696167514Skmacy 4697167514Skmacy#define S_RX_MOD_RATE_LIMIT_TICK 16 4698167514Skmacy#define M_RX_MOD_RATE_LIMIT_TICK 0xff 4699167514Skmacy#define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK) 4700167514Skmacy#define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK) 4701167514Skmacy 4702167514Skmacy#define S_TX_MOD_RATE_LIMIT_INC 8 4703167514Skmacy#define M_TX_MOD_RATE_LIMIT_INC 0xff 4704167514Skmacy#define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC) 4705167514Skmacy#define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC) 4706167514Skmacy 4707167514Skmacy#define S_TX_MOD_RATE_LIMIT_TICK 0 4708167514Skmacy#define M_TX_MOD_RATE_LIMIT_TICK 0xff 4709167514Skmacy#define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK) 4710167514Skmacy#define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK) 4711167514Skmacy 4712167514Skmacy#define A_TP_PIO_ADDR 0x440 4713167514Skmacy#define A_TP_PIO_DATA 0x444 4714167514Skmacy#define A_TP_RESET 0x44c 4715167514Skmacy 4716167514Skmacy#define S_FLSTINITENABLE 1 4717167514Skmacy#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE) 4718167514Skmacy#define F_FLSTINITENABLE V_FLSTINITENABLE(1U) 4719167514Skmacy 4720167514Skmacy#define S_TPRESET 0 4721167514Skmacy#define V_TPRESET(x) ((x) << S_TPRESET) 4722167514Skmacy#define F_TPRESET V_TPRESET(1U) 4723167514Skmacy 4724167514Skmacy#define A_TP_MIB_INDEX 0x450 4725167514Skmacy#define A_TP_MIB_RDATA 0x454 4726167514Skmacy#define A_TP_SYNC_TIME_HI 0x458 4727167514Skmacy#define A_TP_SYNC_TIME_LO 0x45c 4728167514Skmacy#define A_TP_CMM_MM_RX_FLST_BASE 0x460 4729167514Skmacy 4730167514Skmacy#define S_CMRXFLSTBASE 0 4731167514Skmacy#define M_CMRXFLSTBASE 0xfffffff 4732167514Skmacy#define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE) 4733167514Skmacy#define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE) 4734167514Skmacy 4735167514Skmacy#define A_TP_CMM_MM_TX_FLST_BASE 0x464 4736167514Skmacy 4737167514Skmacy#define S_CMTXFLSTBASE 0 4738167514Skmacy#define M_CMTXFLSTBASE 0xfffffff 4739167514Skmacy#define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE) 4740167514Skmacy#define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE) 4741167514Skmacy 4742167514Skmacy#define A_TP_CMM_MM_PS_FLST_BASE 0x468 4743167514Skmacy 4744167514Skmacy#define S_CMPSFLSTBASE 0 4745167514Skmacy#define M_CMPSFLSTBASE 0xfffffff 4746167514Skmacy#define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE) 4747167514Skmacy#define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE) 4748167514Skmacy 4749167514Skmacy#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c 4750167514Skmacy 4751167514Skmacy#define S_CMMAXPSTRUCT 0 4752167514Skmacy#define M_CMMAXPSTRUCT 0x1fffff 4753167514Skmacy#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) 4754167514Skmacy#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) 4755167514Skmacy 4756167514Skmacy#define A_TP_INT_ENABLE 0x470 4757176472Skmacy 4758176472Skmacy#define S_FLMTXFLSTEMPTY 30 4759176472Skmacy#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) 4760176472Skmacy#define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) 4761176472Skmacy 4762176472Skmacy#define S_FLMRXFLSTEMPTY 29 4763176472Skmacy#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) 4764176472Skmacy#define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) 4765176472Skmacy 4766176472Skmacy#define S_FLMPERRSET 28 4767176472Skmacy#define V_FLMPERRSET(x) ((x) << S_FLMPERRSET) 4768176472Skmacy#define F_FLMPERRSET V_FLMPERRSET(1U) 4769176472Skmacy 4770176472Skmacy#define S_PROTOCOLSRAMPERR 27 4771176472Skmacy#define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR) 4772176472Skmacy#define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U) 4773176472Skmacy 4774176472Skmacy#define S_ARPLUTPERR 26 4775176472Skmacy#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR) 4776176472Skmacy#define F_ARPLUTPERR V_ARPLUTPERR(1U) 4777176472Skmacy 4778176472Skmacy#define S_CMRCFOPPERR 25 4779176472Skmacy#define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR) 4780176472Skmacy#define F_CMRCFOPPERR V_CMRCFOPPERR(1U) 4781176472Skmacy 4782176472Skmacy#define S_CMCACHEPERR 24 4783176472Skmacy#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR) 4784176472Skmacy#define F_CMCACHEPERR V_CMCACHEPERR(1U) 4785176472Skmacy 4786176472Skmacy#define S_CMRCFDATAPERR 23 4787176472Skmacy#define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR) 4788176472Skmacy#define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U) 4789176472Skmacy 4790176472Skmacy#define S_DBL2TLUTPERR 22 4791176472Skmacy#define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR) 4792176472Skmacy#define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U) 4793176472Skmacy 4794176472Skmacy#define S_DBTXTIDPERR 21 4795176472Skmacy#define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR) 4796176472Skmacy#define F_DBTXTIDPERR V_DBTXTIDPERR(1U) 4797176472Skmacy 4798176472Skmacy#define S_DBEXTPERR 20 4799176472Skmacy#define V_DBEXTPERR(x) ((x) << S_DBEXTPERR) 4800176472Skmacy#define F_DBEXTPERR V_DBEXTPERR(1U) 4801176472Skmacy 4802176472Skmacy#define S_DBOPPERR 19 4803176472Skmacy#define V_DBOPPERR(x) ((x) << S_DBOPPERR) 4804176472Skmacy#define F_DBOPPERR V_DBOPPERR(1U) 4805176472Skmacy 4806176472Skmacy#define S_TMCACHEPERR 18 4807176472Skmacy#define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR) 4808176472Skmacy#define F_TMCACHEPERR V_TMCACHEPERR(1U) 4809176472Skmacy 4810176472Skmacy#define S_ETPOUTCPLFIFOPERR 17 4811176472Skmacy#define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR) 4812176472Skmacy#define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U) 4813176472Skmacy 4814176472Skmacy#define S_ETPOUTTCPFIFOPERR 16 4815176472Skmacy#define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR) 4816176472Skmacy#define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U) 4817176472Skmacy 4818176472Skmacy#define S_ETPOUTIPFIFOPERR 15 4819176472Skmacy#define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR) 4820176472Skmacy#define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U) 4821176472Skmacy 4822176472Skmacy#define S_ETPOUTETHFIFOPERR 14 4823176472Skmacy#define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR) 4824176472Skmacy#define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U) 4825176472Skmacy 4826176472Skmacy#define S_ETPINCPLFIFOPERR 13 4827176472Skmacy#define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR) 4828176472Skmacy#define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U) 4829176472Skmacy 4830176472Skmacy#define S_ETPINTCPOPTFIFOPERR 12 4831176472Skmacy#define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR) 4832176472Skmacy#define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U) 4833176472Skmacy 4834176472Skmacy#define S_ETPINTCPFIFOPERR 11 4835176472Skmacy#define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR) 4836176472Skmacy#define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U) 4837176472Skmacy 4838176472Skmacy#define S_ETPINIPFIFOPERR 10 4839176472Skmacy#define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR) 4840176472Skmacy#define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U) 4841176472Skmacy 4842176472Skmacy#define S_ETPINETHFIFOPERR 9 4843176472Skmacy#define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR) 4844176472Skmacy#define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U) 4845176472Skmacy 4846176472Skmacy#define S_CTPOUTCPLFIFOPERR 8 4847176472Skmacy#define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR) 4848176472Skmacy#define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U) 4849176472Skmacy 4850176472Skmacy#define S_CTPOUTTCPFIFOPERR 7 4851176472Skmacy#define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR) 4852176472Skmacy#define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U) 4853176472Skmacy 4854176472Skmacy#define S_CTPOUTIPFIFOPERR 6 4855176472Skmacy#define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR) 4856176472Skmacy#define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U) 4857176472Skmacy 4858176472Skmacy#define S_CTPOUTETHFIFOPERR 5 4859176472Skmacy#define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR) 4860176472Skmacy#define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U) 4861176472Skmacy 4862176472Skmacy#define S_CTPINCPLFIFOPERR 4 4863176472Skmacy#define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR) 4864176472Skmacy#define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U) 4865176472Skmacy 4866176472Skmacy#define S_CTPINTCPOPFIFOPERR 3 4867176472Skmacy#define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR) 4868176472Skmacy#define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U) 4869176472Skmacy 4870176472Skmacy#define S_CTPINTCPFIFOPERR 2 4871176472Skmacy#define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR) 4872176472Skmacy#define F_CTPINTCPFIFOPERR V_CTPINTCPFIFOPERR(1U) 4873176472Skmacy 4874176472Skmacy#define S_CTPINIPFIFOPERR 1 4875176472Skmacy#define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR) 4876176472Skmacy#define F_CTPINIPFIFOPERR V_CTPINIPFIFOPERR(1U) 4877176472Skmacy 4878176472Skmacy#define S_CTPINETHFIFOPERR 0 4879176472Skmacy#define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR) 4880176472Skmacy#define F_CTPINETHFIFOPERR V_CTPINETHFIFOPERR(1U) 4881176472Skmacy 4882167514Skmacy#define A_TP_INT_CAUSE 0x474 4883167514Skmacy#define A_TP_FLM_FREE_PS_CNT 0x480 4884167514Skmacy 4885167514Skmacy#define S_FREEPSTRUCTCOUNT 0 4886167514Skmacy#define M_FREEPSTRUCTCOUNT 0x1fffff 4887167514Skmacy#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT) 4888167514Skmacy#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT) 4889167514Skmacy 4890167514Skmacy#define A_TP_FLM_FREE_RX_CNT 0x484 4891167514Skmacy 4892167514Skmacy#define S_FREERXPAGECOUNT 0 4893167514Skmacy#define M_FREERXPAGECOUNT 0x1fffff 4894167514Skmacy#define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT) 4895167514Skmacy#define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT) 4896167514Skmacy 4897167514Skmacy#define A_TP_FLM_FREE_TX_CNT 0x488 4898167514Skmacy 4899167514Skmacy#define S_FREETXPAGECOUNT 0 4900167514Skmacy#define M_FREETXPAGECOUNT 0x1fffff 4901167514Skmacy#define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT) 4902167514Skmacy#define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT) 4903167514Skmacy 4904167514Skmacy#define A_TP_TM_HEAP_PUSH_CNT 0x48c 4905167514Skmacy#define A_TP_TM_HEAP_POP_CNT 0x490 4906167514Skmacy#define A_TP_TM_DACK_PUSH_CNT 0x494 4907167514Skmacy#define A_TP_TM_DACK_POP_CNT 0x498 4908167514Skmacy#define A_TP_TM_MOD_PUSH_CNT 0x49c 4909167514Skmacy#define A_TP_MOD_POP_CNT 0x4a0 4910167514Skmacy#define A_TP_TIMER_SEPARATOR 0x4a4 4911167514Skmacy#define A_TP_DEBUG_SEL 0x4a8 4912167514Skmacy#define A_TP_DEBUG_FLAGS 0x4ac 4913167514Skmacy 4914167514Skmacy#define S_RXTIMERDACKFIRST 26 4915167514Skmacy#define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST) 4916167514Skmacy#define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U) 4917167514Skmacy 4918167514Skmacy#define S_RXTIMERDACK 25 4919167514Skmacy#define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK) 4920167514Skmacy#define F_RXTIMERDACK V_RXTIMERDACK(1U) 4921167514Skmacy 4922167514Skmacy#define S_RXTIMERHEARTBEAT 24 4923167514Skmacy#define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT) 4924167514Skmacy#define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U) 4925167514Skmacy 4926167514Skmacy#define S_RXPAWSDROP 23 4927167514Skmacy#define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP) 4928167514Skmacy#define F_RXPAWSDROP V_RXPAWSDROP(1U) 4929167514Skmacy 4930167514Skmacy#define S_RXURGDATADROP 22 4931167514Skmacy#define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP) 4932167514Skmacy#define F_RXURGDATADROP V_RXURGDATADROP(1U) 4933167514Skmacy 4934167514Skmacy#define S_RXFUTUREDATA 21 4935167514Skmacy#define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA) 4936167514Skmacy#define F_RXFUTUREDATA V_RXFUTUREDATA(1U) 4937167514Skmacy 4938167514Skmacy#define S_RXRCVRXMDATA 20 4939167514Skmacy#define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA) 4940167514Skmacy#define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U) 4941167514Skmacy 4942167514Skmacy#define S_RXRCVOOODATAFIN 19 4943167514Skmacy#define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN) 4944167514Skmacy#define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U) 4945167514Skmacy 4946167514Skmacy#define S_RXRCVOOODATA 18 4947167514Skmacy#define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA) 4948167514Skmacy#define F_RXRCVOOODATA V_RXRCVOOODATA(1U) 4949167514Skmacy 4950167514Skmacy#define S_RXRCVWNDZERO 17 4951167514Skmacy#define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO) 4952167514Skmacy#define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U) 4953167514Skmacy 4954167514Skmacy#define S_RXRCVWNDLTMSS 16 4955167514Skmacy#define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS) 4956167514Skmacy#define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U) 4957167514Skmacy 4958167514Skmacy#define S_TXDUPACKINC 11 4959167514Skmacy#define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC) 4960167514Skmacy#define F_TXDUPACKINC V_TXDUPACKINC(1U) 4961167514Skmacy 4962167514Skmacy#define S_TXRXMURG 10 4963167514Skmacy#define V_TXRXMURG(x) ((x) << S_TXRXMURG) 4964167514Skmacy#define F_TXRXMURG V_TXRXMURG(1U) 4965167514Skmacy 4966167514Skmacy#define S_TXRXMFIN 9 4967167514Skmacy#define V_TXRXMFIN(x) ((x) << S_TXRXMFIN) 4968167514Skmacy#define F_TXRXMFIN V_TXRXMFIN(1U) 4969167514Skmacy 4970167514Skmacy#define S_TXRXMSYN 8 4971167514Skmacy#define V_TXRXMSYN(x) ((x) << S_TXRXMSYN) 4972167514Skmacy#define F_TXRXMSYN V_TXRXMSYN(1U) 4973167514Skmacy 4974167514Skmacy#define S_TXRXMNEWRENO 7 4975167514Skmacy#define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO) 4976167514Skmacy#define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U) 4977167514Skmacy 4978167514Skmacy#define S_TXRXMFAST 6 4979167514Skmacy#define V_TXRXMFAST(x) ((x) << S_TXRXMFAST) 4980167514Skmacy#define F_TXRXMFAST V_TXRXMFAST(1U) 4981167514Skmacy 4982167514Skmacy#define S_TXRXMTIMER 5 4983167514Skmacy#define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER) 4984167514Skmacy#define F_TXRXMTIMER V_TXRXMTIMER(1U) 4985167514Skmacy 4986167514Skmacy#define S_TXRXMTIMERKEEPALIVE 4 4987167514Skmacy#define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE) 4988167514Skmacy#define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U) 4989167514Skmacy 4990167514Skmacy#define S_TXRXMTIMERPERSIST 3 4991167514Skmacy#define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST) 4992167514Skmacy#define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U) 4993167514Skmacy 4994167514Skmacy#define S_TXRCVADVSHRUNK 2 4995167514Skmacy#define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK) 4996167514Skmacy#define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U) 4997167514Skmacy 4998167514Skmacy#define S_TXRCVADVZERO 1 4999167514Skmacy#define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO) 5000167514Skmacy#define F_TXRCVADVZERO V_TXRCVADVZERO(1U) 5001167514Skmacy 5002167514Skmacy#define S_TXRCVADVLTMSS 0 5003167514Skmacy#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) 5004167514Skmacy#define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) 5005167514Skmacy 5006176472Skmacy#define S_RXDEBUGFLAGS 16 5007176472Skmacy#define M_RXDEBUGFLAGS 0xffff 5008176472Skmacy#define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) 5009176472Skmacy#define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) 5010176472Skmacy 5011176472Skmacy#define S_TXDEBUGFLAGS 0 5012176472Skmacy#define M_TXDEBUGFLAGS 0xffff 5013176472Skmacy#define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) 5014176472Skmacy#define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) 5015176472Skmacy 5016176472Skmacy#define A_TP_PROXY_FLOW_CNTL 0x4b0 5017167514Skmacy#define A_TP_CM_FLOW_CNTL_MODE 0x4b0 5018167514Skmacy 5019167514Skmacy#define S_CMFLOWCACHEDISABLE 0 5020167514Skmacy#define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE) 5021167514Skmacy#define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U) 5022167514Skmacy 5023167514Skmacy#define A_TP_PC_CONGESTION_CNTL 0x4b4 5024167514Skmacy 5025167514Skmacy#define S_EDROPTUNNEL 19 5026167514Skmacy#define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL) 5027167514Skmacy#define F_EDROPTUNNEL V_EDROPTUNNEL(1U) 5028167514Skmacy 5029167514Skmacy#define S_CDROPTUNNEL 18 5030167514Skmacy#define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL) 5031167514Skmacy#define F_CDROPTUNNEL V_CDROPTUNNEL(1U) 5032167514Skmacy 5033167514Skmacy#define S_ETHRESHOLD 12 5034167514Skmacy#define M_ETHRESHOLD 0x3f 5035167514Skmacy#define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD) 5036167514Skmacy#define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD) 5037167514Skmacy 5038167514Skmacy#define S_CTHRESHOLD 6 5039167514Skmacy#define M_CTHRESHOLD 0x3f 5040167514Skmacy#define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD) 5041167514Skmacy#define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD) 5042167514Skmacy 5043167514Skmacy#define S_TXTHRESHOLD 0 5044167514Skmacy#define M_TXTHRESHOLD 0x3f 5045167514Skmacy#define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD) 5046167514Skmacy#define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD) 5047167514Skmacy 5048167514Skmacy#define A_TP_TX_DROP_COUNT 0x4bc 5049167514Skmacy#define A_TP_CLEAR_DEBUG 0x4c0 5050167514Skmacy 5051167514Skmacy#define S_CLRDEBUG 0 5052167514Skmacy#define V_CLRDEBUG(x) ((x) << S_CLRDEBUG) 5053167514Skmacy#define F_CLRDEBUG V_CLRDEBUG(1U) 5054167514Skmacy 5055167514Skmacy#define A_TP_DEBUG_VEC 0x4c4 5056167514Skmacy#define A_TP_DEBUG_VEC2 0x4c8 5057167514Skmacy#define A_TP_DEBUG_REG_SEL 0x4cc 5058167514Skmacy#define A_TP_DEBUG 0x4d0 5059167514Skmacy#define A_TP_DBG_LA_CONFIG 0x4d4 5060167514Skmacy#define A_TP_DBG_LA_DATAH 0x4d8 5061167514Skmacy#define A_TP_DBG_LA_DATAL 0x4dc 5062167514Skmacy#define A_TP_EMBED_OP_FIELD0 0x4e8 5063167514Skmacy#define A_TP_EMBED_OP_FIELD1 0x4ec 5064167514Skmacy#define A_TP_EMBED_OP_FIELD2 0x4f0 5065167514Skmacy#define A_TP_EMBED_OP_FIELD3 0x4f4 5066167514Skmacy#define A_TP_EMBED_OP_FIELD4 0x4f8 5067167514Skmacy#define A_TP_EMBED_OP_FIELD5 0x4fc 5068167514Skmacy#define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0 5069167514Skmacy#define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1 5070167514Skmacy#define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2 5071167514Skmacy#define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3 5072167514Skmacy#define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4 5073167514Skmacy#define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5 5074167514Skmacy#define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6 5075167514Skmacy#define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7 5076167514Skmacy#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 5077167514Skmacy#define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9 5078167514Skmacy#define A_TP_TX_TRC_KEY0 0x20 5079167514Skmacy#define A_TP_TX_TRC_MASK0 0x21 5080167514Skmacy#define A_TP_TX_TRC_KEY1 0x22 5081167514Skmacy#define A_TP_TX_TRC_MASK1 0x23 5082167514Skmacy#define A_TP_TX_TRC_KEY2 0x24 5083167514Skmacy#define A_TP_TX_TRC_MASK2 0x25 5084167514Skmacy#define A_TP_TX_TRC_KEY3 0x26 5085167514Skmacy#define A_TP_TX_TRC_MASK3 0x27 5086167514Skmacy#define A_TP_IPMI_CFG1 0x28 5087167514Skmacy 5088167514Skmacy#define S_VLANENABLE 31 5089167514Skmacy#define V_VLANENABLE(x) ((x) << S_VLANENABLE) 5090167514Skmacy#define F_VLANENABLE V_VLANENABLE(1U) 5091167514Skmacy 5092167514Skmacy#define S_PRIMARYPORTENABLE 30 5093167514Skmacy#define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE) 5094167514Skmacy#define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U) 5095167514Skmacy 5096167514Skmacy#define S_SECUREPORTENABLE 29 5097167514Skmacy#define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE) 5098167514Skmacy#define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U) 5099167514Skmacy 5100167514Skmacy#define S_ARPENABLE 28 5101167514Skmacy#define V_ARPENABLE(x) ((x) << S_ARPENABLE) 5102167514Skmacy#define F_ARPENABLE V_ARPENABLE(1U) 5103167514Skmacy 5104167514Skmacy#define S_VLAN 0 5105167514Skmacy#define M_VLAN 0xffff 5106167514Skmacy#define V_VLAN(x) ((x) << S_VLAN) 5107167514Skmacy#define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN) 5108167514Skmacy 5109167514Skmacy#define A_TP_IPMI_CFG2 0x29 5110167514Skmacy 5111167514Skmacy#define S_SECUREPORT 16 5112167514Skmacy#define M_SECUREPORT 0xffff 5113167514Skmacy#define V_SECUREPORT(x) ((x) << S_SECUREPORT) 5114167514Skmacy#define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT) 5115167514Skmacy 5116167514Skmacy#define S_PRIMARYPORT 0 5117167514Skmacy#define M_PRIMARYPORT 0xffff 5118167514Skmacy#define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT) 5119167514Skmacy#define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT) 5120167514Skmacy 5121167514Skmacy#define A_TP_RX_TRC_KEY0 0x120 5122167514Skmacy#define A_TP_RX_TRC_MASK0 0x121 5123167514Skmacy#define A_TP_RX_TRC_KEY1 0x122 5124167514Skmacy#define A_TP_RX_TRC_MASK1 0x123 5125167514Skmacy#define A_TP_RX_TRC_KEY2 0x124 5126167514Skmacy#define A_TP_RX_TRC_MASK2 0x125 5127167514Skmacy#define A_TP_RX_TRC_KEY3 0x126 5128167514Skmacy#define A_TP_RX_TRC_MASK3 0x127 5129167514Skmacy#define A_TP_QOS_RX_TOS_MAP_H 0x128 5130167514Skmacy#define A_TP_QOS_RX_TOS_MAP_L 0x129 5131167514Skmacy#define A_TP_QOS_RX_MAP_MODE 0x12a 5132167514Skmacy 5133167514Skmacy#define S_DEFAULTCH 11 5134167514Skmacy#define V_DEFAULTCH(x) ((x) << S_DEFAULTCH) 5135167514Skmacy#define F_DEFAULTCH V_DEFAULTCH(1U) 5136167514Skmacy 5137167514Skmacy#define S_RXMAPMODE 8 5138167514Skmacy#define M_RXMAPMODE 0x7 5139167514Skmacy#define V_RXMAPMODE(x) ((x) << S_RXMAPMODE) 5140167514Skmacy#define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE) 5141167514Skmacy 5142167514Skmacy#define S_RXVLANMAP 7 5143167514Skmacy#define V_RXVLANMAP(x) ((x) << S_RXVLANMAP) 5144167514Skmacy#define F_RXVLANMAP V_RXVLANMAP(1U) 5145167514Skmacy 5146167514Skmacy#define A_TP_TX_DROP_CFG_CH0 0x12b 5147167514Skmacy 5148167514Skmacy#define S_TIMERENABLED 31 5149167514Skmacy#define V_TIMERENABLED(x) ((x) << S_TIMERENABLED) 5150167514Skmacy#define F_TIMERENABLED V_TIMERENABLED(1U) 5151167514Skmacy 5152167514Skmacy#define S_TIMERERRORENABLE 30 5153167514Skmacy#define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE) 5154167514Skmacy#define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U) 5155167514Skmacy 5156167514Skmacy#define S_TIMERTHRESHOLD 4 5157167514Skmacy#define M_TIMERTHRESHOLD 0x3ffffff 5158167514Skmacy#define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD) 5159167514Skmacy#define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD) 5160167514Skmacy 5161167514Skmacy#define S_PACKETDROPS 0 5162167514Skmacy#define M_PACKETDROPS 0xf 5163167514Skmacy#define V_PACKETDROPS(x) ((x) << S_PACKETDROPS) 5164167514Skmacy#define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS) 5165167514Skmacy 5166167514Skmacy#define A_TP_TX_DROP_CFG_CH1 0x12c 5167167514Skmacy#define A_TP_TX_DROP_CNT_CH0 0x12d 5168167514Skmacy 5169167514Skmacy#define S_TXDROPCNTCH0SENT 16 5170167514Skmacy#define M_TXDROPCNTCH0SENT 0xffff 5171167514Skmacy#define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT) 5172167514Skmacy#define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT) 5173167514Skmacy 5174167514Skmacy#define S_TXDROPCNTCH0RCVD 0 5175167514Skmacy#define M_TXDROPCNTCH0RCVD 0xffff 5176167514Skmacy#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) 5177167514Skmacy#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD) 5178167514Skmacy 5179167514Skmacy#define A_TP_TX_DROP_CNT_CH1 0x12e 5180167514Skmacy 5181167514Skmacy#define S_TXDROPCNTCH1SENT 16 5182167514Skmacy#define M_TXDROPCNTCH1SENT 0xffff 5183167514Skmacy#define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT) 5184167514Skmacy#define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT) 5185167514Skmacy 5186167514Skmacy#define S_TXDROPCNTCH1RCVD 0 5187167514Skmacy#define M_TXDROPCNTCH1RCVD 0xffff 5188167514Skmacy#define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD) 5189167514Skmacy#define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD) 5190167514Skmacy 5191167514Skmacy#define A_TP_TX_DROP_MODE 0x12f 5192167514Skmacy 5193167514Skmacy#define S_TXDROPMODECH1 1 5194167514Skmacy#define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1) 5195167514Skmacy#define F_TXDROPMODECH1 V_TXDROPMODECH1(1U) 5196167514Skmacy 5197167514Skmacy#define S_TXDROPMODECH0 0 5198167514Skmacy#define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0) 5199167514Skmacy#define F_TXDROPMODECH0 V_TXDROPMODECH0(1U) 5200167514Skmacy 5201167514Skmacy#define A_TP_VLAN_PRI_MAP 0x137 5202167514Skmacy 5203167514Skmacy#define S_VLANPRIMAP7 14 5204167514Skmacy#define M_VLANPRIMAP7 0x3 5205167514Skmacy#define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7) 5206167514Skmacy#define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7) 5207167514Skmacy 5208167514Skmacy#define S_VLANPRIMAP6 12 5209167514Skmacy#define M_VLANPRIMAP6 0x3 5210167514Skmacy#define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6) 5211167514Skmacy#define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6) 5212167514Skmacy 5213167514Skmacy#define S_VLANPRIMAP5 10 5214167514Skmacy#define M_VLANPRIMAP5 0x3 5215167514Skmacy#define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5) 5216167514Skmacy#define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5) 5217167514Skmacy 5218167514Skmacy#define S_VLANPRIMAP4 8 5219167514Skmacy#define M_VLANPRIMAP4 0x3 5220167514Skmacy#define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4) 5221167514Skmacy#define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4) 5222167514Skmacy 5223167514Skmacy#define S_VLANPRIMAP3 6 5224167514Skmacy#define M_VLANPRIMAP3 0x3 5225167514Skmacy#define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3) 5226167514Skmacy#define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3) 5227167514Skmacy 5228167514Skmacy#define S_VLANPRIMAP2 4 5229167514Skmacy#define M_VLANPRIMAP2 0x3 5230167514Skmacy#define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2) 5231167514Skmacy#define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2) 5232167514Skmacy 5233167514Skmacy#define S_VLANPRIMAP1 2 5234167514Skmacy#define M_VLANPRIMAP1 0x3 5235167514Skmacy#define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1) 5236167514Skmacy#define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1) 5237167514Skmacy 5238167514Skmacy#define S_VLANPRIMAP0 0 5239167514Skmacy#define M_VLANPRIMAP0 0x3 5240167514Skmacy#define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0) 5241167514Skmacy#define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0) 5242167514Skmacy 5243167514Skmacy#define A_TP_MAC_MATCH_MAP0 0x138 5244167514Skmacy 5245167514Skmacy#define S_MACMATCHMAP7 21 5246167514Skmacy#define M_MACMATCHMAP7 0x7 5247167514Skmacy#define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7) 5248167514Skmacy#define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7) 5249167514Skmacy 5250167514Skmacy#define S_MACMATCHMAP6 18 5251167514Skmacy#define M_MACMATCHMAP6 0x7 5252167514Skmacy#define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6) 5253167514Skmacy#define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6) 5254167514Skmacy 5255167514Skmacy#define S_MACMATCHMAP5 15 5256167514Skmacy#define M_MACMATCHMAP5 0x7 5257167514Skmacy#define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5) 5258167514Skmacy#define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5) 5259167514Skmacy 5260167514Skmacy#define S_MACMATCHMAP4 12 5261167514Skmacy#define M_MACMATCHMAP4 0x7 5262167514Skmacy#define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4) 5263167514Skmacy#define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4) 5264167514Skmacy 5265167514Skmacy#define S_MACMATCHMAP3 9 5266167514Skmacy#define M_MACMATCHMAP3 0x7 5267167514Skmacy#define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3) 5268167514Skmacy#define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3) 5269167514Skmacy 5270167514Skmacy#define S_MACMATCHMAP2 6 5271167514Skmacy#define M_MACMATCHMAP2 0x7 5272167514Skmacy#define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2) 5273167514Skmacy#define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2) 5274167514Skmacy 5275167514Skmacy#define S_MACMATCHMAP1 3 5276167514Skmacy#define M_MACMATCHMAP1 0x7 5277167514Skmacy#define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1) 5278167514Skmacy#define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1) 5279167514Skmacy 5280167514Skmacy#define S_MACMATCHMAP0 0 5281167514Skmacy#define M_MACMATCHMAP0 0x7 5282167514Skmacy#define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0) 5283167514Skmacy#define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0) 5284167514Skmacy 5285167514Skmacy#define A_TP_MAC_MATCH_MAP1 0x139 5286167514Skmacy#define A_TP_INGRESS_CONFIG 0x141 5287167514Skmacy 5288167514Skmacy#define S_LOOKUPEVERYPKT 28 5289167514Skmacy#define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT) 5290167514Skmacy#define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U) 5291167514Skmacy 5292167514Skmacy#define S_ENABLEINSERTIONSFD 27 5293167514Skmacy#define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD) 5294167514Skmacy#define F_ENABLEINSERTIONSFD V_ENABLEINSERTIONSFD(1U) 5295167514Skmacy 5296167514Skmacy#define S_ENABLEINSERTION 26 5297167514Skmacy#define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION) 5298167514Skmacy#define F_ENABLEINSERTION V_ENABLEINSERTION(1U) 5299167514Skmacy 5300167514Skmacy#define S_ENABLEEXTRACTIONSFD 25 5301167514Skmacy#define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD) 5302167514Skmacy#define F_ENABLEEXTRACTIONSFD V_ENABLEEXTRACTIONSFD(1U) 5303167514Skmacy 5304167514Skmacy#define S_ENABLEEXTRACT 24 5305167514Skmacy#define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT) 5306167514Skmacy#define F_ENABLEEXTRACT V_ENABLEEXTRACT(1U) 5307167514Skmacy 5308167514Skmacy#define S_BITPOS3 18 5309167514Skmacy#define M_BITPOS3 0x3f 5310167514Skmacy#define V_BITPOS3(x) ((x) << S_BITPOS3) 5311167514Skmacy#define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3) 5312167514Skmacy 5313167514Skmacy#define S_BITPOS2 12 5314167514Skmacy#define M_BITPOS2 0x3f 5315167514Skmacy#define V_BITPOS2(x) ((x) << S_BITPOS2) 5316167514Skmacy#define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2) 5317167514Skmacy 5318167514Skmacy#define S_BITPOS1 6 5319167514Skmacy#define M_BITPOS1 0x3f 5320167514Skmacy#define V_BITPOS1(x) ((x) << S_BITPOS1) 5321167514Skmacy#define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1) 5322167514Skmacy 5323167514Skmacy#define S_BITPOS0 0 5324167514Skmacy#define M_BITPOS0 0x3f 5325167514Skmacy#define V_BITPOS0(x) ((x) << S_BITPOS0) 5326167514Skmacy#define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0) 5327167514Skmacy 5328167514Skmacy#define A_TP_PREAMBLE_MSB 0x142 5329167514Skmacy#define A_TP_PREAMBLE_LSB 0x143 5330167514Skmacy#define A_TP_EGRESS_CONFIG 0x145 5331167514Skmacy 5332167514Skmacy#define S_REWRITEFORCETOSIZE 0 5333167514Skmacy#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) 5334167514Skmacy#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) 5335167514Skmacy 5336167514Skmacy#define A_TP_INTF_FROM_TX_PKT 0x244 5337167514Skmacy 5338167514Skmacy#define S_INTFFROMTXPKT 0 5339167514Skmacy#define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT) 5340167514Skmacy#define F_INTFFROMTXPKT V_INTFFROMTXPKT(1U) 5341167514Skmacy 5342167514Skmacy#define A_TP_FIFO_CONFIG 0x8c0 5343167514Skmacy 5344167514Skmacy#define S_RXFIFOCONFIG 10 5345167514Skmacy#define M_RXFIFOCONFIG 0x3f 5346167514Skmacy#define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG) 5347167514Skmacy#define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG) 5348167514Skmacy 5349167514Skmacy#define S_TXFIFOCONFIG 2 5350167514Skmacy#define M_TXFIFOCONFIG 0x3f 5351167514Skmacy#define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG) 5352167514Skmacy#define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG) 5353167514Skmacy 5354167514Skmacy/* registers for module ULP2_RX */ 5355167514Skmacy#define ULP2_RX_BASE_ADDR 0x500 5356167514Skmacy 5357167514Skmacy#define A_ULPRX_CTL 0x500 5358167514Skmacy 5359167514Skmacy#define S_PCMD1THRESHOLD 24 5360167514Skmacy#define M_PCMD1THRESHOLD 0xff 5361167514Skmacy#define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD) 5362167514Skmacy#define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD) 5363167514Skmacy 5364167514Skmacy#define S_PCMD0THRESHOLD 16 5365167514Skmacy#define M_PCMD0THRESHOLD 0xff 5366167514Skmacy#define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD) 5367167514Skmacy#define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD) 5368167514Skmacy 5369167514Skmacy#define S_ROUND_ROBIN 4 5370167514Skmacy#define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN) 5371167514Skmacy#define F_ROUND_ROBIN V_ROUND_ROBIN(1U) 5372167514Skmacy 5373167514Skmacy#define S_RDMA_PERMISSIVE_MODE 3 5374167514Skmacy#define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE) 5375167514Skmacy#define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U) 5376167514Skmacy 5377167514Skmacy#define S_PAGEPODME 2 5378167514Skmacy#define V_PAGEPODME(x) ((x) << S_PAGEPODME) 5379167514Skmacy#define F_PAGEPODME V_PAGEPODME(1U) 5380167514Skmacy 5381167514Skmacy#define S_ISCSITAGTCB 1 5382167514Skmacy#define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB) 5383167514Skmacy#define F_ISCSITAGTCB V_ISCSITAGTCB(1U) 5384167514Skmacy 5385167514Skmacy#define S_TDDPTAGTCB 0 5386167514Skmacy#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) 5387167514Skmacy#define F_TDDPTAGTCB V_TDDPTAGTCB(1U) 5388167514Skmacy 5389167514Skmacy#define A_ULPRX_INT_ENABLE 0x504 5390167514Skmacy 5391176472Skmacy#define S_DATASELFRAMEERR0 7 5392176472Skmacy#define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0) 5393176472Skmacy#define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U) 5394176472Skmacy 5395176472Skmacy#define S_DATASELFRAMEERR1 6 5396176472Skmacy#define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1) 5397176472Skmacy#define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U) 5398176472Skmacy 5399176472Skmacy#define S_PCMDMUXPERR 5 5400176472Skmacy#define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR) 5401176472Skmacy#define F_PCMDMUXPERR V_PCMDMUXPERR(1U) 5402176472Skmacy 5403176472Skmacy#define S_ARBFPERR 4 5404176472Skmacy#define V_ARBFPERR(x) ((x) << S_ARBFPERR) 5405176472Skmacy#define F_ARBFPERR V_ARBFPERR(1U) 5406176472Skmacy 5407176472Skmacy#define S_ARBPF0PERR 3 5408176472Skmacy#define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR) 5409176472Skmacy#define F_ARBPF0PERR V_ARBPF0PERR(1U) 5410176472Skmacy 5411176472Skmacy#define S_ARBPF1PERR 2 5412176472Skmacy#define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR) 5413176472Skmacy#define F_ARBPF1PERR V_ARBPF1PERR(1U) 5414176472Skmacy 5415176472Skmacy#define S_PARERRPCMD 1 5416176472Skmacy#define V_PARERRPCMD(x) ((x) << S_PARERRPCMD) 5417176472Skmacy#define F_PARERRPCMD V_PARERRPCMD(1U) 5418176472Skmacy 5419176472Skmacy#define S_PARERRDATA 0 5420176472Skmacy#define V_PARERRDATA(x) ((x) << S_PARERRDATA) 5421176472Skmacy#define F_PARERRDATA V_PARERRDATA(1U) 5422176472Skmacy 5423167514Skmacy#define S_PARERR 0 5424167514Skmacy#define V_PARERR(x) ((x) << S_PARERR) 5425167514Skmacy#define F_PARERR V_PARERR(1U) 5426167514Skmacy 5427167514Skmacy#define A_ULPRX_INT_CAUSE 0x508 5428167514Skmacy#define A_ULPRX_ISCSI_LLIMIT 0x50c 5429167514Skmacy 5430167514Skmacy#define S_ISCSILLIMIT 6 5431167514Skmacy#define M_ISCSILLIMIT 0x3ffffff 5432167514Skmacy#define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT) 5433167514Skmacy#define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT) 5434167514Skmacy 5435167514Skmacy#define A_ULPRX_ISCSI_ULIMIT 0x510 5436167514Skmacy 5437167514Skmacy#define S_ISCSIULIMIT 6 5438167514Skmacy#define M_ISCSIULIMIT 0x3ffffff 5439167514Skmacy#define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT) 5440167514Skmacy#define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT) 5441167514Skmacy 5442167514Skmacy#define A_ULPRX_ISCSI_TAGMASK 0x514 5443167514Skmacy 5444167514Skmacy#define S_ISCSITAGMASK 6 5445167514Skmacy#define M_ISCSITAGMASK 0x3ffffff 5446167514Skmacy#define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK) 5447167514Skmacy#define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK) 5448167514Skmacy 5449167514Skmacy#define A_ULPRX_ISCSI_PSZ 0x518 5450167514Skmacy 5451167514Skmacy#define S_HPZ3 24 5452167514Skmacy#define M_HPZ3 0xf 5453167514Skmacy#define V_HPZ3(x) ((x) << S_HPZ3) 5454167514Skmacy#define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3) 5455167514Skmacy 5456167514Skmacy#define S_HPZ2 16 5457167514Skmacy#define M_HPZ2 0xf 5458167514Skmacy#define V_HPZ2(x) ((x) << S_HPZ2) 5459167514Skmacy#define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2) 5460167514Skmacy 5461167514Skmacy#define S_HPZ1 8 5462167514Skmacy#define M_HPZ1 0xf 5463167514Skmacy#define V_HPZ1(x) ((x) << S_HPZ1) 5464167514Skmacy#define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1) 5465167514Skmacy 5466167514Skmacy#define S_HPZ0 0 5467167514Skmacy#define M_HPZ0 0xf 5468167514Skmacy#define V_HPZ0(x) ((x) << S_HPZ0) 5469167514Skmacy#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) 5470167514Skmacy 5471167514Skmacy#define A_ULPRX_TDDP_LLIMIT 0x51c 5472167514Skmacy 5473167514Skmacy#define S_TDDPLLIMIT 6 5474167514Skmacy#define M_TDDPLLIMIT 0x3ffffff 5475167514Skmacy#define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT) 5476167514Skmacy#define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT) 5477167514Skmacy 5478167514Skmacy#define A_ULPRX_TDDP_ULIMIT 0x520 5479167514Skmacy 5480167514Skmacy#define S_TDDPULIMIT 6 5481167514Skmacy#define M_TDDPULIMIT 0x3ffffff 5482167514Skmacy#define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT) 5483167514Skmacy#define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT) 5484167514Skmacy 5485167514Skmacy#define A_ULPRX_TDDP_TAGMASK 0x524 5486167514Skmacy 5487167514Skmacy#define S_TDDPTAGMASK 6 5488167514Skmacy#define M_TDDPTAGMASK 0x3ffffff 5489167514Skmacy#define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK) 5490167514Skmacy#define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK) 5491167514Skmacy 5492167514Skmacy#define A_ULPRX_TDDP_PSZ 0x528 5493167514Skmacy#define A_ULPRX_STAG_LLIMIT 0x52c 5494167514Skmacy#define A_ULPRX_STAG_ULIMIT 0x530 5495167514Skmacy#define A_ULPRX_RQ_LLIMIT 0x534 5496167514Skmacy#define A_ULPRX_RQ_ULIMIT 0x538 5497167514Skmacy#define A_ULPRX_PBL_LLIMIT 0x53c 5498167514Skmacy#define A_ULPRX_PBL_ULIMIT 0x540 5499167514Skmacy 5500167514Skmacy/* registers for module ULP2_TX */ 5501167514Skmacy#define ULP2_TX_BASE_ADDR 0x580 5502167514Skmacy 5503167514Skmacy#define A_ULPTX_CONFIG 0x580 5504167514Skmacy 5505176472Skmacy#define S_CFG_CQE_SOP_MASK 1 5506176472Skmacy#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK) 5507176472Skmacy#define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U) 5508176472Skmacy 5509167514Skmacy#define S_CFG_RR_ARB 0 5510167514Skmacy#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 5511167514Skmacy#define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 5512167514Skmacy 5513167514Skmacy#define A_ULPTX_INT_ENABLE 0x584 5514167514Skmacy 5515176472Skmacy#define S_CMD_FIFO_PERR_SET1 7 5516176472Skmacy#define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1) 5517176472Skmacy#define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U) 5518176472Skmacy 5519176472Skmacy#define S_CMD_FIFO_PERR_SET0 6 5520176472Skmacy#define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0) 5521176472Skmacy#define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U) 5522176472Skmacy 5523176472Skmacy#define S_LSO_HDR_SRAM_PERR_SET1 5 5524176472Skmacy#define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1) 5525176472Skmacy#define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U) 5526176472Skmacy 5527176472Skmacy#define S_LSO_HDR_SRAM_PERR_SET0 4 5528176472Skmacy#define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0) 5529176472Skmacy#define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U) 5530176472Skmacy 5531176472Skmacy#define S_IMM_DATA_PERR_SET_CH1 3 5532176472Skmacy#define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1) 5533176472Skmacy#define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U) 5534176472Skmacy 5535176472Skmacy#define S_IMM_DATA_PERR_SET_CH0 2 5536176472Skmacy#define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0) 5537176472Skmacy#define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U) 5538176472Skmacy 5539167514Skmacy#define S_PBL_BOUND_ERR_CH1 1 5540167514Skmacy#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 5541167514Skmacy#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 5542167514Skmacy 5543167514Skmacy#define S_PBL_BOUND_ERR_CH0 0 5544167514Skmacy#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 5545167514Skmacy#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 5546167514Skmacy 5547167514Skmacy#define A_ULPTX_INT_CAUSE 0x588 5548167514Skmacy#define A_ULPTX_TPT_LLIMIT 0x58c 5549167514Skmacy#define A_ULPTX_TPT_ULIMIT 0x590 5550167514Skmacy#define A_ULPTX_PBL_LLIMIT 0x594 5551167514Skmacy#define A_ULPTX_PBL_ULIMIT 0x598 5552167514Skmacy#define A_ULPTX_CPL_ERR_OFFSET 0x59c 5553167514Skmacy#define A_ULPTX_CPL_ERR_MASK 0x5a0 5554167514Skmacy#define A_ULPTX_CPL_ERR_VALUE 0x5a4 5555167514Skmacy#define A_ULPTX_CPL_PACK_SIZE 0x5a8 5556167514Skmacy 5557167514Skmacy#define S_VALUE 24 5558167514Skmacy#define M_VALUE 0xff 5559167514Skmacy#define V_VALUE(x) ((x) << S_VALUE) 5560167514Skmacy#define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE) 5561167514Skmacy 5562167514Skmacy#define S_CH1SIZE2 24 5563167514Skmacy#define M_CH1SIZE2 0xff 5564167514Skmacy#define V_CH1SIZE2(x) ((x) << S_CH1SIZE2) 5565167514Skmacy#define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2) 5566167514Skmacy 5567167514Skmacy#define S_CH1SIZE1 16 5568167514Skmacy#define M_CH1SIZE1 0xff 5569167514Skmacy#define V_CH1SIZE1(x) ((x) << S_CH1SIZE1) 5570167514Skmacy#define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1) 5571167514Skmacy 5572167514Skmacy#define S_CH0SIZE2 8 5573167514Skmacy#define M_CH0SIZE2 0xff 5574167514Skmacy#define V_CH0SIZE2(x) ((x) << S_CH0SIZE2) 5575167514Skmacy#define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2) 5576167514Skmacy 5577167514Skmacy#define S_CH0SIZE1 0 5578167514Skmacy#define M_CH0SIZE1 0xff 5579167514Skmacy#define V_CH0SIZE1(x) ((x) << S_CH0SIZE1) 5580167514Skmacy#define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1) 5581167514Skmacy 5582167514Skmacy#define A_ULPTX_DMA_WEIGHT 0x5ac 5583167514Skmacy 5584167514Skmacy#define S_D1_WEIGHT 16 5585167514Skmacy#define M_D1_WEIGHT 0xffff 5586167514Skmacy#define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT) 5587167514Skmacy#define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT) 5588167514Skmacy 5589167514Skmacy#define S_D0_WEIGHT 0 5590167514Skmacy#define M_D0_WEIGHT 0xffff 5591167514Skmacy#define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT) 5592167514Skmacy#define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT) 5593167514Skmacy 5594167514Skmacy/* registers for module PM1_RX */ 5595167514Skmacy#define PM1_RX_BASE_ADDR 0x5c0 5596167514Skmacy 5597167514Skmacy#define A_PM1_RX_CFG 0x5c0 5598167514Skmacy#define A_PM1_RX_MODE 0x5c4 5599167514Skmacy 5600167514Skmacy#define S_STAT_CHANNEL 1 5601167514Skmacy#define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL) 5602167514Skmacy#define F_STAT_CHANNEL V_STAT_CHANNEL(1U) 5603167514Skmacy 5604167514Skmacy#define S_PRIORITY_CH 0 5605167514Skmacy#define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH) 5606167514Skmacy#define F_PRIORITY_CH V_PRIORITY_CH(1U) 5607167514Skmacy 5608167514Skmacy#define A_PM1_RX_STAT_CONFIG 0x5c8 5609167514Skmacy#define A_PM1_RX_STAT_COUNT 0x5cc 5610167514Skmacy#define A_PM1_RX_STAT_MSB 0x5d0 5611167514Skmacy#define A_PM1_RX_STAT_LSB 0x5d4 5612167514Skmacy#define A_PM1_RX_INT_ENABLE 0x5d8 5613167514Skmacy 5614167514Skmacy#define S_ZERO_E_CMD_ERROR 18 5615167514Skmacy#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR) 5616167514Skmacy#define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U) 5617167514Skmacy 5618167514Skmacy#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17 5619167514Skmacy#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR) 5620167514Skmacy#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U) 5621167514Skmacy 5622167514Skmacy#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16 5623167514Skmacy#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR) 5624167514Skmacy#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U) 5625167514Skmacy 5626167514Skmacy#define S_IESPI0_RX_FRAMING_ERROR 15 5627167514Skmacy#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR) 5628167514Skmacy#define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U) 5629167514Skmacy 5630167514Skmacy#define S_IESPI1_RX_FRAMING_ERROR 14 5631167514Skmacy#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR) 5632167514Skmacy#define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U) 5633167514Skmacy 5634167514Skmacy#define S_IESPI0_TX_FRAMING_ERROR 13 5635167514Skmacy#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR) 5636167514Skmacy#define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U) 5637167514Skmacy 5638167514Skmacy#define S_IESPI1_TX_FRAMING_ERROR 12 5639167514Skmacy#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR) 5640167514Skmacy#define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U) 5641167514Skmacy 5642167514Skmacy#define S_OCSPI0_RX_FRAMING_ERROR 11 5643167514Skmacy#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR) 5644167514Skmacy#define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U) 5645167514Skmacy 5646167514Skmacy#define S_OCSPI1_RX_FRAMING_ERROR 10 5647167514Skmacy#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR) 5648167514Skmacy#define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U) 5649167514Skmacy 5650167514Skmacy#define S_OCSPI0_TX_FRAMING_ERROR 9 5651167514Skmacy#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR) 5652167514Skmacy#define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U) 5653167514Skmacy 5654167514Skmacy#define S_OCSPI1_TX_FRAMING_ERROR 8 5655167514Skmacy#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR) 5656167514Skmacy#define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U) 5657167514Skmacy 5658167514Skmacy#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7 5659167514Skmacy#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR) 5660167514Skmacy#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 5661167514Skmacy 5662167514Skmacy#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6 5663167514Skmacy#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) 5664167514Skmacy#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 5665167514Skmacy 5666167514Skmacy#define S_IESPI_PAR_ERROR 3 5667167514Skmacy#define M_IESPI_PAR_ERROR 0x7 5668167514Skmacy#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) 5669167514Skmacy#define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR) 5670167514Skmacy 5671167514Skmacy#define S_OCSPI_PAR_ERROR 0 5672167514Skmacy#define M_OCSPI_PAR_ERROR 0x7 5673167514Skmacy#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) 5674167514Skmacy#define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR) 5675167514Skmacy 5676167514Skmacy#define A_PM1_RX_INT_CAUSE 0x5dc 5677167514Skmacy 5678167514Skmacy/* registers for module PM1_TX */ 5679167514Skmacy#define PM1_TX_BASE_ADDR 0x5e0 5680167514Skmacy 5681167514Skmacy#define A_PM1_TX_CFG 0x5e0 5682167514Skmacy#define A_PM1_TX_MODE 0x5e4 5683167514Skmacy#define A_PM1_TX_STAT_CONFIG 0x5e8 5684167514Skmacy#define A_PM1_TX_STAT_COUNT 0x5ec 5685167514Skmacy#define A_PM1_TX_STAT_MSB 0x5f0 5686167514Skmacy#define A_PM1_TX_STAT_LSB 0x5f4 5687167514Skmacy#define A_PM1_TX_INT_ENABLE 0x5f8 5688167514Skmacy 5689167514Skmacy#define S_ZERO_C_CMD_ERROR 18 5690167514Skmacy#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) 5691167514Skmacy#define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) 5692167514Skmacy 5693167514Skmacy#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17 5694167514Skmacy#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR) 5695167514Skmacy#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) 5696167514Skmacy 5697167514Skmacy#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16 5698167514Skmacy#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR) 5699167514Skmacy#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) 5700167514Skmacy 5701167514Skmacy#define S_ICSPI0_RX_FRAMING_ERROR 15 5702167514Skmacy#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR) 5703167514Skmacy#define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U) 5704167514Skmacy 5705167514Skmacy#define S_ICSPI1_RX_FRAMING_ERROR 14 5706167514Skmacy#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR) 5707167514Skmacy#define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U) 5708167514Skmacy 5709167514Skmacy#define S_ICSPI0_TX_FRAMING_ERROR 13 5710167514Skmacy#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR) 5711167514Skmacy#define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U) 5712167514Skmacy 5713167514Skmacy#define S_ICSPI1_TX_FRAMING_ERROR 12 5714167514Skmacy#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR) 5715167514Skmacy#define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U) 5716167514Skmacy 5717167514Skmacy#define S_OESPI0_RX_FRAMING_ERROR 11 5718167514Skmacy#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR) 5719167514Skmacy#define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U) 5720167514Skmacy 5721167514Skmacy#define S_OESPI1_RX_FRAMING_ERROR 10 5722167514Skmacy#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR) 5723167514Skmacy#define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U) 5724167514Skmacy 5725167514Skmacy#define S_OESPI0_TX_FRAMING_ERROR 9 5726167514Skmacy#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR) 5727167514Skmacy#define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U) 5728167514Skmacy 5729167514Skmacy#define S_OESPI1_TX_FRAMING_ERROR 8 5730167514Skmacy#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR) 5731167514Skmacy#define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U) 5732167514Skmacy 5733167514Skmacy#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7 5734167514Skmacy#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR) 5735167514Skmacy#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 5736167514Skmacy 5737167514Skmacy#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6 5738167514Skmacy#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR) 5739167514Skmacy#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 5740167514Skmacy 5741167514Skmacy#define S_ICSPI_PAR_ERROR 3 5742167514Skmacy#define M_ICSPI_PAR_ERROR 0x7 5743167514Skmacy#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) 5744167514Skmacy#define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR) 5745167514Skmacy 5746167514Skmacy#define S_OESPI_PAR_ERROR 0 5747167514Skmacy#define M_OESPI_PAR_ERROR 0x7 5748167514Skmacy#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) 5749167514Skmacy#define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR) 5750167514Skmacy 5751167514Skmacy#define A_PM1_TX_INT_CAUSE 0x5fc 5752167514Skmacy 5753167514Skmacy/* registers for module MPS0 */ 5754167514Skmacy#define MPS0_BASE_ADDR 0x600 5755167514Skmacy 5756167514Skmacy#define A_MPS_CFG 0x600 5757167514Skmacy 5758176472Skmacy#define S_ENFORCEPKT 11 5759176472Skmacy#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) 5760176472Skmacy#define F_ENFORCEPKT V_ENFORCEPKT(1U) 5761176472Skmacy 5762167514Skmacy#define S_SGETPQID 8 5763167514Skmacy#define M_SGETPQID 0x7 5764167514Skmacy#define V_SGETPQID(x) ((x) << S_SGETPQID) 5765167514Skmacy#define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) 5766167514Skmacy 5767167514Skmacy#define S_TPRXPORTSIZE 7 5768167514Skmacy#define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE) 5769167514Skmacy#define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U) 5770167514Skmacy 5771167514Skmacy#define S_TPTXPORT1SIZE 6 5772167514Skmacy#define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE) 5773167514Skmacy#define F_TPTXPORT1SIZE V_TPTXPORT1SIZE(1U) 5774167514Skmacy 5775167514Skmacy#define S_TPTXPORT0SIZE 5 5776167514Skmacy#define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE) 5777167514Skmacy#define F_TPTXPORT0SIZE V_TPTXPORT0SIZE(1U) 5778167514Skmacy 5779167514Skmacy#define S_TPRXPORTEN 4 5780167514Skmacy#define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN) 5781167514Skmacy#define F_TPRXPORTEN V_TPRXPORTEN(1U) 5782167514Skmacy 5783167514Skmacy#define S_TPTXPORT1EN 3 5784167514Skmacy#define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN) 5785167514Skmacy#define F_TPTXPORT1EN V_TPTXPORT1EN(1U) 5786167514Skmacy 5787167514Skmacy#define S_TPTXPORT0EN 2 5788167514Skmacy#define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN) 5789167514Skmacy#define F_TPTXPORT0EN V_TPTXPORT0EN(1U) 5790167514Skmacy 5791167514Skmacy#define S_PORT1ACTIVE 1 5792167514Skmacy#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) 5793167514Skmacy#define F_PORT1ACTIVE V_PORT1ACTIVE(1U) 5794167514Skmacy 5795167514Skmacy#define S_PORT0ACTIVE 0 5796167514Skmacy#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) 5797167514Skmacy#define F_PORT0ACTIVE V_PORT0ACTIVE(1U) 5798167514Skmacy 5799167514Skmacy#define A_MPS_DRR_CFG1 0x604 5800167514Skmacy 5801167514Skmacy#define S_RLDWTTPD1 11 5802167514Skmacy#define M_RLDWTTPD1 0x7ff 5803167514Skmacy#define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1) 5804167514Skmacy#define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1) 5805167514Skmacy 5806167514Skmacy#define S_RLDWTTPD0 0 5807167514Skmacy#define M_RLDWTTPD0 0x7ff 5808167514Skmacy#define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0) 5809167514Skmacy#define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0) 5810167514Skmacy 5811167514Skmacy#define A_MPS_DRR_CFG2 0x608 5812167514Skmacy 5813167514Skmacy#define S_RLDWTTOTAL 0 5814167514Skmacy#define M_RLDWTTOTAL 0xfff 5815167514Skmacy#define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL) 5816167514Skmacy#define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL) 5817167514Skmacy 5818167514Skmacy#define A_MPS_MCA_STATUS 0x60c 5819167514Skmacy 5820167514Skmacy#define S_MCAPKTCNT 12 5821167514Skmacy#define M_MCAPKTCNT 0xfffff 5822167514Skmacy#define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT) 5823167514Skmacy#define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT) 5824167514Skmacy 5825167514Skmacy#define S_MCADEPTH 0 5826167514Skmacy#define M_MCADEPTH 0xfff 5827167514Skmacy#define V_MCADEPTH(x) ((x) << S_MCADEPTH) 5828167514Skmacy#define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH) 5829167514Skmacy 5830167514Skmacy#define A_MPS_TX0_TP_CNT 0x610 5831167514Skmacy 5832167514Skmacy#define S_TX0TPDISCNT 24 5833167514Skmacy#define M_TX0TPDISCNT 0xff 5834167514Skmacy#define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT) 5835167514Skmacy#define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT) 5836167514Skmacy 5837167514Skmacy#define S_TX0TPCNT 0 5838167514Skmacy#define M_TX0TPCNT 0xffffff 5839167514Skmacy#define V_TX0TPCNT(x) ((x) << S_TX0TPCNT) 5840167514Skmacy#define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT) 5841167514Skmacy 5842167514Skmacy#define A_MPS_TX1_TP_CNT 0x614 5843167514Skmacy 5844167514Skmacy#define S_TX1TPDISCNT 24 5845167514Skmacy#define M_TX1TPDISCNT 0xff 5846167514Skmacy#define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT) 5847167514Skmacy#define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT) 5848167514Skmacy 5849167514Skmacy#define S_TX1TPCNT 0 5850167514Skmacy#define M_TX1TPCNT 0xffffff 5851167514Skmacy#define V_TX1TPCNT(x) ((x) << S_TX1TPCNT) 5852167514Skmacy#define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT) 5853167514Skmacy 5854167514Skmacy#define A_MPS_RX_TP_CNT 0x618 5855167514Skmacy 5856167514Skmacy#define S_RXTPDISCNT 24 5857167514Skmacy#define M_RXTPDISCNT 0xff 5858167514Skmacy#define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT) 5859167514Skmacy#define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT) 5860167514Skmacy 5861167514Skmacy#define S_RXTPCNT 0 5862167514Skmacy#define M_RXTPCNT 0xffffff 5863167514Skmacy#define V_RXTPCNT(x) ((x) << S_RXTPCNT) 5864167514Skmacy#define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT) 5865167514Skmacy 5866167514Skmacy#define A_MPS_INT_ENABLE 0x61c 5867167514Skmacy 5868167514Skmacy#define S_MCAPARERRENB 6 5869167514Skmacy#define M_MCAPARERRENB 0x7 5870167514Skmacy#define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB) 5871167514Skmacy#define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB) 5872167514Skmacy 5873167514Skmacy#define S_RXTPPARERRENB 4 5874167514Skmacy#define M_RXTPPARERRENB 0x3 5875167514Skmacy#define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB) 5876167514Skmacy#define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB) 5877167514Skmacy 5878167514Skmacy#define S_TX1TPPARERRENB 2 5879167514Skmacy#define M_TX1TPPARERRENB 0x3 5880167514Skmacy#define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB) 5881167514Skmacy#define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB) 5882167514Skmacy 5883167514Skmacy#define S_TX0TPPARERRENB 0 5884167514Skmacy#define M_TX0TPPARERRENB 0x3 5885167514Skmacy#define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB) 5886167514Skmacy#define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB) 5887167514Skmacy 5888167514Skmacy#define A_MPS_INT_CAUSE 0x620 5889167514Skmacy 5890167514Skmacy#define S_MCAPARERR 6 5891167514Skmacy#define M_MCAPARERR 0x7 5892167514Skmacy#define V_MCAPARERR(x) ((x) << S_MCAPARERR) 5893167514Skmacy#define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR) 5894167514Skmacy 5895167514Skmacy#define S_RXTPPARERR 4 5896167514Skmacy#define M_RXTPPARERR 0x3 5897167514Skmacy#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) 5898167514Skmacy#define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR) 5899167514Skmacy 5900167514Skmacy#define S_TX1TPPARERR 2 5901167514Skmacy#define M_TX1TPPARERR 0x3 5902167514Skmacy#define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR) 5903167514Skmacy#define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR) 5904167514Skmacy 5905167514Skmacy#define S_TX0TPPARERR 0 5906167514Skmacy#define M_TX0TPPARERR 0x3 5907167514Skmacy#define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR) 5908167514Skmacy#define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR) 5909167514Skmacy 5910167514Skmacy/* registers for module CPL_SWITCH */ 5911167514Skmacy#define CPL_SWITCH_BASE_ADDR 0x640 5912167514Skmacy 5913167514Skmacy#define A_CPL_SWITCH_CNTRL 0x640 5914167514Skmacy 5915167514Skmacy#define S_CPL_PKT_TID 8 5916167514Skmacy#define M_CPL_PKT_TID 0xffffff 5917167514Skmacy#define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID) 5918167514Skmacy#define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID) 5919167514Skmacy 5920176472Skmacy#define S_CIM_TO_UP_FULL_SIZE 4 5921176472Skmacy#define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE) 5922176472Skmacy#define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U) 5923176472Skmacy 5924167514Skmacy#define S_CPU_NO_3F_CIM_ENABLE 3 5925167514Skmacy#define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE) 5926167514Skmacy#define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U) 5927167514Skmacy 5928167514Skmacy#define S_SWITCH_TABLE_ENABLE 2 5929167514Skmacy#define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE) 5930167514Skmacy#define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U) 5931167514Skmacy 5932167514Skmacy#define S_SGE_ENABLE 1 5933167514Skmacy#define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE) 5934167514Skmacy#define F_SGE_ENABLE V_SGE_ENABLE(1U) 5935167514Skmacy 5936167514Skmacy#define S_CIM_ENABLE 0 5937167514Skmacy#define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE) 5938167514Skmacy#define F_CIM_ENABLE V_CIM_ENABLE(1U) 5939167514Skmacy 5940167514Skmacy#define A_CPL_SWITCH_TBL_IDX 0x644 5941167514Skmacy 5942167514Skmacy#define S_SWITCH_TBL_IDX 0 5943167514Skmacy#define M_SWITCH_TBL_IDX 0xf 5944167514Skmacy#define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX) 5945167514Skmacy#define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX) 5946167514Skmacy 5947167514Skmacy#define A_CPL_SWITCH_TBL_DATA 0x648 5948167514Skmacy#define A_CPL_SWITCH_ZERO_ERROR 0x64c 5949167514Skmacy 5950167514Skmacy#define S_ZERO_CMD 0 5951167514Skmacy#define M_ZERO_CMD 0xff 5952167514Skmacy#define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) 5953167514Skmacy#define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) 5954167514Skmacy 5955167514Skmacy#define A_CPL_INTR_ENABLE 0x650 5956167514Skmacy 5957176472Skmacy#define S_CIM_OP_MAP_PERR 5 5958176472Skmacy#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR) 5959176472Skmacy#define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U) 5960176472Skmacy 5961167514Skmacy#define S_CIM_OVFL_ERROR 4 5962167514Skmacy#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 5963167514Skmacy#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 5964167514Skmacy 5965167514Skmacy#define S_TP_FRAMING_ERROR 3 5966167514Skmacy#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 5967167514Skmacy#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 5968167514Skmacy 5969167514Skmacy#define S_SGE_FRAMING_ERROR 2 5970167514Skmacy#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR) 5971167514Skmacy#define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U) 5972167514Skmacy 5973167514Skmacy#define S_CIM_FRAMING_ERROR 1 5974167514Skmacy#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR) 5975167514Skmacy#define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U) 5976167514Skmacy 5977167514Skmacy#define S_ZERO_SWITCH_ERROR 0 5978167514Skmacy#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) 5979167514Skmacy#define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) 5980167514Skmacy 5981167514Skmacy#define A_CPL_INTR_CAUSE 0x654 5982167514Skmacy#define A_CPL_MAP_TBL_IDX 0x658 5983167514Skmacy 5984167514Skmacy#define S_CPL_MAP_TBL_IDX 0 5985167514Skmacy#define M_CPL_MAP_TBL_IDX 0xff 5986167514Skmacy#define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX) 5987167514Skmacy#define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX) 5988167514Skmacy 5989167514Skmacy#define A_CPL_MAP_TBL_DATA 0x65c 5990167514Skmacy 5991167514Skmacy#define S_CPL_MAP_TBL_DATA 0 5992167514Skmacy#define M_CPL_MAP_TBL_DATA 0xff 5993167514Skmacy#define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA) 5994167514Skmacy#define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA) 5995167514Skmacy 5996167514Skmacy/* registers for module SMB0 */ 5997167514Skmacy#define SMB0_BASE_ADDR 0x660 5998167514Skmacy 5999167514Skmacy#define A_SMB_GLOBAL_TIME_CFG 0x660 6000167514Skmacy 6001167514Skmacy#define S_LADBGWRPTR 24 6002167514Skmacy#define M_LADBGWRPTR 0xff 6003167514Skmacy#define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR) 6004167514Skmacy#define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR) 6005167514Skmacy 6006167514Skmacy#define S_LADBGRDPTR 16 6007167514Skmacy#define M_LADBGRDPTR 0xff 6008167514Skmacy#define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR) 6009167514Skmacy#define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR) 6010167514Skmacy 6011167514Skmacy#define S_LADBGEN 13 6012167514Skmacy#define V_LADBGEN(x) ((x) << S_LADBGEN) 6013167514Skmacy#define F_LADBGEN V_LADBGEN(1U) 6014167514Skmacy 6015167514Skmacy#define S_MACROCNTCFG 8 6016167514Skmacy#define M_MACROCNTCFG 0x1f 6017167514Skmacy#define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG) 6018167514Skmacy#define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG) 6019167514Skmacy 6020167514Skmacy#define S_MICROCNTCFG 0 6021167514Skmacy#define M_MICROCNTCFG 0xff 6022167514Skmacy#define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG) 6023167514Skmacy#define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG) 6024167514Skmacy 6025167514Skmacy#define A_SMB_MST_TIMEOUT_CFG 0x664 6026167514Skmacy 6027167514Skmacy#define S_DEBUGSELH 28 6028167514Skmacy#define M_DEBUGSELH 0xf 6029167514Skmacy#define V_DEBUGSELH(x) ((x) << S_DEBUGSELH) 6030167514Skmacy#define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH) 6031167514Skmacy 6032167514Skmacy#define S_DEBUGSELL 24 6033167514Skmacy#define M_DEBUGSELL 0xf 6034167514Skmacy#define V_DEBUGSELL(x) ((x) << S_DEBUGSELL) 6035167514Skmacy#define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL) 6036167514Skmacy 6037167514Skmacy#define S_MSTTIMEOUTCFG 0 6038167514Skmacy#define M_MSTTIMEOUTCFG 0xffffff 6039167514Skmacy#define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG) 6040167514Skmacy#define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG) 6041167514Skmacy 6042167514Skmacy#define A_SMB_MST_CTL_CFG 0x668 6043167514Skmacy 6044167514Skmacy#define S_MSTFIFODBG 31 6045167514Skmacy#define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG) 6046167514Skmacy#define F_MSTFIFODBG V_MSTFIFODBG(1U) 6047167514Skmacy 6048167514Skmacy#define S_MSTFIFODBGCLR 30 6049167514Skmacy#define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR) 6050167514Skmacy#define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U) 6051167514Skmacy 6052167514Skmacy#define S_MSTRXBYTECFG 12 6053167514Skmacy#define M_MSTRXBYTECFG 0x3f 6054167514Skmacy#define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG) 6055167514Skmacy#define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG) 6056167514Skmacy 6057167514Skmacy#define S_MSTTXBYTECFG 6 6058167514Skmacy#define M_MSTTXBYTECFG 0x3f 6059167514Skmacy#define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG) 6060167514Skmacy#define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG) 6061167514Skmacy 6062167514Skmacy#define S_MSTRESET 1 6063167514Skmacy#define V_MSTRESET(x) ((x) << S_MSTRESET) 6064167514Skmacy#define F_MSTRESET V_MSTRESET(1U) 6065167514Skmacy 6066167514Skmacy#define S_MSTCTLEN 0 6067167514Skmacy#define V_MSTCTLEN(x) ((x) << S_MSTCTLEN) 6068167514Skmacy#define F_MSTCTLEN V_MSTCTLEN(1U) 6069167514Skmacy 6070167514Skmacy#define A_SMB_MST_CTL_STS 0x66c 6071167514Skmacy 6072167514Skmacy#define S_MSTRXBYTECNT 12 6073167514Skmacy#define M_MSTRXBYTECNT 0x3f 6074167514Skmacy#define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT) 6075167514Skmacy#define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT) 6076167514Skmacy 6077167514Skmacy#define S_MSTTXBYTECNT 6 6078167514Skmacy#define M_MSTTXBYTECNT 0x3f 6079167514Skmacy#define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT) 6080167514Skmacy#define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT) 6081167514Skmacy 6082167514Skmacy#define S_MSTBUSYSTS 0 6083167514Skmacy#define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS) 6084167514Skmacy#define F_MSTBUSYSTS V_MSTBUSYSTS(1U) 6085167514Skmacy 6086167514Skmacy#define A_SMB_MST_TX_FIFO_RDWR 0x670 6087167514Skmacy#define A_SMB_MST_RX_FIFO_RDWR 0x674 6088167514Skmacy#define A_SMB_SLV_TIMEOUT_CFG 0x678 6089167514Skmacy 6090167514Skmacy#define S_SLVTIMEOUTCFG 0 6091167514Skmacy#define M_SLVTIMEOUTCFG 0xffffff 6092167514Skmacy#define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG) 6093167514Skmacy#define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG) 6094167514Skmacy 6095167514Skmacy#define A_SMB_SLV_CTL_CFG 0x67c 6096167514Skmacy 6097167514Skmacy#define S_SLVFIFODBG 31 6098167514Skmacy#define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG) 6099167514Skmacy#define F_SLVFIFODBG V_SLVFIFODBG(1U) 6100167514Skmacy 6101167514Skmacy#define S_SLVFIFODBGCLR 30 6102167514Skmacy#define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR) 6103167514Skmacy#define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U) 6104167514Skmacy 6105167514Skmacy#define S_SLVADDRCFG 4 6106167514Skmacy#define M_SLVADDRCFG 0x7f 6107167514Skmacy#define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG) 6108167514Skmacy#define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG) 6109167514Skmacy 6110167514Skmacy#define S_SLVALRTSET 2 6111167514Skmacy#define V_SLVALRTSET(x) ((x) << S_SLVALRTSET) 6112167514Skmacy#define F_SLVALRTSET V_SLVALRTSET(1U) 6113167514Skmacy 6114167514Skmacy#define S_SLVRESET 1 6115167514Skmacy#define V_SLVRESET(x) ((x) << S_SLVRESET) 6116167514Skmacy#define F_SLVRESET V_SLVRESET(1U) 6117167514Skmacy 6118167514Skmacy#define S_SLVCTLEN 0 6119167514Skmacy#define V_SLVCTLEN(x) ((x) << S_SLVCTLEN) 6120167514Skmacy#define F_SLVCTLEN V_SLVCTLEN(1U) 6121167514Skmacy 6122167514Skmacy#define A_SMB_SLV_CTL_STS 0x680 6123167514Skmacy 6124167514Skmacy#define S_SLVFIFOTXCNT 12 6125167514Skmacy#define M_SLVFIFOTXCNT 0x3f 6126167514Skmacy#define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT) 6127167514Skmacy#define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT) 6128167514Skmacy 6129167514Skmacy#define S_SLVFIFOCNT 6 6130167514Skmacy#define M_SLVFIFOCNT 0x3f 6131167514Skmacy#define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT) 6132167514Skmacy#define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT) 6133167514Skmacy 6134167514Skmacy#define S_SLVALRTSTS 2 6135167514Skmacy#define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS) 6136167514Skmacy#define F_SLVALRTSTS V_SLVALRTSTS(1U) 6137167514Skmacy 6138167514Skmacy#define S_SLVBUSYSTS 0 6139167514Skmacy#define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS) 6140167514Skmacy#define F_SLVBUSYSTS V_SLVBUSYSTS(1U) 6141167514Skmacy 6142167514Skmacy#define A_SMB_SLV_FIFO_RDWR 0x684 6143167514Skmacy#define A_SMB_SLV_CMD_FIFO_RDWR 0x688 6144167514Skmacy#define A_SMB_INT_ENABLE 0x68c 6145167514Skmacy 6146167514Skmacy#define S_SLVTIMEOUTINTEN 7 6147167514Skmacy#define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN) 6148167514Skmacy#define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U) 6149167514Skmacy 6150167514Skmacy#define S_SLVERRINTEN 6 6151167514Skmacy#define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN) 6152167514Skmacy#define F_SLVERRINTEN V_SLVERRINTEN(1U) 6153167514Skmacy 6154167514Skmacy#define S_SLVDONEINTEN 5 6155167514Skmacy#define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN) 6156167514Skmacy#define F_SLVDONEINTEN V_SLVDONEINTEN(1U) 6157167514Skmacy 6158167514Skmacy#define S_SLVRXRDYINTEN 4 6159167514Skmacy#define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN) 6160167514Skmacy#define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U) 6161167514Skmacy 6162167514Skmacy#define S_MSTTIMEOUTINTEN 3 6163167514Skmacy#define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN) 6164167514Skmacy#define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U) 6165167514Skmacy 6166167514Skmacy#define S_MSTNACKINTEN 2 6167167514Skmacy#define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN) 6168167514Skmacy#define F_MSTNACKINTEN V_MSTNACKINTEN(1U) 6169167514Skmacy 6170167514Skmacy#define S_MSTLOSTARBINTEN 1 6171167514Skmacy#define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN) 6172167514Skmacy#define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U) 6173167514Skmacy 6174167514Skmacy#define S_MSTDONEINTEN 0 6175167514Skmacy#define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN) 6176167514Skmacy#define F_MSTDONEINTEN V_MSTDONEINTEN(1U) 6177167514Skmacy 6178167514Skmacy#define A_SMB_INT_CAUSE 0x690 6179167514Skmacy 6180167514Skmacy#define S_SLVTIMEOUTINT 7 6181167514Skmacy#define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT) 6182167514Skmacy#define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U) 6183167514Skmacy 6184167514Skmacy#define S_SLVERRINT 6 6185167514Skmacy#define V_SLVERRINT(x) ((x) << S_SLVERRINT) 6186167514Skmacy#define F_SLVERRINT V_SLVERRINT(1U) 6187167514Skmacy 6188167514Skmacy#define S_SLVDONEINT 5 6189167514Skmacy#define V_SLVDONEINT(x) ((x) << S_SLVDONEINT) 6190167514Skmacy#define F_SLVDONEINT V_SLVDONEINT(1U) 6191167514Skmacy 6192167514Skmacy#define S_SLVRXRDYINT 4 6193167514Skmacy#define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT) 6194167514Skmacy#define F_SLVRXRDYINT V_SLVRXRDYINT(1U) 6195167514Skmacy 6196167514Skmacy#define S_MSTTIMEOUTINT 3 6197167514Skmacy#define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT) 6198167514Skmacy#define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U) 6199167514Skmacy 6200167514Skmacy#define S_MSTNACKINT 2 6201167514Skmacy#define V_MSTNACKINT(x) ((x) << S_MSTNACKINT) 6202167514Skmacy#define F_MSTNACKINT V_MSTNACKINT(1U) 6203167514Skmacy 6204167514Skmacy#define S_MSTLOSTARBINT 1 6205167514Skmacy#define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT) 6206167514Skmacy#define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U) 6207167514Skmacy 6208167514Skmacy#define S_MSTDONEINT 0 6209167514Skmacy#define V_MSTDONEINT(x) ((x) << S_MSTDONEINT) 6210167514Skmacy#define F_MSTDONEINT V_MSTDONEINT(1U) 6211167514Skmacy 6212167514Skmacy#define A_SMB_DEBUG_DATA 0x694 6213167514Skmacy 6214167514Skmacy#define S_DEBUGDATAH 16 6215167514Skmacy#define M_DEBUGDATAH 0xffff 6216167514Skmacy#define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH) 6217167514Skmacy#define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH) 6218167514Skmacy 6219167514Skmacy#define S_DEBUGDATAL 0 6220167514Skmacy#define M_DEBUGDATAL 0xffff 6221167514Skmacy#define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL) 6222167514Skmacy#define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL) 6223167514Skmacy 6224167514Skmacy#define A_SMB_DEBUG_LA 0x69c 6225167514Skmacy 6226167514Skmacy#define S_DEBUGLAREQADDR 0 6227167514Skmacy#define M_DEBUGLAREQADDR 0x3ff 6228167514Skmacy#define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR) 6229167514Skmacy#define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR) 6230167514Skmacy 6231167514Skmacy/* registers for module I2CM0 */ 6232167514Skmacy#define I2CM0_BASE_ADDR 0x6a0 6233167514Skmacy 6234167514Skmacy#define A_I2C_CFG 0x6a0 6235167514Skmacy 6236167514Skmacy#define S_I2C_CLKDIV 0 6237167514Skmacy#define M_I2C_CLKDIV 0xfff 6238167514Skmacy#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) 6239167514Skmacy#define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV) 6240167514Skmacy 6241167514Skmacy#define A_I2C_DATA 0x6a4 6242167514Skmacy#define A_I2C_OP 0x6a8 6243167514Skmacy 6244167514Skmacy#define S_ACK 30 6245167514Skmacy#define V_ACK(x) ((x) << S_ACK) 6246167514Skmacy#define F_ACK V_ACK(1U) 6247167514Skmacy 6248197791Snp#define S_I2C_DATA 0 6249197791Snp#define M_I2C_DATA 0xff 6250197791Snp#define V_I2C_DATA(x) ((x) << S_I2C_DATA) 6251197791Snp#define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA) 6252197791Snp 6253197791Snp#define S_I2C_BUSY 31 6254197791Snp#define V_I2C_BUSY(x) ((x) << S_I2C_BUSY) 6255197791Snp#define F_I2C_BUSY V_I2C_BUSY(1U) 6256197791Snp 6257197791Snp#define S_I2C_ACK 30 6258197791Snp#define V_I2C_ACK(x) ((x) << S_I2C_ACK) 6259197791Snp#define F_I2C_ACK V_I2C_ACK(1U) 6260197791Snp 6261167514Skmacy#define S_I2C_CONT 1 6262167514Skmacy#define V_I2C_CONT(x) ((x) << S_I2C_CONT) 6263167514Skmacy#define F_I2C_CONT V_I2C_CONT(1U) 6264167514Skmacy 6265197791Snp#define S_I2C_RDWR 0 6266197791Snp#define V_I2C_RDWR(x) ((x) << S_I2C_RDWR) 6267197791Snp#define F_I2C_READ V_I2C_RDWR(0U) 6268197791Snp#define F_I2C_WRITE V_I2C_RDWR(1U) 6269197791Snp 6270167514Skmacy/* registers for module MI1 */ 6271167514Skmacy#define MI1_BASE_ADDR 0x6b0 6272167514Skmacy 6273167514Skmacy#define A_MI1_CFG 0x6b0 6274167514Skmacy 6275167514Skmacy#define S_CLKDIV 5 6276167514Skmacy#define M_CLKDIV 0xff 6277167514Skmacy#define V_CLKDIV(x) ((x) << S_CLKDIV) 6278167514Skmacy#define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV) 6279167514Skmacy 6280167514Skmacy#define S_ST 3 6281167514Skmacy#define M_ST 0x3 6282167514Skmacy#define V_ST(x) ((x) << S_ST) 6283167514Skmacy#define G_ST(x) (((x) >> S_ST) & M_ST) 6284167514Skmacy 6285167514Skmacy#define S_PREEN 2 6286167514Skmacy#define V_PREEN(x) ((x) << S_PREEN) 6287167514Skmacy#define F_PREEN V_PREEN(1U) 6288167514Skmacy 6289167514Skmacy#define S_MDIINV 1 6290167514Skmacy#define V_MDIINV(x) ((x) << S_MDIINV) 6291167514Skmacy#define F_MDIINV V_MDIINV(1U) 6292167514Skmacy 6293167514Skmacy#define S_MDIEN 0 6294167514Skmacy#define V_MDIEN(x) ((x) << S_MDIEN) 6295167514Skmacy#define F_MDIEN V_MDIEN(1U) 6296167514Skmacy 6297167514Skmacy#define A_MI1_ADDR 0x6b4 6298167514Skmacy 6299167514Skmacy#define S_PHYADDR 5 6300167514Skmacy#define M_PHYADDR 0x1f 6301167514Skmacy#define V_PHYADDR(x) ((x) << S_PHYADDR) 6302167514Skmacy#define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR) 6303167514Skmacy 6304167514Skmacy#define S_REGADDR 0 6305167514Skmacy#define M_REGADDR 0x1f 6306167514Skmacy#define V_REGADDR(x) ((x) << S_REGADDR) 6307167514Skmacy#define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR) 6308167514Skmacy 6309167514Skmacy#define A_MI1_DATA 0x6b8 6310167514Skmacy 6311167514Skmacy#define S_MDI_DATA 0 6312167514Skmacy#define M_MDI_DATA 0xffff 6313167514Skmacy#define V_MDI_DATA(x) ((x) << S_MDI_DATA) 6314167514Skmacy#define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA) 6315167514Skmacy 6316167514Skmacy#define A_MI1_OP 0x6bc 6317167514Skmacy 6318167514Skmacy#define S_INC 2 6319167514Skmacy#define V_INC(x) ((x) << S_INC) 6320167514Skmacy#define F_INC V_INC(1U) 6321167514Skmacy 6322167514Skmacy#define S_MDI_OP 0 6323167514Skmacy#define M_MDI_OP 0x3 6324167514Skmacy#define V_MDI_OP(x) ((x) << S_MDI_OP) 6325167514Skmacy#define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP) 6326167514Skmacy 6327167514Skmacy/* registers for module JM1 */ 6328167514Skmacy#define JM1_BASE_ADDR 0x6c0 6329167514Skmacy 6330167514Skmacy#define A_JM_CFG 0x6c0 6331167514Skmacy 6332167514Skmacy#define S_JM_CLKDIV 2 6333167514Skmacy#define M_JM_CLKDIV 0xff 6334167514Skmacy#define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV) 6335167514Skmacy#define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV) 6336167514Skmacy 6337167514Skmacy#define S_TRST 1 6338167514Skmacy#define V_TRST(x) ((x) << S_TRST) 6339167514Skmacy#define F_TRST V_TRST(1U) 6340167514Skmacy 6341167514Skmacy#define S_EN 0 6342167514Skmacy#define V_EN(x) ((x) << S_EN) 6343167514Skmacy#define F_EN V_EN(1U) 6344167514Skmacy 6345167514Skmacy#define A_JM_MODE 0x6c4 6346167514Skmacy#define A_JM_DATA 0x6c8 6347167514Skmacy#define A_JM_OP 0x6cc 6348167514Skmacy 6349167514Skmacy#define S_CNT 0 6350167514Skmacy#define M_CNT 0x1f 6351167514Skmacy#define V_CNT(x) ((x) << S_CNT) 6352167514Skmacy#define G_CNT(x) (((x) >> S_CNT) & M_CNT) 6353167514Skmacy 6354167514Skmacy/* registers for module SF1 */ 6355167514Skmacy#define SF1_BASE_ADDR 0x6d8 6356167514Skmacy 6357167514Skmacy#define A_SF_DATA 0x6d8 6358167514Skmacy#define A_SF_OP 0x6dc 6359167514Skmacy 6360167514Skmacy#define S_BYTECNT 1 6361167514Skmacy#define M_BYTECNT 0x3 6362167514Skmacy#define V_BYTECNT(x) ((x) << S_BYTECNT) 6363167514Skmacy#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 6364167514Skmacy 6365167514Skmacy/* registers for module PL3 */ 6366167514Skmacy#define PL3_BASE_ADDR 0x6e0 6367167514Skmacy 6368167514Skmacy#define A_PL_INT_ENABLE0 0x6e0 6369167514Skmacy 6370176472Skmacy#define S_SW 25 6371176472Skmacy#define V_SW(x) ((x) << S_SW) 6372176472Skmacy#define F_SW V_SW(1U) 6373176472Skmacy 6374167514Skmacy#define S_EXT 24 6375167514Skmacy#define V_EXT(x) ((x) << S_EXT) 6376167514Skmacy#define F_EXT V_EXT(1U) 6377167514Skmacy 6378167514Skmacy#define S_T3DBG 23 6379167514Skmacy#define V_T3DBG(x) ((x) << S_T3DBG) 6380167514Skmacy#define F_T3DBG V_T3DBG(1U) 6381167514Skmacy 6382167514Skmacy#define S_XGMAC0_1 20 6383167514Skmacy#define V_XGMAC0_1(x) ((x) << S_XGMAC0_1) 6384167514Skmacy#define F_XGMAC0_1 V_XGMAC0_1(1U) 6385167514Skmacy 6386167514Skmacy#define S_XGMAC0_0 19 6387167514Skmacy#define V_XGMAC0_0(x) ((x) << S_XGMAC0_0) 6388167514Skmacy#define F_XGMAC0_0 V_XGMAC0_0(1U) 6389167514Skmacy 6390167514Skmacy#define S_MC5A 18 6391167514Skmacy#define V_MC5A(x) ((x) << S_MC5A) 6392167514Skmacy#define F_MC5A V_MC5A(1U) 6393167514Skmacy 6394167514Skmacy#define S_SF1 17 6395167514Skmacy#define V_SF1(x) ((x) << S_SF1) 6396167514Skmacy#define F_SF1 V_SF1(1U) 6397167514Skmacy 6398167514Skmacy#define S_SMB0 15 6399167514Skmacy#define V_SMB0(x) ((x) << S_SMB0) 6400167514Skmacy#define F_SMB0 V_SMB0(1U) 6401167514Skmacy 6402167514Skmacy#define S_I2CM0 14 6403167514Skmacy#define V_I2CM0(x) ((x) << S_I2CM0) 6404167514Skmacy#define F_I2CM0 V_I2CM0(1U) 6405167514Skmacy 6406167514Skmacy#define S_MI1 13 6407167514Skmacy#define V_MI1(x) ((x) << S_MI1) 6408167514Skmacy#define F_MI1 V_MI1(1U) 6409167514Skmacy 6410167514Skmacy#define S_CPL_SWITCH 12 6411167514Skmacy#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) 6412167514Skmacy#define F_CPL_SWITCH V_CPL_SWITCH(1U) 6413167514Skmacy 6414167514Skmacy#define S_MPS0 11 6415167514Skmacy#define V_MPS0(x) ((x) << S_MPS0) 6416167514Skmacy#define F_MPS0 V_MPS0(1U) 6417167514Skmacy 6418167514Skmacy#define S_PM1_TX 10 6419167514Skmacy#define V_PM1_TX(x) ((x) << S_PM1_TX) 6420167514Skmacy#define F_PM1_TX V_PM1_TX(1U) 6421167514Skmacy 6422167514Skmacy#define S_PM1_RX 9 6423167514Skmacy#define V_PM1_RX(x) ((x) << S_PM1_RX) 6424167514Skmacy#define F_PM1_RX V_PM1_RX(1U) 6425167514Skmacy 6426167514Skmacy#define S_ULP2_TX 8 6427167514Skmacy#define V_ULP2_TX(x) ((x) << S_ULP2_TX) 6428167514Skmacy#define F_ULP2_TX V_ULP2_TX(1U) 6429167514Skmacy 6430167514Skmacy#define S_ULP2_RX 7 6431167514Skmacy#define V_ULP2_RX(x) ((x) << S_ULP2_RX) 6432167514Skmacy#define F_ULP2_RX V_ULP2_RX(1U) 6433167514Skmacy 6434167514Skmacy#define S_TP1 6 6435167514Skmacy#define V_TP1(x) ((x) << S_TP1) 6436167514Skmacy#define F_TP1 V_TP1(1U) 6437167514Skmacy 6438167514Skmacy#define S_CIM 5 6439167514Skmacy#define V_CIM(x) ((x) << S_CIM) 6440167514Skmacy#define F_CIM V_CIM(1U) 6441167514Skmacy 6442167514Skmacy#define S_MC7_CM 4 6443167514Skmacy#define V_MC7_CM(x) ((x) << S_MC7_CM) 6444167514Skmacy#define F_MC7_CM V_MC7_CM(1U) 6445167514Skmacy 6446167514Skmacy#define S_MC7_PMTX 3 6447167514Skmacy#define V_MC7_PMTX(x) ((x) << S_MC7_PMTX) 6448167514Skmacy#define F_MC7_PMTX V_MC7_PMTX(1U) 6449167514Skmacy 6450167514Skmacy#define S_MC7_PMRX 2 6451167514Skmacy#define V_MC7_PMRX(x) ((x) << S_MC7_PMRX) 6452167514Skmacy#define F_MC7_PMRX V_MC7_PMRX(1U) 6453167514Skmacy 6454167514Skmacy#define S_PCIM0 1 6455167514Skmacy#define V_PCIM0(x) ((x) << S_PCIM0) 6456167514Skmacy#define F_PCIM0 V_PCIM0(1U) 6457167514Skmacy 6458167514Skmacy#define S_SGE3 0 6459167514Skmacy#define V_SGE3(x) ((x) << S_SGE3) 6460167514Skmacy#define F_SGE3 V_SGE3(1U) 6461167514Skmacy 6462167514Skmacy#define A_PL_INT_CAUSE0 0x6e4 6463167514Skmacy#define A_PL_INT_ENABLE1 0x6e8 6464167514Skmacy#define A_PL_INT_CAUSE1 0x6ec 6465167514Skmacy#define A_PL_RST 0x6f0 6466167514Skmacy 6467176472Skmacy#define S_FATALPERREN 4 6468176472Skmacy#define V_FATALPERREN(x) ((x) << S_FATALPERREN) 6469176472Skmacy#define F_FATALPERREN V_FATALPERREN(1U) 6470167514Skmacy 6471167514Skmacy#define S_SWINT1 3 6472167514Skmacy#define V_SWINT1(x) ((x) << S_SWINT1) 6473167514Skmacy#define F_SWINT1 V_SWINT1(1U) 6474167514Skmacy 6475167514Skmacy#define S_SWINT0 2 6476167514Skmacy#define V_SWINT0(x) ((x) << S_SWINT0) 6477167514Skmacy#define F_SWINT0 V_SWINT0(1U) 6478167514Skmacy 6479176472Skmacy#define S_CRSTWRM 1 6480176472Skmacy#define V_CRSTWRM(x) ((x) << S_CRSTWRM) 6481176472Skmacy#define F_CRSTWRM V_CRSTWRM(1U) 6482176472Skmacy 6483167514Skmacy#define A_PL_REV 0x6f4 6484167514Skmacy 6485167514Skmacy#define S_REV 0 6486167514Skmacy#define M_REV 0xf 6487167514Skmacy#define V_REV(x) ((x) << S_REV) 6488167514Skmacy#define G_REV(x) (((x) >> S_REV) & M_REV) 6489167514Skmacy 6490167514Skmacy#define A_PL_CLI 0x6f8 6491167514Skmacy#define A_PL_LCK 0x6fc 6492167514Skmacy 6493167514Skmacy#define S_LCK 0 6494167514Skmacy#define M_LCK 0x3 6495167514Skmacy#define V_LCK(x) ((x) << S_LCK) 6496167514Skmacy#define G_LCK(x) (((x) >> S_LCK) & M_LCK) 6497167514Skmacy 6498167514Skmacy/* registers for module MC5A */ 6499167514Skmacy#define MC5A_BASE_ADDR 0x700 6500167514Skmacy 6501167514Skmacy#define A_MC5_BUF_CONFIG 0x700 6502167514Skmacy 6503167514Skmacy#define S_TERM300_240 31 6504167514Skmacy#define V_TERM300_240(x) ((x) << S_TERM300_240) 6505167514Skmacy#define F_TERM300_240 V_TERM300_240(1U) 6506167514Skmacy 6507167514Skmacy#define S_MC5_TERM150 30 6508167514Skmacy#define V_MC5_TERM150(x) ((x) << S_MC5_TERM150) 6509167514Skmacy#define F_MC5_TERM150 V_MC5_TERM150(1U) 6510167514Skmacy 6511167514Skmacy#define S_TERM60 29 6512167514Skmacy#define V_TERM60(x) ((x) << S_TERM60) 6513167514Skmacy#define F_TERM60 V_TERM60(1U) 6514167514Skmacy 6515167514Skmacy#define S_GDDRIII 28 6516167514Skmacy#define V_GDDRIII(x) ((x) << S_GDDRIII) 6517167514Skmacy#define F_GDDRIII V_GDDRIII(1U) 6518167514Skmacy 6519167514Skmacy#define S_GDDRII 27 6520167514Skmacy#define V_GDDRII(x) ((x) << S_GDDRII) 6521167514Skmacy#define F_GDDRII V_GDDRII(1U) 6522167514Skmacy 6523167514Skmacy#define S_GDDRI 26 6524167514Skmacy#define V_GDDRI(x) ((x) << S_GDDRI) 6525167514Skmacy#define F_GDDRI V_GDDRI(1U) 6526167514Skmacy 6527167514Skmacy#define S_READ 25 6528167514Skmacy#define V_READ(x) ((x) << S_READ) 6529167514Skmacy#define F_READ V_READ(1U) 6530167514Skmacy 6531176472Skmacy#define S_IMP_SET_UPDATE 24 6532176472Skmacy#define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE) 6533176472Skmacy#define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U) 6534167514Skmacy 6535176472Skmacy#define S_CAL_UPDATE 23 6536176472Skmacy#define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE) 6537176472Skmacy#define F_CAL_UPDATE V_CAL_UPDATE(1U) 6538176472Skmacy 6539167514Skmacy#define S_CAL_BUSY 22 6540167514Skmacy#define V_CAL_BUSY(x) ((x) << S_CAL_BUSY) 6541167514Skmacy#define F_CAL_BUSY V_CAL_BUSY(1U) 6542167514Skmacy 6543167514Skmacy#define S_CAL_ERROR 21 6544167514Skmacy#define V_CAL_ERROR(x) ((x) << S_CAL_ERROR) 6545167514Skmacy#define F_CAL_ERROR V_CAL_ERROR(1U) 6546167514Skmacy 6547167514Skmacy#define S_SGL_CAL_EN 20 6548167514Skmacy#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) 6549167514Skmacy#define F_SGL_CAL_EN V_SGL_CAL_EN(1U) 6550167514Skmacy 6551167514Skmacy#define S_IMP_UPD_MODE 19 6552167514Skmacy#define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) 6553167514Skmacy#define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) 6554167514Skmacy 6555167514Skmacy#define S_IMP_SEL 18 6556167514Skmacy#define V_IMP_SEL(x) ((x) << S_IMP_SEL) 6557167514Skmacy#define F_IMP_SEL V_IMP_SEL(1U) 6558167514Skmacy 6559167514Skmacy#define S_MAN_PU 15 6560167514Skmacy#define M_MAN_PU 0x7 6561167514Skmacy#define V_MAN_PU(x) ((x) << S_MAN_PU) 6562167514Skmacy#define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU) 6563167514Skmacy 6564167514Skmacy#define S_MAN_PD 12 6565167514Skmacy#define M_MAN_PD 0x7 6566167514Skmacy#define V_MAN_PD(x) ((x) << S_MAN_PD) 6567167514Skmacy#define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD) 6568167514Skmacy 6569167514Skmacy#define S_CAL_PU 9 6570167514Skmacy#define M_CAL_PU 0x7 6571167514Skmacy#define V_CAL_PU(x) ((x) << S_CAL_PU) 6572167514Skmacy#define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU) 6573167514Skmacy 6574167514Skmacy#define S_CAL_PD 6 6575167514Skmacy#define M_CAL_PD 0x7 6576167514Skmacy#define V_CAL_PD(x) ((x) << S_CAL_PD) 6577167514Skmacy#define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD) 6578167514Skmacy 6579167514Skmacy#define S_SET_PU 3 6580167514Skmacy#define M_SET_PU 0x7 6581167514Skmacy#define V_SET_PU(x) ((x) << S_SET_PU) 6582167514Skmacy#define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) 6583167514Skmacy 6584167514Skmacy#define S_SET_PD 0 6585167514Skmacy#define M_SET_PD 0x7 6586167514Skmacy#define V_SET_PD(x) ((x) << S_SET_PD) 6587167514Skmacy#define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) 6588167514Skmacy 6589176472Skmacy#define S_CAL_IMP_UPD 23 6590176472Skmacy#define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD) 6591176472Skmacy#define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U) 6592167514Skmacy 6593167514Skmacy#define A_MC5_DB_CONFIG 0x704 6594167514Skmacy 6595167514Skmacy#define S_TMCFGWRLOCK 31 6596167514Skmacy#define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK) 6597167514Skmacy#define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U) 6598167514Skmacy 6599167514Skmacy#define S_TMTYPEHI 30 6600167514Skmacy#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) 6601167514Skmacy#define F_TMTYPEHI V_TMTYPEHI(1U) 6602167514Skmacy 6603167514Skmacy#define S_TMPARTSIZE 28 6604167514Skmacy#define M_TMPARTSIZE 0x3 6605167514Skmacy#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE) 6606167514Skmacy#define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE) 6607167514Skmacy 6608167514Skmacy#define S_TMTYPE 26 6609167514Skmacy#define M_TMTYPE 0x3 6610167514Skmacy#define V_TMTYPE(x) ((x) << S_TMTYPE) 6611167514Skmacy#define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE) 6612167514Skmacy 6613167514Skmacy#define S_TMPARTCOUNT 24 6614167514Skmacy#define M_TMPARTCOUNT 0x3 6615167514Skmacy#define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT) 6616167514Skmacy#define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT) 6617167514Skmacy 6618167514Skmacy#define S_NLIP 18 6619167514Skmacy#define M_NLIP 0x3f 6620167514Skmacy#define V_NLIP(x) ((x) << S_NLIP) 6621167514Skmacy#define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP) 6622167514Skmacy 6623167514Skmacy#define S_COMPEN 17 6624167514Skmacy#define V_COMPEN(x) ((x) << S_COMPEN) 6625167514Skmacy#define F_COMPEN V_COMPEN(1U) 6626167514Skmacy 6627167514Skmacy#define S_BUILD 16 6628167514Skmacy#define V_BUILD(x) ((x) << S_BUILD) 6629167514Skmacy#define F_BUILD V_BUILD(1U) 6630167514Skmacy 6631176472Skmacy#define S_FILTEREN 11 6632176472Skmacy#define V_FILTEREN(x) ((x) << S_FILTEREN) 6633176472Skmacy#define F_FILTEREN V_FILTEREN(1U) 6634176472Skmacy 6635176472Skmacy#define S_CLIPUPDATE 10 6636176472Skmacy#define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE) 6637176472Skmacy#define F_CLIPUPDATE V_CLIPUPDATE(1U) 6638176472Skmacy 6639167514Skmacy#define S_TM_IO_PDOWN 9 6640167514Skmacy#define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN) 6641167514Skmacy#define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U) 6642167514Skmacy 6643167514Skmacy#define S_SYNMODE 7 6644167514Skmacy#define M_SYNMODE 0x3 6645167514Skmacy#define V_SYNMODE(x) ((x) << S_SYNMODE) 6646167514Skmacy#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) 6647167514Skmacy 6648167514Skmacy#define S_PRTYEN 6 6649167514Skmacy#define V_PRTYEN(x) ((x) << S_PRTYEN) 6650167514Skmacy#define F_PRTYEN V_PRTYEN(1U) 6651167514Skmacy 6652167514Skmacy#define S_MBUSEN 5 6653167514Skmacy#define V_MBUSEN(x) ((x) << S_MBUSEN) 6654167514Skmacy#define F_MBUSEN V_MBUSEN(1U) 6655167514Skmacy 6656167514Skmacy#define S_DBGIEN 4 6657167514Skmacy#define V_DBGIEN(x) ((x) << S_DBGIEN) 6658167514Skmacy#define F_DBGIEN V_DBGIEN(1U) 6659167514Skmacy 6660176472Skmacy#define S_TCMCFGOVR 3 6661176472Skmacy#define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR) 6662176472Skmacy#define F_TCMCFGOVR V_TCMCFGOVR(1U) 6663176472Skmacy 6664167514Skmacy#define S_TMRDY 2 6665167514Skmacy#define V_TMRDY(x) ((x) << S_TMRDY) 6666167514Skmacy#define F_TMRDY V_TMRDY(1U) 6667167514Skmacy 6668167514Skmacy#define S_TMRST 1 6669167514Skmacy#define V_TMRST(x) ((x) << S_TMRST) 6670167514Skmacy#define F_TMRST V_TMRST(1U) 6671167514Skmacy 6672167514Skmacy#define S_TMMODE 0 6673167514Skmacy#define V_TMMODE(x) ((x) << S_TMMODE) 6674167514Skmacy#define F_TMMODE V_TMMODE(1U) 6675167514Skmacy 6676167514Skmacy#define A_MC5_MISC 0x708 6677167514Skmacy 6678167514Skmacy#define S_LIP_CMP_UNAVAILABLE 0 6679167514Skmacy#define M_LIP_CMP_UNAVAILABLE 0xf 6680167514Skmacy#define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) 6681167514Skmacy#define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) 6682167514Skmacy 6683167514Skmacy#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c 6684167514Skmacy 6685167514Skmacy#define S_RTINDX 0 6686167514Skmacy#define M_RTINDX 0x3fffff 6687167514Skmacy#define V_RTINDX(x) ((x) << S_RTINDX) 6688167514Skmacy#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) 6689167514Skmacy 6690167514Skmacy#define A_MC5_DB_FILTER_TABLE 0x710 6691167514Skmacy 6692167514Skmacy#define S_SRINDX 0 6693167514Skmacy#define M_SRINDX 0x3fffff 6694167514Skmacy#define V_SRINDX(x) ((x) << S_SRINDX) 6695167514Skmacy#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) 6696167514Skmacy 6697176472Skmacy#define A_MC5_DB_SERVER_INDEX 0x714 6698167514Skmacy#define A_MC5_DB_LIP_RAM_ADDR 0x718 6699167514Skmacy 6700167514Skmacy#define S_RAMWR 8 6701167514Skmacy#define V_RAMWR(x) ((x) << S_RAMWR) 6702167514Skmacy#define F_RAMWR V_RAMWR(1U) 6703167514Skmacy 6704167514Skmacy#define S_RAMADDR 0 6705167514Skmacy#define M_RAMADDR 0x3f 6706167514Skmacy#define V_RAMADDR(x) ((x) << S_RAMADDR) 6707167514Skmacy#define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR) 6708167514Skmacy 6709167514Skmacy#define A_MC5_DB_LIP_RAM_DATA 0x71c 6710167514Skmacy#define A_MC5_DB_RSP_LATENCY 0x720 6711167514Skmacy 6712167514Skmacy#define S_RDLAT 16 6713167514Skmacy#define M_RDLAT 0x1f 6714167514Skmacy#define V_RDLAT(x) ((x) << S_RDLAT) 6715167514Skmacy#define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT) 6716167514Skmacy 6717167514Skmacy#define S_LRNLAT 8 6718167514Skmacy#define M_LRNLAT 0x1f 6719167514Skmacy#define V_LRNLAT(x) ((x) << S_LRNLAT) 6720167514Skmacy#define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT) 6721167514Skmacy 6722167514Skmacy#define S_SRCHLAT 0 6723167514Skmacy#define M_SRCHLAT 0x1f 6724167514Skmacy#define V_SRCHLAT(x) ((x) << S_SRCHLAT) 6725167514Skmacy#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) 6726167514Skmacy 6727167514Skmacy#define A_MC5_DB_PARITY_LATENCY 0x724 6728167514Skmacy 6729167514Skmacy#define S_PARLAT 0 6730167514Skmacy#define M_PARLAT 0xf 6731167514Skmacy#define V_PARLAT(x) ((x) << S_PARLAT) 6732167514Skmacy#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) 6733167514Skmacy 6734167514Skmacy#define A_MC5_DB_WR_LRN_VERIFY 0x728 6735167514Skmacy 6736167514Skmacy#define S_VWVEREN 2 6737167514Skmacy#define V_VWVEREN(x) ((x) << S_VWVEREN) 6738167514Skmacy#define F_VWVEREN V_VWVEREN(1U) 6739167514Skmacy 6740167514Skmacy#define S_LRNVEREN 1 6741167514Skmacy#define V_LRNVEREN(x) ((x) << S_LRNVEREN) 6742167514Skmacy#define F_LRNVEREN V_LRNVEREN(1U) 6743167514Skmacy 6744167514Skmacy#define S_POVEREN 0 6745167514Skmacy#define V_POVEREN(x) ((x) << S_POVEREN) 6746167514Skmacy#define F_POVEREN V_POVEREN(1U) 6747167514Skmacy 6748167514Skmacy#define A_MC5_DB_PART_ID_INDEX 0x72c 6749167514Skmacy 6750167514Skmacy#define S_IDINDEX 0 6751167514Skmacy#define M_IDINDEX 0xf 6752167514Skmacy#define V_IDINDEX(x) ((x) << S_IDINDEX) 6753167514Skmacy#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) 6754167514Skmacy 6755167514Skmacy#define A_MC5_DB_RESET_MAX 0x730 6756167514Skmacy 6757167514Skmacy#define S_RSTMAX 0 6758167514Skmacy#define M_RSTMAX 0xf 6759167514Skmacy#define V_RSTMAX(x) ((x) << S_RSTMAX) 6760167514Skmacy#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) 6761167514Skmacy 6762167514Skmacy#define A_MC5_DB_ACT_CNT 0x734 6763167514Skmacy 6764167514Skmacy#define S_ACTCNT 0 6765167514Skmacy#define M_ACTCNT 0xfffff 6766167514Skmacy#define V_ACTCNT(x) ((x) << S_ACTCNT) 6767167514Skmacy#define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT) 6768167514Skmacy 6769167514Skmacy#define A_MC5_DB_CLIP_MAP 0x738 6770167514Skmacy 6771167514Skmacy#define S_CLIPMAPOP 31 6772167514Skmacy#define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP) 6773167514Skmacy#define F_CLIPMAPOP V_CLIPMAPOP(1U) 6774167514Skmacy 6775167514Skmacy#define S_CLIPMAPVAL 16 6776167514Skmacy#define M_CLIPMAPVAL 0x3f 6777167514Skmacy#define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) 6778167514Skmacy#define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) 6779167514Skmacy 6780167514Skmacy#define S_CLIPMAPADDR 0 6781167514Skmacy#define M_CLIPMAPADDR 0x3f 6782167514Skmacy#define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) 6783167514Skmacy#define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) 6784167514Skmacy 6785176472Skmacy#define A_MC5_DB_SIZE 0x73c 6786167514Skmacy#define A_MC5_DB_INT_ENABLE 0x740 6787167514Skmacy 6788167514Skmacy#define S_MSGSEL 28 6789167514Skmacy#define M_MSGSEL 0xf 6790167514Skmacy#define V_MSGSEL(x) ((x) << S_MSGSEL) 6791167514Skmacy#define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL) 6792167514Skmacy 6793167514Skmacy#define S_DELACTEMPTY 18 6794167514Skmacy#define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY) 6795167514Skmacy#define F_DELACTEMPTY V_DELACTEMPTY(1U) 6796167514Skmacy 6797167514Skmacy#define S_DISPQPARERR 17 6798167514Skmacy#define V_DISPQPARERR(x) ((x) << S_DISPQPARERR) 6799167514Skmacy#define F_DISPQPARERR V_DISPQPARERR(1U) 6800167514Skmacy 6801167514Skmacy#define S_REQQPARERR 16 6802167514Skmacy#define V_REQQPARERR(x) ((x) << S_REQQPARERR) 6803167514Skmacy#define F_REQQPARERR V_REQQPARERR(1U) 6804167514Skmacy 6805167514Skmacy#define S_UNKNOWNCMD 15 6806167514Skmacy#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) 6807167514Skmacy#define F_UNKNOWNCMD V_UNKNOWNCMD(1U) 6808167514Skmacy 6809167514Skmacy#define S_SYNCOOKIEOFF 11 6810167514Skmacy#define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF) 6811167514Skmacy#define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U) 6812167514Skmacy 6813167514Skmacy#define S_SYNCOOKIEBAD 10 6814167514Skmacy#define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD) 6815167514Skmacy#define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U) 6816167514Skmacy 6817167514Skmacy#define S_SYNCOOKIE 9 6818167514Skmacy#define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE) 6819167514Skmacy#define F_SYNCOOKIE V_SYNCOOKIE(1U) 6820167514Skmacy 6821167514Skmacy#define S_NFASRCHFAIL 8 6822167514Skmacy#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) 6823167514Skmacy#define F_NFASRCHFAIL V_NFASRCHFAIL(1U) 6824167514Skmacy 6825167514Skmacy#define S_ACTRGNFULL 7 6826167514Skmacy#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL) 6827167514Skmacy#define F_ACTRGNFULL V_ACTRGNFULL(1U) 6828167514Skmacy 6829167514Skmacy#define S_PARITYERR 6 6830167514Skmacy#define V_PARITYERR(x) ((x) << S_PARITYERR) 6831167514Skmacy#define F_PARITYERR V_PARITYERR(1U) 6832167514Skmacy 6833167514Skmacy#define S_LIPMISS 5 6834167514Skmacy#define V_LIPMISS(x) ((x) << S_LIPMISS) 6835167514Skmacy#define F_LIPMISS V_LIPMISS(1U) 6836167514Skmacy 6837167514Skmacy#define S_LIP0 4 6838167514Skmacy#define V_LIP0(x) ((x) << S_LIP0) 6839167514Skmacy#define F_LIP0 V_LIP0(1U) 6840167514Skmacy 6841167514Skmacy#define S_MISS 3 6842167514Skmacy#define V_MISS(x) ((x) << S_MISS) 6843167514Skmacy#define F_MISS V_MISS(1U) 6844167514Skmacy 6845167514Skmacy#define S_ROUTINGHIT 2 6846167514Skmacy#define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT) 6847167514Skmacy#define F_ROUTINGHIT V_ROUTINGHIT(1U) 6848167514Skmacy 6849167514Skmacy#define S_ACTIVEHIT 1 6850167514Skmacy#define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT) 6851167514Skmacy#define F_ACTIVEHIT V_ACTIVEHIT(1U) 6852167514Skmacy 6853167514Skmacy#define S_ACTIVEOUTHIT 0 6854167514Skmacy#define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT) 6855167514Skmacy#define F_ACTIVEOUTHIT V_ACTIVEOUTHIT(1U) 6856167514Skmacy 6857167514Skmacy#define A_MC5_DB_INT_CAUSE 0x744 6858167514Skmacy#define A_MC5_DB_INT_TID 0x748 6859167514Skmacy 6860167514Skmacy#define S_INTTID 0 6861167514Skmacy#define M_INTTID 0xfffff 6862167514Skmacy#define V_INTTID(x) ((x) << S_INTTID) 6863167514Skmacy#define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID) 6864167514Skmacy 6865167514Skmacy#define A_MC5_DB_INT_PTID 0x74c 6866167514Skmacy 6867167514Skmacy#define S_INTPTID 0 6868167514Skmacy#define M_INTPTID 0xfffff 6869167514Skmacy#define V_INTPTID(x) ((x) << S_INTPTID) 6870167514Skmacy#define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID) 6871167514Skmacy 6872167514Skmacy#define A_MC5_DB_DBGI_CONFIG 0x774 6873167514Skmacy 6874167514Skmacy#define S_WRREQSIZE 22 6875167514Skmacy#define M_WRREQSIZE 0x3ff 6876167514Skmacy#define V_WRREQSIZE(x) ((x) << S_WRREQSIZE) 6877167514Skmacy#define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE) 6878167514Skmacy 6879167514Skmacy#define S_SADRSEL 4 6880167514Skmacy#define V_SADRSEL(x) ((x) << S_SADRSEL) 6881167514Skmacy#define F_SADRSEL V_SADRSEL(1U) 6882167514Skmacy 6883167514Skmacy#define S_CMDMODE 0 6884167514Skmacy#define M_CMDMODE 0x7 6885167514Skmacy#define V_CMDMODE(x) ((x) << S_CMDMODE) 6886167514Skmacy#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) 6887167514Skmacy 6888167514Skmacy#define A_MC5_DB_DBGI_REQ_CMD 0x778 6889167514Skmacy 6890167514Skmacy#define S_MBUSCMD 0 6891167514Skmacy#define M_MBUSCMD 0xf 6892167514Skmacy#define V_MBUSCMD(x) ((x) << S_MBUSCMD) 6893167514Skmacy#define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD) 6894167514Skmacy 6895167514Skmacy#define S_IDTCMDHI 11 6896167514Skmacy#define M_IDTCMDHI 0x7 6897167514Skmacy#define V_IDTCMDHI(x) ((x) << S_IDTCMDHI) 6898167514Skmacy#define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI) 6899167514Skmacy 6900167514Skmacy#define S_IDTCMDLO 0 6901167514Skmacy#define M_IDTCMDLO 0xf 6902167514Skmacy#define V_IDTCMDLO(x) ((x) << S_IDTCMDLO) 6903167514Skmacy#define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO) 6904167514Skmacy 6905167514Skmacy#define S_IDTCMD 0 6906167514Skmacy#define M_IDTCMD 0xfffff 6907167514Skmacy#define V_IDTCMD(x) ((x) << S_IDTCMD) 6908167514Skmacy#define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD) 6909167514Skmacy 6910167514Skmacy#define S_LCMDB 16 6911167514Skmacy#define M_LCMDB 0x7ff 6912167514Skmacy#define V_LCMDB(x) ((x) << S_LCMDB) 6913167514Skmacy#define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB) 6914167514Skmacy 6915167514Skmacy#define S_LCMDA 0 6916167514Skmacy#define M_LCMDA 0x7ff 6917167514Skmacy#define V_LCMDA(x) ((x) << S_LCMDA) 6918167514Skmacy#define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA) 6919167514Skmacy 6920167514Skmacy#define A_MC5_DB_DBGI_REQ_ADDR0 0x77c 6921167514Skmacy#define A_MC5_DB_DBGI_REQ_ADDR1 0x780 6922167514Skmacy#define A_MC5_DB_DBGI_REQ_ADDR2 0x784 6923167514Skmacy 6924167514Skmacy#define S_DBGIREQADRHI 0 6925167514Skmacy#define M_DBGIREQADRHI 0xff 6926167514Skmacy#define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI) 6927167514Skmacy#define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI) 6928167514Skmacy 6929167514Skmacy#define A_MC5_DB_DBGI_REQ_DATA0 0x788 6930167514Skmacy#define A_MC5_DB_DBGI_REQ_DATA1 0x78c 6931167514Skmacy#define A_MC5_DB_DBGI_REQ_DATA2 0x790 6932167514Skmacy#define A_MC5_DB_DBGI_REQ_DATA3 0x794 6933167514Skmacy#define A_MC5_DB_DBGI_REQ_DATA4 0x798 6934167514Skmacy 6935167514Skmacy#define S_DBGIREQDATA4 0 6936167514Skmacy#define M_DBGIREQDATA4 0xffff 6937167514Skmacy#define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4) 6938167514Skmacy#define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4) 6939167514Skmacy 6940167514Skmacy#define A_MC5_DB_DBGI_REQ_MASK0 0x79c 6941167514Skmacy#define A_MC5_DB_DBGI_REQ_MASK1 0x7a0 6942167514Skmacy#define A_MC5_DB_DBGI_REQ_MASK2 0x7a4 6943167514Skmacy#define A_MC5_DB_DBGI_REQ_MASK3 0x7a8 6944167514Skmacy#define A_MC5_DB_DBGI_REQ_MASK4 0x7ac 6945167514Skmacy 6946167514Skmacy#define S_DBGIREQMSK4 0 6947167514Skmacy#define M_DBGIREQMSK4 0xffff 6948167514Skmacy#define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4) 6949167514Skmacy#define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4) 6950167514Skmacy 6951167514Skmacy#define A_MC5_DB_DBGI_RSP_STATUS 0x7b0 6952167514Skmacy 6953167514Skmacy#define S_DBGIRSPMSG 8 6954167514Skmacy#define M_DBGIRSPMSG 0xf 6955167514Skmacy#define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG) 6956167514Skmacy#define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG) 6957167514Skmacy 6958167514Skmacy#define S_DBGIRSPMSGVLD 2 6959167514Skmacy#define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD) 6960167514Skmacy#define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U) 6961167514Skmacy 6962167514Skmacy#define S_DBGIRSPHIT 1 6963167514Skmacy#define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT) 6964167514Skmacy#define F_DBGIRSPHIT V_DBGIRSPHIT(1U) 6965167514Skmacy 6966167514Skmacy#define S_DBGIRSPVALID 0 6967167514Skmacy#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) 6968167514Skmacy#define F_DBGIRSPVALID V_DBGIRSPVALID(1U) 6969167514Skmacy 6970167514Skmacy#define A_MC5_DB_DBGI_RSP_DATA0 0x7b4 6971167514Skmacy#define A_MC5_DB_DBGI_RSP_DATA1 0x7b8 6972167514Skmacy#define A_MC5_DB_DBGI_RSP_DATA2 0x7bc 6973167514Skmacy#define A_MC5_DB_DBGI_RSP_DATA3 0x7c0 6974167514Skmacy#define A_MC5_DB_DBGI_RSP_DATA4 0x7c4 6975167514Skmacy 6976167514Skmacy#define S_DBGIRSPDATA3 0 6977167514Skmacy#define M_DBGIRSPDATA3 0xffff 6978167514Skmacy#define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3) 6979167514Skmacy#define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3) 6980167514Skmacy 6981167514Skmacy#define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8 6982167514Skmacy 6983167514Skmacy#define S_LASTCMDB 16 6984167514Skmacy#define M_LASTCMDB 0x7ff 6985167514Skmacy#define V_LASTCMDB(x) ((x) << S_LASTCMDB) 6986167514Skmacy#define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB) 6987167514Skmacy 6988167514Skmacy#define S_LASTCMDA 0 6989167514Skmacy#define M_LASTCMDA 0x7ff 6990167514Skmacy#define V_LASTCMDA(x) ((x) << S_LASTCMDA) 6991167514Skmacy#define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA) 6992167514Skmacy 6993167514Skmacy#define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc 6994167514Skmacy 6995167514Skmacy#define S_PO_DWR 0 6996167514Skmacy#define M_PO_DWR 0xfffff 6997167514Skmacy#define V_PO_DWR(x) ((x) << S_PO_DWR) 6998167514Skmacy#define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR) 6999167514Skmacy 7000167514Skmacy#define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0 7001167514Skmacy 7002167514Skmacy#define S_PO_MWR 0 7003167514Skmacy#define M_PO_MWR 0xfffff 7004167514Skmacy#define V_PO_MWR(x) ((x) << S_PO_MWR) 7005167514Skmacy#define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR) 7006167514Skmacy 7007167514Skmacy#define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4 7008167514Skmacy 7009167514Skmacy#define S_AO_SRCH 0 7010167514Skmacy#define M_AO_SRCH 0xfffff 7011167514Skmacy#define V_AO_SRCH(x) ((x) << S_AO_SRCH) 7012167514Skmacy#define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH) 7013167514Skmacy 7014167514Skmacy#define A_MC5_DB_AOPEN_LRN_CMD 0x7d8 7015167514Skmacy 7016167514Skmacy#define S_AO_LRN 0 7017167514Skmacy#define M_AO_LRN 0xfffff 7018167514Skmacy#define V_AO_LRN(x) ((x) << S_AO_LRN) 7019167514Skmacy#define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN) 7020167514Skmacy 7021167514Skmacy#define A_MC5_DB_SYN_SRCH_CMD 0x7dc 7022167514Skmacy 7023167514Skmacy#define S_SYN_SRCH 0 7024167514Skmacy#define M_SYN_SRCH 0xfffff 7025167514Skmacy#define V_SYN_SRCH(x) ((x) << S_SYN_SRCH) 7026167514Skmacy#define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH) 7027167514Skmacy 7028167514Skmacy#define A_MC5_DB_SYN_LRN_CMD 0x7e0 7029167514Skmacy 7030167514Skmacy#define S_SYN_LRN 0 7031167514Skmacy#define M_SYN_LRN 0xfffff 7032167514Skmacy#define V_SYN_LRN(x) ((x) << S_SYN_LRN) 7033167514Skmacy#define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN) 7034167514Skmacy 7035167514Skmacy#define A_MC5_DB_ACK_SRCH_CMD 0x7e4 7036167514Skmacy 7037167514Skmacy#define S_ACK_SRCH 0 7038167514Skmacy#define M_ACK_SRCH 0xfffff 7039167514Skmacy#define V_ACK_SRCH(x) ((x) << S_ACK_SRCH) 7040167514Skmacy#define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH) 7041167514Skmacy 7042167514Skmacy#define A_MC5_DB_ACK_LRN_CMD 0x7e8 7043167514Skmacy 7044167514Skmacy#define S_ACK_LRN 0 7045167514Skmacy#define M_ACK_LRN 0xfffff 7046167514Skmacy#define V_ACK_LRN(x) ((x) << S_ACK_LRN) 7047167514Skmacy#define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN) 7048167514Skmacy 7049167514Skmacy#define A_MC5_DB_ILOOKUP_CMD 0x7ec 7050167514Skmacy 7051167514Skmacy#define S_I_SRCH 0 7052167514Skmacy#define M_I_SRCH 0xfffff 7053167514Skmacy#define V_I_SRCH(x) ((x) << S_I_SRCH) 7054167514Skmacy#define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH) 7055167514Skmacy 7056167514Skmacy#define A_MC5_DB_ELOOKUP_CMD 0x7f0 7057167514Skmacy 7058167514Skmacy#define S_E_SRCH 0 7059167514Skmacy#define M_E_SRCH 0xfffff 7060167514Skmacy#define V_E_SRCH(x) ((x) << S_E_SRCH) 7061167514Skmacy#define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH) 7062167514Skmacy 7063167514Skmacy#define A_MC5_DB_DATA_WRITE_CMD 0x7f4 7064167514Skmacy 7065167514Skmacy#define S_WRITE 0 7066167514Skmacy#define M_WRITE 0xfffff 7067167514Skmacy#define V_WRITE(x) ((x) << S_WRITE) 7068167514Skmacy#define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE) 7069167514Skmacy 7070167514Skmacy#define A_MC5_DB_DATA_READ_CMD 0x7f8 7071167514Skmacy 7072167514Skmacy#define S_READCMD 0 7073167514Skmacy#define M_READCMD 0xfffff 7074167514Skmacy#define V_READCMD(x) ((x) << S_READCMD) 7075167514Skmacy#define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD) 7076167514Skmacy 7077167514Skmacy#define A_MC5_DB_MASK_WRITE_CMD 0x7fc 7078167514Skmacy 7079167514Skmacy#define S_MASKWR 0 7080167514Skmacy#define M_MASKWR 0xffff 7081167514Skmacy#define V_MASKWR(x) ((x) << S_MASKWR) 7082167514Skmacy#define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR) 7083167514Skmacy 7084167514Skmacy/* registers for module XGMAC0_0 */ 7085167514Skmacy#define XGMAC0_0_BASE_ADDR 0x800 7086167514Skmacy 7087167514Skmacy#define A_XGM_TX_CTRL 0x800 7088167514Skmacy 7089167514Skmacy#define S_SENDPAUSE 2 7090167514Skmacy#define V_SENDPAUSE(x) ((x) << S_SENDPAUSE) 7091167514Skmacy#define F_SENDPAUSE V_SENDPAUSE(1U) 7092167514Skmacy 7093167514Skmacy#define S_SENDZEROPAUSE 1 7094167514Skmacy#define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE) 7095167514Skmacy#define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U) 7096167514Skmacy 7097167514Skmacy#define S_TXEN 0 7098167514Skmacy#define V_TXEN(x) ((x) << S_TXEN) 7099167514Skmacy#define F_TXEN V_TXEN(1U) 7100167514Skmacy 7101167514Skmacy#define A_XGM_TX_CFG 0x804 7102167514Skmacy 7103167514Skmacy#define S_CFGCLKSPEED 2 7104167514Skmacy#define M_CFGCLKSPEED 0x7 7105167514Skmacy#define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED) 7106167514Skmacy#define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED) 7107167514Skmacy 7108167514Skmacy#define S_STRETCHMODE 1 7109167514Skmacy#define V_STRETCHMODE(x) ((x) << S_STRETCHMODE) 7110167514Skmacy#define F_STRETCHMODE V_STRETCHMODE(1U) 7111167514Skmacy 7112167514Skmacy#define S_TXPAUSEEN 0 7113167514Skmacy#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) 7114167514Skmacy#define F_TXPAUSEEN V_TXPAUSEEN(1U) 7115167514Skmacy 7116167514Skmacy#define A_XGM_TX_PAUSE_QUANTA 0x808 7117167514Skmacy 7118167514Skmacy#define S_TXPAUSEQUANTA 0 7119167514Skmacy#define M_TXPAUSEQUANTA 0xffff 7120167514Skmacy#define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA) 7121167514Skmacy#define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA) 7122167514Skmacy 7123167514Skmacy#define A_XGM_RX_CTRL 0x80c 7124167514Skmacy 7125167514Skmacy#define S_RXEN 0 7126167514Skmacy#define V_RXEN(x) ((x) << S_RXEN) 7127167514Skmacy#define F_RXEN V_RXEN(1U) 7128167514Skmacy 7129167514Skmacy#define A_XGM_RX_CFG 0x810 7130167514Skmacy 7131167514Skmacy#define S_CON802_3PREAMBLE 12 7132167514Skmacy#define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE) 7133167514Skmacy#define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U) 7134167514Skmacy 7135167514Skmacy#define S_ENNON802_3PREAMBLE 11 7136167514Skmacy#define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE) 7137167514Skmacy#define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U) 7138167514Skmacy 7139167514Skmacy#define S_COPYPREAMBLE 10 7140167514Skmacy#define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE) 7141167514Skmacy#define F_COPYPREAMBLE V_COPYPREAMBLE(1U) 7142167514Skmacy 7143167514Skmacy#define S_DISPAUSEFRAMES 9 7144167514Skmacy#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES) 7145167514Skmacy#define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U) 7146167514Skmacy 7147167514Skmacy#define S_EN1536BFRAMES 8 7148167514Skmacy#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES) 7149167514Skmacy#define F_EN1536BFRAMES V_EN1536BFRAMES(1U) 7150167514Skmacy 7151167514Skmacy#define S_ENJUMBO 7 7152167514Skmacy#define V_ENJUMBO(x) ((x) << S_ENJUMBO) 7153167514Skmacy#define F_ENJUMBO V_ENJUMBO(1U) 7154167514Skmacy 7155167514Skmacy#define S_RMFCS 6 7156167514Skmacy#define V_RMFCS(x) ((x) << S_RMFCS) 7157167514Skmacy#define F_RMFCS V_RMFCS(1U) 7158167514Skmacy 7159167514Skmacy#define S_DISNONVLAN 5 7160167514Skmacy#define V_DISNONVLAN(x) ((x) << S_DISNONVLAN) 7161167514Skmacy#define F_DISNONVLAN V_DISNONVLAN(1U) 7162167514Skmacy 7163167514Skmacy#define S_ENEXTMATCH 4 7164167514Skmacy#define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH) 7165167514Skmacy#define F_ENEXTMATCH V_ENEXTMATCH(1U) 7166167514Skmacy 7167167514Skmacy#define S_ENHASHUCAST 3 7168167514Skmacy#define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST) 7169167514Skmacy#define F_ENHASHUCAST V_ENHASHUCAST(1U) 7170167514Skmacy 7171167514Skmacy#define S_ENHASHMCAST 2 7172167514Skmacy#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST) 7173167514Skmacy#define F_ENHASHMCAST V_ENHASHMCAST(1U) 7174167514Skmacy 7175167514Skmacy#define S_DISBCAST 1 7176167514Skmacy#define V_DISBCAST(x) ((x) << S_DISBCAST) 7177167514Skmacy#define F_DISBCAST V_DISBCAST(1U) 7178167514Skmacy 7179167514Skmacy#define S_COPYALLFRAMES 0 7180167514Skmacy#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES) 7181167514Skmacy#define F_COPYALLFRAMES V_COPYALLFRAMES(1U) 7182167514Skmacy 7183167514Skmacy#define A_XGM_RX_HASH_LOW 0x814 7184167514Skmacy#define A_XGM_RX_HASH_HIGH 0x818 7185167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c 7186167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820 7187167514Skmacy 7188167514Skmacy#define S_ADDRESS_HIGH 0 7189167514Skmacy#define M_ADDRESS_HIGH 0xffff 7190167514Skmacy#define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH) 7191167514Skmacy#define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH) 7192167514Skmacy 7193167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_2 0x824 7194167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828 7195167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c 7196167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830 7197167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_4 0x834 7198167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838 7199167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c 7200167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840 7201167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_6 0x844 7202167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848 7203167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c 7204167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850 7205167514Skmacy#define A_XGM_RX_EXACT_MATCH_LOW_8 0x854 7206167514Skmacy#define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858 7207167514Skmacy#define A_XGM_RX_TYPE_MATCH_1 0x85c 7208167514Skmacy 7209167514Skmacy#define S_ENTYPEMATCH 31 7210167514Skmacy#define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH) 7211167514Skmacy#define F_ENTYPEMATCH V_ENTYPEMATCH(1U) 7212167514Skmacy 7213167514Skmacy#define S_TYPE 0 7214167514Skmacy#define M_TYPE 0xffff 7215167514Skmacy#define V_TYPE(x) ((x) << S_TYPE) 7216167514Skmacy#define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE) 7217167514Skmacy 7218167514Skmacy#define A_XGM_RX_TYPE_MATCH_2 0x860 7219167514Skmacy#define A_XGM_RX_TYPE_MATCH_3 0x864 7220167514Skmacy#define A_XGM_RX_TYPE_MATCH_4 0x868 7221167514Skmacy#define A_XGM_INT_STATUS 0x86c 7222167514Skmacy 7223167514Skmacy#define S_XGMIIEXTINT 10 7224167514Skmacy#define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT) 7225167514Skmacy#define F_XGMIIEXTINT V_XGMIIEXTINT(1U) 7226167514Skmacy 7227167514Skmacy#define S_LINKFAULTCHANGE 9 7228167514Skmacy#define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE) 7229167514Skmacy#define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U) 7230167514Skmacy 7231167514Skmacy#define S_PHYFRAMECOMPLETE 8 7232167514Skmacy#define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE) 7233167514Skmacy#define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U) 7234167514Skmacy 7235167514Skmacy#define S_PAUSEFRAMETXMT 7 7236167514Skmacy#define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT) 7237167514Skmacy#define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U) 7238167514Skmacy 7239167514Skmacy#define S_PAUSECNTRTIMEOUT 6 7240167514Skmacy#define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT) 7241167514Skmacy#define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U) 7242167514Skmacy 7243167514Skmacy#define S_NON0PAUSERCVD 5 7244167514Skmacy#define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD) 7245167514Skmacy#define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U) 7246167514Skmacy 7247167514Skmacy#define S_STATOFLOW 4 7248167514Skmacy#define V_STATOFLOW(x) ((x) << S_STATOFLOW) 7249167514Skmacy#define F_STATOFLOW V_STATOFLOW(1U) 7250167514Skmacy 7251167514Skmacy#define S_TXERRFIFO 3 7252167514Skmacy#define V_TXERRFIFO(x) ((x) << S_TXERRFIFO) 7253167514Skmacy#define F_TXERRFIFO V_TXERRFIFO(1U) 7254167514Skmacy 7255167514Skmacy#define S_TXUFLOW 2 7256167514Skmacy#define V_TXUFLOW(x) ((x) << S_TXUFLOW) 7257167514Skmacy#define F_TXUFLOW V_TXUFLOW(1U) 7258167514Skmacy 7259167514Skmacy#define S_FRAMETXMT 1 7260167514Skmacy#define V_FRAMETXMT(x) ((x) << S_FRAMETXMT) 7261167514Skmacy#define F_FRAMETXMT V_FRAMETXMT(1U) 7262167514Skmacy 7263167514Skmacy#define S_FRAMERCVD 0 7264167514Skmacy#define V_FRAMERCVD(x) ((x) << S_FRAMERCVD) 7265167514Skmacy#define F_FRAMERCVD V_FRAMERCVD(1U) 7266167514Skmacy 7267167514Skmacy#define A_XGM_XGM_INT_MASK 0x870 7268167514Skmacy#define A_XGM_XGM_INT_ENABLE 0x874 7269167514Skmacy#define A_XGM_XGM_INT_DISABLE 0x878 7270167514Skmacy#define A_XGM_TX_PAUSE_TIMER 0x87c 7271167514Skmacy 7272167514Skmacy#define S_CURPAUSETIMER 0 7273167514Skmacy#define M_CURPAUSETIMER 0xffff 7274167514Skmacy#define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER) 7275167514Skmacy#define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER) 7276167514Skmacy 7277167514Skmacy#define A_XGM_STAT_CTRL 0x880 7278167514Skmacy 7279167514Skmacy#define S_READSNPSHOT 4 7280167514Skmacy#define V_READSNPSHOT(x) ((x) << S_READSNPSHOT) 7281167514Skmacy#define F_READSNPSHOT V_READSNPSHOT(1U) 7282167514Skmacy 7283167514Skmacy#define S_TAKESNPSHOT 3 7284167514Skmacy#define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT) 7285167514Skmacy#define F_TAKESNPSHOT V_TAKESNPSHOT(1U) 7286167514Skmacy 7287167514Skmacy#define S_CLRSTATS 2 7288167514Skmacy#define V_CLRSTATS(x) ((x) << S_CLRSTATS) 7289167514Skmacy#define F_CLRSTATS V_CLRSTATS(1U) 7290167514Skmacy 7291167514Skmacy#define S_INCRSTATS 1 7292167514Skmacy#define V_INCRSTATS(x) ((x) << S_INCRSTATS) 7293167514Skmacy#define F_INCRSTATS V_INCRSTATS(1U) 7294167514Skmacy 7295167514Skmacy#define S_ENTESTMODEWR 0 7296167514Skmacy#define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR) 7297167514Skmacy#define F_ENTESTMODEWR V_ENTESTMODEWR(1U) 7298167514Skmacy 7299167514Skmacy#define A_XGM_RXFIFO_CFG 0x884 7300167514Skmacy 7301176472Skmacy#define S_RXFIFO_EMPTY 31 7302176472Skmacy#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) 7303176472Skmacy#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) 7304176472Skmacy 7305176472Skmacy#define S_RXFIFO_FULL 30 7306176472Skmacy#define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL) 7307176472Skmacy#define F_RXFIFO_FULL V_RXFIFO_FULL(1U) 7308176472Skmacy 7309167514Skmacy#define S_RXFIFOPAUSEHWM 17 7310167514Skmacy#define M_RXFIFOPAUSEHWM 0xfff 7311167514Skmacy#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) 7312167514Skmacy#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) 7313167514Skmacy 7314167514Skmacy#define S_RXFIFOPAUSELWM 5 7315167514Skmacy#define M_RXFIFOPAUSELWM 0xfff 7316167514Skmacy#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) 7317167514Skmacy#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) 7318167514Skmacy 7319167514Skmacy#define S_FORCEDPAUSE 4 7320167514Skmacy#define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE) 7321167514Skmacy#define F_FORCEDPAUSE V_FORCEDPAUSE(1U) 7322167514Skmacy 7323167514Skmacy#define S_EXTERNLOOPBACK 3 7324167514Skmacy#define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK) 7325167514Skmacy#define F_EXTERNLOOPBACK V_EXTERNLOOPBACK(1U) 7326167514Skmacy 7327167514Skmacy#define S_RXBYTESWAP 2 7328167514Skmacy#define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP) 7329167514Skmacy#define F_RXBYTESWAP V_RXBYTESWAP(1U) 7330167514Skmacy 7331167514Skmacy#define S_RXSTRFRWRD 1 7332167514Skmacy#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) 7333167514Skmacy#define F_RXSTRFRWRD V_RXSTRFRWRD(1U) 7334167514Skmacy 7335167514Skmacy#define S_DISERRFRAMES 0 7336167514Skmacy#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) 7337167514Skmacy#define F_DISERRFRAMES V_DISERRFRAMES(1U) 7338167514Skmacy 7339167514Skmacy#define A_XGM_TXFIFO_CFG 0x888 7340167514Skmacy 7341176472Skmacy#define S_TXFIFO_EMPTY 31 7342176472Skmacy#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY) 7343176472Skmacy#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U) 7344176472Skmacy 7345176472Skmacy#define S_TXFIFO_FULL 30 7346176472Skmacy#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL) 7347176472Skmacy#define F_TXFIFO_FULL V_TXFIFO_FULL(1U) 7348176472Skmacy 7349176472Skmacy#define S_UNDERUNFIX 22 7350176472Skmacy#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) 7351176472Skmacy#define F_UNDERUNFIX V_UNDERUNFIX(1U) 7352176472Skmacy 7353176472Skmacy#define S_ENDROPPKT 21 7354176472Skmacy#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) 7355176472Skmacy#define F_ENDROPPKT V_ENDROPPKT(1U) 7356176472Skmacy 7357167514Skmacy#define S_TXIPG 13 7358167514Skmacy#define M_TXIPG 0xff 7359167514Skmacy#define V_TXIPG(x) ((x) << S_TXIPG) 7360167514Skmacy#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) 7361167514Skmacy 7362167514Skmacy#define S_TXFIFOTHRESH 4 7363167514Skmacy#define M_TXFIFOTHRESH 0x1ff 7364167514Skmacy#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) 7365167514Skmacy#define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH) 7366167514Skmacy 7367167514Skmacy#define S_INTERNLOOPBACK 3 7368167514Skmacy#define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK) 7369167514Skmacy#define F_INTERNLOOPBACK V_INTERNLOOPBACK(1U) 7370167514Skmacy 7371167514Skmacy#define S_TXBYTESWAP 2 7372167514Skmacy#define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP) 7373167514Skmacy#define F_TXBYTESWAP V_TXBYTESWAP(1U) 7374167514Skmacy 7375167514Skmacy#define S_DISCRC 1 7376167514Skmacy#define V_DISCRC(x) ((x) << S_DISCRC) 7377167514Skmacy#define F_DISCRC V_DISCRC(1U) 7378167514Skmacy 7379167514Skmacy#define S_DISPREAMBLE 0 7380167514Skmacy#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) 7381167514Skmacy#define F_DISPREAMBLE V_DISPREAMBLE(1U) 7382167514Skmacy 7383167514Skmacy#define A_XGM_SLOW_TIMER 0x88c 7384167514Skmacy 7385167514Skmacy#define S_PAUSESLOWTIMEREN 31 7386167514Skmacy#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) 7387167514Skmacy#define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) 7388167514Skmacy 7389167514Skmacy#define S_PAUSESLOWTIMER 0 7390167514Skmacy#define M_PAUSESLOWTIMER 0xfffff 7391167514Skmacy#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) 7392167514Skmacy#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) 7393167514Skmacy 7394176472Skmacy#define A_XGM_PAUSE_TIMER 0x890 7395176472Skmacy 7396176472Skmacy#define S_PAUSETIMER 0 7397176472Skmacy#define M_PAUSETIMER 0xfffff 7398176472Skmacy#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) 7399176472Skmacy#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) 7400176472Skmacy 7401167514Skmacy#define A_XGM_SERDES_CTRL 0x890 7402167514Skmacy 7403167514Skmacy#define S_SERDESEN 25 7404167514Skmacy#define V_SERDESEN(x) ((x) << S_SERDESEN) 7405167514Skmacy#define F_SERDESEN V_SERDESEN(1U) 7406167514Skmacy 7407167514Skmacy#define S_SERDESRESET_ 24 7408167514Skmacy#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) 7409167514Skmacy#define F_SERDESRESET_ V_SERDESRESET_(1U) 7410167514Skmacy 7411167514Skmacy#define S_CMURANGE 21 7412167514Skmacy#define M_CMURANGE 0x7 7413167514Skmacy#define V_CMURANGE(x) ((x) << S_CMURANGE) 7414167514Skmacy#define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE) 7415167514Skmacy 7416167514Skmacy#define S_BGENB 20 7417167514Skmacy#define V_BGENB(x) ((x) << S_BGENB) 7418167514Skmacy#define F_BGENB V_BGENB(1U) 7419167514Skmacy 7420167514Skmacy#define S_ENSKPDROP 19 7421167514Skmacy#define V_ENSKPDROP(x) ((x) << S_ENSKPDROP) 7422167514Skmacy#define F_ENSKPDROP V_ENSKPDROP(1U) 7423167514Skmacy 7424167514Skmacy#define S_ENCOMMA 18 7425167514Skmacy#define V_ENCOMMA(x) ((x) << S_ENCOMMA) 7426167514Skmacy#define F_ENCOMMA V_ENCOMMA(1U) 7427167514Skmacy 7428167514Skmacy#define S_EN8B10B 17 7429167514Skmacy#define V_EN8B10B(x) ((x) << S_EN8B10B) 7430167514Skmacy#define F_EN8B10B V_EN8B10B(1U) 7431167514Skmacy 7432167514Skmacy#define S_ENELBUF 16 7433167514Skmacy#define V_ENELBUF(x) ((x) << S_ENELBUF) 7434167514Skmacy#define F_ENELBUF V_ENELBUF(1U) 7435167514Skmacy 7436167514Skmacy#define S_GAIN 11 7437167514Skmacy#define M_GAIN 0x1f 7438167514Skmacy#define V_GAIN(x) ((x) << S_GAIN) 7439167514Skmacy#define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN) 7440167514Skmacy 7441167514Skmacy#define S_BANDGAP 7 7442167514Skmacy#define M_BANDGAP 0xf 7443167514Skmacy#define V_BANDGAP(x) ((x) << S_BANDGAP) 7444167514Skmacy#define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP) 7445167514Skmacy 7446167514Skmacy#define S_LPBKEN 5 7447167514Skmacy#define M_LPBKEN 0x3 7448167514Skmacy#define V_LPBKEN(x) ((x) << S_LPBKEN) 7449167514Skmacy#define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN) 7450167514Skmacy 7451167514Skmacy#define S_RXENABLE 4 7452167514Skmacy#define V_RXENABLE(x) ((x) << S_RXENABLE) 7453167514Skmacy#define F_RXENABLE V_RXENABLE(1U) 7454167514Skmacy 7455167514Skmacy#define S_TXENABLE 3 7456167514Skmacy#define V_TXENABLE(x) ((x) << S_TXENABLE) 7457167514Skmacy#define F_TXENABLE V_TXENABLE(1U) 7458167514Skmacy 7459167514Skmacy#define A_XGM_XAUI_PCS_TEST 0x894 7460167514Skmacy 7461167514Skmacy#define S_TESTPATTERN 1 7462167514Skmacy#define M_TESTPATTERN 0x3 7463167514Skmacy#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) 7464167514Skmacy#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) 7465167514Skmacy 7466167514Skmacy#define S_ENTEST 0 7467167514Skmacy#define V_ENTEST(x) ((x) << S_ENTEST) 7468167514Skmacy#define F_ENTEST V_ENTEST(1U) 7469167514Skmacy 7470167514Skmacy#define A_XGM_RGMII_CTRL 0x898 7471167514Skmacy 7472167514Skmacy#define S_PHALIGNFIFOTHRESH 1 7473167514Skmacy#define M_PHALIGNFIFOTHRESH 0x3 7474167514Skmacy#define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH) 7475167514Skmacy#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) 7476167514Skmacy 7477167514Skmacy#define S_TXCLK90SHIFT 0 7478167514Skmacy#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) 7479167514Skmacy#define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) 7480167514Skmacy 7481167514Skmacy#define A_XGM_RGMII_IMP 0x89c 7482167514Skmacy 7483176472Skmacy#define S_CALRESET 8 7484176472Skmacy#define V_CALRESET(x) ((x) << S_CALRESET) 7485176472Skmacy#define F_CALRESET V_CALRESET(1U) 7486176472Skmacy 7487176472Skmacy#define S_CALUPDATE 7 7488176472Skmacy#define V_CALUPDATE(x) ((x) << S_CALUPDATE) 7489176472Skmacy#define F_CALUPDATE V_CALUPDATE(1U) 7490176472Skmacy 7491167514Skmacy#define S_XGM_IMPSETUPDATE 6 7492167514Skmacy#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) 7493167514Skmacy#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) 7494167514Skmacy 7495167514Skmacy#define S_RGMIIIMPPD 3 7496167514Skmacy#define M_RGMIIIMPPD 0x7 7497167514Skmacy#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) 7498167514Skmacy#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) 7499167514Skmacy 7500167514Skmacy#define S_RGMIIIMPPU 0 7501167514Skmacy#define M_RGMIIIMPPU 0x7 7502167514Skmacy#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) 7503167514Skmacy#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) 7504167514Skmacy 7505167514Skmacy#define A_XGM_XAUI_IMP 0x8a0 7506167514Skmacy 7507167514Skmacy#define S_XGM_CALFAULT 29 7508167514Skmacy#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) 7509167514Skmacy#define F_XGM_CALFAULT V_XGM_CALFAULT(1U) 7510167514Skmacy 7511167514Skmacy#define S_CALIMP 24 7512167514Skmacy#define M_CALIMP 0x1f 7513167514Skmacy#define V_CALIMP(x) ((x) << S_CALIMP) 7514167514Skmacy#define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP) 7515167514Skmacy 7516167514Skmacy#define S_XAUIIMP 0 7517167514Skmacy#define M_XAUIIMP 0x7 7518167514Skmacy#define V_XAUIIMP(x) ((x) << S_XAUIIMP) 7519167514Skmacy#define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP) 7520167514Skmacy 7521167514Skmacy#define A_XGM_SERDES_BIST 0x8a4 7522167514Skmacy 7523167514Skmacy#define S_BISTDONE 28 7524167514Skmacy#define M_BISTDONE 0xf 7525167514Skmacy#define V_BISTDONE(x) ((x) << S_BISTDONE) 7526167514Skmacy#define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE) 7527167514Skmacy 7528167514Skmacy#define S_BISTCYCLETHRESH 3 7529167514Skmacy#define M_BISTCYCLETHRESH 0x1ffff 7530167514Skmacy#define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) 7531167514Skmacy#define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) 7532167514Skmacy 7533167514Skmacy#define A_XGM_RX_MAX_PKT_SIZE 0x8a8 7534167514Skmacy 7535176472Skmacy#define S_RXMAXFRAMERSIZE 17 7536176472Skmacy#define M_RXMAXFRAMERSIZE 0x3fff 7537176472Skmacy#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) 7538176472Skmacy#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) 7539176472Skmacy 7540176472Skmacy#define S_RXENERRORGATHER 16 7541176472Skmacy#define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER) 7542176472Skmacy#define F_RXENERRORGATHER V_RXENERRORGATHER(1U) 7543176472Skmacy 7544176472Skmacy#define S_RXENSINGLEFLIT 15 7545176472Skmacy#define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT) 7546176472Skmacy#define F_RXENSINGLEFLIT V_RXENSINGLEFLIT(1U) 7547176472Skmacy 7548176472Skmacy#define S_RXENFRAMER 14 7549176472Skmacy#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) 7550176472Skmacy#define F_RXENFRAMER V_RXENFRAMER(1U) 7551176472Skmacy 7552167514Skmacy#define S_RXMAXPKTSIZE 0 7553167514Skmacy#define M_RXMAXPKTSIZE 0x3fff 7554167514Skmacy#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) 7555167514Skmacy#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) 7556167514Skmacy 7557167514Skmacy#define A_XGM_RESET_CTRL 0x8ac 7558167514Skmacy 7559176472Skmacy#define S_XGMAC_STOP_EN 4 7560176472Skmacy#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN) 7561176472Skmacy#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U) 7562176472Skmacy 7563167514Skmacy#define S_XG2G_RESET_ 3 7564167514Skmacy#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) 7565167514Skmacy#define F_XG2G_RESET_ V_XG2G_RESET_(1U) 7566167514Skmacy 7567167514Skmacy#define S_RGMII_RESET_ 2 7568167514Skmacy#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) 7569167514Skmacy#define F_RGMII_RESET_ V_RGMII_RESET_(1U) 7570167514Skmacy 7571167514Skmacy#define S_PCS_RESET_ 1 7572167514Skmacy#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_) 7573167514Skmacy#define F_PCS_RESET_ V_PCS_RESET_(1U) 7574167514Skmacy 7575167514Skmacy#define S_MAC_RESET_ 0 7576167514Skmacy#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) 7577167514Skmacy#define F_MAC_RESET_ V_MAC_RESET_(1U) 7578167514Skmacy 7579167514Skmacy#define A_XGM_XAUI1G_CTRL 0x8b0 7580167514Skmacy 7581167514Skmacy#define S_XAUI1GLINKID 0 7582167514Skmacy#define M_XAUI1GLINKID 0x3 7583167514Skmacy#define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID) 7584167514Skmacy#define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID) 7585167514Skmacy 7586167514Skmacy#define A_XGM_SERDES_LANE_CTRL 0x8b4 7587167514Skmacy 7588167514Skmacy#define S_LANEREVERSAL 8 7589167514Skmacy#define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL) 7590167514Skmacy#define F_LANEREVERSAL V_LANEREVERSAL(1U) 7591167514Skmacy 7592167514Skmacy#define S_TXPOLARITY 4 7593167514Skmacy#define M_TXPOLARITY 0xf 7594167514Skmacy#define V_TXPOLARITY(x) ((x) << S_TXPOLARITY) 7595167514Skmacy#define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY) 7596167514Skmacy 7597167514Skmacy#define S_RXPOLARITY 0 7598167514Skmacy#define M_RXPOLARITY 0xf 7599167514Skmacy#define V_RXPOLARITY(x) ((x) << S_RXPOLARITY) 7600167514Skmacy#define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY) 7601167514Skmacy 7602167514Skmacy#define A_XGM_PORT_CFG 0x8b8 7603167514Skmacy 7604167514Skmacy#define S_SAFESPEEDCHANGE 4 7605167514Skmacy#define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE) 7606167514Skmacy#define F_SAFESPEEDCHANGE V_SAFESPEEDCHANGE(1U) 7607167514Skmacy 7608167514Skmacy#define S_CLKDIVRESET_ 3 7609167514Skmacy#define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_) 7610167514Skmacy#define F_CLKDIVRESET_ V_CLKDIVRESET_(1U) 7611167514Skmacy 7612167514Skmacy#define S_PORTSPEED 1 7613167514Skmacy#define M_PORTSPEED 0x3 7614167514Skmacy#define V_PORTSPEED(x) ((x) << S_PORTSPEED) 7615167514Skmacy#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) 7616167514Skmacy 7617167514Skmacy#define S_ENRGMII 0 7618167514Skmacy#define V_ENRGMII(x) ((x) << S_ENRGMII) 7619167514Skmacy#define F_ENRGMII V_ENRGMII(1U) 7620167514Skmacy 7621167514Skmacy#define A_XGM_EPIO_DATA0 0x8c0 7622167514Skmacy#define A_XGM_EPIO_DATA1 0x8c4 7623167514Skmacy#define A_XGM_EPIO_DATA2 0x8c8 7624167514Skmacy#define A_XGM_EPIO_DATA3 0x8cc 7625167514Skmacy#define A_XGM_EPIO_OP 0x8d0 7626167514Skmacy 7627167514Skmacy#define S_PIO_READY 31 7628167514Skmacy#define V_PIO_READY(x) ((x) << S_PIO_READY) 7629167514Skmacy#define F_PIO_READY V_PIO_READY(1U) 7630167514Skmacy 7631167514Skmacy#define S_PIO_WRRD 24 7632167514Skmacy#define V_PIO_WRRD(x) ((x) << S_PIO_WRRD) 7633167514Skmacy#define F_PIO_WRRD V_PIO_WRRD(1U) 7634167514Skmacy 7635167514Skmacy#define S_PIO_ADDRESS 0 7636167514Skmacy#define M_PIO_ADDRESS 0xff 7637167514Skmacy#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) 7638167514Skmacy#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) 7639167514Skmacy 7640167514Skmacy#define A_XGM_INT_ENABLE 0x8d4 7641167514Skmacy 7642176472Skmacy#define S_XAUIPCSDECERR 24 7643176472Skmacy#define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR) 7644176472Skmacy#define F_XAUIPCSDECERR V_XAUIPCSDECERR(1U) 7645167514Skmacy 7646167514Skmacy#define S_RGMIIRXFIFOOVERFLOW 23 7647167514Skmacy#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) 7648167514Skmacy#define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) 7649167514Skmacy 7650167514Skmacy#define S_RGMIIRXFIFOUNDERFLOW 22 7651167514Skmacy#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) 7652167514Skmacy#define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) 7653167514Skmacy 7654167514Skmacy#define S_RXPKTSIZEERROR 21 7655167514Skmacy#define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR) 7656167514Skmacy#define F_RXPKTSIZEERROR V_RXPKTSIZEERROR(1U) 7657167514Skmacy 7658167514Skmacy#define S_WOLPATDETECTED 20 7659167514Skmacy#define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED) 7660167514Skmacy#define F_WOLPATDETECTED V_WOLPATDETECTED(1U) 7661167514Skmacy 7662167514Skmacy#define S_TXFIFO_PRTY_ERR 17 7663167514Skmacy#define M_TXFIFO_PRTY_ERR 0x7 7664167514Skmacy#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) 7665167514Skmacy#define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR) 7666167514Skmacy 7667167514Skmacy#define S_RXFIFO_PRTY_ERR 14 7668167514Skmacy#define M_RXFIFO_PRTY_ERR 0x7 7669167514Skmacy#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) 7670167514Skmacy#define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR) 7671167514Skmacy 7672167514Skmacy#define S_TXFIFO_UNDERRUN 13 7673167514Skmacy#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) 7674167514Skmacy#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) 7675167514Skmacy 7676167514Skmacy#define S_RXFIFO_OVERFLOW 12 7677167514Skmacy#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) 7678167514Skmacy#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) 7679167514Skmacy 7680176472Skmacy#define S_SERDESBISTERR 8 7681176472Skmacy#define M_SERDESBISTERR 0xf 7682176472Skmacy#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) 7683176472Skmacy#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) 7684167514Skmacy 7685176472Skmacy#define S_SERDESLOWSIGCHANGE 4 7686176472Skmacy#define M_SERDESLOWSIGCHANGE 0xf 7687176472Skmacy#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) 7688176472Skmacy#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) 7689167514Skmacy 7690167514Skmacy#define S_XAUIPCSCTCERR 3 7691167514Skmacy#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) 7692167514Skmacy#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) 7693167514Skmacy 7694167514Skmacy#define S_XAUIPCSALIGNCHANGE 2 7695167514Skmacy#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) 7696167514Skmacy#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) 7697167514Skmacy 7698167514Skmacy#define S_RGMIILINKSTSCHANGE 1 7699167514Skmacy#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) 7700167514Skmacy#define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) 7701167514Skmacy 7702167514Skmacy#define S_XGM_INT 0 7703167514Skmacy#define V_XGM_INT(x) ((x) << S_XGM_INT) 7704167514Skmacy#define F_XGM_INT V_XGM_INT(1U) 7705167514Skmacy 7706176472Skmacy#define S_SERDESCMULOCK_LOSS 24 7707176472Skmacy#define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS) 7708176472Skmacy#define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U) 7709167514Skmacy 7710176472Skmacy#define S_SERDESBIST_ERR 8 7711176472Skmacy#define M_SERDESBIST_ERR 0xf 7712176472Skmacy#define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) 7713176472Skmacy#define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) 7714167514Skmacy 7715176472Skmacy#define S_SERDES_LOS 4 7716176472Skmacy#define M_SERDES_LOS 0xf 7717176472Skmacy#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) 7718176472Skmacy#define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) 7719176472Skmacy 7720167514Skmacy#define A_XGM_INT_CAUSE 0x8d8 7721167514Skmacy#define A_XGM_XAUI_ACT_CTRL 0x8dc 7722167514Skmacy 7723167514Skmacy#define S_TXACTENABLE 1 7724167514Skmacy#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) 7725167514Skmacy#define F_TXACTENABLE V_TXACTENABLE(1U) 7726167514Skmacy 7727167514Skmacy#define A_XGM_SERDES_CTRL0 0x8e0 7728167514Skmacy 7729167514Skmacy#define S_INTSERLPBK3 27 7730167514Skmacy#define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3) 7731167514Skmacy#define F_INTSERLPBK3 V_INTSERLPBK3(1U) 7732167514Skmacy 7733167514Skmacy#define S_INTSERLPBK2 26 7734167514Skmacy#define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2) 7735167514Skmacy#define F_INTSERLPBK2 V_INTSERLPBK2(1U) 7736167514Skmacy 7737167514Skmacy#define S_INTSERLPBK1 25 7738167514Skmacy#define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1) 7739167514Skmacy#define F_INTSERLPBK1 V_INTSERLPBK1(1U) 7740167514Skmacy 7741167514Skmacy#define S_INTSERLPBK0 24 7742167514Skmacy#define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0) 7743167514Skmacy#define F_INTSERLPBK0 V_INTSERLPBK0(1U) 7744167514Skmacy 7745167514Skmacy#define S_RESET3 23 7746167514Skmacy#define V_RESET3(x) ((x) << S_RESET3) 7747167514Skmacy#define F_RESET3 V_RESET3(1U) 7748167514Skmacy 7749167514Skmacy#define S_RESET2 22 7750167514Skmacy#define V_RESET2(x) ((x) << S_RESET2) 7751167514Skmacy#define F_RESET2 V_RESET2(1U) 7752167514Skmacy 7753167514Skmacy#define S_RESET1 21 7754167514Skmacy#define V_RESET1(x) ((x) << S_RESET1) 7755167514Skmacy#define F_RESET1 V_RESET1(1U) 7756167514Skmacy 7757167514Skmacy#define S_RESET0 20 7758167514Skmacy#define V_RESET0(x) ((x) << S_RESET0) 7759167514Skmacy#define F_RESET0 V_RESET0(1U) 7760167514Skmacy 7761167514Skmacy#define S_PWRDN3 19 7762167514Skmacy#define V_PWRDN3(x) ((x) << S_PWRDN3) 7763167514Skmacy#define F_PWRDN3 V_PWRDN3(1U) 7764167514Skmacy 7765167514Skmacy#define S_PWRDN2 18 7766167514Skmacy#define V_PWRDN2(x) ((x) << S_PWRDN2) 7767167514Skmacy#define F_PWRDN2 V_PWRDN2(1U) 7768167514Skmacy 7769167514Skmacy#define S_PWRDN1 17 7770167514Skmacy#define V_PWRDN1(x) ((x) << S_PWRDN1) 7771167514Skmacy#define F_PWRDN1 V_PWRDN1(1U) 7772167514Skmacy 7773167514Skmacy#define S_PWRDN0 16 7774167514Skmacy#define V_PWRDN0(x) ((x) << S_PWRDN0) 7775167514Skmacy#define F_PWRDN0 V_PWRDN0(1U) 7776167514Skmacy 7777167514Skmacy#define S_RESETPLL23 15 7778167514Skmacy#define V_RESETPLL23(x) ((x) << S_RESETPLL23) 7779167514Skmacy#define F_RESETPLL23 V_RESETPLL23(1U) 7780167514Skmacy 7781167514Skmacy#define S_RESETPLL01 14 7782167514Skmacy#define V_RESETPLL01(x) ((x) << S_RESETPLL01) 7783167514Skmacy#define F_RESETPLL01 V_RESETPLL01(1U) 7784167514Skmacy 7785167514Skmacy#define S_PW23 12 7786167514Skmacy#define M_PW23 0x3 7787167514Skmacy#define V_PW23(x) ((x) << S_PW23) 7788167514Skmacy#define G_PW23(x) (((x) >> S_PW23) & M_PW23) 7789167514Skmacy 7790167514Skmacy#define S_PW01 10 7791167514Skmacy#define M_PW01 0x3 7792167514Skmacy#define V_PW01(x) ((x) << S_PW01) 7793167514Skmacy#define G_PW01(x) (((x) >> S_PW01) & M_PW01) 7794167514Skmacy 7795167514Skmacy#define S_XGM_DEQ 6 7796167514Skmacy#define M_XGM_DEQ 0xf 7797167514Skmacy#define V_XGM_DEQ(x) ((x) << S_XGM_DEQ) 7798167514Skmacy#define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ) 7799167514Skmacy 7800167514Skmacy#define S_XGM_DTX 2 7801167514Skmacy#define M_XGM_DTX 0xf 7802167514Skmacy#define V_XGM_DTX(x) ((x) << S_XGM_DTX) 7803167514Skmacy#define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX) 7804167514Skmacy 7805167514Skmacy#define S_XGM_LODRV 1 7806167514Skmacy#define V_XGM_LODRV(x) ((x) << S_XGM_LODRV) 7807167514Skmacy#define F_XGM_LODRV V_XGM_LODRV(1U) 7808167514Skmacy 7809167514Skmacy#define S_XGM_HIDRV 0 7810167514Skmacy#define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV) 7811167514Skmacy#define F_XGM_HIDRV V_XGM_HIDRV(1U) 7812167514Skmacy 7813167514Skmacy#define A_XGM_SERDES_CTRL1 0x8e4 7814167514Skmacy 7815167514Skmacy#define S_FMOFFSET3 19 7816167514Skmacy#define M_FMOFFSET3 0x1f 7817167514Skmacy#define V_FMOFFSET3(x) ((x) << S_FMOFFSET3) 7818167514Skmacy#define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3) 7819167514Skmacy 7820167514Skmacy#define S_FMOFFSETEN3 18 7821167514Skmacy#define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3) 7822167514Skmacy#define F_FMOFFSETEN3 V_FMOFFSETEN3(1U) 7823167514Skmacy 7824167514Skmacy#define S_FMOFFSET2 13 7825167514Skmacy#define M_FMOFFSET2 0x1f 7826167514Skmacy#define V_FMOFFSET2(x) ((x) << S_FMOFFSET2) 7827167514Skmacy#define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2) 7828167514Skmacy 7829167514Skmacy#define S_FMOFFSETEN2 12 7830167514Skmacy#define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2) 7831167514Skmacy#define F_FMOFFSETEN2 V_FMOFFSETEN2(1U) 7832167514Skmacy 7833167514Skmacy#define S_FMOFFSET1 7 7834167514Skmacy#define M_FMOFFSET1 0x1f 7835167514Skmacy#define V_FMOFFSET1(x) ((x) << S_FMOFFSET1) 7836167514Skmacy#define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1) 7837167514Skmacy 7838167514Skmacy#define S_FMOFFSETEN1 6 7839167514Skmacy#define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1) 7840167514Skmacy#define F_FMOFFSETEN1 V_FMOFFSETEN1(1U) 7841167514Skmacy 7842167514Skmacy#define S_FMOFFSET0 1 7843167514Skmacy#define M_FMOFFSET0 0x1f 7844167514Skmacy#define V_FMOFFSET0(x) ((x) << S_FMOFFSET0) 7845167514Skmacy#define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0) 7846167514Skmacy 7847167514Skmacy#define S_FMOFFSETEN0 0 7848167514Skmacy#define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0) 7849167514Skmacy#define F_FMOFFSETEN0 V_FMOFFSETEN0(1U) 7850167514Skmacy 7851167514Skmacy#define A_XGM_SERDES_CTRL2 0x8e8 7852167514Skmacy 7853167514Skmacy#define S_DNIN3 11 7854167514Skmacy#define V_DNIN3(x) ((x) << S_DNIN3) 7855167514Skmacy#define F_DNIN3 V_DNIN3(1U) 7856167514Skmacy 7857167514Skmacy#define S_UPIN3 10 7858167514Skmacy#define V_UPIN3(x) ((x) << S_UPIN3) 7859167514Skmacy#define F_UPIN3 V_UPIN3(1U) 7860167514Skmacy 7861167514Skmacy#define S_RXSLAVE3 9 7862167514Skmacy#define V_RXSLAVE3(x) ((x) << S_RXSLAVE3) 7863167514Skmacy#define F_RXSLAVE3 V_RXSLAVE3(1U) 7864167514Skmacy 7865167514Skmacy#define S_DNIN2 8 7866167514Skmacy#define V_DNIN2(x) ((x) << S_DNIN2) 7867167514Skmacy#define F_DNIN2 V_DNIN2(1U) 7868167514Skmacy 7869167514Skmacy#define S_UPIN2 7 7870167514Skmacy#define V_UPIN2(x) ((x) << S_UPIN2) 7871167514Skmacy#define F_UPIN2 V_UPIN2(1U) 7872167514Skmacy 7873167514Skmacy#define S_RXSLAVE2 6 7874167514Skmacy#define V_RXSLAVE2(x) ((x) << S_RXSLAVE2) 7875167514Skmacy#define F_RXSLAVE2 V_RXSLAVE2(1U) 7876167514Skmacy 7877167514Skmacy#define S_DNIN1 5 7878167514Skmacy#define V_DNIN1(x) ((x) << S_DNIN1) 7879167514Skmacy#define F_DNIN1 V_DNIN1(1U) 7880167514Skmacy 7881167514Skmacy#define S_UPIN1 4 7882167514Skmacy#define V_UPIN1(x) ((x) << S_UPIN1) 7883167514Skmacy#define F_UPIN1 V_UPIN1(1U) 7884167514Skmacy 7885167514Skmacy#define S_RXSLAVE1 3 7886167514Skmacy#define V_RXSLAVE1(x) ((x) << S_RXSLAVE1) 7887167514Skmacy#define F_RXSLAVE1 V_RXSLAVE1(1U) 7888167514Skmacy 7889167514Skmacy#define S_DNIN0 2 7890167514Skmacy#define V_DNIN0(x) ((x) << S_DNIN0) 7891167514Skmacy#define F_DNIN0 V_DNIN0(1U) 7892167514Skmacy 7893167514Skmacy#define S_UPIN0 1 7894167514Skmacy#define V_UPIN0(x) ((x) << S_UPIN0) 7895167514Skmacy#define F_UPIN0 V_UPIN0(1U) 7896167514Skmacy 7897167514Skmacy#define S_RXSLAVE0 0 7898167514Skmacy#define V_RXSLAVE0(x) ((x) << S_RXSLAVE0) 7899167514Skmacy#define F_RXSLAVE0 V_RXSLAVE0(1U) 7900167514Skmacy 7901167514Skmacy#define A_XGM_SERDES_CTRL3 0x8ec 7902167514Skmacy 7903167514Skmacy#define S_EXTBISTCHKERRCLR3 31 7904167514Skmacy#define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3) 7905167514Skmacy#define F_EXTBISTCHKERRCLR3 V_EXTBISTCHKERRCLR3(1U) 7906167514Skmacy 7907167514Skmacy#define S_EXTBISTCHKEN3 30 7908167514Skmacy#define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3) 7909167514Skmacy#define F_EXTBISTCHKEN3 V_EXTBISTCHKEN3(1U) 7910167514Skmacy 7911167514Skmacy#define S_EXTBISTGENEN3 29 7912167514Skmacy#define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3) 7913167514Skmacy#define F_EXTBISTGENEN3 V_EXTBISTGENEN3(1U) 7914167514Skmacy 7915167514Skmacy#define S_EXTBISTPAT3 26 7916167514Skmacy#define M_EXTBISTPAT3 0x7 7917167514Skmacy#define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3) 7918167514Skmacy#define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3) 7919167514Skmacy 7920167514Skmacy#define S_EXTPARRESET3 25 7921167514Skmacy#define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3) 7922167514Skmacy#define F_EXTPARRESET3 V_EXTPARRESET3(1U) 7923167514Skmacy 7924167514Skmacy#define S_EXTPARLPBK3 24 7925167514Skmacy#define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3) 7926167514Skmacy#define F_EXTPARLPBK3 V_EXTPARLPBK3(1U) 7927167514Skmacy 7928167514Skmacy#define S_EXTBISTCHKERRCLR2 23 7929167514Skmacy#define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2) 7930167514Skmacy#define F_EXTBISTCHKERRCLR2 V_EXTBISTCHKERRCLR2(1U) 7931167514Skmacy 7932167514Skmacy#define S_EXTBISTCHKEN2 22 7933167514Skmacy#define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2) 7934167514Skmacy#define F_EXTBISTCHKEN2 V_EXTBISTCHKEN2(1U) 7935167514Skmacy 7936167514Skmacy#define S_EXTBISTGENEN2 21 7937167514Skmacy#define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2) 7938167514Skmacy#define F_EXTBISTGENEN2 V_EXTBISTGENEN2(1U) 7939167514Skmacy 7940167514Skmacy#define S_EXTBISTPAT2 18 7941167514Skmacy#define M_EXTBISTPAT2 0x7 7942167514Skmacy#define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2) 7943167514Skmacy#define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2) 7944167514Skmacy 7945167514Skmacy#define S_EXTPARRESET2 17 7946167514Skmacy#define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2) 7947167514Skmacy#define F_EXTPARRESET2 V_EXTPARRESET2(1U) 7948167514Skmacy 7949167514Skmacy#define S_EXTPARLPBK2 16 7950167514Skmacy#define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2) 7951167514Skmacy#define F_EXTPARLPBK2 V_EXTPARLPBK2(1U) 7952167514Skmacy 7953167514Skmacy#define S_EXTBISTCHKERRCLR1 15 7954167514Skmacy#define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1) 7955167514Skmacy#define F_EXTBISTCHKERRCLR1 V_EXTBISTCHKERRCLR1(1U) 7956167514Skmacy 7957167514Skmacy#define S_EXTBISTCHKEN1 14 7958167514Skmacy#define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1) 7959167514Skmacy#define F_EXTBISTCHKEN1 V_EXTBISTCHKEN1(1U) 7960167514Skmacy 7961167514Skmacy#define S_EXTBISTGENEN1 13 7962167514Skmacy#define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1) 7963167514Skmacy#define F_EXTBISTGENEN1 V_EXTBISTGENEN1(1U) 7964167514Skmacy 7965167514Skmacy#define S_EXTBISTPAT1 10 7966167514Skmacy#define M_EXTBISTPAT1 0x7 7967167514Skmacy#define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1) 7968167514Skmacy#define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1) 7969167514Skmacy 7970167514Skmacy#define S_EXTPARRESET1 9 7971167514Skmacy#define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1) 7972167514Skmacy#define F_EXTPARRESET1 V_EXTPARRESET1(1U) 7973167514Skmacy 7974167514Skmacy#define S_EXTPARLPBK1 8 7975167514Skmacy#define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1) 7976167514Skmacy#define F_EXTPARLPBK1 V_EXTPARLPBK1(1U) 7977167514Skmacy 7978167514Skmacy#define S_EXTBISTCHKERRCLR0 7 7979167514Skmacy#define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0) 7980167514Skmacy#define F_EXTBISTCHKERRCLR0 V_EXTBISTCHKERRCLR0(1U) 7981167514Skmacy 7982167514Skmacy#define S_EXTBISTCHKEN0 6 7983167514Skmacy#define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0) 7984167514Skmacy#define F_EXTBISTCHKEN0 V_EXTBISTCHKEN0(1U) 7985167514Skmacy 7986167514Skmacy#define S_EXTBISTGENEN0 5 7987167514Skmacy#define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0) 7988167514Skmacy#define F_EXTBISTGENEN0 V_EXTBISTGENEN0(1U) 7989167514Skmacy 7990167514Skmacy#define S_EXTBISTPAT0 2 7991167514Skmacy#define M_EXTBISTPAT0 0x7 7992167514Skmacy#define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0) 7993167514Skmacy#define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0) 7994167514Skmacy 7995167514Skmacy#define S_EXTPARRESET0 1 7996167514Skmacy#define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0) 7997167514Skmacy#define F_EXTPARRESET0 V_EXTPARRESET0(1U) 7998167514Skmacy 7999167514Skmacy#define S_EXTPARLPBK0 0 8000167514Skmacy#define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0) 8001167514Skmacy#define F_EXTPARLPBK0 V_EXTPARLPBK0(1U) 8002167514Skmacy 8003167514Skmacy#define A_XGM_SERDES_STAT0 0x8f0 8004167514Skmacy 8005167514Skmacy#define S_EXTBISTCHKERRCNT0 4 8006167514Skmacy#define M_EXTBISTCHKERRCNT0 0xffffff 8007167514Skmacy#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) 8008167514Skmacy#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) 8009167514Skmacy 8010167514Skmacy#define S_EXTBISTCHKFMD0 3 8011167514Skmacy#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) 8012167514Skmacy#define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) 8013167514Skmacy 8014176472Skmacy#define S_LOWSIGFORCEEN0 2 8015176472Skmacy#define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0) 8016176472Skmacy#define F_LOWSIGFORCEEN0 V_LOWSIGFORCEEN0(1U) 8017176472Skmacy 8018176472Skmacy#define S_LOWSIGFORCEVALUE0 1 8019176472Skmacy#define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0) 8020176472Skmacy#define F_LOWSIGFORCEVALUE0 V_LOWSIGFORCEVALUE0(1U) 8021176472Skmacy 8022167514Skmacy#define S_LOWSIG0 0 8023167514Skmacy#define V_LOWSIG0(x) ((x) << S_LOWSIG0) 8024167514Skmacy#define F_LOWSIG0 V_LOWSIG0(1U) 8025167514Skmacy 8026167514Skmacy#define A_XGM_SERDES_STAT1 0x8f4 8027167514Skmacy 8028167514Skmacy#define S_EXTBISTCHKERRCNT1 4 8029167514Skmacy#define M_EXTBISTCHKERRCNT1 0xffffff 8030167514Skmacy#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) 8031167514Skmacy#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) 8032167514Skmacy 8033167514Skmacy#define S_EXTBISTCHKFMD1 3 8034167514Skmacy#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) 8035167514Skmacy#define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) 8036167514Skmacy 8037176472Skmacy#define S_LOWSIGFORCEEN1 2 8038176472Skmacy#define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1) 8039176472Skmacy#define F_LOWSIGFORCEEN1 V_LOWSIGFORCEEN1(1U) 8040176472Skmacy 8041176472Skmacy#define S_LOWSIGFORCEVALUE1 1 8042176472Skmacy#define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1) 8043176472Skmacy#define F_LOWSIGFORCEVALUE1 V_LOWSIGFORCEVALUE1(1U) 8044176472Skmacy 8045167514Skmacy#define S_LOWSIG1 0 8046167514Skmacy#define V_LOWSIG1(x) ((x) << S_LOWSIG1) 8047167514Skmacy#define F_LOWSIG1 V_LOWSIG1(1U) 8048167514Skmacy 8049167514Skmacy#define A_XGM_SERDES_STAT2 0x8f8 8050167514Skmacy 8051167514Skmacy#define S_EXTBISTCHKERRCNT2 4 8052167514Skmacy#define M_EXTBISTCHKERRCNT2 0xffffff 8053167514Skmacy#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) 8054167514Skmacy#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) 8055167514Skmacy 8056167514Skmacy#define S_EXTBISTCHKFMD2 3 8057167514Skmacy#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) 8058167514Skmacy#define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) 8059167514Skmacy 8060176472Skmacy#define S_LOWSIGFORCEEN2 2 8061176472Skmacy#define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2) 8062176472Skmacy#define F_LOWSIGFORCEEN2 V_LOWSIGFORCEEN2(1U) 8063176472Skmacy 8064176472Skmacy#define S_LOWSIGFORCEVALUE2 1 8065176472Skmacy#define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2) 8066176472Skmacy#define F_LOWSIGFORCEVALUE2 V_LOWSIGFORCEVALUE2(1U) 8067176472Skmacy 8068167514Skmacy#define S_LOWSIG2 0 8069167514Skmacy#define V_LOWSIG2(x) ((x) << S_LOWSIG2) 8070167514Skmacy#define F_LOWSIG2 V_LOWSIG2(1U) 8071167514Skmacy 8072167514Skmacy#define A_XGM_SERDES_STAT3 0x8fc 8073167514Skmacy 8074167514Skmacy#define S_EXTBISTCHKERRCNT3 4 8075167514Skmacy#define M_EXTBISTCHKERRCNT3 0xffffff 8076167514Skmacy#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) 8077167514Skmacy#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) 8078167514Skmacy 8079167514Skmacy#define S_EXTBISTCHKFMD3 3 8080167514Skmacy#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) 8081167514Skmacy#define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) 8082167514Skmacy 8083176472Skmacy#define S_LOWSIGFORCEEN3 2 8084176472Skmacy#define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3) 8085176472Skmacy#define F_LOWSIGFORCEEN3 V_LOWSIGFORCEEN3(1U) 8086176472Skmacy 8087176472Skmacy#define S_LOWSIGFORCEVALUE3 1 8088176472Skmacy#define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3) 8089176472Skmacy#define F_LOWSIGFORCEVALUE3 V_LOWSIGFORCEVALUE3(1U) 8090176472Skmacy 8091167514Skmacy#define S_LOWSIG3 0 8092167514Skmacy#define V_LOWSIG3(x) ((x) << S_LOWSIG3) 8093167514Skmacy#define F_LOWSIG3 V_LOWSIG3(1U) 8094167514Skmacy 8095167514Skmacy#define A_XGM_STAT_TX_BYTE_LOW 0x900 8096167514Skmacy#define A_XGM_STAT_TX_BYTE_HIGH 0x904 8097167514Skmacy 8098167514Skmacy#define S_TXBYTES_HIGH 0 8099167514Skmacy#define M_TXBYTES_HIGH 0x1fff 8100167514Skmacy#define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH) 8101167514Skmacy#define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH) 8102167514Skmacy 8103167514Skmacy#define A_XGM_STAT_TX_FRAME_LOW 0x908 8104167514Skmacy#define A_XGM_STAT_TX_FRAME_HIGH 0x90c 8105167514Skmacy 8106167514Skmacy#define S_TXFRAMES_HIGH 0 8107167514Skmacy#define M_TXFRAMES_HIGH 0xf 8108167514Skmacy#define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH) 8109167514Skmacy#define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH) 8110167514Skmacy 8111167514Skmacy#define A_XGM_STAT_TX_BCAST 0x910 8112167514Skmacy#define A_XGM_STAT_TX_MCAST 0x914 8113167514Skmacy#define A_XGM_STAT_TX_PAUSE 0x918 8114167514Skmacy#define A_XGM_STAT_TX_64B_FRAMES 0x91c 8115167514Skmacy#define A_XGM_STAT_TX_65_127B_FRAMES 0x920 8116167514Skmacy#define A_XGM_STAT_TX_128_255B_FRAMES 0x924 8117167514Skmacy#define A_XGM_STAT_TX_256_511B_FRAMES 0x928 8118167514Skmacy#define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c 8119167514Skmacy#define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930 8120167514Skmacy#define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934 8121167514Skmacy#define A_XGM_STAT_TX_ERR_FRAMES 0x938 8122167514Skmacy#define A_XGM_STAT_RX_BYTES_LOW 0x93c 8123167514Skmacy#define A_XGM_STAT_RX_BYTES_HIGH 0x940 8124167514Skmacy 8125167514Skmacy#define S_RXBYTES_HIGH 0 8126167514Skmacy#define M_RXBYTES_HIGH 0x1fff 8127167514Skmacy#define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH) 8128167514Skmacy#define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH) 8129167514Skmacy 8130167514Skmacy#define A_XGM_STAT_RX_FRAMES_LOW 0x944 8131167514Skmacy#define A_XGM_STAT_RX_FRAMES_HIGH 0x948 8132167514Skmacy 8133167514Skmacy#define S_RXFRAMES_HIGH 0 8134167514Skmacy#define M_RXFRAMES_HIGH 0xf 8135167514Skmacy#define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH) 8136167514Skmacy#define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH) 8137167514Skmacy 8138167514Skmacy#define A_XGM_STAT_RX_BCAST_FRAMES 0x94c 8139167514Skmacy#define A_XGM_STAT_RX_MCAST_FRAMES 0x950 8140167514Skmacy#define A_XGM_STAT_RX_PAUSE_FRAMES 0x954 8141167514Skmacy 8142167514Skmacy#define S_RXPAUSEFRAMES 0 8143167514Skmacy#define M_RXPAUSEFRAMES 0xffff 8144167514Skmacy#define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES) 8145167514Skmacy#define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES) 8146167514Skmacy 8147167514Skmacy#define A_XGM_STAT_RX_64B_FRAMES 0x958 8148167514Skmacy#define A_XGM_STAT_RX_65_127B_FRAMES 0x95c 8149167514Skmacy#define A_XGM_STAT_RX_128_255B_FRAMES 0x960 8150167514Skmacy#define A_XGM_STAT_RX_256_511B_FRAMES 0x964 8151167514Skmacy#define A_XGM_STAT_RX_512_1023B_FRAMES 0x968 8152167514Skmacy#define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c 8153167514Skmacy#define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970 8154167514Skmacy#define A_XGM_STAT_RX_SHORT_FRAMES 0x974 8155167514Skmacy 8156167514Skmacy#define S_RXSHORTFRAMES 0 8157167514Skmacy#define M_RXSHORTFRAMES 0xffff 8158167514Skmacy#define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES) 8159167514Skmacy#define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES) 8160167514Skmacy 8161167514Skmacy#define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978 8162167514Skmacy 8163167514Skmacy#define S_RXOVERSIZEFRAMES 0 8164167514Skmacy#define M_RXOVERSIZEFRAMES 0xffff 8165167514Skmacy#define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES) 8166167514Skmacy#define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES) 8167167514Skmacy 8168167514Skmacy#define A_XGM_STAT_RX_JABBER_FRAMES 0x97c 8169167514Skmacy 8170167514Skmacy#define S_RXJABBERFRAMES 0 8171167514Skmacy#define M_RXJABBERFRAMES 0xffff 8172167514Skmacy#define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES) 8173167514Skmacy#define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES) 8174167514Skmacy 8175167514Skmacy#define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980 8176167514Skmacy 8177167514Skmacy#define S_RXCRCERRFRAMES 0 8178167514Skmacy#define M_RXCRCERRFRAMES 0xffff 8179167514Skmacy#define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES) 8180167514Skmacy#define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES) 8181167514Skmacy 8182167514Skmacy#define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984 8183167514Skmacy 8184167514Skmacy#define S_RXLENGTHERRFRAMES 0 8185167514Skmacy#define M_RXLENGTHERRFRAMES 0xffff 8186167514Skmacy#define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES) 8187167514Skmacy#define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES) 8188167514Skmacy 8189167514Skmacy#define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988 8190167514Skmacy 8191167514Skmacy#define S_RXSYMCODEERRFRAMES 0 8192167514Skmacy#define M_RXSYMCODEERRFRAMES 0xffff 8193167514Skmacy#define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES) 8194167514Skmacy#define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES) 8195167514Skmacy 8196167514Skmacy#define A_XGM_SERDES_STATUS0 0x98c 8197167514Skmacy 8198167514Skmacy#define S_RXERRLANE3 9 8199167514Skmacy#define M_RXERRLANE3 0x7 8200167514Skmacy#define V_RXERRLANE3(x) ((x) << S_RXERRLANE3) 8201167514Skmacy#define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3) 8202167514Skmacy 8203167514Skmacy#define S_RXERRLANE2 6 8204167514Skmacy#define M_RXERRLANE2 0x7 8205167514Skmacy#define V_RXERRLANE2(x) ((x) << S_RXERRLANE2) 8206167514Skmacy#define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2) 8207167514Skmacy 8208167514Skmacy#define S_RXERRLANE1 3 8209167514Skmacy#define M_RXERRLANE1 0x7 8210167514Skmacy#define V_RXERRLANE1(x) ((x) << S_RXERRLANE1) 8211167514Skmacy#define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1) 8212167514Skmacy 8213167514Skmacy#define S_RXERRLANE0 0 8214167514Skmacy#define M_RXERRLANE0 0x7 8215167514Skmacy#define V_RXERRLANE0(x) ((x) << S_RXERRLANE0) 8216167514Skmacy#define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0) 8217167514Skmacy 8218167514Skmacy#define A_XGM_SERDES_STATUS1 0x990 8219167514Skmacy 8220167514Skmacy#define S_RXKLOCKLANE3 11 8221167514Skmacy#define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3) 8222167514Skmacy#define F_RXKLOCKLANE3 V_RXKLOCKLANE3(1U) 8223167514Skmacy 8224167514Skmacy#define S_RXKLOCKLANE2 10 8225167514Skmacy#define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2) 8226167514Skmacy#define F_RXKLOCKLANE2 V_RXKLOCKLANE2(1U) 8227167514Skmacy 8228167514Skmacy#define S_RXKLOCKLANE1 9 8229167514Skmacy#define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1) 8230167514Skmacy#define F_RXKLOCKLANE1 V_RXKLOCKLANE1(1U) 8231167514Skmacy 8232167514Skmacy#define S_RXKLOCKLANE0 8 8233167514Skmacy#define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0) 8234167514Skmacy#define F_RXKLOCKLANE0 V_RXKLOCKLANE0(1U) 8235167514Skmacy 8236167514Skmacy#define S_RXUFLOWLANE3 7 8237167514Skmacy#define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3) 8238167514Skmacy#define F_RXUFLOWLANE3 V_RXUFLOWLANE3(1U) 8239167514Skmacy 8240167514Skmacy#define S_RXUFLOWLANE2 6 8241167514Skmacy#define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2) 8242167514Skmacy#define F_RXUFLOWLANE2 V_RXUFLOWLANE2(1U) 8243167514Skmacy 8244167514Skmacy#define S_RXUFLOWLANE1 5 8245167514Skmacy#define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1) 8246167514Skmacy#define F_RXUFLOWLANE1 V_RXUFLOWLANE1(1U) 8247167514Skmacy 8248167514Skmacy#define S_RXUFLOWLANE0 4 8249167514Skmacy#define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0) 8250167514Skmacy#define F_RXUFLOWLANE0 V_RXUFLOWLANE0(1U) 8251167514Skmacy 8252167514Skmacy#define S_RXOFLOWLANE3 3 8253167514Skmacy#define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3) 8254167514Skmacy#define F_RXOFLOWLANE3 V_RXOFLOWLANE3(1U) 8255167514Skmacy 8256167514Skmacy#define S_RXOFLOWLANE2 2 8257167514Skmacy#define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2) 8258167514Skmacy#define F_RXOFLOWLANE2 V_RXOFLOWLANE2(1U) 8259167514Skmacy 8260167514Skmacy#define S_RXOFLOWLANE1 1 8261167514Skmacy#define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1) 8262167514Skmacy#define F_RXOFLOWLANE1 V_RXOFLOWLANE1(1U) 8263167514Skmacy 8264167514Skmacy#define S_RXOFLOWLANE0 0 8265167514Skmacy#define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0) 8266167514Skmacy#define F_RXOFLOWLANE0 V_RXOFLOWLANE0(1U) 8267167514Skmacy 8268167514Skmacy#define A_XGM_SERDES_STATUS2 0x994 8269167514Skmacy 8270167514Skmacy#define S_XGM_RXEIDLANE3 11 8271167514Skmacy#define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3) 8272167514Skmacy#define F_XGM_RXEIDLANE3 V_XGM_RXEIDLANE3(1U) 8273167514Skmacy 8274167514Skmacy#define S_XGM_RXEIDLANE2 10 8275167514Skmacy#define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2) 8276167514Skmacy#define F_XGM_RXEIDLANE2 V_XGM_RXEIDLANE2(1U) 8277167514Skmacy 8278167514Skmacy#define S_XGM_RXEIDLANE1 9 8279167514Skmacy#define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1) 8280167514Skmacy#define F_XGM_RXEIDLANE1 V_XGM_RXEIDLANE1(1U) 8281167514Skmacy 8282167514Skmacy#define S_XGM_RXEIDLANE0 8 8283167514Skmacy#define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0) 8284167514Skmacy#define F_XGM_RXEIDLANE0 V_XGM_RXEIDLANE0(1U) 8285167514Skmacy 8286167514Skmacy#define S_RXREMSKIPLANE3 7 8287167514Skmacy#define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3) 8288167514Skmacy#define F_RXREMSKIPLANE3 V_RXREMSKIPLANE3(1U) 8289167514Skmacy 8290167514Skmacy#define S_RXREMSKIPLANE2 6 8291167514Skmacy#define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2) 8292167514Skmacy#define F_RXREMSKIPLANE2 V_RXREMSKIPLANE2(1U) 8293167514Skmacy 8294167514Skmacy#define S_RXREMSKIPLANE1 5 8295167514Skmacy#define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1) 8296167514Skmacy#define F_RXREMSKIPLANE1 V_RXREMSKIPLANE1(1U) 8297167514Skmacy 8298167514Skmacy#define S_RXREMSKIPLANE0 4 8299167514Skmacy#define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0) 8300167514Skmacy#define F_RXREMSKIPLANE0 V_RXREMSKIPLANE0(1U) 8301167514Skmacy 8302167514Skmacy#define S_RXADDSKIPLANE3 3 8303167514Skmacy#define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3) 8304167514Skmacy#define F_RXADDSKIPLANE3 V_RXADDSKIPLANE3(1U) 8305167514Skmacy 8306167514Skmacy#define S_RXADDSKIPLANE2 2 8307167514Skmacy#define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2) 8308167514Skmacy#define F_RXADDSKIPLANE2 V_RXADDSKIPLANE2(1U) 8309167514Skmacy 8310167514Skmacy#define S_RXADDSKIPLANE1 1 8311167514Skmacy#define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1) 8312167514Skmacy#define F_RXADDSKIPLANE1 V_RXADDSKIPLANE1(1U) 8313167514Skmacy 8314167514Skmacy#define S_RXADDSKIPLANE0 0 8315167514Skmacy#define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0) 8316167514Skmacy#define F_RXADDSKIPLANE0 V_RXADDSKIPLANE0(1U) 8317167514Skmacy 8318167514Skmacy#define A_XGM_XAUI_PCS_ERR 0x998 8319167514Skmacy 8320167514Skmacy#define S_PCS_SYNCSTATUS 5 8321167514Skmacy#define M_PCS_SYNCSTATUS 0xf 8322167514Skmacy#define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS) 8323167514Skmacy#define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS) 8324167514Skmacy 8325167514Skmacy#define S_PCS_CTCFIFOERR 1 8326167514Skmacy#define M_PCS_CTCFIFOERR 0xf 8327167514Skmacy#define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR) 8328167514Skmacy#define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR) 8329167514Skmacy 8330167514Skmacy#define S_PCS_NOTALIGNED 0 8331167514Skmacy#define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED) 8332167514Skmacy#define F_PCS_NOTALIGNED V_PCS_NOTALIGNED(1U) 8333167514Skmacy 8334167514Skmacy#define A_XGM_RGMII_STATUS 0x99c 8335167514Skmacy 8336167514Skmacy#define S_GMIIDUPLEX 3 8337167514Skmacy#define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX) 8338167514Skmacy#define F_GMIIDUPLEX V_GMIIDUPLEX(1U) 8339167514Skmacy 8340167514Skmacy#define S_GMIISPEED 1 8341167514Skmacy#define M_GMIISPEED 0x3 8342167514Skmacy#define V_GMIISPEED(x) ((x) << S_GMIISPEED) 8343167514Skmacy#define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED) 8344167514Skmacy 8345167514Skmacy#define S_GMIILINKSTATUS 0 8346167514Skmacy#define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS) 8347167514Skmacy#define F_GMIILINKSTATUS V_GMIILINKSTATUS(1U) 8348167514Skmacy 8349167514Skmacy#define A_XGM_WOL_STATUS 0x9a0 8350167514Skmacy 8351167514Skmacy#define S_PATDETECTED 31 8352167514Skmacy#define V_PATDETECTED(x) ((x) << S_PATDETECTED) 8353167514Skmacy#define F_PATDETECTED V_PATDETECTED(1U) 8354167514Skmacy 8355167514Skmacy#define S_MATCHEDFILTER 0 8356167514Skmacy#define M_MATCHEDFILTER 0x7 8357167514Skmacy#define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER) 8358167514Skmacy#define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER) 8359167514Skmacy 8360167514Skmacy#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 8361167514Skmacy#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8 8362167514Skmacy 8363167514Skmacy#define S_TXSPI4SOPCNT 16 8364167514Skmacy#define M_TXSPI4SOPCNT 0xffff 8365167514Skmacy#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) 8366167514Skmacy#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) 8367167514Skmacy 8368167514Skmacy#define S_TXSPI4EOPCNT 0 8369167514Skmacy#define M_TXSPI4EOPCNT 0xffff 8370167514Skmacy#define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT) 8371167514Skmacy#define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT) 8372167514Skmacy 8373167514Skmacy#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac 8374167514Skmacy 8375167514Skmacy#define S_RXSPI4SOPCNT 16 8376167514Skmacy#define M_RXSPI4SOPCNT 0xffff 8377167514Skmacy#define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT) 8378167514Skmacy#define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT) 8379167514Skmacy 8380167514Skmacy#define S_RXSPI4EOPCNT 0 8381167514Skmacy#define M_RXSPI4EOPCNT 0xffff 8382167514Skmacy#define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT) 8383167514Skmacy#define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT) 8384167514Skmacy 8385167514Skmacy/* registers for module XGMAC0_1 */ 8386167514Skmacy#define XGMAC0_1_BASE_ADDR 0xa00 8387