1139749Simp/*-
2123120Simp * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
3123120Simp * controller RISC processor CL-CD2400/2401.
4123120Simp *
5123120Simp * Copyright (C) 1994-2000 Cronyx Engineering.
6123120Simp * Author: Serge Vakulenko, <vak@cronyx.ru>
7123120Simp *
8123120Simp * This software is distributed with NO WARRANTIES, not even the implied
9123120Simp * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
10123120Simp *
11123120Simp * Authors grant any other persons or organisations permission to use
12123120Simp * or modify this software as long as this message is kept with the software,
13123120Simp * all derivative works or modified versions.
14123120Simp *
15123120Simp * Cronyx Id: cxreg.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
16123120Simp * $FreeBSD$
17123120Simp */
18123120Simp#define REVCL_MIN   7		/* CD2400 min. revision number G */
19123120Simp#define REVCL_MAX   13		/* CD2400 max. revision number M */
20123120Simp#define REVCL31_MIN 0x33	/* CD2431 min. revision number C */
21123120Simp#define REVCL31_MAX 0x34	/* CD2431 max. revision number D */
22123120Simp
23123120Simp#define BRD_INTR_LEVEL 0x5a	/* interrupt level (arbitrary PILR value) */
24123120Simp
25123120Simp#define CS0(p)	((p) | 0x8000)	/* chip select 0 */
26123120Simp#define CS1(p)	((p) | 0xc000)	/* chip select 1 */
27123120Simp#define CS1A(p)	((p) | 0x8010)	/* chip select 1 for agp-compatible models */
28123120Simp#define BSR(p)	(p)		/* board status register, read only */
29123120Simp#define BCR0(p)	(p)		/* board command register 0, write only */
30123120Simp#define BCR1(p)	((p) | 0x2000)	/* board command register 1, write only */
31123120Simp
32123120Simp/*
33123120Simp * For Sigma-800 only.
34123120Simp */
35123120Simp#define BDET(p)	((p) | 0x2000)	/* board detection register, read only */
36123120Simp#define BCR2(p)	((p) | 0x4000)	/* board command register 2, write only */
37123120Simp
38123120Simp/*
39123120Simp * Chip register address, B is chip base port, R is chip register number.
40123120Simp */
41123120Simp#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
42123120Simp
43123120Simp/*
44123120Simp * Interrupt acknowledge register, P is board port, L is interrupt level,
45123120Simp * as prodrammed in PILR.
46123120Simp */
47123120Simp#define IACK(p,l)   (R(p,l) | 0x4000)
48123120Simp
49123120Simp/*
50123120Simp * Global registers.
51123120Simp */
52123120Simp#define GFRCR(b)    R(b,0x82)	/* global firmware revision code register */
53123120Simp#define CAR(b)      R(b,0xec)	/* channel access register */
54123120Simp
55123120Simp/*
56123120Simp * Option registers.
57123120Simp */
58123120Simp#define CMR(b)      R(b,0x18)	/* channel mode register */
59123120Simp#define COR1(b)     R(b,0x13)	/* channel option register 1 */
60123120Simp#define COR2(b)     R(b,0x14)	/* channel option register 2 */
61123120Simp#define COR3(b)     R(b,0x15)	/* channel option register 3 */
62123120Simp#define COR4(b)     R(b,0x16)	/* channel option register 4 */
63123120Simp#define COR5(b)     R(b,0x17)	/* channel option register 5 */
64123120Simp#define COR6(b)     R(b,0x1b)	/* channel option register 6 */
65123120Simp#define COR7(b)     R(b,0x04)	/* channel option register 7 */
66123120Simp#define SCHR1(b)    R(b,0x1c)	/* special character register 1 */
67123120Simp#define SCHR2(b)    R(b,0x1d)	/* special character register 2 */
68123120Simp#define SCHR3(b)    R(b,0x1e)	/* special character register 3 */
69123120Simp#define SCHR4(b)    R(b,0x1f)	/* special character register 4 */
70123120Simp#define SCRL(b)     R(b,0x20)	/* special character range low */
71123120Simp#define SCRH(b)     R(b,0x21)	/* special character range high */
72123120Simp#define LNXT(b)     R(b,0x2d)	/* LNext character */
73123120Simp#define RFAR1(b)    R(b,0x1c)	/* receive frame address register 1 */
74123120Simp#define RFAR2(b)    R(b,0x1d)	/* receive frame address register 2 */
75123120Simp#define RFAR3(b)    R(b,0x1e)	/* receive frame address register 3 */
76123120Simp#define RFAR4(b)    R(b,0x1f)	/* receive frame address register 4 */
77123120Simp#define CPSR(b)     R(b,0xd4)	/* CRC polynomial select register */
78123120Simp
79123120Simp/*
80123120Simp * Bit rate and clock option registers.
81123120Simp */
82123120Simp#define RBPR(b)     R(b,0xc9)	/* receive baud rate period register */
83123120Simp#define RCOR(b)     R(b,0xca)	/* receive clock option register */
84123120Simp#define TBPR(b)     R(b,0xc1)	/* transmit baud rate period register */
85123120Simp#define TCOR(b)     R(b,0xc2)	/* receive clock option register */
86123120Simp
87123120Simp/*
88123120Simp * Channel command and status registers.
89123120Simp */
90123120Simp#define CCR(b)      R(b,0x10)	/* channel command register */
91123120Simp#define STCR(b)     R(b,0x11)	/* special transmit command register */
92123120Simp#define CSR(b)      R(b,0x19)	/* channel status register */
93123120Simp#define MSVR(b)     R(b,0xdc)	/* modem signal value register */
94123120Simp#define MSVR_RTS(b) R(b,0xdc)	/* modem RTS setup register */
95123120Simp#define MSVR_DTR(b) R(b,0xdd)	/* modem DTR setup register */
96123120Simp
97123120Simp/*
98123120Simp * Interrupt registers.
99123120Simp */
100123120Simp#define LIVR(b)     R(b,0x0a)	/* local interrupt vector register */
101123120Simp#define IER(b)      R(b,0x12)	/* interrupt enable register */
102123120Simp#define LICR(b)     R(b,0x25)	/* local interrupting channel register */
103123120Simp#define STK(b)      R(b,0xe0)	/* stack register */
104123120Simp
105123120Simp/*
106123120Simp * Receive interrupt registers.
107123120Simp */
108123120Simp#define RPILR(b)    R(b,0xe3)	/* receive priority interrupt level register */
109123120Simp#define RIR(b)      R(b,0xef)	/* receive interrupt register */
110123120Simp#define RISR(b)     R(b,0x8a)	/* receive interrupt status register */
111123120Simp#define RISRL(b)    R(b,0x8a)	/* receive interrupt status register low */
112123120Simp#define RISRH(b)    R(b,0x8b)	/* receive interrupt status register high */
113123120Simp#define RFOC(b)     R(b,0x33)	/* receive FIFO output count */
114123120Simp#define RDR(b)      R(b,0xf8)	/* receive data register */
115123120Simp#define REOIR(b)    R(b,0x87)	/* receive end of interrupt register */
116123120Simp
117123120Simp/*
118123120Simp * Transmit interrupt registers.
119123120Simp */
120123120Simp#define TPILR(b)    R(b,0xe2)	/* transmit priority interrupt level reg */
121123120Simp#define TIR(b)      R(b,0xee)	/* transmit interrupt register */
122123120Simp#define TISR(b)     R(b,0x89)	/* transmit interrupt status register */
123123120Simp#define TFTC(b)     R(b,0x83)	/* transmit FIFO transfer count */
124123120Simp#define TDR(b)      R(b,0xf8)	/* transmit data register */
125123120Simp#define TEOIR(b)    R(b,0x86)	/* transmit end of interrupt register */
126123120Simp
127123120Simp/*
128123120Simp * Modem interrupt registers.
129123120Simp */
130123120Simp#define MPILR(b)    R(b,0xe1)	/* modem priority interrupt level register */
131123120Simp#define MIR(b)      R(b,0xed)	/* modem interrupt register */
132123120Simp#define MISR(b)     R(b,0x88)	/* modem/timer interrupt status register */
133123120Simp#define MEOIR(b)    R(b,0x85)	/* modem end of interrupt register */
134123120Simp
135123120Simp/*
136123120Simp * DMA registers.
137123120Simp */
138123120Simp#define DMR(b)      R(b,0xf4)	/* DMA mode register */
139123120Simp#define BERCNT(b)   R(b,0x8d)	/* bus error retry count */
140123120Simp#define DMABSTS(b)  R(b,0x1a)	/* DMA buffer status */
141123120Simp
142123120Simp/*
143123120Simp * DMA receive registers.
144123120Simp */
145123120Simp#define ARBADRL(b)  R(b,0x40)	/* A receive buffer address lower */
146123120Simp#define ARBADRU(b)  R(b,0x42)	/* A receive buffer address upper */
147123120Simp#define BRBADRL(b)  R(b,0x44)	/* B receive buffer address lower */
148123120Simp#define BRBADRU(b)  R(b,0x46)	/* B receive buffer address upper */
149123120Simp#define ARBCNT(b)   R(b,0x48)	/* A receive buffer byte count */
150123120Simp#define BRBCNT(b)   R(b,0x4a)	/* B receive buffer byte count */
151123120Simp#define ARBSTS(b)   R(b,0x4c)	/* A receive buffer status */
152123120Simp#define BRBSTS(b)   R(b,0x4d)	/* B receive buffer status */
153123120Simp#define RCBADRL(b)  R(b,0x3c)	/* receive current buffer address lower */
154123120Simp#define RCBADRU(b)  R(b,0x3e)	/* receive current buffer address upper */
155123120Simp
156123120Simp/*
157123120Simp * DMA transmit registers.
158123120Simp */
159123120Simp#define ATBADRL(b)  R(b,0x50)	/* A transmit buffer address lower */
160123120Simp#define ATBADRU(b)  R(b,0x52)	/* A transmit buffer address upper */
161123120Simp#define BTBADRL(b)  R(b,0x54)	/* B transmit buffer address lower */
162123120Simp#define BTBADRU(b)  R(b,0x56)	/* B transmit buffer address upper */
163123120Simp#define ATBCNT(b)   R(b,0x58)	/* A transmit buffer byte count */
164123120Simp#define BTBCNT(b)   R(b,0x5a)	/* B transmit buffer byte count */
165123120Simp#define ATBSTS(b)   R(b,0x5c)	/* A transmit buffer status */
166123120Simp#define BTBSTS(b)   R(b,0x5d)	/* B transmit buffer status */
167123120Simp#define TCBADRL(b)  R(b,0x38)	/* transmit current buffer address lower */
168123120Simp#define TCBADRU(b)  R(b,0x3a)	/* transmit current buffer address upper */
169123120Simp
170123120Simp/*
171123120Simp * Timer registers.
172123120Simp */
173123120Simp#define TPR(b)      R(b,0xd8)	/* timer period register */
174123120Simp#define RTPR(b)     R(b,0x26)	/* receive timeout period register */
175123120Simp#define RTPRL(b)    R(b,0x26)	/* receive timeout period register low */
176123120Simp#define RTPTH(b)    R(b,0x27)	/* receive timeout period register high */
177123120Simp#define GT1(b)      R(b,0x28)	/* general timer 1 */
178123120Simp#define GT1L(b)     R(b,0x28)	/* general timer 1 low */
179123120Simp#define GT1H(b)     R(b,0x29)	/* general timer 1 high */
180123120Simp#define GT2(b)      R(b,0x2a)	/* general timer 2 */
181123120Simp#define TTR(b)      R(b,0x2a)	/* transmit timer register */
182123120Simp
183123120Simp/*
184123120Simp * Board status register bits, for all models.
185123120Simp */
186123120Simp#define BSR_NOINTR     0x01	/* no interrupt pending flag */
187123120Simp#define BSR_NOCHAIN    0x80	/* no daisy chained board, all but Sigma-22 */
188123120Simp
189123120Simp/*
190123120Simp * For old Sigmas only.
191123120Simp */
192123120Simp#define BSR_VAR_MASK   0x66	/* adapter variant mask */
193123120Simp#define BSR_OSC_MASK   0x18	/* oscillator frequency mask */
194123120Simp#define BSR_OSC_20     0x18	/* 20 MHz */
195123120Simp#define BSR_OSC_18432  0x10	/* 18.432 MHz */
196123120Simp
197123120Simp#define BSR_NODSR(n)   (0x100 << (n))	/* DSR from channels 0-3, inverted */
198123120Simp#define BSR_NOCD(n)    (0x1000 << (n))	/* CD from channels 0-3, inverted */
199123120Simp
200123120Simp/*
201123120Simp * Board status register bits for Sigma-2x.
202123120Simp */
203123120Simp#define BSR2X_OSC_33     0x08	/* oscillator 33/20 MHz bit */
204123120Simp#define BSR2X_VAR_MASK   0x30	/* Sigma-2x variant mask */
205123120Simp
206123120Simp/*
207123120Simp * Board status register bits for Sigma-800.
208123120Simp */
209123120Simp#define BSR800_NU0       0x02	/* no channels 0-3 installed */
210123120Simp#define BSR800_NU1       0x04	/* no channels 4-7 installed */
211123120Simp#define BSR800_LERR      0x08	/* firmware load error */
212123120Simp#define BSR800_MIRQ      0x10	/* modem IRQ active */
213123120Simp#define BSR800_TIRQ      0x20	/* transmit IRQ active */
214123120Simp#define BSR800_RIRQ      0x40	/* receive IRQ active */
215123120Simp
216123120Simp#define BDET_IB          0x08	/* identification bit */
217123120Simp#define BDET_IB_NEG      0x80	/* negated identification bit */
218123120Simp
219123120Simp/*
220123120Simp * Sigma-800 control register 2 bits.
221123120Simp */
222123120Simp#define BCR2_BUS0       0x01	/* bus timing control */
223123120Simp#define BCR2_BUS1       0x02	/* bus timing control */
224123120Simp#define BCR2_TMS  	0x08	/* firmware download signal */
225123120Simp#define BCR2_TDI  	0x80	/* firmware download signal */
226123120Simp
227123120Simp/*
228123120Simp * Board revision mask.
229123120Simp */
230123120Simp#define BSR_REV_MASK     (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
231123120Simp#define BSR2X_REV_MASK   (BSR_OSC_MASK|BSR_VAR_MASK)
232123120Simp
233123120Simp/*
234123120Simp * Sigma-2x variants.
235123120Simp */
236123120Simp#define CRONYX_22	0x20
237123120Simp#define CRONYX_24	0x00
238123120Simp
239123120Simp/*
240123120Simp * Sigma-XXX variants.
241123120Simp */
242123120Simp#define CRONYX_100	0x64
243123120Simp#define CRONYX_400	0x62
244123120Simp#define CRONYX_500	0x60
245123120Simp#define CRONYX_410	0x24
246123120Simp#define CRONYX_810	0x20
247123120Simp#define CRONYX_410s	0x04
248123120Simp#define CRONYX_810s	0x00
249123120Simp#define CRONYX_440	0x44
250123120Simp#define CRONYX_840	0x40
251123120Simp#define CRONYX_401	0x26
252123120Simp#define CRONYX_801	0x22
253123120Simp#define CRONYX_401s	0x06
254123120Simp#define CRONYX_801s	0x02
255123120Simp#define CRONYX_404	0x46
256123120Simp#define CRONYX_703	0x42
257123120Simp
258123120Simp/*
259123120Simp * Board control register 0 bits.
260123120Simp */
261123120Simp#define BCR0_IRQ_DIS  0x00	/* no interrupt generated */
262123120Simp#define BCR0_IRQ_3    0x01	/* select IRQ number 3 */
263123120Simp#define BCR0_IRQ_5    0x02	/* select IRQ number 5 */
264123120Simp#define BCR0_IRQ_7    0x03	/* select IRQ number 7 */
265123120Simp#define BCR0_IRQ_10   0x04	/* select IRQ number 10 */
266123120Simp#define BCR0_IRQ_11   0x05	/* select IRQ number 11 */
267123120Simp#define BCR0_IRQ_12   0x06	/* select IRQ number 12 */
268123120Simp#define BCR0_IRQ_15   0x07	/* select IRQ number 15 */
269123120Simp#define BCR0_IRQ_MASK 0x07	/* irq select mask */
270123120Simp
271123120Simp#define BCR0_DMA_DIS  0x00	/* no interrupt generated */
272123120Simp#define BCR0_DMA_5    0x10	/* select DMA channel 5 */
273123120Simp#define BCR0_DMA_6    0x20	/* select DMA channel 6 */
274123120Simp#define BCR0_DMA_7    0x30	/* select DMA channel 7 */
275123120Simp#define BCR0_DMA_MASK 0x30	/* drq select mask */
276123120Simp
277123120Simp/* For old Sigmas only. */
278123120Simp#define BCR0_NORESET  0x08	/* CD2400 reset flag (inverted) */
279123120Simp
280123120Simp#define BCR0_UM_ASYNC 0x00	/* channel 0 mode - async */
281123120Simp#define BCR0_UM_SYNC  0x80	/* channel 0 mode - sync */
282123120Simp#define BCR0_UI_RS232 0x00	/* channel 0 interface - RS-232 */
283123120Simp#define BCR0_UI_RS449 0x40	/* channel 0 interface - RS-449/V.35 */
284123120Simp#define BCR0_UMASK    0xc0	/* channel 0 interface mask */
285123120Simp
286123120Simp/* For Sigma-22 only. */
287123120Simp#define BCR02X_FAST   0x40	/* fast bus timing */
288123120Simp#define BCR02X_LED    0x80	/* LED control */
289123120Simp
290123120Simp/* For Sigma-800 only. */
291123120Simp#define BCR0800_TCK   0x80	/* firmware download signal */
292123120Simp
293123120Simp/*
294123120Simp * Board control register 1 bits.
295123120Simp */
296123120Simp/* For old Sigmas only. */
297123120Simp#define BCR1_DTR(n)    (0x100 << (n))	/* DTR for channels 0-3 sync */
298123120Simp
299123120Simp/* For Sigma-800 only. */
300123120Simp#define BCR1800_DTR(n) (1 << ((n) & 7))	/* DTR for channels 0-7 sync */
301123120Simp
302123120Simp/*
303123120Simp * Channel commands (CCR).
304123120Simp */
305123120Simp#define CCR_CLRCH  0x40		/* clear channel */
306123120Simp#define CCR_INITCH 0x20		/* initialize channel */
307123120Simp#define CCR_RSTALL 0x10		/* reset all channels */
308123120Simp#define CCR_ENTX   0x08		/* enable transmitter */
309123120Simp#define CCR_DISTX  0x04		/* disable transmitter */
310123120Simp#define CCR_ENRX   0x02		/* enable receiver */
311123120Simp#define CCR_DISRX  0x01		/* disable receiver */
312123120Simp#define CCR_CLRT1  0xc0		/* clear timer 1 */
313123120Simp#define CCR_CLRT2  0xa0		/* clear timer 2 */
314123120Simp#define CCR_CLRRCV 0x90		/* clear receiver */
315123120Simp#define CCR_CLRTX  0x88		/* clear transmitter */
316123120Simp
317123120Simp/*
318123120Simp * Interrupt enable register (IER) bits.
319123120Simp */
320123120Simp#define IER_MDM    0x80		/* modem status changed */
321123120Simp#define IER_RET    0x20		/* receive exception timeout */
322123120Simp#define IER_RXD    0x08		/* data received */
323123120Simp#define IER_TIMER  0x04		/* timer expired */
324123120Simp#define IER_TXMPTY 0x02		/* transmitter empty */
325123120Simp#define IER_TXD    0x01		/* data transmitted */
326123120Simp
327123120Simp/*
328123120Simp * Modem signal values register bits (MSVR).
329123120Simp */
330123120Simp#define MSV_DSR    0x80		/* state of Data Set Ready input */
331123120Simp#define MSV_CD     0x40		/* state of Carrier Detect input */
332123120Simp#define MSV_CTS    0x20		/* state of Clear to Send input */
333123120Simp#define MSV_TXCOUT 0x10		/* TXCout/DTR pin output flag */
334123120Simp#define MSV_PORTID 0x04		/* device is CL-CD2401 (not 2400) */
335123120Simp#define MSV_DTR    0x02		/* state of Data Terminal Ready output */
336123120Simp#define MSV_RTS    0x01		/* state of Request to Send output */
337123120Simp#define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
338123120Simp
339123120Simp/*
340123120Simp * DMA buffer status register bits (DMABSTS).
341123120Simp */
342123120Simp#define DMABSTS_TDALIGN 0x80	/* internal data alignment in transmit FIFO */
343123120Simp#define DMABSTS_RSTAPD  0x40	/* reset append mode */
344123120Simp#define DMABSTS_CRTTBUF 0x20	/* internal current transmit buffer in use */
345123120Simp#define DMABSTS_APPEND  0x10	/* append buffer is in use */
346123120Simp#define DMABSTS_NTBUF   0x08	/* next transmit buffer is B (not A) */
347123120Simp#define DMABSTS_TBUSY   0x04	/* current transmit buffer is in use */
348123120Simp#define DMABSTS_NRBUF   0x02	/* next receive buffer is B (not A) */
349123120Simp#define DMABSTS_RBUSY   0x01	/* current receive buffer is in use */
350123120Simp
351123120Simp/*
352123120Simp * Buffer status register bits ([AB][RT]BSTS).
353123120Simp */
354123120Simp#define BSTS_BUSERR 0x80	/* bus error */
355123120Simp#define BSTS_EOFR   0x40	/* end of frame */
356123120Simp#define BSTS_EOBUF  0x20	/* end of buffer */
357123120Simp#define BSTS_APPEND 0x08	/* append mode */
358123120Simp#define BSTS_INTR   0x02	/* interrupt required */
359123120Simp#define BSTS_OWN24  0x01	/* buffer is (free to be) used by CD2400 */
360123120Simp#define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
361123120Simp
362123120Simp/*
363123120Simp * Receive interrupt status register (RISR) bits.
364123120Simp */
365123120Simp#define RIS_OVERRUN   0x0008	/* overrun error */
366123120Simp#define RIS_BB        0x0800	/* buffer B status (not A) */
367123120Simp#define RIS_EOBUF     0x2000	/* end of buffer reached */
368123120Simp#define RIS_EOFR      0x4000	/* frame reception complete */
369123120Simp#define RIS_BUSERR    0x8000	/* bus error */
370123120Simp
371123120Simp#define RISH_CLRDCT   0x0001	/* X.21 clear detect */
372123120Simp#define RISH_RESIND   0x0004	/* residual indication */
373123120Simp#define RISH_CRCERR   0x0010	/* CRC error */
374123120Simp#define RISH_RXABORT  0x0020	/* abort sequence received */
375123120Simp#define RISH_EOFR     0x0040	/* complete frame received */
376123120Simp#define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
377123120Simp
378123120Simp#define RISA_BREAK    0x0001	/* break signal detected */
379123120Simp#define RISA_FRERR    0x0002	/* frame error (bad stop bits) */
380123120Simp#define RISA_PARERR   0x0004	/* parity error */
381123120Simp#define RISA_SCMASK   0x0070	/* special character detect mask */
382123120Simp#define RISA_SCHR1    0x0010	/* special character 1 detected */
383123120Simp#define RISA_SCHR2    0x0020	/* special character 2 detected */
384123120Simp#define RISA_SCHR3    0x0030	/* special character 3 detected */
385123120Simp#define RISA_SCHR4    0x0040	/* special character 4 detected */
386123120Simp#define RISA_SCRANGE  0x0070	/* special character in range detected */
387123120Simp#define RISA_TIMEOUT  0x0080	/* receive timeout, no data */
388123120Simp#define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
389123120Simp
390123120Simp#define RISB_CRCERR   0x0010	/* CRC error */
391123120Simp#define RISB_RXABORT  0x0020	/* abort sequence received */
392123120Simp#define RISB_EOFR     0x0040	/* complete frame received */
393123120Simp
394123120Simp#define RISX_LEADCHG  0x0001	/* CTS lead change */
395123120Simp#define RISX_PARERR   0x0004	/* parity error */
396123120Simp#define RISX_SCMASK   0x0070	/* special character detect mask */
397123120Simp#define RISX_SCHR1    0x0010	/* special character 1 detected */
398123120Simp#define RISX_SCHR2    0x0020	/* special character 2 detected */
399123120Simp#define RISX_SCHR3    0x0030	/* special character 3 detected */
400123120Simp#define RISX_ALLZERO  0x0040	/* all 0 condition detected */
401123120Simp#define RISX_ALLONE   0x0050	/* all 1 condition detected */
402123120Simp#define RISX_ALTOZ    0x0060	/* alternating 1 0 condition detected */
403123120Simp#define RISX_SYN      0x0070	/* SYN detected */
404123120Simp#define RISX_LEAD     0x0080	/* leading value */
405123120Simp
406123120Simp/*
407123120Simp * Channel mode register (CMR) bits.
408123120Simp */
409123120Simp#define CMR_RXDMA     0x80	/* DMA receive transfer mode */
410123120Simp#define CMR_TXDMA     0x40	/* DMA transmit transfer mode */
411123120Simp#define CMR_HDLC      0x00	/* HDLC protocol mode */
412123120Simp#define CMR_BISYNC    0x01	/* BISYNC protocol mode */
413123120Simp#define CMR_ASYNC     0x02	/* ASYNC protocol mode */
414123120Simp#define CMR_X21       0x03	/* X.21 protocol mode */
415123120Simp
416123120Simp/*
417123120Simp * Modem interrupt status register (MISR) bits.
418123120Simp */
419123120Simp#define MIS_CDSR      0x80	/* DSR changed */
420123120Simp#define MIS_CCD       0x40	/* CD changed */
421123120Simp#define MIS_CCTS      0x20	/* CTS changed */
422123120Simp#define MIS_CGT2      0x02	/* GT2 timer expired */
423123120Simp#define MIS_CGT1      0x01	/* GT1 timer expired */
424123120Simp#define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
425123120Simp
426123120Simp/*
427123120Simp * Transmit interrupt status register (TISR) bits.
428123120Simp */
429123120Simp#define TIS_BUSERR    0x80	/* Bus error */
430123120Simp#define TIS_EOFR      0x40	/* End of frame */
431123120Simp#define TIS_EOBUF     0x20	/* end of transmit buffer reached */
432123120Simp#define TIS_UNDERRUN  0x10	/* transmit underrun */
433123120Simp#define TIS_BB        0x08	/* buffer B status (not A) */
434123120Simp#define TIS_TXEMPTY   0x02	/* transmitter empty */
435123120Simp#define TIS_TXDATA    0x01	/* transmit data below threshold */
436123120Simp#define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
437123120Simp
438123120Simp/*
439123120Simp * Local interrupt vector register (LIVR) bits.
440123120Simp */
441123120Simp#define LIV_EXCEP     0
442123120Simp#define LIV_MODEM     1
443123120Simp#define LIV_TXDATA    2
444123120Simp#define LIV_RXDATA    3
445123120Simp
446123120Simp/*
447123120Simp * Transmit end of interrupt registers (TEOIR) bits.
448123120Simp */
449123120Simp#define TEOI_TERMBUFF  0x80	/* force current buffer to be discarded */
450123120Simp#define TEOI_EOFR      0x40	/* end of frame in interrupt mode */
451123120Simp#define TEOI_SETTM2    0x20	/* set general timer 2 in sync mode */
452123120Simp#define TEOI_SETTM1    0x10	/* set general timer 1 in sync mode */
453123120Simp#define TEOI_NOTRANSF  0x08	/* no transfer of data on this interrupt */
454123120Simp
455123120Simp/*
456123120Simp * Receive end of interrupt registers (REOIR) bits.
457123120Simp */
458123120Simp#define REOI_TERMBUFF  0x80	/* force current buffer to be terminated */
459123120Simp#define REOI_DISCEXC   0x40	/* discard exception character */
460123120Simp#define REOI_SETTM2    0x20	/* set general timer 2 */
461123120Simp#define REOI_SETTM1    0x10	/* set general timer 1 */
462123120Simp#define REOI_NOTRANSF  0x08	/* no transfer of data */
463123120Simp#define REOI_GAP_MASK  0x07	/* optional gap size to leave in buffer */
464123120Simp
465123120Simp/*
466123120Simp * Special transmit command register (STCR) bits.
467123120Simp */
468123120Simp#define STC_ABORTTX   0x40	/* abort transmission (HDLC mode) */
469123120Simp#define STC_APPDCMP   0x20	/* append complete (async DMA mode) */
470123120Simp#define STC_SNDSPC    0x08	/* send special characters (async mode) */
471123120Simp#define STC_SSPC_MASK 0x07	/* special character select */
472123120Simp#define STC_SSPC_1    0x01	/* send special character #1 */
473123120Simp#define STC_SSPC_2    0x02	/* send special character #2 */
474123120Simp#define STC_SSPC_3    0x03	/* send special character #3 */
475123120Simp#define STC_SSPC_4    0x04	/* send special character #4 */
476123120Simp
477123120Simp/*
478123120Simp * Channel status register (CSR) bits, asynchronous mode.
479123120Simp */
480123120Simp#define CSRA_RXEN    0x80       /* receiver enable */
481123120Simp#define CSRA_RXFLOFF 0x40       /* receiver flow off */
482123120Simp#define CSRA_RXFLON  0x20       /* receiver flow on */
483123120Simp#define CSRA_TXEN    0x08       /* transmitter enable */
484123120Simp#define CSRA_TXFLOFF 0x04       /* transmitter flow off */
485123120Simp#define CSRA_TXFLON  0x02       /* transmitter flow on */
486123120Simp#define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"
487