1227730Sraj/*- 2227730Sraj * Copyright (C) 2009-2011 Semihalf. 3227730Sraj * All rights reserved. 4227730Sraj * 5227730Sraj * Redistribution and use in source and binary forms, with or without 6227730Sraj * modification, are permitted provided that the following conditions 7227730Sraj * are met: 8227730Sraj * 1. Redistributions of source code must retain the above copyright 9227730Sraj * notice, this list of conditions and the following disclaimer. 10227730Sraj * 2. Redistributions in binary form must reproduce the above copyright 11227730Sraj * notice, this list of conditions and the following disclaimer in the 12227730Sraj * documentation and/or other materials provided with the distribution. 13227730Sraj * 14227730Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15227730Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16227730Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17227730Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18227730Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19227730Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20227730Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21227730Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22227730Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23227730Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24227730Sraj * SUCH DAMAGE. 25227730Sraj */ 26227730Sraj 27227730Sraj/* 28227730Sraj * CESA SRAM Memory Map: 29227730Sraj * 30227730Sraj * +------------------------+ <= sc->sc_sram_base + CESA_SRAM_SIZE 31227730Sraj * | | 32227730Sraj * | DATA | 33227730Sraj * | | 34227730Sraj * +------------------------+ <= sc->sc_sram_base + CESA_DATA(0) 35227730Sraj * | struct cesa_sa_data | 36227730Sraj * +------------------------+ 37227730Sraj * | struct cesa_sa_hdesc | 38227730Sraj * +------------------------+ <= sc->sc_sram_base 39227730Sraj */ 40227730Sraj 41227730Sraj#include <sys/cdefs.h> 42227730Sraj__FBSDID("$FreeBSD$"); 43227730Sraj 44227730Sraj#include <sys/param.h> 45227730Sraj#include <sys/systm.h> 46227730Sraj#include <sys/bus.h> 47227730Sraj#include <sys/endian.h> 48227730Sraj#include <sys/kernel.h> 49227730Sraj#include <sys/lock.h> 50227730Sraj#include <sys/mbuf.h> 51227730Sraj#include <sys/module.h> 52227730Sraj#include <sys/mutex.h> 53227730Sraj#include <sys/rman.h> 54227730Sraj 55227730Sraj#include <machine/bus.h> 56227730Sraj#include <machine/intr.h> 57227730Sraj#include <machine/resource.h> 58227730Sraj 59227730Sraj#include <dev/fdt/fdt_common.h> 60227730Sraj#include <dev/ofw/ofw_bus.h> 61227730Sraj#include <dev/ofw/ofw_bus_subr.h> 62227730Sraj 63227730Sraj#include <sys/md5.h> 64227730Sraj#include <crypto/sha1.h> 65227730Sraj#include <crypto/rijndael/rijndael.h> 66227730Sraj#include <opencrypto/cryptodev.h> 67227730Sraj#include "cryptodev_if.h" 68227730Sraj 69227730Sraj#include <arm/mv/mvreg.h> 70227730Sraj#include <arm/mv/mvwin.h> 71227730Sraj#include <arm/mv/mvvar.h> 72227730Sraj#include "cesa.h" 73227730Sraj 74227730Sraj#undef DEBUG 75227730Sraj 76227730Srajstatic int cesa_probe(device_t); 77227730Srajstatic int cesa_attach(device_t); 78227730Srajstatic int cesa_detach(device_t); 79227730Srajstatic void cesa_intr(void *); 80227730Srajstatic int cesa_newsession(device_t, u_int32_t *, struct cryptoini *); 81227730Srajstatic int cesa_freesession(device_t, u_int64_t); 82227730Srajstatic int cesa_process(device_t, struct cryptop *, int); 83227730Sraj 84227730Srajstatic struct resource_spec cesa_res_spec[] = { 85227730Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 86227730Sraj { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 87227730Sraj { -1, 0 } 88227730Sraj}; 89227730Sraj 90227730Srajstatic device_method_t cesa_methods[] = { 91227730Sraj /* Device interface */ 92227730Sraj DEVMETHOD(device_probe, cesa_probe), 93227730Sraj DEVMETHOD(device_attach, cesa_attach), 94227730Sraj DEVMETHOD(device_detach, cesa_detach), 95227730Sraj 96227730Sraj /* Bus interface */ 97227730Sraj DEVMETHOD(bus_print_child, bus_generic_print_child), 98227730Sraj DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99227730Sraj 100227730Sraj /* Crypto device methods */ 101227730Sraj DEVMETHOD(cryptodev_newsession, cesa_newsession), 102227730Sraj DEVMETHOD(cryptodev_freesession,cesa_freesession), 103227730Sraj DEVMETHOD(cryptodev_process, cesa_process), 104227730Sraj 105227730Sraj { 0, 0 } 106227730Sraj}; 107227730Sraj 108227730Srajstatic driver_t cesa_driver = { 109227730Sraj "cesa", 110227730Sraj cesa_methods, 111227730Sraj sizeof (struct cesa_softc) 112227730Sraj}; 113227730Srajstatic devclass_t cesa_devclass; 114227730Sraj 115227730SrajDRIVER_MODULE(cesa, simplebus, cesa_driver, cesa_devclass, 0, 0); 116227730SrajMODULE_DEPEND(cesa, crypto, 1, 1, 1); 117227730Sraj 118227730Srajstatic void 119227730Srajcesa_dump_cshd(struct cesa_softc *sc, struct cesa_sa_hdesc *cshd) 120227730Sraj{ 121227730Sraj#ifdef DEBUG 122227730Sraj device_t dev; 123227730Sraj 124227730Sraj dev = sc->sc_dev; 125227730Sraj device_printf(dev, "CESA SA Hardware Descriptor:\n"); 126227730Sraj device_printf(dev, "\t\tconfig: 0x%08X\n", cshd->cshd_config); 127227730Sraj device_printf(dev, "\t\te_src: 0x%08X\n", cshd->cshd_enc_src); 128227730Sraj device_printf(dev, "\t\te_dst: 0x%08X\n", cshd->cshd_enc_dst); 129227730Sraj device_printf(dev, "\t\te_dlen: 0x%08X\n", cshd->cshd_enc_dlen); 130227730Sraj device_printf(dev, "\t\te_key: 0x%08X\n", cshd->cshd_enc_key); 131227730Sraj device_printf(dev, "\t\te_iv_1: 0x%08X\n", cshd->cshd_enc_iv); 132227730Sraj device_printf(dev, "\t\te_iv_2: 0x%08X\n", cshd->cshd_enc_iv_buf); 133227730Sraj device_printf(dev, "\t\tm_src: 0x%08X\n", cshd->cshd_mac_src); 134227730Sraj device_printf(dev, "\t\tm_dst: 0x%08X\n", cshd->cshd_mac_dst); 135227730Sraj device_printf(dev, "\t\tm_dlen: 0x%08X\n", cshd->cshd_mac_dlen); 136227730Sraj device_printf(dev, "\t\tm_tlen: 0x%08X\n", cshd->cshd_mac_total_dlen); 137227730Sraj device_printf(dev, "\t\tm_iv_i: 0x%08X\n", cshd->cshd_mac_iv_in); 138227730Sraj device_printf(dev, "\t\tm_iv_o: 0x%08X\n", cshd->cshd_mac_iv_out); 139227730Sraj#endif 140227730Sraj} 141227730Sraj 142227730Srajstatic void 143227730Srajcesa_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 144227730Sraj{ 145227730Sraj struct cesa_dma_mem *cdm; 146227730Sraj 147227730Sraj if (error) 148227730Sraj return; 149227730Sraj 150227730Sraj KASSERT(nseg == 1, ("Got wrong number of DMA segments, should be 1.")); 151227730Sraj cdm = arg; 152227730Sraj cdm->cdm_paddr = segs->ds_addr; 153227730Sraj} 154227730Sraj 155227730Srajstatic int 156227730Srajcesa_alloc_dma_mem(struct cesa_softc *sc, struct cesa_dma_mem *cdm, 157227730Sraj bus_size_t size) 158227730Sraj{ 159227730Sraj int error; 160227730Sraj 161227730Sraj KASSERT(cdm->cdm_vaddr == NULL, 162227730Sraj ("%s(): DMA memory descriptor in use.", __func__)); 163227730Sraj 164227730Sraj error = bus_dma_tag_create(NULL, /* parent */ 165227730Sraj PAGE_SIZE, 0, /* alignment, boundary */ 166227730Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 167227730Sraj BUS_SPACE_MAXADDR, /* highaddr */ 168227730Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 169227730Sraj size, 1, /* maxsize, nsegments */ 170227730Sraj size, 0, /* maxsegsz, flags */ 171227730Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 172227730Sraj &cdm->cdm_tag); /* dmat */ 173227730Sraj if (error) { 174227730Sraj device_printf(sc->sc_dev, "failed to allocate busdma tag, error" 175227730Sraj " %i!\n", error); 176227730Sraj 177227730Sraj goto err1; 178227730Sraj } 179227730Sraj 180227730Sraj error = bus_dmamem_alloc(cdm->cdm_tag, &cdm->cdm_vaddr, 181227730Sraj BUS_DMA_NOWAIT | BUS_DMA_ZERO, &cdm->cdm_map); 182227730Sraj if (error) { 183227730Sraj device_printf(sc->sc_dev, "failed to allocate DMA safe" 184227730Sraj " memory, error %i!\n", error); 185227730Sraj 186227730Sraj goto err2; 187227730Sraj } 188227730Sraj 189227730Sraj error = bus_dmamap_load(cdm->cdm_tag, cdm->cdm_map, cdm->cdm_vaddr, 190227730Sraj size, cesa_alloc_dma_mem_cb, cdm, BUS_DMA_NOWAIT); 191227730Sraj if (error) { 192227730Sraj device_printf(sc->sc_dev, "cannot get address of the DMA" 193227730Sraj " memory, error %i\n", error); 194227730Sraj 195227730Sraj goto err3; 196227730Sraj } 197227730Sraj 198227730Sraj return (0); 199227730Srajerr3: 200227730Sraj bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 201227730Srajerr2: 202227730Sraj bus_dma_tag_destroy(cdm->cdm_tag); 203227730Srajerr1: 204227730Sraj cdm->cdm_vaddr = NULL; 205227730Sraj return (error); 206227730Sraj} 207227730Sraj 208227730Srajstatic void 209227730Srajcesa_free_dma_mem(struct cesa_dma_mem *cdm) 210227730Sraj{ 211227730Sraj 212227730Sraj bus_dmamap_unload(cdm->cdm_tag, cdm->cdm_map); 213227730Sraj bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 214227730Sraj bus_dma_tag_destroy(cdm->cdm_tag); 215227730Sraj cdm->cdm_vaddr = NULL; 216227730Sraj} 217227730Sraj 218227730Srajstatic void 219227730Srajcesa_sync_dma_mem(struct cesa_dma_mem *cdm, bus_dmasync_op_t op) 220227730Sraj{ 221227730Sraj 222227730Sraj /* Sync only if dma memory is valid */ 223227730Sraj if (cdm->cdm_vaddr != NULL) 224227730Sraj bus_dmamap_sync(cdm->cdm_tag, cdm->cdm_map, op); 225227730Sraj} 226227730Sraj 227227730Srajstatic void 228227730Srajcesa_sync_desc(struct cesa_softc *sc, bus_dmasync_op_t op) 229227730Sraj{ 230227730Sraj 231227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, op); 232227730Sraj cesa_sync_dma_mem(&sc->sc_sdesc_cdm, op); 233227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, op); 234227730Sraj} 235227730Sraj 236227730Srajstatic struct cesa_session * 237227730Srajcesa_alloc_session(struct cesa_softc *sc) 238227730Sraj{ 239227730Sraj struct cesa_session *cs; 240227730Sraj 241227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, cs, sessions); 242227730Sraj 243227730Sraj return (cs); 244227730Sraj} 245227730Sraj 246227730Srajstatic struct cesa_session * 247227730Srajcesa_get_session(struct cesa_softc *sc, uint32_t sid) 248227730Sraj{ 249227730Sraj 250227730Sraj if (sid >= CESA_SESSIONS) 251227730Sraj return (NULL); 252227730Sraj 253227730Sraj return (&sc->sc_sessions[sid]); 254227730Sraj} 255227730Sraj 256227730Srajstatic void 257227730Srajcesa_free_session(struct cesa_softc *sc, struct cesa_session *cs) 258227730Sraj{ 259227730Sraj 260227730Sraj CESA_GENERIC_FREE_LOCKED(sc, cs, sessions); 261227730Sraj} 262227730Sraj 263227730Srajstatic struct cesa_request * 264227730Srajcesa_alloc_request(struct cesa_softc *sc) 265227730Sraj{ 266227730Sraj struct cesa_request *cr; 267227730Sraj 268227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, cr, requests); 269227730Sraj if (!cr) 270227730Sraj return (NULL); 271227730Sraj 272227730Sraj STAILQ_INIT(&cr->cr_tdesc); 273227730Sraj STAILQ_INIT(&cr->cr_sdesc); 274227730Sraj 275227730Sraj return (cr); 276227730Sraj} 277227730Sraj 278227730Srajstatic void 279227730Srajcesa_free_request(struct cesa_softc *sc, struct cesa_request *cr) 280227730Sraj{ 281227730Sraj 282227730Sraj /* Free TDMA descriptors assigned to this request */ 283227730Sraj CESA_LOCK(sc, tdesc); 284227730Sraj STAILQ_CONCAT(&sc->sc_free_tdesc, &cr->cr_tdesc); 285227730Sraj CESA_UNLOCK(sc, tdesc); 286227730Sraj 287227730Sraj /* Free SA descriptors assigned to this request */ 288227730Sraj CESA_LOCK(sc, sdesc); 289227730Sraj STAILQ_CONCAT(&sc->sc_free_sdesc, &cr->cr_sdesc); 290227730Sraj CESA_UNLOCK(sc, sdesc); 291227730Sraj 292227730Sraj /* Unload DMA memory asociated with request */ 293227730Sraj if (cr->cr_dmap_loaded) { 294227730Sraj bus_dmamap_unload(sc->sc_data_dtag, cr->cr_dmap); 295227730Sraj cr->cr_dmap_loaded = 0; 296227730Sraj } 297227730Sraj 298227730Sraj CESA_GENERIC_FREE_LOCKED(sc, cr, requests); 299227730Sraj} 300227730Sraj 301227730Srajstatic void 302227730Srajcesa_enqueue_request(struct cesa_softc *sc, struct cesa_request *cr) 303227730Sraj{ 304227730Sraj 305227730Sraj CESA_LOCK(sc, requests); 306227730Sraj STAILQ_INSERT_TAIL(&sc->sc_ready_requests, cr, cr_stq); 307227730Sraj CESA_UNLOCK(sc, requests); 308227730Sraj} 309227730Sraj 310227730Srajstatic struct cesa_tdma_desc * 311227730Srajcesa_alloc_tdesc(struct cesa_softc *sc) 312227730Sraj{ 313227730Sraj struct cesa_tdma_desc *ctd; 314227730Sraj 315227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, ctd, tdesc); 316227730Sraj 317227730Sraj if (!ctd) 318227730Sraj device_printf(sc->sc_dev, "TDMA descriptors pool exhaused. " 319227730Sraj "Consider increasing CESA_TDMA_DESCRIPTORS.\n"); 320227730Sraj 321227730Sraj return (ctd); 322227730Sraj} 323227730Sraj 324227730Srajstatic struct cesa_sa_desc * 325227730Srajcesa_alloc_sdesc(struct cesa_softc *sc, struct cesa_request *cr) 326227730Sraj{ 327227730Sraj struct cesa_sa_desc *csd; 328227730Sraj 329227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, csd, sdesc); 330227730Sraj if (!csd) { 331227730Sraj device_printf(sc->sc_dev, "SA descriptors pool exhaused. " 332227730Sraj "Consider increasing CESA_SA_DESCRIPTORS.\n"); 333227730Sraj return (NULL); 334227730Sraj } 335227730Sraj 336227730Sraj STAILQ_INSERT_TAIL(&cr->cr_sdesc, csd, csd_stq); 337227730Sraj 338227730Sraj /* Fill-in SA descriptor with default values */ 339227730Sraj csd->csd_cshd->cshd_enc_key = CESA_SA_DATA(csd_key); 340227730Sraj csd->csd_cshd->cshd_enc_iv = CESA_SA_DATA(csd_iv); 341227730Sraj csd->csd_cshd->cshd_enc_iv_buf = CESA_SA_DATA(csd_iv); 342227730Sraj csd->csd_cshd->cshd_enc_src = 0; 343227730Sraj csd->csd_cshd->cshd_enc_dst = 0; 344227730Sraj csd->csd_cshd->cshd_enc_dlen = 0; 345227730Sraj csd->csd_cshd->cshd_mac_dst = CESA_SA_DATA(csd_hash); 346227730Sraj csd->csd_cshd->cshd_mac_iv_in = CESA_SA_DATA(csd_hiv_in); 347227730Sraj csd->csd_cshd->cshd_mac_iv_out = CESA_SA_DATA(csd_hiv_out); 348227730Sraj csd->csd_cshd->cshd_mac_src = 0; 349227730Sraj csd->csd_cshd->cshd_mac_dlen = 0; 350227730Sraj 351227730Sraj return (csd); 352227730Sraj} 353227730Sraj 354227730Srajstatic struct cesa_tdma_desc * 355227730Srajcesa_tdma_copy(struct cesa_softc *sc, bus_addr_t dst, bus_addr_t src, 356227730Sraj bus_size_t size) 357227730Sraj{ 358227730Sraj struct cesa_tdma_desc *ctd; 359227730Sraj 360227730Sraj ctd = cesa_alloc_tdesc(sc); 361227730Sraj if (!ctd) 362227730Sraj return (NULL); 363227730Sraj 364227730Sraj ctd->ctd_cthd->cthd_dst = dst; 365227730Sraj ctd->ctd_cthd->cthd_src = src; 366227730Sraj ctd->ctd_cthd->cthd_byte_count = size; 367227730Sraj 368227730Sraj /* Handle special control packet */ 369227730Sraj if (size != 0) 370227730Sraj ctd->ctd_cthd->cthd_flags = CESA_CTHD_OWNED; 371227730Sraj else 372227730Sraj ctd->ctd_cthd->cthd_flags = 0; 373227730Sraj 374227730Sraj return (ctd); 375227730Sraj} 376227730Sraj 377227730Srajstatic struct cesa_tdma_desc * 378227730Srajcesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 379227730Sraj{ 380227730Sraj 381227730Sraj return (cesa_tdma_copy(sc, sc->sc_sram_base + 382227730Sraj sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr, 383227730Sraj sizeof(struct cesa_sa_data))); 384227730Sraj} 385227730Sraj 386227730Srajstatic struct cesa_tdma_desc * 387227730Srajcesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 388227730Sraj{ 389227730Sraj 390227730Sraj return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base + 391227730Sraj sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data))); 392227730Sraj} 393227730Sraj 394227730Srajstatic struct cesa_tdma_desc * 395227730Srajcesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd) 396227730Sraj{ 397227730Sraj 398227730Sraj return (cesa_tdma_copy(sc, sc->sc_sram_base, csd->csd_cshd_paddr, 399227730Sraj sizeof(struct cesa_sa_hdesc))); 400227730Sraj} 401227730Sraj 402227730Srajstatic void 403227730Srajcesa_append_tdesc(struct cesa_request *cr, struct cesa_tdma_desc *ctd) 404227730Sraj{ 405227730Sraj struct cesa_tdma_desc *ctd_prev; 406227730Sraj 407227730Sraj if (!STAILQ_EMPTY(&cr->cr_tdesc)) { 408227730Sraj ctd_prev = STAILQ_LAST(&cr->cr_tdesc, cesa_tdma_desc, ctd_stq); 409227730Sraj ctd_prev->ctd_cthd->cthd_next = ctd->ctd_cthd_paddr; 410227730Sraj } 411227730Sraj 412227730Sraj ctd->ctd_cthd->cthd_next = 0; 413227730Sraj STAILQ_INSERT_TAIL(&cr->cr_tdesc, ctd, ctd_stq); 414227730Sraj} 415227730Sraj 416227730Srajstatic int 417227730Srajcesa_append_packet(struct cesa_softc *sc, struct cesa_request *cr, 418227730Sraj struct cesa_packet *cp, struct cesa_sa_desc *csd) 419227730Sraj{ 420227730Sraj struct cesa_tdma_desc *ctd, *tmp; 421227730Sraj 422227730Sraj /* Copy SA descriptor for this packet */ 423227730Sraj ctd = cesa_tdma_copy_sdesc(sc, csd); 424227730Sraj if (!ctd) 425227730Sraj return (ENOMEM); 426227730Sraj 427227730Sraj cesa_append_tdesc(cr, ctd); 428227730Sraj 429227730Sraj /* Copy data to be processed */ 430227730Sraj STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyin, ctd_stq, tmp) 431227730Sraj cesa_append_tdesc(cr, ctd); 432227730Sraj STAILQ_INIT(&cp->cp_copyin); 433227730Sraj 434227730Sraj /* Insert control descriptor */ 435227730Sraj ctd = cesa_tdma_copy(sc, 0, 0, 0); 436227730Sraj if (!ctd) 437227730Sraj return (ENOMEM); 438227730Sraj 439227730Sraj cesa_append_tdesc(cr, ctd); 440227730Sraj 441227730Sraj /* Copy back results */ 442227730Sraj STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyout, ctd_stq, tmp) 443227730Sraj cesa_append_tdesc(cr, ctd); 444227730Sraj STAILQ_INIT(&cp->cp_copyout); 445227730Sraj 446227730Sraj return (0); 447227730Sraj} 448227730Sraj 449227730Srajstatic int 450227730Srajcesa_set_mkey(struct cesa_session *cs, int alg, const uint8_t *mkey, int mklen) 451227730Sraj{ 452227730Sraj uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN]; 453227730Sraj uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN]; 454227730Sraj SHA1_CTX sha1ctx; 455227730Sraj MD5_CTX md5ctx; 456227730Sraj uint32_t *hout; 457227730Sraj uint32_t *hin; 458227730Sraj int i; 459227730Sraj 460227730Sraj memset(ipad, HMAC_IPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 461227730Sraj memset(opad, HMAC_OPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 462227730Sraj for (i = 0; i < mklen; i++) { 463227730Sraj ipad[i] ^= mkey[i]; 464227730Sraj opad[i] ^= mkey[i]; 465227730Sraj } 466227730Sraj 467227730Sraj hin = (uint32_t *)cs->cs_hiv_in; 468227730Sraj hout = (uint32_t *)cs->cs_hiv_out; 469227730Sraj 470227730Sraj switch (alg) { 471227730Sraj case CRYPTO_MD5_HMAC: 472227730Sraj MD5Init(&md5ctx); 473227730Sraj MD5Update(&md5ctx, ipad, MD5_HMAC_BLOCK_LEN); 474227730Sraj memcpy(hin, md5ctx.state, sizeof(md5ctx.state)); 475227730Sraj MD5Init(&md5ctx); 476227730Sraj MD5Update(&md5ctx, opad, MD5_HMAC_BLOCK_LEN); 477227730Sraj memcpy(hout, md5ctx.state, sizeof(md5ctx.state)); 478227730Sraj break; 479227730Sraj case CRYPTO_SHA1_HMAC: 480227730Sraj SHA1Init(&sha1ctx); 481227730Sraj SHA1Update(&sha1ctx, ipad, SHA1_HMAC_BLOCK_LEN); 482227730Sraj memcpy(hin, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 483227730Sraj SHA1Init(&sha1ctx); 484227730Sraj SHA1Update(&sha1ctx, opad, SHA1_HMAC_BLOCK_LEN); 485227730Sraj memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 486227730Sraj break; 487227730Sraj default: 488227730Sraj return (EINVAL); 489227730Sraj } 490227730Sraj 491227730Sraj for (i = 0; i < CESA_MAX_HASH_LEN / sizeof(uint32_t); i++) { 492227730Sraj hin[i] = htobe32(hin[i]); 493227730Sraj hout[i] = htobe32(hout[i]); 494227730Sraj } 495227730Sraj 496227730Sraj return (0); 497227730Sraj} 498227730Sraj 499227730Srajstatic int 500227730Srajcesa_prep_aes_key(struct cesa_session *cs) 501227730Sraj{ 502227730Sraj uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 503227730Sraj uint32_t *dkey; 504227730Sraj int i; 505227730Sraj 506227730Sraj rijndaelKeySetupEnc(ek, cs->cs_key, cs->cs_klen * 8); 507227730Sraj 508227730Sraj cs->cs_config &= ~CESA_CSH_AES_KLEN_MASK; 509227730Sraj dkey = (uint32_t *)cs->cs_aes_dkey; 510227730Sraj 511227730Sraj switch (cs->cs_klen) { 512227730Sraj case 16: 513227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_128; 514227730Sraj for (i = 0; i < 4; i++) 515227730Sraj *dkey++ = htobe32(ek[4 * 10 + i]); 516227730Sraj break; 517227730Sraj case 24: 518227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_192; 519227730Sraj for (i = 0; i < 4; i++) 520227730Sraj *dkey++ = htobe32(ek[4 * 12 + i]); 521227730Sraj for (i = 0; i < 2; i++) 522227730Sraj *dkey++ = htobe32(ek[4 * 11 + 2 + i]); 523227730Sraj break; 524227730Sraj case 32: 525227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_256; 526227730Sraj for (i = 0; i < 4; i++) 527227730Sraj *dkey++ = htobe32(ek[4 * 14 + i]); 528227730Sraj for (i = 0; i < 4; i++) 529227730Sraj *dkey++ = htobe32(ek[4 * 13 + i]); 530227730Sraj break; 531227730Sraj default: 532227730Sraj return (EINVAL); 533227730Sraj } 534227730Sraj 535227730Sraj return (0); 536227730Sraj} 537227730Sraj 538227730Srajstatic int 539227730Srajcesa_is_hash(int alg) 540227730Sraj{ 541227730Sraj 542227730Sraj switch (alg) { 543227730Sraj case CRYPTO_MD5: 544227730Sraj case CRYPTO_MD5_HMAC: 545227730Sraj case CRYPTO_SHA1: 546227730Sraj case CRYPTO_SHA1_HMAC: 547227730Sraj return (1); 548227730Sraj default: 549227730Sraj return (0); 550227730Sraj } 551227730Sraj} 552227730Sraj 553227730Srajstatic void 554227730Srajcesa_start_packet(struct cesa_packet *cp, unsigned int size) 555227730Sraj{ 556227730Sraj 557227730Sraj cp->cp_size = size; 558227730Sraj cp->cp_offset = 0; 559227730Sraj STAILQ_INIT(&cp->cp_copyin); 560227730Sraj STAILQ_INIT(&cp->cp_copyout); 561227730Sraj} 562227730Sraj 563227730Srajstatic int 564227730Srajcesa_fill_packet(struct cesa_softc *sc, struct cesa_packet *cp, 565227730Sraj bus_dma_segment_t *seg) 566227730Sraj{ 567227730Sraj struct cesa_tdma_desc *ctd; 568227730Sraj unsigned int bsize; 569227730Sraj 570227730Sraj /* Calculate size of block copy */ 571227730Sraj bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset); 572227730Sraj 573227730Sraj if (bsize > 0) { 574227730Sraj ctd = cesa_tdma_copy(sc, sc->sc_sram_base + 575227730Sraj CESA_DATA(cp->cp_offset), seg->ds_addr, bsize); 576227730Sraj if (!ctd) 577227730Sraj return (-ENOMEM); 578227730Sraj 579227730Sraj STAILQ_INSERT_TAIL(&cp->cp_copyin, ctd, ctd_stq); 580227730Sraj 581227730Sraj ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base + 582227730Sraj CESA_DATA(cp->cp_offset), bsize); 583227730Sraj if (!ctd) 584227730Sraj return (-ENOMEM); 585227730Sraj 586227730Sraj STAILQ_INSERT_TAIL(&cp->cp_copyout, ctd, ctd_stq); 587227730Sraj 588227730Sraj seg->ds_len -= bsize; 589227730Sraj seg->ds_addr += bsize; 590227730Sraj cp->cp_offset += bsize; 591227730Sraj } 592227730Sraj 593227730Sraj return (bsize); 594227730Sraj} 595227730Sraj 596227730Srajstatic void 597227730Srajcesa_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 598227730Sraj{ 599227730Sraj unsigned int mpsize, fragmented; 600227730Sraj unsigned int mlen, mskip, tmlen; 601227730Sraj struct cesa_chain_info *cci; 602227730Sraj unsigned int elen, eskip; 603227730Sraj unsigned int skip, len; 604227730Sraj struct cesa_sa_desc *csd; 605227730Sraj struct cesa_request *cr; 606227730Sraj struct cesa_softc *sc; 607227730Sraj struct cesa_packet cp; 608227730Sraj bus_dma_segment_t seg; 609227730Sraj uint32_t config; 610227730Sraj int size; 611227730Sraj 612227730Sraj cci = arg; 613227730Sraj sc = cci->cci_sc; 614227730Sraj cr = cci->cci_cr; 615227730Sraj 616227730Sraj if (error) { 617227730Sraj cci->cci_error = error; 618227730Sraj return; 619227730Sraj } 620227730Sraj 621227730Sraj elen = cci->cci_enc ? cci->cci_enc->crd_len : 0; 622227730Sraj eskip = cci->cci_enc ? cci->cci_enc->crd_skip : 0; 623227730Sraj mlen = cci->cci_mac ? cci->cci_mac->crd_len : 0; 624227730Sraj mskip = cci->cci_mac ? cci->cci_mac->crd_skip : 0; 625227730Sraj 626227730Sraj if (elen && mlen && 627227730Sraj ((eskip > mskip && ((eskip - mskip) & (cr->cr_cs->cs_ivlen - 1))) || 628227730Sraj (mskip > eskip && ((mskip - eskip) & (cr->cr_cs->cs_mblen - 1))) || 629227730Sraj (eskip > (mskip + mlen)) || (mskip > (eskip + elen)))) { 630227730Sraj /* 631227730Sraj * Data alignment in the request does not meet CESA requiremnts 632227730Sraj * for combined encryption/decryption and hashing. We have to 633227730Sraj * split the request to separate operations and process them 634227730Sraj * one by one. 635227730Sraj */ 636227730Sraj config = cci->cci_config; 637227730Sraj if ((config & CESA_CSHD_OP_MASK) == CESA_CSHD_MAC_AND_ENC) { 638227730Sraj config &= ~CESA_CSHD_OP_MASK; 639227730Sraj 640227730Sraj cci->cci_config = config | CESA_CSHD_MAC; 641227730Sraj cci->cci_enc = NULL; 642227730Sraj cci->cci_mac = cr->cr_mac; 643227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 644227730Sraj 645227730Sraj cci->cci_config = config | CESA_CSHD_ENC; 646227730Sraj cci->cci_enc = cr->cr_enc; 647227730Sraj cci->cci_mac = NULL; 648227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 649227730Sraj } else { 650227730Sraj config &= ~CESA_CSHD_OP_MASK; 651227730Sraj 652227730Sraj cci->cci_config = config | CESA_CSHD_ENC; 653227730Sraj cci->cci_enc = cr->cr_enc; 654227730Sraj cci->cci_mac = NULL; 655227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 656227730Sraj 657227730Sraj cci->cci_config = config | CESA_CSHD_MAC; 658227730Sraj cci->cci_enc = NULL; 659227730Sraj cci->cci_mac = cr->cr_mac; 660227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 661227730Sraj } 662227730Sraj 663227730Sraj return; 664227730Sraj } 665227730Sraj 666227730Sraj tmlen = mlen; 667227730Sraj fragmented = 0; 668227730Sraj mpsize = CESA_MAX_PACKET_SIZE; 669227730Sraj mpsize &= ~((cr->cr_cs->cs_ivlen - 1) | (cr->cr_cs->cs_mblen - 1)); 670227730Sraj 671227730Sraj if (elen && mlen) { 672227730Sraj skip = MIN(eskip, mskip); 673227730Sraj len = MAX(elen + eskip, mlen + mskip) - skip; 674227730Sraj } else if (elen) { 675227730Sraj skip = eskip; 676227730Sraj len = elen; 677227730Sraj } else { 678227730Sraj skip = mskip; 679227730Sraj len = mlen; 680227730Sraj } 681227730Sraj 682227730Sraj /* Start first packet in chain */ 683227730Sraj cesa_start_packet(&cp, MIN(mpsize, len)); 684227730Sraj 685227730Sraj while (nseg-- && len > 0) { 686227730Sraj seg = *(segs++); 687227730Sraj 688227730Sraj /* 689227730Sraj * Skip data in buffer on which neither ENC nor MAC operation 690227730Sraj * is requested. 691227730Sraj */ 692227730Sraj if (skip > 0) { 693227730Sraj size = MIN(skip, seg.ds_len); 694227730Sraj skip -= size; 695227730Sraj 696227730Sraj seg.ds_addr += size; 697227730Sraj seg.ds_len -= size; 698227730Sraj 699227730Sraj if (eskip > 0) 700227730Sraj eskip -= size; 701227730Sraj 702227730Sraj if (mskip > 0) 703227730Sraj mskip -= size; 704227730Sraj 705227730Sraj if (seg.ds_len == 0) 706227730Sraj continue; 707227730Sraj } 708227730Sraj 709227730Sraj while (1) { 710227730Sraj /* 711227730Sraj * Fill in current packet with data. Break if there is 712227730Sraj * no more data in current DMA segment or an error 713227730Sraj * occured. 714227730Sraj */ 715227730Sraj size = cesa_fill_packet(sc, &cp, &seg); 716227730Sraj if (size <= 0) { 717227730Sraj error = -size; 718227730Sraj break; 719227730Sraj } 720227730Sraj 721227730Sraj len -= size; 722227730Sraj 723227730Sraj /* If packet is full, append it to the chain */ 724227730Sraj if (cp.cp_size == cp.cp_offset) { 725227730Sraj csd = cesa_alloc_sdesc(sc, cr); 726227730Sraj if (!csd) { 727227730Sraj error = ENOMEM; 728227730Sraj break; 729227730Sraj } 730227730Sraj 731227730Sraj /* Create SA descriptor for this packet */ 732227730Sraj csd->csd_cshd->cshd_config = cci->cci_config; 733227730Sraj csd->csd_cshd->cshd_mac_total_dlen = tmlen; 734227730Sraj 735227730Sraj /* 736227730Sraj * Enable fragmentation if request will not fit 737227730Sraj * into one packet. 738227730Sraj */ 739227730Sraj if (len > 0) { 740227730Sraj if (!fragmented) { 741227730Sraj fragmented = 1; 742227730Sraj csd->csd_cshd->cshd_config |= 743227730Sraj CESA_CSHD_FRAG_FIRST; 744227730Sraj } else 745227730Sraj csd->csd_cshd->cshd_config |= 746227730Sraj CESA_CSHD_FRAG_MIDDLE; 747227730Sraj } else if (fragmented) 748227730Sraj csd->csd_cshd->cshd_config |= 749227730Sraj CESA_CSHD_FRAG_LAST; 750227730Sraj 751227730Sraj if (eskip < cp.cp_size && elen > 0) { 752227730Sraj csd->csd_cshd->cshd_enc_src = 753227730Sraj CESA_DATA(eskip); 754227730Sraj csd->csd_cshd->cshd_enc_dst = 755227730Sraj CESA_DATA(eskip); 756227730Sraj csd->csd_cshd->cshd_enc_dlen = 757227730Sraj MIN(elen, cp.cp_size - eskip); 758227730Sraj } 759227730Sraj 760227730Sraj if (mskip < cp.cp_size && mlen > 0) { 761227730Sraj csd->csd_cshd->cshd_mac_src = 762227730Sraj CESA_DATA(mskip); 763227730Sraj csd->csd_cshd->cshd_mac_dlen = 764227730Sraj MIN(mlen, cp.cp_size - mskip); 765227730Sraj } 766227730Sraj 767227730Sraj elen -= csd->csd_cshd->cshd_enc_dlen; 768227730Sraj eskip -= MIN(eskip, cp.cp_size); 769227730Sraj mlen -= csd->csd_cshd->cshd_mac_dlen; 770227730Sraj mskip -= MIN(mskip, cp.cp_size); 771227730Sraj 772227730Sraj cesa_dump_cshd(sc, csd->csd_cshd); 773227730Sraj 774227730Sraj /* Append packet to the request */ 775227730Sraj error = cesa_append_packet(sc, cr, &cp, csd); 776227730Sraj if (error) 777227730Sraj break; 778227730Sraj 779227730Sraj /* Start a new packet, as current is full */ 780227730Sraj cesa_start_packet(&cp, MIN(mpsize, len)); 781227730Sraj } 782227730Sraj } 783227730Sraj 784227730Sraj if (error) 785227730Sraj break; 786227730Sraj } 787227730Sraj 788227730Sraj if (error) { 789227730Sraj /* 790227730Sraj * Move all allocated resources to the request. They will be 791227730Sraj * freed later. 792227730Sraj */ 793227730Sraj STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyin); 794227730Sraj STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyout); 795227730Sraj cci->cci_error = error; 796227730Sraj } 797227730Sraj} 798227730Sraj 799227730Srajstatic void 800227730Srajcesa_create_chain_cb2(void *arg, bus_dma_segment_t *segs, int nseg, 801227730Sraj bus_size_t size, int error) 802227730Sraj{ 803227730Sraj 804227730Sraj cesa_create_chain_cb(arg, segs, nseg, error); 805227730Sraj} 806227730Sraj 807227730Srajstatic int 808227730Srajcesa_create_chain(struct cesa_softc *sc, struct cesa_request *cr) 809227730Sraj{ 810227730Sraj struct cesa_chain_info cci; 811227730Sraj struct cesa_tdma_desc *ctd; 812227730Sraj uint32_t config; 813227730Sraj int error; 814227730Sraj 815227730Sraj error = 0; 816227730Sraj CESA_LOCK_ASSERT(sc, sessions); 817227730Sraj 818227730Sraj /* Create request metadata */ 819227730Sraj if (cr->cr_enc) { 820227730Sraj if (cr->cr_enc->crd_alg == CRYPTO_AES_CBC && 821227730Sraj (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 822227730Sraj memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_aes_dkey, 823227730Sraj cr->cr_cs->cs_klen); 824227730Sraj else 825227730Sraj memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_key, 826227730Sraj cr->cr_cs->cs_klen); 827227730Sraj } 828227730Sraj 829227730Sraj if (cr->cr_mac) { 830227730Sraj memcpy(cr->cr_csd->csd_hiv_in, cr->cr_cs->cs_hiv_in, 831227730Sraj CESA_MAX_HASH_LEN); 832227730Sraj memcpy(cr->cr_csd->csd_hiv_out, cr->cr_cs->cs_hiv_out, 833227730Sraj CESA_MAX_HASH_LEN); 834227730Sraj } 835227730Sraj 836227730Sraj ctd = cesa_tdma_copyin_sa_data(sc, cr); 837227730Sraj if (!ctd) 838227730Sraj return (ENOMEM); 839227730Sraj 840227730Sraj cesa_append_tdesc(cr, ctd); 841227730Sraj 842227730Sraj /* Prepare SA configuration */ 843227730Sraj config = cr->cr_cs->cs_config; 844227730Sraj 845227730Sraj if (cr->cr_enc && (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 846227730Sraj config |= CESA_CSHD_DECRYPT; 847227730Sraj if (cr->cr_enc && !cr->cr_mac) 848227730Sraj config |= CESA_CSHD_ENC; 849227730Sraj if (!cr->cr_enc && cr->cr_mac) 850227730Sraj config |= CESA_CSHD_MAC; 851227730Sraj if (cr->cr_enc && cr->cr_mac) 852227730Sraj config |= (config & CESA_CSHD_DECRYPT) ? CESA_CSHD_MAC_AND_ENC : 853227730Sraj CESA_CSHD_ENC_AND_MAC; 854227730Sraj 855227730Sraj /* Create data packets */ 856227730Sraj cci.cci_sc = sc; 857227730Sraj cci.cci_cr = cr; 858227730Sraj cci.cci_enc = cr->cr_enc; 859227730Sraj cci.cci_mac = cr->cr_mac; 860227730Sraj cci.cci_config = config; 861227730Sraj cci.cci_error = 0; 862227730Sraj 863227730Sraj if (cr->cr_crp->crp_flags & CRYPTO_F_IOV) 864227730Sraj error = bus_dmamap_load_uio(sc->sc_data_dtag, 865227730Sraj cr->cr_dmap, (struct uio *)cr->cr_crp->crp_buf, 866227730Sraj cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 867227730Sraj else if (cr->cr_crp->crp_flags & CRYPTO_F_IMBUF) 868227730Sraj error = bus_dmamap_load_mbuf(sc->sc_data_dtag, 869227730Sraj cr->cr_dmap, (struct mbuf *)cr->cr_crp->crp_buf, 870227730Sraj cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 871227730Sraj else 872227730Sraj error = bus_dmamap_load(sc->sc_data_dtag, 873227730Sraj cr->cr_dmap, cr->cr_crp->crp_buf, 874227730Sraj cr->cr_crp->crp_ilen, cesa_create_chain_cb, &cci, 875227730Sraj BUS_DMA_NOWAIT); 876227730Sraj 877227730Sraj if (!error) 878227730Sraj cr->cr_dmap_loaded = 1; 879227730Sraj 880227730Sraj if (cci.cci_error) 881227730Sraj error = cci.cci_error; 882227730Sraj 883227730Sraj if (error) 884227730Sraj return (error); 885227730Sraj 886227730Sraj /* Read back request metadata */ 887227730Sraj ctd = cesa_tdma_copyout_sa_data(sc, cr); 888227730Sraj if (!ctd) 889227730Sraj return (ENOMEM); 890227730Sraj 891227730Sraj cesa_append_tdesc(cr, ctd); 892227730Sraj 893227730Sraj return (0); 894227730Sraj} 895227730Sraj 896227730Srajstatic void 897227730Srajcesa_execute(struct cesa_softc *sc) 898227730Sraj{ 899227730Sraj struct cesa_tdma_desc *prev_ctd, *ctd; 900227730Sraj struct cesa_request *prev_cr, *cr; 901227730Sraj 902227730Sraj CESA_LOCK(sc, requests); 903227730Sraj 904227730Sraj /* 905227730Sraj * If ready list is empty, there is nothing to execute. If queued list 906227730Sraj * is not empty, the hardware is busy and we cannot start another 907227730Sraj * execution. 908227730Sraj */ 909227730Sraj if (STAILQ_EMPTY(&sc->sc_ready_requests) || 910227730Sraj !STAILQ_EMPTY(&sc->sc_queued_requests)) { 911227730Sraj CESA_UNLOCK(sc, requests); 912227730Sraj return; 913227730Sraj } 914227730Sraj 915227730Sraj /* Move all ready requests to queued list */ 916227730Sraj STAILQ_CONCAT(&sc->sc_queued_requests, &sc->sc_ready_requests); 917227730Sraj STAILQ_INIT(&sc->sc_ready_requests); 918227730Sraj 919227730Sraj /* Create one execution chain from all requests on the list */ 920227730Sraj if (STAILQ_FIRST(&sc->sc_queued_requests) != 921227730Sraj STAILQ_LAST(&sc->sc_queued_requests, cesa_request, cr_stq)) { 922227730Sraj prev_cr = NULL; 923227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_POSTREAD | 924227730Sraj BUS_DMASYNC_POSTWRITE); 925227730Sraj 926227730Sraj STAILQ_FOREACH(cr, &sc->sc_queued_requests, cr_stq) { 927227730Sraj if (prev_cr) { 928227730Sraj ctd = STAILQ_FIRST(&cr->cr_tdesc); 929227730Sraj prev_ctd = STAILQ_LAST(&prev_cr->cr_tdesc, 930227730Sraj cesa_tdma_desc, ctd_stq); 931227730Sraj 932227730Sraj prev_ctd->ctd_cthd->cthd_next = 933227730Sraj ctd->ctd_cthd_paddr; 934227730Sraj } 935227730Sraj 936227730Sraj prev_cr = cr; 937227730Sraj } 938227730Sraj 939227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_PREREAD | 940227730Sraj BUS_DMASYNC_PREWRITE); 941227730Sraj } 942227730Sraj 943227730Sraj /* Start chain execution in hardware */ 944227730Sraj cr = STAILQ_FIRST(&sc->sc_queued_requests); 945227730Sraj ctd = STAILQ_FIRST(&cr->cr_tdesc); 946227730Sraj 947227730Sraj CESA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr); 948227730Sraj CESA_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE); 949227730Sraj 950227730Sraj CESA_UNLOCK(sc, requests); 951227730Sraj} 952227730Sraj 953227730Srajstatic int 954227730Srajcesa_setup_sram(struct cesa_softc *sc) 955227730Sraj{ 956227730Sraj phandle_t sram_node; 957227730Sraj ihandle_t sram_ihandle; 958227730Sraj pcell_t sram_handle, sram_reg; 959227730Sraj 960227730Sraj if (OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle", 961227730Sraj (void *)&sram_handle, sizeof(sram_handle)) <= 0) 962227730Sraj return (ENXIO); 963227730Sraj 964227730Sraj sram_ihandle = (ihandle_t)sram_handle; 965227730Sraj sram_ihandle = fdt32_to_cpu(sram_ihandle); 966227730Sraj sram_node = OF_instance_to_package(sram_ihandle); 967227730Sraj 968227730Sraj if (OF_getprop(sram_node, "reg", (void *)&sram_reg, 969227730Sraj sizeof(sram_reg)) <= 0) 970227730Sraj return (ENXIO); 971227730Sraj 972227730Sraj sc->sc_sram_base = fdt32_to_cpu(sram_reg); 973227730Sraj 974227730Sraj return (0); 975227730Sraj} 976227730Sraj 977227730Srajstatic int 978227730Srajcesa_probe(device_t dev) 979227730Sraj{ 980227730Sraj if (!ofw_bus_is_compatible(dev, "mrvl,cesa")) 981227730Sraj return (ENXIO); 982227730Sraj 983227730Sraj device_set_desc(dev, "Marvell Cryptographic Engine and Security " 984227730Sraj "Accelerator"); 985227730Sraj 986227730Sraj return (BUS_PROBE_DEFAULT); 987227730Sraj} 988227730Sraj 989227730Srajstatic int 990227730Srajcesa_attach(device_t dev) 991227730Sraj{ 992227730Sraj struct cesa_softc *sc; 993227730Sraj uint32_t d, r; 994227730Sraj int error; 995227730Sraj int i; 996227730Sraj 997227730Sraj sc = device_get_softc(dev); 998227730Sraj sc->sc_blocked = 0; 999227730Sraj sc->sc_error = 0; 1000227730Sraj sc->sc_dev = dev; 1001227730Sraj 1002227730Sraj error = cesa_setup_sram(sc); 1003227730Sraj if (error) { 1004227730Sraj device_printf(dev, "could not setup SRAM\n"); 1005227730Sraj return (error); 1006227730Sraj } 1007227730Sraj 1008227730Sraj soc_id(&d, &r); 1009227730Sraj 1010227730Sraj switch (d) { 1011227730Sraj case MV_DEV_88F6281: 1012227730Sraj sc->sc_tperr = 0; 1013227730Sraj break; 1014227730Sraj case MV_DEV_MV78100: 1015227730Sraj case MV_DEV_MV78100_Z0: 1016227730Sraj sc->sc_tperr = CESA_ICR_TPERR; 1017227730Sraj break; 1018227730Sraj default: 1019227730Sraj return (ENXIO); 1020227730Sraj } 1021227730Sraj 1022227730Sraj /* Initialize mutexes */ 1023227730Sraj mtx_init(&sc->sc_sc_lock, device_get_nameunit(dev), 1024227730Sraj "CESA Shared Data", MTX_DEF); 1025227730Sraj mtx_init(&sc->sc_tdesc_lock, device_get_nameunit(dev), 1026227730Sraj "CESA TDMA Descriptors Pool", MTX_DEF); 1027227730Sraj mtx_init(&sc->sc_sdesc_lock, device_get_nameunit(dev), 1028227730Sraj "CESA SA Descriptors Pool", MTX_DEF); 1029227730Sraj mtx_init(&sc->sc_requests_lock, device_get_nameunit(dev), 1030227730Sraj "CESA Requests Pool", MTX_DEF); 1031227730Sraj mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev), 1032227730Sraj "CESA Sessions Pool", MTX_DEF); 1033227730Sraj 1034227730Sraj /* Allocate I/O and IRQ resources */ 1035227730Sraj error = bus_alloc_resources(dev, cesa_res_spec, sc->sc_res); 1036227730Sraj if (error) { 1037227730Sraj device_printf(dev, "could not allocate resources\n"); 1038227730Sraj goto err0; 1039227730Sraj } 1040227730Sraj 1041227730Sraj sc->sc_bsh = rman_get_bushandle(*(sc->sc_res)); 1042227730Sraj sc->sc_bst = rman_get_bustag(*(sc->sc_res)); 1043227730Sraj 1044227730Sraj /* Setup interrupt handler */ 1045227730Sraj error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1046227730Sraj NULL, cesa_intr, sc, &(sc->sc_icookie)); 1047227730Sraj if (error) { 1048227730Sraj device_printf(dev, "could not setup engine completion irq\n"); 1049227730Sraj goto err1; 1050227730Sraj } 1051227730Sraj 1052227730Sraj /* Create DMA tag for processed data */ 1053227730Sraj error = bus_dma_tag_create(NULL, /* parent */ 1054227730Sraj 1, 0, /* alignment, boundary */ 1055227730Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1056227730Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1057227730Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1058227730Sraj CESA_MAX_REQUEST_SIZE, /* maxsize */ 1059227730Sraj CESA_MAX_FRAGMENTS, /* nsegments */ 1060227730Sraj CESA_MAX_REQUEST_SIZE, 0, /* maxsegsz, flags */ 1061227730Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1062227730Sraj &sc->sc_data_dtag); /* dmat */ 1063227730Sraj if (error) 1064227730Sraj goto err2; 1065227730Sraj 1066227730Sraj /* Initialize data structures: TDMA Descriptors Pool */ 1067227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_tdesc_cdm, 1068227730Sraj CESA_TDMA_DESCRIPTORS * sizeof(struct cesa_tdma_hdesc)); 1069227730Sraj if (error) 1070227730Sraj goto err3; 1071227730Sraj 1072227730Sraj STAILQ_INIT(&sc->sc_free_tdesc); 1073227730Sraj for (i = 0; i < CESA_TDMA_DESCRIPTORS; i++) { 1074227730Sraj sc->sc_tdesc[i].ctd_cthd = 1075227730Sraj (struct cesa_tdma_hdesc *)(sc->sc_tdesc_cdm.cdm_vaddr) + i; 1076227730Sraj sc->sc_tdesc[i].ctd_cthd_paddr = sc->sc_tdesc_cdm.cdm_paddr + 1077227730Sraj (i * sizeof(struct cesa_tdma_hdesc)); 1078227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_tdesc, &sc->sc_tdesc[i], 1079227730Sraj ctd_stq); 1080227730Sraj } 1081227730Sraj 1082227730Sraj /* Initialize data structures: SA Descriptors Pool */ 1083227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_sdesc_cdm, 1084227730Sraj CESA_SA_DESCRIPTORS * sizeof(struct cesa_sa_hdesc)); 1085227730Sraj if (error) 1086227730Sraj goto err4; 1087227730Sraj 1088227730Sraj STAILQ_INIT(&sc->sc_free_sdesc); 1089227730Sraj for (i = 0; i < CESA_SA_DESCRIPTORS; i++) { 1090227730Sraj sc->sc_sdesc[i].csd_cshd = 1091227730Sraj (struct cesa_sa_hdesc *)(sc->sc_sdesc_cdm.cdm_vaddr) + i; 1092227730Sraj sc->sc_sdesc[i].csd_cshd_paddr = sc->sc_sdesc_cdm.cdm_paddr + 1093227730Sraj (i * sizeof(struct cesa_sa_hdesc)); 1094227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_sdesc, &sc->sc_sdesc[i], 1095227730Sraj csd_stq); 1096227730Sraj } 1097227730Sraj 1098227730Sraj /* Initialize data structures: Requests Pool */ 1099227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_requests_cdm, 1100227730Sraj CESA_REQUESTS * sizeof(struct cesa_sa_data)); 1101227730Sraj if (error) 1102227730Sraj goto err5; 1103227730Sraj 1104227730Sraj STAILQ_INIT(&sc->sc_free_requests); 1105227730Sraj STAILQ_INIT(&sc->sc_ready_requests); 1106227730Sraj STAILQ_INIT(&sc->sc_queued_requests); 1107227730Sraj for (i = 0; i < CESA_REQUESTS; i++) { 1108227730Sraj sc->sc_requests[i].cr_csd = 1109227730Sraj (struct cesa_sa_data *)(sc->sc_requests_cdm.cdm_vaddr) + i; 1110227730Sraj sc->sc_requests[i].cr_csd_paddr = 1111227730Sraj sc->sc_requests_cdm.cdm_paddr + 1112227730Sraj (i * sizeof(struct cesa_sa_data)); 1113227730Sraj 1114227730Sraj /* Preallocate DMA maps */ 1115227730Sraj error = bus_dmamap_create(sc->sc_data_dtag, 0, 1116227730Sraj &sc->sc_requests[i].cr_dmap); 1117227730Sraj if (error && i > 0) { 1118227730Sraj i--; 1119227730Sraj do { 1120227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1121227730Sraj sc->sc_requests[i].cr_dmap); 1122227730Sraj } while (i--); 1123227730Sraj 1124227730Sraj goto err6; 1125227730Sraj } 1126227730Sraj 1127227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_requests, &sc->sc_requests[i], 1128227730Sraj cr_stq); 1129227730Sraj } 1130227730Sraj 1131227730Sraj /* Initialize data structures: Sessions Pool */ 1132227730Sraj STAILQ_INIT(&sc->sc_free_sessions); 1133227730Sraj for (i = 0; i < CESA_SESSIONS; i++) { 1134227730Sraj sc->sc_sessions[i].cs_sid = i; 1135227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_sessions, &sc->sc_sessions[i], 1136227730Sraj cs_stq); 1137227730Sraj } 1138227730Sraj 1139227730Sraj /* 1140227730Sraj * Initialize TDMA: 1141227730Sraj * - Burst limit: 128 bytes, 1142227730Sraj * - Outstanding reads enabled, 1143227730Sraj * - No byte-swap. 1144227730Sraj */ 1145227730Sraj CESA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 | CESA_TDMA_CR_SBL128 | 1146227730Sraj CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | CESA_TDMA_CR_ENABLE); 1147227730Sraj 1148227730Sraj /* 1149227730Sraj * Initialize SA: 1150227730Sraj * - SA descriptor is present at beginning of CESA SRAM, 1151227730Sraj * - Multi-packet chain mode, 1152227730Sraj * - Cooperation with TDMA enabled. 1153227730Sraj */ 1154227730Sraj CESA_WRITE(sc, CESA_SA_DPR, 0); 1155227730Sraj CESA_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA | 1156227730Sraj CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE); 1157227730Sraj 1158227730Sraj /* Unmask interrupts */ 1159227730Sraj CESA_WRITE(sc, CESA_ICR, 0); 1160227730Sraj CESA_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr); 1161227730Sraj CESA_WRITE(sc, CESA_TDMA_ECR, 0); 1162227730Sraj CESA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS | 1163227730Sraj CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT | 1164227730Sraj CESA_TDMA_EMR_DATA_ERROR); 1165227730Sraj 1166227730Sraj /* Register in OCF */ 1167227730Sraj sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1168227730Sraj if (sc->sc_cid) { 1169227730Sraj device_printf(dev, "could not get crypto driver id\n"); 1170227730Sraj goto err7; 1171227730Sraj } 1172227730Sraj 1173227730Sraj crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 1174227730Sraj crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 1175227730Sraj crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 1176227730Sraj crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 1177227730Sraj crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 1178227730Sraj crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 1179227730Sraj crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 1180227730Sraj 1181227730Sraj return (0); 1182227730Srajerr7: 1183227730Sraj for (i = 0; i < CESA_REQUESTS; i++) 1184227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1185227730Sraj sc->sc_requests[i].cr_dmap); 1186227730Srajerr6: 1187227730Sraj cesa_free_dma_mem(&sc->sc_requests_cdm); 1188227730Srajerr5: 1189227730Sraj cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1190227730Srajerr4: 1191227730Sraj cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1192227730Srajerr3: 1193227730Sraj bus_dma_tag_destroy(sc->sc_data_dtag); 1194227730Srajerr2: 1195227730Sraj bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie); 1196227730Srajerr1: 1197227730Sraj bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1198227730Srajerr0: 1199227730Sraj mtx_destroy(&sc->sc_sessions_lock); 1200227730Sraj mtx_destroy(&sc->sc_requests_lock); 1201227730Sraj mtx_destroy(&sc->sc_sdesc_lock); 1202227730Sraj mtx_destroy(&sc->sc_tdesc_lock); 1203227730Sraj mtx_destroy(&sc->sc_sc_lock); 1204227730Sraj return (ENXIO); 1205227730Sraj} 1206227730Sraj 1207227730Srajstatic int 1208227730Srajcesa_detach(device_t dev) 1209227730Sraj{ 1210227730Sraj struct cesa_softc *sc; 1211227730Sraj int i; 1212227730Sraj 1213227730Sraj sc = device_get_softc(dev); 1214227730Sraj 1215227730Sraj /* TODO: Wait for queued requests completion before shutdown. */ 1216227730Sraj 1217227730Sraj /* Mask interrupts */ 1218227730Sraj CESA_WRITE(sc, CESA_ICM, 0); 1219227730Sraj CESA_WRITE(sc, CESA_TDMA_EMR, 0); 1220227730Sraj 1221227730Sraj /* Unregister from OCF */ 1222227730Sraj crypto_unregister_all(sc->sc_cid); 1223227730Sraj 1224227730Sraj /* Free DMA Maps */ 1225227730Sraj for (i = 0; i < CESA_REQUESTS; i++) 1226227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1227227730Sraj sc->sc_requests[i].cr_dmap); 1228227730Sraj 1229227730Sraj /* Free DMA Memory */ 1230227730Sraj cesa_free_dma_mem(&sc->sc_requests_cdm); 1231227730Sraj cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1232227730Sraj cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1233227730Sraj 1234227730Sraj /* Free DMA Tag */ 1235227730Sraj bus_dma_tag_destroy(sc->sc_data_dtag); 1236227730Sraj 1237227730Sraj /* Stop interrupt */ 1238227730Sraj bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie); 1239227730Sraj 1240227730Sraj /* Relase I/O and IRQ resources */ 1241227730Sraj bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1242227730Sraj 1243227730Sraj /* Destory mutexes */ 1244227730Sraj mtx_destroy(&sc->sc_sessions_lock); 1245227730Sraj mtx_destroy(&sc->sc_requests_lock); 1246227730Sraj mtx_destroy(&sc->sc_sdesc_lock); 1247227730Sraj mtx_destroy(&sc->sc_tdesc_lock); 1248227730Sraj mtx_destroy(&sc->sc_sc_lock); 1249227730Sraj 1250227730Sraj return (0); 1251227730Sraj} 1252227730Sraj 1253227730Srajstatic void 1254227730Srajcesa_intr(void *arg) 1255227730Sraj{ 1256227730Sraj STAILQ_HEAD(, cesa_request) requests; 1257227730Sraj struct cesa_request *cr, *tmp; 1258227730Sraj struct cesa_softc *sc; 1259227730Sraj uint32_t ecr, icr; 1260227730Sraj int blocked; 1261227730Sraj 1262227730Sraj sc = arg; 1263227730Sraj 1264227730Sraj /* Ack interrupt */ 1265227730Sraj ecr = CESA_READ(sc, CESA_TDMA_ECR); 1266227730Sraj CESA_WRITE(sc, CESA_TDMA_ECR, 0); 1267227730Sraj icr = CESA_READ(sc, CESA_ICR); 1268227730Sraj CESA_WRITE(sc, CESA_ICR, 0); 1269227730Sraj 1270227730Sraj /* Check for TDMA errors */ 1271227730Sraj if (ecr & CESA_TDMA_ECR_MISS) { 1272227730Sraj device_printf(sc->sc_dev, "TDMA Miss error detected!\n"); 1273227730Sraj sc->sc_error = EIO; 1274227730Sraj } 1275227730Sraj 1276227730Sraj if (ecr & CESA_TDMA_ECR_DOUBLE_HIT) { 1277227730Sraj device_printf(sc->sc_dev, "TDMA Double Hit error detected!\n"); 1278227730Sraj sc->sc_error = EIO; 1279227730Sraj } 1280227730Sraj 1281227730Sraj if (ecr & CESA_TDMA_ECR_BOTH_HIT) { 1282227730Sraj device_printf(sc->sc_dev, "TDMA Both Hit error detected!\n"); 1283227730Sraj sc->sc_error = EIO; 1284227730Sraj } 1285227730Sraj 1286227730Sraj if (ecr & CESA_TDMA_ECR_DATA_ERROR) { 1287227730Sraj device_printf(sc->sc_dev, "TDMA Data error detected!\n"); 1288227730Sraj sc->sc_error = EIO; 1289227730Sraj } 1290227730Sraj 1291227730Sraj /* Check for CESA errors */ 1292227730Sraj if (icr & sc->sc_tperr) { 1293227730Sraj device_printf(sc->sc_dev, "CESA SRAM Parity error detected!\n"); 1294227730Sraj sc->sc_error = EIO; 1295227730Sraj } 1296227730Sraj 1297227730Sraj /* If there is nothing more to do, return */ 1298227730Sraj if ((icr & CESA_ICR_ACCTDMA) == 0) 1299227730Sraj return; 1300227730Sraj 1301227730Sraj /* Get all finished requests */ 1302227730Sraj CESA_LOCK(sc, requests); 1303227730Sraj STAILQ_INIT(&requests); 1304227730Sraj STAILQ_CONCAT(&requests, &sc->sc_queued_requests); 1305227730Sraj STAILQ_INIT(&sc->sc_queued_requests); 1306227730Sraj CESA_UNLOCK(sc, requests); 1307227730Sraj 1308227730Sraj /* Execute all ready requests */ 1309227730Sraj cesa_execute(sc); 1310227730Sraj 1311227730Sraj /* Process completed requests */ 1312227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_POSTREAD | 1313227730Sraj BUS_DMASYNC_POSTWRITE); 1314227730Sraj 1315227730Sraj STAILQ_FOREACH_SAFE(cr, &requests, cr_stq, tmp) { 1316227730Sraj bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, 1317227730Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1318227730Sraj 1319227730Sraj cr->cr_crp->crp_etype = sc->sc_error; 1320227730Sraj if (cr->cr_mac) 1321227730Sraj crypto_copyback(cr->cr_crp->crp_flags, 1322227730Sraj cr->cr_crp->crp_buf, cr->cr_mac->crd_inject, 1323227730Sraj cr->cr_cs->cs_hlen, cr->cr_csd->csd_hash); 1324227730Sraj 1325227730Sraj crypto_done(cr->cr_crp); 1326227730Sraj cesa_free_request(sc, cr); 1327227730Sraj } 1328227730Sraj 1329227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_PREREAD | 1330227730Sraj BUS_DMASYNC_PREWRITE); 1331227730Sraj 1332227730Sraj sc->sc_error = 0; 1333227730Sraj 1334227730Sraj /* Unblock driver if it ran out of resources */ 1335227730Sraj CESA_LOCK(sc, sc); 1336227730Sraj blocked = sc->sc_blocked; 1337227730Sraj sc->sc_blocked = 0; 1338227730Sraj CESA_UNLOCK(sc, sc); 1339227730Sraj 1340227730Sraj if (blocked) 1341227730Sraj crypto_unblock(sc->sc_cid, blocked); 1342227730Sraj} 1343227730Sraj 1344227730Srajstatic int 1345227730Srajcesa_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1346227730Sraj{ 1347227730Sraj struct cesa_session *cs; 1348227730Sraj struct cesa_softc *sc; 1349227730Sraj struct cryptoini *enc; 1350227730Sraj struct cryptoini *mac; 1351227730Sraj int error; 1352227730Sraj 1353227730Sraj sc = device_get_softc(dev); 1354227730Sraj enc = NULL; 1355227730Sraj mac = NULL; 1356227730Sraj error = 0; 1357227730Sraj 1358227730Sraj /* Check and parse input */ 1359227730Sraj if (cesa_is_hash(cri->cri_alg)) 1360227730Sraj mac = cri; 1361227730Sraj else 1362227730Sraj enc = cri; 1363227730Sraj 1364227730Sraj cri = cri->cri_next; 1365227730Sraj 1366227730Sraj if (cri) { 1367227730Sraj if (!enc && !cesa_is_hash(cri->cri_alg)) 1368227730Sraj enc = cri; 1369227730Sraj 1370227730Sraj if (!mac && cesa_is_hash(cri->cri_alg)) 1371227730Sraj mac = cri; 1372227730Sraj 1373227730Sraj if (cri->cri_next || !(enc && mac)) 1374227730Sraj return (EINVAL); 1375227730Sraj } 1376227730Sraj 1377227730Sraj if ((enc && (enc->cri_klen / 8) > CESA_MAX_KEY_LEN) || 1378227730Sraj (mac && (mac->cri_klen / 8) > CESA_MAX_MKEY_LEN)) 1379227730Sraj return (E2BIG); 1380227730Sraj 1381227730Sraj /* Allocate session */ 1382227730Sraj cs = cesa_alloc_session(sc); 1383227730Sraj if (!cs) 1384227730Sraj return (ENOMEM); 1385227730Sraj 1386227730Sraj /* Prepare CESA configuration */ 1387227730Sraj cs->cs_config = 0; 1388227730Sraj cs->cs_ivlen = 1; 1389227730Sraj cs->cs_mblen = 1; 1390227730Sraj 1391227730Sraj if (enc) { 1392227730Sraj switch (enc->cri_alg) { 1393227730Sraj case CRYPTO_AES_CBC: 1394227730Sraj cs->cs_config |= CESA_CSHD_AES | CESA_CSHD_CBC; 1395227730Sraj cs->cs_ivlen = AES_BLOCK_LEN; 1396227730Sraj break; 1397227730Sraj case CRYPTO_DES_CBC: 1398227730Sraj cs->cs_config |= CESA_CSHD_DES | CESA_CSHD_CBC; 1399227730Sraj cs->cs_ivlen = DES_BLOCK_LEN; 1400227730Sraj break; 1401227730Sraj case CRYPTO_3DES_CBC: 1402227730Sraj cs->cs_config |= CESA_CSHD_3DES | CESA_CSHD_3DES_EDE | 1403227730Sraj CESA_CSHD_CBC; 1404227730Sraj cs->cs_ivlen = DES3_BLOCK_LEN; 1405227730Sraj break; 1406227730Sraj default: 1407227730Sraj error = EINVAL; 1408227730Sraj break; 1409227730Sraj } 1410227730Sraj } 1411227730Sraj 1412227730Sraj if (!error && mac) { 1413227730Sraj switch (mac->cri_alg) { 1414227730Sraj case CRYPTO_MD5: 1415227730Sraj cs->cs_config |= CESA_CSHD_MD5; 1416227730Sraj cs->cs_mblen = 1; 1417227730Sraj cs->cs_hlen = MD5_HASH_LEN; 1418227730Sraj break; 1419227730Sraj case CRYPTO_MD5_HMAC: 1420227730Sraj cs->cs_config |= CESA_CSHD_MD5_HMAC; 1421227730Sraj cs->cs_mblen = MD5_HMAC_BLOCK_LEN; 1422227730Sraj cs->cs_hlen = CESA_HMAC_HASH_LENGTH; 1423227730Sraj break; 1424227730Sraj case CRYPTO_SHA1: 1425227730Sraj cs->cs_config |= CESA_CSHD_SHA1; 1426227730Sraj cs->cs_mblen = 1; 1427227730Sraj cs->cs_hlen = SHA1_HASH_LEN; 1428227730Sraj break; 1429227730Sraj case CRYPTO_SHA1_HMAC: 1430227730Sraj cs->cs_config |= CESA_CSHD_SHA1_HMAC; 1431227730Sraj cs->cs_mblen = SHA1_HMAC_BLOCK_LEN; 1432227730Sraj cs->cs_hlen = CESA_HMAC_HASH_LENGTH; 1433227730Sraj break; 1434227730Sraj default: 1435227730Sraj error = EINVAL; 1436227730Sraj break; 1437227730Sraj } 1438227730Sraj } 1439227730Sraj 1440227730Sraj /* Save cipher key */ 1441227730Sraj if (!error && enc && enc->cri_key) { 1442227730Sraj cs->cs_klen = enc->cri_klen / 8; 1443227730Sraj memcpy(cs->cs_key, enc->cri_key, cs->cs_klen); 1444227730Sraj if (enc->cri_alg == CRYPTO_AES_CBC) 1445227730Sraj error = cesa_prep_aes_key(cs); 1446227730Sraj } 1447227730Sraj 1448227730Sraj /* Save digest key */ 1449227730Sraj if (!error && mac && mac->cri_key) 1450227730Sraj error = cesa_set_mkey(cs, mac->cri_alg, mac->cri_key, 1451227730Sraj mac->cri_klen / 8); 1452227730Sraj 1453227730Sraj if (error) { 1454227730Sraj cesa_free_session(sc, cs); 1455227730Sraj return (EINVAL); 1456227730Sraj } 1457227730Sraj 1458227730Sraj *sidp = cs->cs_sid; 1459227730Sraj 1460227730Sraj return (0); 1461227730Sraj} 1462227730Sraj 1463227730Srajstatic int 1464227730Srajcesa_freesession(device_t dev, uint64_t tid) 1465227730Sraj{ 1466227730Sraj struct cesa_session *cs; 1467227730Sraj struct cesa_softc *sc; 1468227730Sraj 1469227730Sraj sc = device_get_softc(dev); 1470227730Sraj cs = cesa_get_session(sc, CRYPTO_SESID2LID(tid)); 1471227730Sraj if (!cs) 1472227730Sraj return (EINVAL); 1473227730Sraj 1474227730Sraj /* Free session */ 1475227730Sraj cesa_free_session(sc, cs); 1476227730Sraj 1477227730Sraj return (0); 1478227730Sraj} 1479227730Sraj 1480227730Srajstatic int 1481227730Srajcesa_process(device_t dev, struct cryptop *crp, int hint) 1482227730Sraj{ 1483227730Sraj struct cesa_request *cr; 1484227730Sraj struct cesa_session *cs; 1485227730Sraj struct cryptodesc *crd; 1486227730Sraj struct cryptodesc *enc; 1487227730Sraj struct cryptodesc *mac; 1488227730Sraj struct cesa_softc *sc; 1489227730Sraj int error; 1490227730Sraj 1491227730Sraj sc = device_get_softc(dev); 1492227730Sraj crd = crp->crp_desc; 1493227730Sraj enc = NULL; 1494227730Sraj mac = NULL; 1495227730Sraj error = 0; 1496227730Sraj 1497227730Sraj /* Check session ID */ 1498227730Sraj cs = cesa_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid)); 1499227730Sraj if (!cs) { 1500227730Sraj crp->crp_etype = EINVAL; 1501227730Sraj crypto_done(crp); 1502227730Sraj return (0); 1503227730Sraj } 1504227730Sraj 1505227730Sraj /* Check and parse input */ 1506227730Sraj if (crp->crp_ilen > CESA_MAX_REQUEST_SIZE) { 1507227730Sraj crp->crp_etype = E2BIG; 1508227730Sraj crypto_done(crp); 1509227730Sraj return (0); 1510227730Sraj } 1511227730Sraj 1512227730Sraj if (cesa_is_hash(crd->crd_alg)) 1513227730Sraj mac = crd; 1514227730Sraj else 1515227730Sraj enc = crd; 1516227730Sraj 1517227730Sraj crd = crd->crd_next; 1518227730Sraj 1519227730Sraj if (crd) { 1520227730Sraj if (!enc && !cesa_is_hash(crd->crd_alg)) 1521227730Sraj enc = crd; 1522227730Sraj 1523227730Sraj if (!mac && cesa_is_hash(crd->crd_alg)) 1524227730Sraj mac = crd; 1525227730Sraj 1526227730Sraj if (crd->crd_next || !(enc && mac)) { 1527227730Sraj crp->crp_etype = EINVAL; 1528227730Sraj crypto_done(crp); 1529227730Sraj return (0); 1530227730Sraj } 1531227730Sraj } 1532227730Sraj 1533227730Sraj /* 1534227730Sraj * Get request descriptor. Block driver if there is no free 1535227730Sraj * descriptors in pool. 1536227730Sraj */ 1537227730Sraj cr = cesa_alloc_request(sc); 1538227730Sraj if (!cr) { 1539227730Sraj CESA_LOCK(sc, sc); 1540227730Sraj sc->sc_blocked = CRYPTO_SYMQ; 1541227730Sraj CESA_UNLOCK(sc, sc); 1542227730Sraj return (ERESTART); 1543227730Sraj } 1544227730Sraj 1545227730Sraj /* Prepare request */ 1546227730Sraj cr->cr_crp = crp; 1547227730Sraj cr->cr_enc = enc; 1548227730Sraj cr->cr_mac = mac; 1549227730Sraj cr->cr_cs = cs; 1550227730Sraj 1551227730Sraj CESA_LOCK(sc, sessions); 1552227730Sraj cesa_sync_desc(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1553227730Sraj 1554227730Sraj if (enc && enc->crd_flags & CRD_F_ENCRYPT) { 1555227730Sraj if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1556227730Sraj memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1557227730Sraj else 1558227730Sraj arc4rand(cr->cr_csd->csd_iv, cs->cs_ivlen, 0); 1559227730Sraj 1560227730Sraj if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0) 1561227730Sraj crypto_copyback(crp->crp_flags, crp->crp_buf, 1562227730Sraj enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1563227730Sraj } else if (enc) { 1564227730Sraj if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1565227730Sraj memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1566227730Sraj else 1567227730Sraj crypto_copydata(crp->crp_flags, crp->crp_buf, 1568227730Sraj enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1569227730Sraj } 1570227730Sraj 1571227730Sraj if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) { 1572227730Sraj if ((enc->crd_klen / 8) <= CESA_MAX_KEY_LEN) { 1573227730Sraj cs->cs_klen = enc->crd_klen / 8; 1574227730Sraj memcpy(cs->cs_key, enc->crd_key, cs->cs_klen); 1575227730Sraj if (enc->crd_alg == CRYPTO_AES_CBC) 1576227730Sraj error = cesa_prep_aes_key(cs); 1577227730Sraj } else 1578227730Sraj error = E2BIG; 1579227730Sraj } 1580227730Sraj 1581227730Sraj if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) { 1582227730Sraj if ((mac->crd_klen / 8) <= CESA_MAX_MKEY_LEN) 1583227730Sraj error = cesa_set_mkey(cs, mac->crd_alg, mac->crd_key, 1584227730Sraj mac->crd_klen / 8); 1585227730Sraj else 1586227730Sraj error = E2BIG; 1587227730Sraj } 1588227730Sraj 1589227730Sraj /* Convert request to chain of TDMA and SA descriptors */ 1590227730Sraj if (!error) 1591227730Sraj error = cesa_create_chain(sc, cr); 1592227730Sraj 1593227730Sraj cesa_sync_desc(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1594227730Sraj CESA_UNLOCK(sc, sessions); 1595227730Sraj 1596227730Sraj if (error) { 1597227730Sraj cesa_free_request(sc, cr); 1598227730Sraj crp->crp_etype = error; 1599227730Sraj crypto_done(crp); 1600227730Sraj return (0); 1601227730Sraj } 1602227730Sraj 1603227730Sraj bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, BUS_DMASYNC_PREREAD | 1604227730Sraj BUS_DMASYNC_PREWRITE); 1605227730Sraj 1606227730Sraj /* Enqueue request to execution */ 1607227730Sraj cesa_enqueue_request(sc, cr); 1608227730Sraj 1609227730Sraj /* Start execution, if we have no more requests in queue */ 1610227730Sraj if ((hint & CRYPTO_HINT_MORE) == 0) 1611227730Sraj cesa_execute(sc); 1612227730Sraj 1613227730Sraj return (0); 1614227730Sraj} 1615