1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD$ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46220033Sadrian/* 47220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 48220033Sadrian */ 49220053Sadrian#ifdef ATH_ENABLE_11N 50220033Sadrian#define ATH_TXBUF 512 51220033Sadrian#define ATH_RXBUF 512 52220033Sadrian#endif 53220033Sadrian 54155481Ssam#ifndef ATH_RXBUF 55116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 56155481Ssam#endif 57155481Ssam#ifndef ATH_TXBUF 58170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 59155481Ssam#endif 60178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 61178354Ssam 62140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66116743Ssam 67147067Ssam#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 68147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70147067Ssam 71147057Ssam/* 72147057Ssam * The key cache is used for h/w cipher state and also for 73147057Ssam * tracking station state such as the current tx antenna. 74147057Ssam * We also setup a mapping table between key cache slot indices 75147057Ssam * and station state to short-circuit node lookups on rx. 76147057Ssam * Different parts have different size key caches. We handle 77147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 78147057Ssam */ 79147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 80147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81147057Ssam 82170530Ssamstruct taskqueue; 83170530Ssamstruct kthread; 84170530Ssamstruct ath_buf; 85170530Ssam 86138570Ssam/* driver-specific node state */ 87116743Ssamstruct ath_node { 88119150Ssam struct ieee80211_node an_node; /* base class */ 89178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 90178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 91170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 92138570Ssam /* variable-length rate control state follows */ 93116743Ssam}; 94138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 95138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 96116743Ssam 97138570Ssam#define ATH_RSSI_LPF_LEN 10 98138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 99138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 100138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 101138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 102138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 103138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 104138570Ssam if ((y) >= -20) \ 105138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 106138570Ssam} while (0) 107184358Ssam#define ATH_EP_RND(x,mul) \ 108184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 109184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 110138570Ssam 111116743Ssamstruct ath_buf { 112138570Ssam STAILQ_ENTRY(ath_buf) bf_list; 113116743Ssam int bf_nseg; 114186904Ssam uint16_t bf_txflags; /* tx descriptor flags */ 115186904Ssam uint16_t bf_flags; /* status flags (below) */ 116116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 117165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 118116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 119138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 120116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 121116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 122116743Ssam bus_size_t bf_mapsize; 123140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 124116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 125116743Ssam}; 126138570Ssamtypedef STAILQ_HEAD(, ath_buf) ath_bufhead; 127116743Ssam 128186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 129186904Ssam 130138570Ssam/* 131138570Ssam * DMA state for tx/rx descriptors. 132138570Ssam */ 133138570Ssamstruct ath_descdma { 134138570Ssam const char* dd_name; 135138570Ssam struct ath_desc *dd_desc; /* descriptors */ 136138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 137158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 138138570Ssam bus_dma_segment_t dd_dseg; 139138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 140138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 141138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 142138570Ssam}; 143138570Ssam 144138570Ssam/* 145138570Ssam * Data transmit queue state. One of these exists for each 146138570Ssam * hardware transmit queue. Packets sent to us from above 147138570Ssam * are assigned to queues based on their priority. Not all 148138570Ssam * devices support a complete set of hardware transmit queues. 149138570Ssam * For those devices the array sc_ac2q will map multiple 150138570Ssam * priorities to fewer hardware queues (typically all to one 151138570Ssam * hardware queue). 152138570Ssam */ 153138570Ssamstruct ath_txq { 154138570Ssam u_int axq_qnum; /* hardware q number */ 155178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 156190579Ssam u_int axq_ac; /* WME AC */ 157186904Ssam u_int axq_flags; 158186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 159156073Ssam u_int axq_depth; /* queue depth (stat only) */ 160138570Ssam u_int axq_intrcnt; /* interrupt count */ 161138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 162138570Ssam STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 163138570Ssam struct mtx axq_lock; /* lock on q and link */ 164155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 165138570Ssam}; 166138570Ssam 167155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 168155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 169155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 170167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 171161425Simp} while (0) 172138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 173138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 174138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 175138570Ssam#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 176138570Ssam 177138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 178138570Ssam STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 179138570Ssam (_tq)->axq_depth++; \ 180138570Ssam} while (0) 181138570Ssam#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 182138570Ssam STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 183138570Ssam (_tq)->axq_depth--; \ 184138570Ssam} while (0) 185178354Ssam/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 186178354Ssam#define ATH_TXQ_LAST(_tq) \ 187178354Ssam ((struct ath_buf *)(void *) \ 188178354Ssam ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 189138570Ssam 190178354Ssamstruct ath_vap { 191178354Ssam struct ieee80211vap av_vap; /* base class */ 192178354Ssam int av_bslot; /* beacon slot index */ 193178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 194178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 195178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 196178354Ssam 197178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 198192468Ssam struct mbuf *, int, int, int); 199178354Ssam int (*av_newstate)(struct ieee80211vap *, 200178354Ssam enum ieee80211_state, int); 201178354Ssam void (*av_bmiss)(struct ieee80211vap *); 202178354Ssam}; 203178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 204178354Ssam 205155491Ssamstruct taskqueue; 206155486Ssamstruct ath_tx99; 207155486Ssam 208116743Ssamstruct ath_softc { 209147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 210138570Ssam struct ath_stats sc_stats; /* interface statistics */ 211138570Ssam int sc_debug; 212178354Ssam int sc_nvaps; /* # vaps */ 213178354Ssam int sc_nstavaps; /* # station vaps */ 214195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 215178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 216178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 217178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 218178354Ssam 219138570Ssam void (*sc_node_free)(struct ieee80211_node *); 220116743Ssam device_t sc_dev; 221159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 222159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 223116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 224116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 225155491Ssam struct taskqueue *sc_tq; /* private task queue */ 226116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 227138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 228155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 229138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 230178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 231178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 232178354Ssam sc_softled : 1,/* enable LED gpio status */ 233178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 234178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 235178354Ssam sc_diversity: 1,/* enable rx diversity */ 236178354Ssam sc_hasveol : 1,/* tx VEOL support */ 237178354Ssam sc_ledstate : 1,/* LED on/off state */ 238178354Ssam sc_blinking : 1,/* LED blink operation active */ 239178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 240178354Ssam sc_scanning : 1,/* scanning active */ 241155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 242178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 243165571Ssam sc_xchanmode: 1,/* extended channel mode */ 244170530Ssam sc_outdoor : 1,/* outdoor operation */ 245178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 246178354Ssam sc_hasbmask : 1,/* bssid mask support */ 247195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 248178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 249178354Ssam sc_beacons : 1,/* beacons running */ 250178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 251178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 252179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 253185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 254186904Ssam sc_tdma : 1,/* TDMA in use */ 255189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 256220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 257224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 258225444Sadrian sc_kickpcu : 1,/* kick PCU RX on next RX proc */ 259225444Sadrian sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 260178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 261178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 262116743Ssam /* rate tables */ 263188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 264116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 265116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 266155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 267138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 268170530Ssam u_int16_t sc_curaid; /* current association id */ 269187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 270170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 271116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 272140432Ssam struct { 273140432Ssam u_int8_t ieeerate; /* IEEE rate */ 274140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 275140761Ssam u_int8_t txflags; /* radiotap tx flags */ 276140432Ssam u_int16_t ledon; /* softled on time */ 277140432Ssam u_int16_t ledoff; /* softled off time */ 278140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 279138570Ssam u_int8_t sc_protrix; /* protection rate index */ 280170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 281155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 282170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 283170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 284138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 285116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 286138570Ssam u_int sc_keymax; /* size of key cache */ 287147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 288116743Ssam 289140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 290140432Ssam u_int sc_ledon; /* pin setting for LED on */ 291140432Ssam u_int sc_ledidle; /* idle polling interval */ 292140432Ssam int sc_ledevent; /* time of last LED event */ 293184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 294140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 295140432Ssam struct callout sc_ledtimer; /* led off timer */ 296138570Ssam 297155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 298155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 299155515Ssam 300178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 301138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 302170530Ssam struct mbuf *sc_rxpending; /* pending receive data */ 303116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 304116743Ssam struct task sc_rxtask; /* rx int processing */ 305138570Ssam u_int8_t sc_defant; /* current default antenna */ 306138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 307155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 308192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 309192468Ssam struct ath_rx_radiotap_header sc_rx_th; 310192468Ssam int sc_rx_th_len; 311192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 312116743Ssam 313138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 314138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 315138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 316155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 317138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 318138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 319138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 320138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 321116743Ssam struct task sc_txtask; /* tx int processing */ 322189605Ssam int sc_wd_timer; /* count down for wd timer */ 323189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 324192468Ssam struct ath_tx_radiotap_header sc_tx_th; 325192468Ssam int sc_tx_th_len; 326116743Ssam 327138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 328138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 329116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 330138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 331138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 332138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 333116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 334138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 335138570Ssam enum { 336138570Ssam OK, /* no change needed */ 337138570Ssam UPDATE, /* update pending */ 338138570Ssam COMMIT /* beacon sent, commit change */ 339138570Ssam } sc_updateslot; /* slot time update fsm */ 340178354Ssam int sc_slotupdate; /* slot to advance fsm */ 341178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 342178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 343116743Ssam 344116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 345185744Ssam int sc_lastlongcal; /* last long cal completed */ 346185744Ssam int sc_lastcalreset;/* last cal reset done */ 347217684Sadrian int sc_lastani; /* last ANI poll */ 348217684Sadrian int sc_lastshortcal; /* last short calibration */ 349217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 350155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 351186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 352186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 353186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 354186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 355186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 356186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 357186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 358186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 359217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 360218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 361218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 362222585Sadrian 363222585Sadrian /* DFS related state */ 364222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 365222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 366222585Sadrian struct task sc_dfstask; /* DFS processing task */ 367116743Ssam}; 368116743Ssam 369121100Ssam#define ATH_LOCK_INIT(_sc) \ 370121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 371167252Ssam NULL, MTX_DEF | MTX_RECURSE) 372121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 373121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 374121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 375121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 376121100Ssam 377138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 378138570Ssam 379155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 380155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 381155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 382167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 383155482Ssam} while (0) 384121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 385121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 386121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 387121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 388121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 389121100Ssam 390116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 391116743Ssamint ath_detach(struct ath_softc *); 392116743Ssamvoid ath_resume(struct ath_softc *); 393116743Ssamvoid ath_suspend(struct ath_softc *); 394116743Ssamvoid ath_shutdown(struct ath_softc *); 395116743Ssamvoid ath_intr(void *); 396116743Ssam 397116743Ssam/* 398116743Ssam * HAL definitions to comply with local coding convention. 399116743Ssam */ 400138570Ssam#define ath_hal_detach(_ah) \ 401138570Ssam ((*(_ah)->ah_detach)((_ah))) 402116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 403116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 404186904Ssam#define ath_hal_macversion(_ah) \ 405186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 406116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 407116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 408116743Ssam#define ath_hal_getmac(_ah, _mac) \ 409116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 410138570Ssam#define ath_hal_setmac(_ah, _mac) \ 411138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 412178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 413178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 414178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 415178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 416116743Ssam#define ath_hal_intrset(_ah, _mask) \ 417116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 418116743Ssam#define ath_hal_intrget(_ah) \ 419116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 420116743Ssam#define ath_hal_intrpend(_ah) \ 421116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 422116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 423116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 424116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 425116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 426155515Ssam#define ath_hal_setpower(_ah, _mode) \ 427155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 428138570Ssam#define ath_hal_keycachesize(_ah) \ 429138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 430116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 431116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 432138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 433138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 434116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 435116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 436116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 437116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 438116743Ssam#define ath_hal_getrxfilter(_ah) \ 439116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 440116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 441116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 442116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 443116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 444116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 445116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 446116743Ssam#define ath_hal_putrxbuf(_ah, _bufaddr) \ 447116743Ssam ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 448186904Ssam/* NB: common across all chips */ 449186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 450116743Ssam#define ath_hal_gettsf32(_ah) \ 451186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 452116743Ssam#define ath_hal_gettsf64(_ah) \ 453116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 454116743Ssam#define ath_hal_resettsf(_ah) \ 455116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 456116743Ssam#define ath_hal_rxena(_ah) \ 457116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 458116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 459116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 460116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 461116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 462138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 463138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 464116743Ssam#define ath_hal_getrxbuf(_ah) \ 465116743Ssam ((*(_ah)->ah_getRxDP)((_ah))) 466116743Ssam#define ath_hal_txstart(_ah, _q) \ 467116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 468116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 469116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 470155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 471155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 472185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 473185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 474185744Ssam#define ath_hal_calreset(_ah, _chan) \ 475185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 476116743Ssam#define ath_hal_setledstate(_ah, _state) \ 477116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 478138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 479138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 480116743Ssam#define ath_hal_beaconreset(_ah) \ 481116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 482186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 483186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 484138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 485138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 486225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 487225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 488116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 489138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 490138570Ssam#define ath_hal_phydisable(_ah) \ 491138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 492138570Ssam#define ath_hal_setopmode(_ah) \ 493138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 494116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 495116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 496116743Ssam#define ath_hal_stoppcurecv(_ah) \ 497116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 498116743Ssam#define ath_hal_startpcurecv(_ah) \ 499116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 500116743Ssam#define ath_hal_stopdmarecv(_ah) \ 501116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 502138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 503138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 504138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 505155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 506170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 507116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 508116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 509116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 510116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 511116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 512116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 513138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 514138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 515138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 516138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 517186904Ssam/* NB: common across all chips */ 518186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 519186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 520186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 521116743Ssam#define ath_hal_getrfgain(_ah) \ 522116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 523138570Ssam#define ath_hal_getdefantenna(_ah) \ 524138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 525138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 526138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 527155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 528155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 529217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 530217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 531138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 532138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 533138570Ssam#define ath_hal_setslottime(_ah, _us) \ 534138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 535138570Ssam#define ath_hal_getslottime(_ah) \ 536138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 537138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 538138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 539138570Ssam#define ath_hal_getacktimeout(_ah) \ 540138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 541138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 542138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 543138570Ssam#define ath_hal_getctstimeout(_ah) \ 544138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 545138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 546138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 547138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 548138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 549138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 550138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 551138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 552155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 553155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 554184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 555138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 556138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 557178354Ssam#define ath_hal_gettkipmic(_ah) \ 558178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 559178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 560178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 561162410Ssam#define ath_hal_hastkipsplit(_ah) \ 562138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 563162410Ssam#define ath_hal_gettkipsplit(_ah) \ 564162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 565162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 566162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 567178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 568178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 569138570Ssam#define ath_hal_hwphycounters(_ah) \ 570138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 571138570Ssam#define ath_hal_hasdiversity(_ah) \ 572138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 573138570Ssam#define ath_hal_getdiversity(_ah) \ 574138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 575138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 576138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 577166954Ssam#define ath_hal_getantennaswitch(_ah) \ 578166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 579166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 580166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 581138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 582138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 583138570Ssam#define ath_hal_setdiag(_ah, _v) \ 584138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 585138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 586138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 587138570Ssam#define ath_hal_hasveol(_ah) \ 588138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 589138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 590138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 591138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 592138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 593138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 594138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 595138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 596138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 597138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 598138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 599138570Ssam#define ath_hal_settpscale(_ah, _v) \ 600138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 601138570Ssam#define ath_hal_hastpc(_ah) \ 602138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 603138570Ssam#define ath_hal_gettpc(_ah) \ 604138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 605138570Ssam#define ath_hal_settpc(_ah, _v) \ 606138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 607138570Ssam#define ath_hal_hasbursting(_ah) \ 608138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 609203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 610203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 611147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 612147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 613147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 614147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 615170530Ssam#define ath_hal_hasfastframes(_ah) \ 616170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 617178354Ssam#define ath_hal_hasbssidmask(_ah) \ 618178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 619195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 620195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 621178354Ssam#define ath_hal_hastsfadjust(_ah) \ 622178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 623178354Ssam#define ath_hal_gettsfadjust(_ah) \ 624178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 625178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 626178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 627155515Ssam#define ath_hal_hasrfsilent(_ah) \ 628155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 629155515Ssam#define ath_hal_getrfkill(_ah) \ 630155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 631155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 632155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 633155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 634155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 635155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 636155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 637155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 638155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 639155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 640155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 641155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 642155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 643155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 644155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 645184354Ssam#define ath_hal_hasintmit(_ah) \ 646222277Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 647184354Ssam#define ath_hal_getintmit(_ah) \ 648222277Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 649184354Ssam#define ath_hal_setintmit(_ah, _v) \ 650222277Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, _v, NULL) 651154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 652154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 653218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 654218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 655218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 656218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 657218490Sadrian#define ath_hal_split4ktrans(_ah) \ 658224540Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, 0, NULL) == HAL_OK) 659220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 660220324Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, 0, NULL) == HAL_OK) 661220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 662220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 663225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 664225444Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, 0, NULL) == HAL_OK) 665116743Ssam 666116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 667116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 668165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 669165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 670116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 671116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 672116743Ssam _rtsrate, _rtsdura) \ 673116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 674116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 675155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 676138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 677116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 678138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 679116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 680138570Ssam#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 681138570Ssam ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 682165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 683165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 684155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 685155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 686217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 687217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 688116743Ssam 689218066Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 690218067Sadrian _cipher, _delims, _seglen, _first, _last) \ 691218066Sadrian ((*(_ah)->ah_chainTxDesc((_ah), (_ds), (_pktlen), (_hdrlen), \ 692218066Sadrian (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 693218066Sadrian (_first), (_last)))) 694218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 695218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 696218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 697218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 698218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 699218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 700218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 701218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 702218067Sadrian (_series), (_ns), (_flags))) 703218066Sadrian#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 704218066Sadrian ((*(_ah)->ah_set11nAggrMiddle((_ah), (_ds), (_num)))) 705218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 706218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 707218066Sadrian 708222585Sadrian/* 709222585Sadrian * This is badly-named; you need to set the correct parameters 710222585Sadrian * to begin to receive useful radar events; and even then 711222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 712222585Sadrian * more information. 713222585Sadrian */ 714222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 715222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 716222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 717222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 718222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 719222815Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), (_buf), (_event))) 720224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 721224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 722222585Sadrian 723188974Ssam#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 724188974Ssam ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 725138570Ssam#define ath_hal_gpioset(_ah, _gpio, _b) \ 726138570Ssam ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 727155515Ssam#define ath_hal_gpioget(_ah, _gpio) \ 728155515Ssam ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 729155515Ssam#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 730155515Ssam ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 731138570Ssam 732155515Ssam#define ath_hal_radar_wait(_ah, _chan) \ 733155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 734155515Ssam 735116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 736