ar9287_olc.c revision 222308 
1/*
2 * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9287_olc.c 222308 2011-05-26 14:29:05Z adrian $
26 */
27#include "opt_ah.h"
28
29#include "ah.h"
30#include "ah_internal.h"
31
32#include "ah_eeprom_v14.h"
33#include "ah_eeprom_9287.h"
34
35#include "ar9002/ar9280.h"
36#include "ar5416/ar5416reg.h"
37#include "ar5416/ar5416phy.h"
38#include "ar9002/ar9002phy.h"
39
40#include "ar9002/ar9287phy.h"
41#include "ar9002/ar9287an.h"
42#include "ar9002/ar9287_olc.h"
43
44void
45ar9287olcInit(struct ath_hal *ah)
46{
47	OS_REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
48	    AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
49	OS_A_REG_RMW_FIELD(ah, AR9287_AN_TXPC0,
50	    AR9287_AN_TXPC0_TXPCMODE,
51	    AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
52	OS_DELAY(100);
53}
54
55/*
56 * Run temperature compensation calibration.
57 *
58 * The TX gain table is adjusted depending upon the difference
59 * between the initial PDADC value and the currently read
60 * average TX power sample value. This value is only valid if
61 * frames have been transmitted, so currPDADC will be 0 if
62 * no frames have yet been transmitted.
63 */
64void
65ar9287olcTemperatureCompensation(struct ath_hal *ah)
66{
67	uint32_t rddata;
68	int32_t delta, currPDADC, slope;
69
70	rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);
71	currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
72
73	if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) {
74		/*
75		 * Zero value indicates that no frames have been transmitted
76		 * yet, can't do temperature compensation until frames are
77		 * transmitted.
78		 */
79		return;
80	} else {
81		int8_t val;
82		(void) (ath_hal_eepromGet(ah, AR_EEP_TEMPSENSE_SLOPE, &val));
83		slope = val;
84
85		if (slope == 0) { /* to avoid divide by zero case */
86			delta = 0;
87		} else {
88			delta = ((currPDADC - AH5416(ah)->initPDADC)*4) / slope;
89		}
90		OS_REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
91		    AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
92		OS_REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
93		    AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
94	}
95}
96
97void
98ar9287olcGetTxGainIndex(struct ath_hal *ah,
99    const struct ieee80211_channel *chan,
100    struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
101    uint8_t *pCalChans,  uint16_t availPiers, int8_t *pPwr)
102{
103        uint16_t idxL = 0, idxR = 0, numPiers;
104        HAL_BOOL match;
105        CHAN_CENTERS centers;
106
107        ar5416GetChannelCenters(ah, chan, &centers);
108
109        for (numPiers = 0; numPiers < availPiers; numPiers++) {
110                if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
111                        break;
112        }
113
114        match = ath_ee_getLowerUpperIndex(
115                (uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
116                pCalChans, numPiers, &idxL, &idxR);
117
118        if (match) {
119                *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
120        } else {
121                *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
122                         (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
123        }
124}
125
126void
127ar9287olcSetPDADCs(struct ath_hal *ah, int32_t txPower,
128    uint16_t chain)
129{
130        uint32_t tmpVal;
131        uint32_t a;
132
133        /* Enable OLPC for chain 0 */
134
135        tmpVal = OS_REG_READ(ah, 0xa270);
136        tmpVal = tmpVal & 0xFCFFFFFF;
137        tmpVal = tmpVal | (0x3 << 24);
138        OS_REG_WRITE(ah, 0xa270, tmpVal);
139
140        /* Enable OLPC for chain 1 */
141
142        tmpVal = OS_REG_READ(ah, 0xb270);
143        tmpVal = tmpVal & 0xFCFFFFFF;
144        tmpVal = tmpVal | (0x3 << 24);
145        OS_REG_WRITE(ah, 0xb270, tmpVal);
146
147        /* Write the OLPC ref power for chain 0 */
148
149        if (chain == 0) {
150                tmpVal = OS_REG_READ(ah, 0xa398);
151                tmpVal = tmpVal & 0xff00ffff;
152                a = (txPower)&0xff;
153                tmpVal = tmpVal | (a << 16);
154                OS_REG_WRITE(ah, 0xa398, tmpVal);
155        }
156
157        /* Write the OLPC ref power for chain 1 */
158
159        if (chain == 1) {
160                tmpVal = OS_REG_READ(ah, 0xb398);
161                tmpVal = tmpVal & 0xff00ffff;
162                a = (txPower)&0xff;
163                tmpVal = tmpVal | (a << 16);
164                OS_REG_WRITE(ah, 0xb398, tmpVal);
165        }
166}
167