ar9280_attach.c revision 219393
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 219393 2011-03-08 06:59:59Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9002/ar9280v1.ini" 32#include "ar9002/ar9280v2.ini" 33#include "ar9002/ar9280_olc.h" 34 35static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41}; 42static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MIN_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48}; 49static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MIN_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55}; 56static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62}; 63 64static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66static void ar9280WriteIni(struct ath_hal *ah, 67 const struct ieee80211_channel *chan); 68 69static void 70ar9280AniSetup(struct ath_hal *ah) 71{ 72 /* 73 * These are the parameters from the AR5416 ANI code; 74 * they likely need quite a bit of adjustment for the 75 * AR9280. 76 */ 77 static const struct ar5212AniParams aniparams = { 78 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80 .coarseHigh = { -14, -14, -14, -14, -12 }, 81 .coarseLow = { -64, -64, -64, -64, -70 }, 82 .firpwr = { -78, -78, -78, -78, -80 }, 83 .maxSpurImmunityLevel = 2, 84 .cycPwrThr1 = { 2, 4, 6 }, 85 .maxFirstepLevel = 2, /* levels 0..2 */ 86 .firstep = { 0, 4, 8 }, 87 .ofdmTrigHigh = 500, 88 .ofdmTrigLow = 200, 89 .cckTrigHigh = 200, 90 .cckTrigLow = 100, 91 .rssiThrHigh = 40, 92 .rssiThrLow = 7, 93 .period = 100, 94 }; 95 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 97 98 /* NB: ANI is not enabled yet */ 99 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 100} 101 102/* 103 * Attach for an AR9280 part. 104 */ 105static struct ath_hal * 106ar9280Attach(uint16_t devid, HAL_SOFTC sc, 107 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 108 HAL_STATUS *status) 109{ 110 struct ath_hal_9280 *ahp9280; 111 struct ath_hal_5212 *ahp; 112 struct ath_hal *ah; 113 uint32_t val; 114 HAL_STATUS ecode; 115 HAL_BOOL rfStatus; 116 int8_t pwr_table_offset; 117 118 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 119 __func__, sc, (void*) st, (void*) sh); 120 121 /* NB: memory is returned zero'd */ 122 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 123 if (ahp9280 == AH_NULL) { 124 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 125 "%s: cannot allocate memory for state block\n", __func__); 126 *status = HAL_ENOMEM; 127 return AH_NULL; 128 } 129 ahp = AH5212(ahp9280); 130 ah = &ahp->ah_priv.h; 131 132 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 133 134 /* XXX override with 9280 specific state */ 135 /* override 5416 methods for our needs */ 136 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 137 ah->ah_configPCIE = ar9280ConfigPCIE; 138 139 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 140 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 141 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 142 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 143 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 144 145 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 146 AH5416(ah)->ah_writeIni = ar9280WriteIni; 147 AH5416(ah)->ah_olcInit = ar9280olcInit; 148 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 149 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 150 151 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 152 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 153 154 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 155 /* reset chip */ 156 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 157 __func__); 158 ecode = HAL_EIO; 159 goto bad; 160 } 161 162 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 163 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 164 __func__); 165 ecode = HAL_EIO; 166 goto bad; 167 } 168 /* Read Revisions from Chips before taking out of reset */ 169 val = OS_REG_READ(ah, AR_SREV); 170 HALDEBUG(ah, HAL_DEBUG_ATTACH, 171 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 172 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 173 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 174 /* NB: include chip type to differentiate from pre-Sowl versions */ 175 AH_PRIVATE(ah)->ah_macVersion = 176 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 177 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 178 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 179 180 /* setup common ini data; rf backends handle remainder */ 181 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 182 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 183 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 184 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 185 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 186 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 187 ar9280Modes_fast_clock_v2, 3); 188 } else { 189 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 190 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 191 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 192 ar9280PciePhy_v1, 2); 193 } 194 ar5416AttachPCIE(ah); 195 196 ecode = ath_hal_v14EepromAttach(ah); 197 if (ecode != HAL_OK) 198 goto bad; 199 200 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 201 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 202 ecode = HAL_EIO; 203 goto bad; 204 } 205 206 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 207 208 if (!ar5212ChipTest(ah)) { 209 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 210 __func__); 211 ecode = HAL_ESELFTEST; 212 goto bad; 213 } 214 215 /* 216 * Set correct Baseband to analog shift 217 * setting to access analog chips. 218 */ 219 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 220 221 /* Read Radio Chip Rev Extract */ 222 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 223 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 224 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 225 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 226 break; 227 default: 228 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 229 AH_PRIVATE(ah)->ah_analog5GhzRev = 230 AR_RAD5133_SREV_MAJOR; 231 break; 232 } 233#ifdef AH_DEBUG 234 HALDEBUG(ah, HAL_DEBUG_ANY, 235 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 236 "this driver\n", __func__, 237 AH_PRIVATE(ah)->ah_analog5GhzRev); 238 ecode = HAL_ENOTSUPP; 239 goto bad; 240#endif 241 } 242 rfStatus = ar9280RfAttach(ah, &ecode); 243 if (!rfStatus) { 244 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 245 __func__, ecode); 246 goto bad; 247 } 248 249 /* 250 * Check whether the power table offset isn't the default. 251 * This can occur with eeprom minor V21 or greater on Merlin. 252 */ 253 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 254 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) { 255 ath_hal_printf(ah, "ERROR: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm\n", 256 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 257 ecode = HAL_ENOTSUPP; 258 goto bad; 259 } 260 261 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 262 /* setup rxgain table */ 263 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 264 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 265 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 266 ar9280Modes_backoff_13db_rxgain_v2, 6); 267 break; 268 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 269 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 270 ar9280Modes_backoff_23db_rxgain_v2, 6); 271 break; 272 case AR5416_EEP_RXGAIN_ORIG: 273 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 274 ar9280Modes_original_rxgain_v2, 6); 275 break; 276 default: 277 HALASSERT(AH_FALSE); 278 goto bad; /* XXX ? try to continue */ 279 } 280 } 281 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 282 /* setp txgain table */ 283 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 284 case AR5416_EEP_TXGAIN_HIGH_POWER: 285 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 286 ar9280Modes_high_power_tx_gain_v2, 6); 287 break; 288 case AR5416_EEP_TXGAIN_ORIG: 289 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 290 ar9280Modes_original_tx_gain_v2, 6); 291 break; 292 default: 293 HALASSERT(AH_FALSE); 294 goto bad; /* XXX ? try to continue */ 295 } 296 } 297 298 /* 299 * Got everything we need now to setup the capabilities. 300 */ 301 if (!ar9280FillCapabilityInfo(ah)) { 302 ecode = HAL_EEREAD; 303 goto bad; 304 } 305 306 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 307 if (ecode != HAL_OK) { 308 HALDEBUG(ah, HAL_DEBUG_ANY, 309 "%s: error getting mac address from EEPROM\n", __func__); 310 goto bad; 311 } 312 /* XXX How about the serial number ? */ 313 /* Read Reg Domain */ 314 AH_PRIVATE(ah)->ah_currentRD = 315 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 316 317 /* 318 * ah_miscMode is populated by ar5416FillCapabilityInfo() 319 * starting from griffin. Set here to make sure that 320 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 321 * placed into hardware. 322 */ 323 if (ahp->ah_miscMode != 0) 324 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 325 326 ar9280AniSetup(ah); /* Anti Noise Immunity */ 327 328 /* Setup noise floor min/max/nominal values */ 329 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 330 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 331 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 332 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 333 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 334 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 335 336 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 337 338 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 339 340 return ah; 341bad: 342 if (ah != AH_NULL) 343 ah->ah_detach(ah); 344 if (status) 345 *status = ecode; 346 return AH_NULL; 347} 348 349static void 350ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 351{ 352 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 353 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 354 OS_DELAY(1000); 355 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 356 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 357 } 358} 359 360static void 361ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 362{ 363 u_int modesIndex, freqIndex; 364 int regWrites = 0; 365 366 /* Setup the indices for the next set of register array writes */ 367 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 368 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 369 freqIndex = 2; 370 if (IEEE80211_IS_CHAN_HT40(chan)) 371 modesIndex = 3; 372 else if (IEEE80211_IS_CHAN_108G(chan)) 373 modesIndex = 5; 374 else 375 modesIndex = 4; 376 } else { 377 freqIndex = 1; 378 if (IEEE80211_IS_CHAN_HT40(chan) || 379 IEEE80211_IS_CHAN_TURBO(chan)) 380 modesIndex = 2; 381 else 382 modesIndex = 1; 383 } 384 385 /* Set correct Baseband to analog shift setting to access analog chips. */ 386 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 387 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 388 389 /* XXX Merlin ini fixups */ 390 /* XXX Merlin 100us delay for shift registers */ 391 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 392 modesIndex, regWrites); 393 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 394 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 395 modesIndex, regWrites); 396 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 397 modesIndex, regWrites); 398 } 399 /* XXX Merlin 100us delay for shift registers */ 400 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 401 1, regWrites); 402 403 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 404 /* 5GHz channels w/ Fast Clock use different modal values */ 405 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 406 modesIndex, regWrites); 407 } 408} 409 410#define AR_BASE_FREQ_2GHZ 2300 411#define AR_BASE_FREQ_5GHZ 4900 412#define AR_SPUR_FEEQ_BOUND_HT40 19 413#define AR_SPUR_FEEQ_BOUND_HT20 10 414 415void 416ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 417{ 418 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 419 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 420 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 421 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 422 static int inc[4] = { 0, 100, 0, 0 }; 423 424 int bb_spur = AR_NO_SPUR; 425 int freq; 426 int bin, cur_bin; 427 int bb_spur_off, spur_subchannel_sd; 428 int spur_freq_sd; 429 int spur_delta_phase; 430 int denominator; 431 int upper, lower, cur_vit_mask; 432 int tmp, newVal; 433 int i; 434 CHAN_CENTERS centers; 435 436 int8_t mask_m[123]; 437 int8_t mask_p[123]; 438 int8_t mask_amt; 439 int tmp_mask; 440 int cur_bb_spur; 441 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 442 443 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 444 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 445 446 ar5416GetChannelCenters(ah, chan, ¢ers); 447 freq = centers.synth_center; 448 449 /* 450 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 451 * otherwise spur is out-of-band and can be ignored. 452 */ 453 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 454 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 455 /* Get actual spur freq in MHz from EEPROM read value */ 456 if (is2GHz) { 457 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 458 } else { 459 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 460 } 461 462 if (AR_NO_SPUR == cur_bb_spur) 463 break; 464 cur_bb_spur = cur_bb_spur - freq; 465 466 if (IEEE80211_IS_CHAN_HT40(chan)) { 467 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 468 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 469 bb_spur = cur_bb_spur; 470 break; 471 } 472 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 473 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 474 bb_spur = cur_bb_spur; 475 break; 476 } 477 } 478 479 if (AR_NO_SPUR == bb_spur) { 480#if 1 481 /* 482 * MRC CCK can interfere with beacon detection and cause deaf/mute. 483 * Disable MRC CCK for now. 484 */ 485 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 486#else 487 /* Enable MRC CCK if no spur is found in this channel. */ 488 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 489#endif 490 return; 491 } else { 492 /* 493 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 494 * is found in this channel. 495 */ 496 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 497 } 498 499 bin = bb_spur * 320; 500 501 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 502 503 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 504 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 505 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 506 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 507 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 508 509 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 510 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 511 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 512 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 513 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 514 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 515 516 /* Pick control or extn channel to cancel the spur */ 517 if (IEEE80211_IS_CHAN_HT40(chan)) { 518 if (bb_spur < 0) { 519 spur_subchannel_sd = 1; 520 bb_spur_off = bb_spur + 10; 521 } else { 522 spur_subchannel_sd = 0; 523 bb_spur_off = bb_spur - 10; 524 } 525 } else { 526 spur_subchannel_sd = 0; 527 bb_spur_off = bb_spur; 528 } 529 530 /* 531 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 532 * /80 for dyn2040. 533 */ 534 if (IEEE80211_IS_CHAN_HT40(chan)) 535 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 536 else 537 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 538 539 /* 540 * in 11A mode the denominator of spur_freq_sd should be 40 and 541 * it should be 44 in 11G 542 */ 543 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 544 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 545 546 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 547 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 548 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 549 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 550 551 /* Choose to cancel between control and extension channels */ 552 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 553 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 554 555 /* 556 * ============================================ 557 * Set Pilot and Channel Masks 558 * 559 * pilot mask 1 [31:0] = +6..-26, no 0 bin 560 * pilot mask 2 [19:0] = +26..+7 561 * 562 * channel mask 1 [31:0] = +6..-26, no 0 bin 563 * channel mask 2 [19:0] = +26..+7 564 */ 565 cur_bin = -6000; 566 upper = bin + 100; 567 lower = bin - 100; 568 569 for (i = 0; i < 4; i++) { 570 int pilot_mask = 0; 571 int chan_mask = 0; 572 int bp = 0; 573 for (bp = 0; bp < 30; bp++) { 574 if ((cur_bin > lower) && (cur_bin < upper)) { 575 pilot_mask = pilot_mask | 0x1 << bp; 576 chan_mask = chan_mask | 0x1 << bp; 577 } 578 cur_bin += 100; 579 } 580 cur_bin += inc[i]; 581 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 582 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 583 } 584 585 /* ================================================= 586 * viterbi mask 1 based on channel magnitude 587 * four levels 0-3 588 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 589 * [1 2 2 1] for -9.6 or [1 2 1] for +16 590 * - enable_mask_ppm, all bins move with freq 591 * 592 * - mask_select, 8 bits for rates (reg 67,0x990c) 593 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 594 * choose which mask to use mask or mask2 595 */ 596 597 /* 598 * viterbi mask 2 2nd set for per data rate puncturing 599 * four levels 0-3 600 * - mask_select, 8 bits for rates (reg 67) 601 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 602 * [1 2 2 1] for -9.6 or [1 2 1] for +16 603 */ 604 cur_vit_mask = 6100; 605 upper = bin + 120; 606 lower = bin - 120; 607 608 for (i = 0; i < 123; i++) { 609 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 610 if ((abs(cur_vit_mask - bin)) < 75) { 611 mask_amt = 1; 612 } else { 613 mask_amt = 0; 614 } 615 if (cur_vit_mask < 0) { 616 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 617 } else { 618 mask_p[cur_vit_mask / 100] = mask_amt; 619 } 620 } 621 cur_vit_mask -= 100; 622 } 623 624 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 625 | (mask_m[48] << 26) | (mask_m[49] << 24) 626 | (mask_m[50] << 22) | (mask_m[51] << 20) 627 | (mask_m[52] << 18) | (mask_m[53] << 16) 628 | (mask_m[54] << 14) | (mask_m[55] << 12) 629 | (mask_m[56] << 10) | (mask_m[57] << 8) 630 | (mask_m[58] << 6) | (mask_m[59] << 4) 631 | (mask_m[60] << 2) | (mask_m[61] << 0); 632 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 633 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 634 635 tmp_mask = (mask_m[31] << 28) 636 | (mask_m[32] << 26) | (mask_m[33] << 24) 637 | (mask_m[34] << 22) | (mask_m[35] << 20) 638 | (mask_m[36] << 18) | (mask_m[37] << 16) 639 | (mask_m[48] << 14) | (mask_m[39] << 12) 640 | (mask_m[40] << 10) | (mask_m[41] << 8) 641 | (mask_m[42] << 6) | (mask_m[43] << 4) 642 | (mask_m[44] << 2) | (mask_m[45] << 0); 643 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 644 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 645 646 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 647 | (mask_m[18] << 26) | (mask_m[18] << 24) 648 | (mask_m[20] << 22) | (mask_m[20] << 20) 649 | (mask_m[22] << 18) | (mask_m[22] << 16) 650 | (mask_m[24] << 14) | (mask_m[24] << 12) 651 | (mask_m[25] << 10) | (mask_m[26] << 8) 652 | (mask_m[27] << 6) | (mask_m[28] << 4) 653 | (mask_m[29] << 2) | (mask_m[30] << 0); 654 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 655 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 656 657 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 658 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 659 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 660 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 661 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 662 | (mask_m[10] << 10) | (mask_m[11] << 8) 663 | (mask_m[12] << 6) | (mask_m[13] << 4) 664 | (mask_m[14] << 2) | (mask_m[15] << 0); 665 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 666 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 667 668 tmp_mask = (mask_p[15] << 28) 669 | (mask_p[14] << 26) | (mask_p[13] << 24) 670 | (mask_p[12] << 22) | (mask_p[11] << 20) 671 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 672 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 673 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 674 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 675 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 676 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 677 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 678 679 tmp_mask = (mask_p[30] << 28) 680 | (mask_p[29] << 26) | (mask_p[28] << 24) 681 | (mask_p[27] << 22) | (mask_p[26] << 20) 682 | (mask_p[25] << 18) | (mask_p[24] << 16) 683 | (mask_p[23] << 14) | (mask_p[22] << 12) 684 | (mask_p[21] << 10) | (mask_p[20] << 8) 685 | (mask_p[19] << 6) | (mask_p[18] << 4) 686 | (mask_p[17] << 2) | (mask_p[16] << 0); 687 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 688 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 689 690 tmp_mask = (mask_p[45] << 28) 691 | (mask_p[44] << 26) | (mask_p[43] << 24) 692 | (mask_p[42] << 22) | (mask_p[41] << 20) 693 | (mask_p[40] << 18) | (mask_p[39] << 16) 694 | (mask_p[38] << 14) | (mask_p[37] << 12) 695 | (mask_p[36] << 10) | (mask_p[35] << 8) 696 | (mask_p[34] << 6) | (mask_p[33] << 4) 697 | (mask_p[32] << 2) | (mask_p[31] << 0); 698 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 699 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 700 701 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 702 | (mask_p[59] << 26) | (mask_p[58] << 24) 703 | (mask_p[57] << 22) | (mask_p[56] << 20) 704 | (mask_p[55] << 18) | (mask_p[54] << 16) 705 | (mask_p[53] << 14) | (mask_p[52] << 12) 706 | (mask_p[51] << 10) | (mask_p[50] << 8) 707 | (mask_p[49] << 6) | (mask_p[48] << 4) 708 | (mask_p[47] << 2) | (mask_p[46] << 0); 709 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 710 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 711} 712 713/* 714 * Fill all software cached or static hardware state information. 715 * Return failure if capabilities are to come from EEPROM and 716 * cannot be read. 717 */ 718static HAL_BOOL 719ar9280FillCapabilityInfo(struct ath_hal *ah) 720{ 721 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 722 723 if (!ar5416FillCapabilityInfo(ah)) 724 return AH_FALSE; 725 pCap->halNumGpioPins = 10; 726 pCap->halWowSupport = AH_TRUE; 727 pCap->halWowMatchPatternExact = AH_TRUE; 728#if 0 729 pCap->halWowMatchPatternDword = AH_TRUE; 730#endif 731 /* AR9280 is a 2x2 stream device */ 732 pCap->halTxStreams = 2; 733 pCap->halRxStreams = 2; 734 735 pCap->halCSTSupport = AH_TRUE; 736 pCap->halRifsRxSupport = AH_TRUE; 737 pCap->halRifsTxSupport = AH_TRUE; 738 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 739 pCap->halExtChanDfsSupport = AH_TRUE; 740#if 0 741 /* XXX bluetooth */ 742 pCap->halBtCoexSupport = AH_TRUE; 743#endif 744 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 745 pCap->hal4kbSplitTransSupport = AH_FALSE; 746 pCap->halRxStbcSupport = 1; 747 pCap->halTxStbcSupport = 1; 748 749 return AH_TRUE; 750} 751 752/* 753 * This has been disabled - having the HAL flip chainmasks on/off 754 * when attempting to implement 11n disrupts things. For now, just 755 * leave this flipped off and worry about implementing TX diversity 756 * for legacy and MCS0-7 when 11n is fully functioning. 757 */ 758HAL_BOOL 759ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 760{ 761#define ANTENNA0_CHAINMASK 0x1 762#define ANTENNA1_CHAINMASK 0x2 763#if 0 764 struct ath_hal_5416 *ahp = AH5416(ah); 765 766 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 767 switch (settings) { 768 case HAL_ANT_FIXED_A: 769 /* Enable first antenna only */ 770 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 771 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 772 break; 773 case HAL_ANT_FIXED_B: 774 /* Enable second antenna only, after checking capability */ 775 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 776 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 777 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 778 break; 779 case HAL_ANT_VARIABLE: 780 /* Restore original chainmask settings */ 781 /* XXX */ 782 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 783 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 784 break; 785 } 786 787 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 788 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 789 790#endif 791 return AH_TRUE; 792#undef ANTENNA0_CHAINMASK 793#undef ANTENNA1_CHAINMASK 794} 795 796static const char* 797ar9280Probe(uint16_t vendorid, uint16_t devid) 798{ 799 if (vendorid == ATHEROS_VENDOR_ID && 800 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 801 return "Atheros 9280"; 802 return AH_NULL; 803} 804AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 805