1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203159Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416PHY_H_ 20185377Ssam#define _DEV_ATH_AR5416PHY_H_ 21185377Ssam 22185377Ssam#include "ar5212/ar5212phy.h" 23185377Ssam 24222584Sadrian/* For AR_PHY_RADAR0 */ 25222584Sadrian#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 26222584Sadrian 27222584Sadrian#define AR_PHY_RADAR_EXT 0x9940 28222584Sadrian#define AR_PHY_RADAR_EXT_ENA 0x00004000 29222584Sadrian 30222584Sadrian#define AR_PHY_RADAR_1 0x9958 31222584Sadrian#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 32222584Sadrian#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 33222584Sadrian#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 34222584Sadrian#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 35222584Sadrian#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 36222584Sadrian#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 37222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 38222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 39222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 40222584Sadrian#define AR_PHY_RADAR_1_MAXLEN 0x000000FF 41222584Sadrian#define AR_PHY_RADAR_1_MAXLEN_S 0 42222584Sadrian 43185377Ssam#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 44185377Ssam#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 45185377Ssam 46185377Ssam#define RFSILENT_BB 0x00002000 /* shush bb */ 47185377Ssam#define AR_PHY_RESTART 0x9970 /* restart */ 48185377Ssam#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 49185377Ssam#define AR_PHY_RESTART_DIV_GC_S 18 50185377Ssam 51185377Ssam/* PLL settling times */ 52185377Ssam#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 53185377Ssam#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */ 54185377Ssam 55185377Ssam#define AR_PHY_RFBUS_REQ 0x997C 56185377Ssam#define AR_PHY_RFBUS_REQ_EN 0x00000001 57185377Ssam 58185377Ssam#define AR_2040_MODE 0x8318 59185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 60185377Ssam 61185377Ssam#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 62185377Ssam#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ 63185377Ssam#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 64185377Ssam#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 65185377Ssam#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 66185377Ssam#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ 67185377Ssam#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 68185377Ssam#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 69185377Ssam#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 70203682Srpaulo#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 71185377Ssam 72185377Ssam#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ 73185377Ssam#define AR_PHY_TIMING2_USE_FORCE 0x00001000 74185377Ssam#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff 75185377Ssam 76185377Ssam#define AR_PHY_TIMING_CTRL4_CHAIN(_i) \ 77185377Ssam (AR_PHY_TIMING_CTRL4 + ((_i) << 12)) 78185377Ssam#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */ 79185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ 80185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 81185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ 82185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 83185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ 84185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 85185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 86185377Ssam 87185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 88185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */ 89185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 90185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 91185377Ssam 92185377Ssam#define AR_PHY_ADC_SERIAL_CTL 0x9830 93185377Ssam#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 94185377Ssam#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 95185377Ssam 96185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 97185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 98185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 99185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 100185377Ssam 101203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 102203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 103203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 104203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 105203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 106203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 107203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 108203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 109203682Srpaulo 110203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 111203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 112203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 113203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 114203682Srpaulo 115221878Sadrian#define AR_PHY_SEARCH_START_DELAY 0x9918 /* search start delay */ 116221878Sadrian 117185377Ssam#define AR_PHY_EXT_CCA 0x99bc 118185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 119185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 120185377Ssam#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 121185377Ssam#define AR_PHY_EXT_MINCCA_PWR_S 23 122185377Ssam#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 123185377Ssam#define AR_PHY_EXT_CCA_THRESH62_S 16 124221600Sadrian/* 125221600Sadrian * This duplicates AR_PHY_EXT_CCA_CYCPWR_THR1; it reads more like 126221600Sadrian * an ANI register this way. 127221600Sadrian */ 128221600Sadrian#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00 129221600Sadrian#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9 130221600Sadrian 131185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 132185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR_S 16 133185377Ssam 134185377Ssam#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */ 135185377Ssam#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 136185377Ssam#define AR_PHY_HALFGI_DSC_MAN_S 4 137185377Ssam#define AR_PHY_HALFGI_DSC_EXP 0x0000000F 138185377Ssam#define AR_PHY_HALFGI_DSC_EXP_S 0 139185377Ssam 140185377Ssam#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 141185377Ssam 142208711Srpaulo#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 143208711Srpaulo#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 144208711Srpaulo 145185377Ssam#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 146185377Ssam#define AR_PHY_REFCLKDLY 0x99f4 147185377Ssam#define AR_PHY_REFCLKPD 0x99f8 148185377Ssam 149185377Ssam#define AR_PHY_CALMODE 0x99f0 150185377Ssam/* Calibration Types */ 151185377Ssam#define AR_PHY_CALMODE_IQ 0x00000000 152185377Ssam#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 153185377Ssam#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 154185377Ssam#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 155185377Ssam/* Calibration results */ 156185377Ssam#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 157185377Ssam#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 158185377Ssam#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 159185377Ssam#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 160185377Ssam 161185377Ssam 162185377Ssam#define AR_PHY_CCA 0x9864 163185377Ssam#define AR_PHY_MINCCA_PWR 0x0FF80000 164185377Ssam#define AR_PHY_MINCCA_PWR_S 19 165185377Ssam#define AR9280_PHY_MINCCA_PWR 0x1FF00000 166185377Ssam#define AR9280_PHY_MINCCA_PWR_S 20 167185377Ssam#define AR9280_PHY_CCA_THRESH62 0x000FF000 168185377Ssam#define AR9280_PHY_CCA_THRESH62_S 12 169185377Ssam 170185377Ssam#define AR_PHY_CH1_CCA 0xa864 171185377Ssam#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 172185377Ssam#define AR_PHY_CH1_MINCCA_PWR_S 19 173185377Ssam#define AR_PHY_CCA_THRESH62 0x0007F000 174185377Ssam#define AR_PHY_CCA_THRESH62_S 12 175185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 176185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR_S 20 177185377Ssam 178185377Ssam#define AR_PHY_CH2_CCA 0xb864 179185377Ssam#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 180185377Ssam#define AR_PHY_CH2_MINCCA_PWR_S 19 181185377Ssam 182185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 183185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 184185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 185185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 186185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 187185377Ssam 188185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 189185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 190185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 191185377Ssam 192185377Ssam#define AR_PHY_RX_CHAINMASK 0x99a4 193185377Ssam 194185377Ssam#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 195185377Ssam#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 196185377Ssam#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 197185377Ssam#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 198185377Ssam 199185377Ssam#define AR_PHY_EXT_CCA0 0x99b8 200185377Ssam#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 201185377Ssam#define AR_PHY_EXT_CCA0_THRESH62_S 0 202185377Ssam 203185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 204185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 205185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 206185377Ssam 207185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 208185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 209185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 210185377Ssam#define AR_PHY_ANALOG_SWAP 0xa268 211185377Ssam#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 212185377Ssam#define AR_PHY_CAL_CHAINMASK 0xa39c 213185377Ssam 214185377Ssam#define AR_PHY_SWITCH_CHAIN_0 0x9960 215185377Ssam#define AR_PHY_SWITCH_COM 0x9964 216185377Ssam 217185377Ssam#define AR_PHY_RF_CTL2 0x9824 218185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF 219185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START_S 0 220185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00 221185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON_S 8 222185377Ssam 223185377Ssam#define AR_PHY_RF_CTL3 0x9828 224185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 225185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 226185377Ssam 227185377Ssam#define AR_PHY_RF_CTL4 0x9834 228185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 229185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 230185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 231185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 232185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 233185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 234185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 235185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 236185377Ssam 237185377Ssam#define AR_PHY_SYNTH_CONTROL 0x9874 238185377Ssam 239185377Ssam#define AR_PHY_FORCE_CLKEN_CCK 0xA22C 240185377Ssam#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 241185377Ssam 242185377Ssam#define AR_PHY_POWER_TX_SUB 0xA3C8 243185377Ssam#define AR_PHY_POWER_TX_RATE5 0xA38C 244185377Ssam#define AR_PHY_POWER_TX_RATE6 0xA390 245185377Ssam#define AR_PHY_POWER_TX_RATE7 0xA3CC 246185377Ssam#define AR_PHY_POWER_TX_RATE8 0xA3D0 247185377Ssam#define AR_PHY_POWER_TX_RATE9 0xA3D4 248185377Ssam 249185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 250185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 251185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 252185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 253185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 254185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 255185377Ssam 256203159Srpaulo#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 257203159Srpaulo#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 258203159Srpaulo 259185377Ssam#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 260185377Ssam#define AR_PHY_MASK2_M_31_45 0xa3a4 261185377Ssam#define AR_PHY_MASK2_M_16_30 0xa3a8 262185377Ssam#define AR_PHY_MASK2_M_00_15 0xa3ac 263185377Ssam#define AR_PHY_MASK2_P_15_01 0xa3b8 264185377Ssam#define AR_PHY_MASK2_P_30_16 0xa3bc 265185377Ssam#define AR_PHY_MASK2_P_45_31 0xa3c0 266185377Ssam#define AR_PHY_MASK2_P_61_45 0xa3c4 267185377Ssam 268185377Ssam#define AR_PHY_SPUR_REG 0x994c 269185377Ssam#define AR_PHY_SFCORR_EXT 0x99c0 270185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 271185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 272185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 273185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 274185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 275185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 276185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 277185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 278185377Ssam#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 279185377Ssam 280185377Ssam/* enable vit puncture per rate, 8 bits, lsb is low rate */ 281185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 282185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 283185377Ssam 284185377Ssam#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 285185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 286185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 287185377Ssam#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 288185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 289185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 290185377Ssam 291185377Ssam#define AR_PHY_PILOT_MASK_01_30 0xa3b0 292185377Ssam#define AR_PHY_PILOT_MASK_31_60 0xa3b4 293185377Ssam 294185377Ssam#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 295185377Ssam#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 296185377Ssam 297185380Ssam#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */ 298185380Ssam#define AR_PHY_CL_CAL_ENABLE 0x00000002 299203159Srpaulo#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 300218068Sadrian 301218068Sadrian/* empirically determined "good" CCA value ranges from atheros */ 302218068Sadrian#define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90 303218068Sadrian#define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100 304218068Sadrian#define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100 305218068Sadrian#define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110 306218068Sadrian#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80 307218068Sadrian#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90 308218068Sadrian 309218420Sadrian/* ar9280 specific? */ 310218420Sadrian#define AR_PHY_XPA_CFG 0xA3D8 311218420Sadrian#define AR_PHY_FORCE_XPA_CFG 0x000000001 312218420Sadrian#define AR_PHY_FORCE_XPA_CFG_S 0 313218420Sadrian 314218420Sadrian#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 315218420Sadrian#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 316218420Sadrian 317218420Sadrian#define AR_PHY_TX_PWRCTRL9 0xa27C 318218420Sadrian#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 319218420Sadrian#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 320218420Sadrian#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 321218420Sadrian#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 322218420Sadrian 323222301Sadrian#define AR_PHY_MODE_ASYNCFIFO 0x80 /* Enable async fifo */ 324222301Sadrian 325185377Ssam#endif /* _DEV_ATH_AR5416PHY_H_ */ 326