1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187611Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ah_eeprom_v14.h" 26185377Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 32185377Ssam#define EEP_MINOR(_ah) \ 33185377Ssam (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 34185377Ssam#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 35185377Ssam#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 36185377Ssam 37185377Ssam/* Additional Time delay to wait after activiting the Base band */ 38185377Ssam#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 39185377Ssam#define PLL_SETTLE_DELAY 300 /* 300 usec */ 40185377Ssam#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 41185377Ssam 42185377Ssamstatic void ar5416InitDMA(struct ath_hal *ah); 43187831Ssamstatic void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *); 44185377Ssamstatic void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); 45185377Ssamstatic void ar5416InitQoS(struct ath_hal *ah); 46185377Ssamstatic void ar5416InitUserSettings(struct ath_hal *ah); 47217930Sadrianstatic void ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht); 48219218Sadrianstatic void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *); 49185377Ssam 50185377Ssam#if 0 51187831Ssamstatic HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *); 52185377Ssam#endif 53187831Ssamstatic void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *); 54185377Ssam 55185377Ssamstatic HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); 56185377Ssamstatic HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); 57185377Ssamstatic HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, 58185377Ssam struct ar5416eeprom *pEepData, 59187831Ssam const struct ieee80211_channel *chan, int16_t *ratesArray, 60185377Ssam uint16_t cfgCtl, uint16_t AntennaReduction, 61185377Ssam uint16_t twiceMaxRegulatoryPower, 62185377Ssam uint16_t powerLimit); 63187831Ssamstatic void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan); 64220738Sadrianstatic void ar5416MarkPhyInactive(struct ath_hal *ah); 65185377Ssam 66185377Ssam/* 67185377Ssam * Places the device in and out of reset and then places sane 68185377Ssam * values in the registers based on EEPROM config, initialization 69185377Ssam * vectors (as determined by the mode), and station configuration 70185377Ssam * 71185377Ssam * bChannelChange is used to preserve DMA/PCU registers across 72185377Ssam * a HW Reset during channel change. 73185377Ssam */ 74185377SsamHAL_BOOL 75185377Ssamar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 76187831Ssam struct ieee80211_channel *chan, 77187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status) 78185377Ssam{ 79185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 80185377Ssam#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 81185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 82185377Ssam HAL_CHANNEL_INTERNAL *ichan; 83185377Ssam uint32_t saveDefAntenna, saveLedState; 84185377Ssam uint32_t macStaId1; 85185377Ssam uint16_t rfXpdGain[2]; 86185377Ssam HAL_STATUS ecode; 87185377Ssam uint32_t powerVal, rssiThrReg; 88185377Ssam uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 89189747Ssam int i; 90219419Sadrian uint64_t tsf = 0; 91185377Ssam 92185377Ssam OS_MARK(ah, AH_MARK_RESET, bChannelChange); 93185377Ssam 94185377Ssam /* Bring out of sleep mode */ 95185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 96185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 97185377Ssam __func__); 98195135Sphk FAIL(HAL_EIO); 99185377Ssam } 100185377Ssam 101185377Ssam /* 102185377Ssam * Map public channel to private. 103185377Ssam */ 104185377Ssam ichan = ath_hal_checkchannel(ah, chan); 105187831Ssam if (ichan == AH_NULL) 106185377Ssam FAIL(HAL_EINVAL); 107185377Ssam switch (opmode) { 108185377Ssam case HAL_M_STA: 109185377Ssam case HAL_M_IBSS: 110185377Ssam case HAL_M_HOSTAP: 111185377Ssam case HAL_M_MONITOR: 112185377Ssam break; 113185377Ssam default: 114185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 115185377Ssam __func__, opmode); 116185377Ssam FAIL(HAL_EINVAL); 117185377Ssam break; 118185377Ssam } 119185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 120185377Ssam 121185377Ssam /* XXX Turn on fast channel change for 5416 */ 122185377Ssam /* 123185377Ssam * Preserve the bmiss rssi threshold and count threshold 124185377Ssam * across resets 125185377Ssam */ 126185377Ssam rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); 127185377Ssam /* If reg is zero, first time thru set to default val */ 128185377Ssam if (rssiThrReg == 0) 129185377Ssam rssiThrReg = INIT_RSSI_THR; 130185377Ssam 131185377Ssam /* 132185377Ssam * Preserve the antenna on a channel change 133185377Ssam */ 134185377Ssam saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 135185377Ssam if (saveDefAntenna == 0) /* XXX magic constants */ 136185377Ssam saveDefAntenna = 1; 137185377Ssam 138185377Ssam /* Save hardware flag before chip reset clears the register */ 139185377Ssam macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 140185377Ssam (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 141185377Ssam 142185377Ssam /* Save led state from pci config register */ 143185377Ssam saveLedState = OS_REG_READ(ah, AR_MAC_LED) & 144185377Ssam (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | 145185377Ssam AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); 146185377Ssam 147219419Sadrian /* For chips on which the RTC reset is done, save TSF before it gets cleared */ 148221163Sadrian if (AR_SREV_HOWL(ah) || 149221875Sadrian (AR_SREV_MERLIN(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))) 150225444Sadrian tsf = ar5416GetTsf64(ah); 151219419Sadrian 152220738Sadrian /* Mark PHY as inactive; marked active in ar5416InitBB() */ 153220738Sadrian ar5416MarkPhyInactive(ah); 154220738Sadrian 155185377Ssam if (!ar5416ChipReset(ah, chan)) { 156185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 157185377Ssam FAIL(HAL_EIO); 158185377Ssam } 159185377Ssam 160219419Sadrian /* Restore TSF */ 161219419Sadrian if (tsf) 162225444Sadrian ar5416SetTsf64(ah, tsf); 163219419Sadrian 164185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 165208711Srpaulo if (AR_SREV_MERLIN_10_OR_LATER(ah)) 166208711Srpaulo OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 167185377Ssam 168189747Ssam AH5416(ah)->ah_writeIni(ah, chan); 169185377Ssam 170222301Sadrian if(AR_SREV_KIWI_13_OR_LATER(ah) ) { 171222301Sadrian /* Enable ASYNC FIFO */ 172222301Sadrian OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 173222301Sadrian AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 174222301Sadrian OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 175222301Sadrian OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 176222301Sadrian AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 177222301Sadrian OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 178222301Sadrian AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 179222301Sadrian } 180222301Sadrian 181219218Sadrian /* Override ini values (that can be overriden in this fashion) */ 182219218Sadrian ar5416OverrideIni(ah, chan); 183219218Sadrian 184185377Ssam /* Setup 11n MAC/Phy mode registers */ 185187831Ssam ar5416Set11nRegs(ah, chan); 186185377Ssam 187185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 188185377Ssam 189221163Sadrian /* 190221163Sadrian * Some AR91xx SoC devices frequently fail to accept TSF writes 191221163Sadrian * right after the chip reset. When that happens, write a new 192221163Sadrian * value after the initvals have been applied, with an offset 193221163Sadrian * based on measured time difference 194221163Sadrian */ 195225444Sadrian if (AR_SREV_HOWL(ah) && (ar5416GetTsf64(ah) < tsf)) { 196221163Sadrian tsf += 1500; 197225444Sadrian ar5416SetTsf64(ah, tsf); 198221163Sadrian } 199221163Sadrian 200185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", 201185377Ssam __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); 202185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", 203185377Ssam __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); 204185377Ssam 205217879Sadrian /* 206217930Sadrian * Setup ah_tx_chainmask / ah_rx_chainmask before we fiddle 207217930Sadrian * with enabling the TX/RX radio chains. 208217930Sadrian */ 209217930Sadrian ar5416UpdateChainMasks(ah, IEEE80211_IS_CHAN_HT(chan)); 210217930Sadrian /* 211217879Sadrian * This routine swaps the analog chains - it should be done 212217879Sadrian * before any radio register twiddling is done. 213217879Sadrian */ 214217879Sadrian ar5416InitChainMasks(ah); 215221206Sadrian 216221837Sadrian /* Setup the open-loop power calibration if required */ 217221837Sadrian if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 218221837Sadrian AH5416(ah)->ah_olcInit(ah); 219221837Sadrian AH5416(ah)->ah_olcTempCompensation(ah); 220221837Sadrian } 221185377Ssam 222185377Ssam /* Setup the transmit power values. */ 223203930Srpaulo if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 224185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 225185377Ssam "%s: error init'ing transmit power\n", __func__); 226185377Ssam FAIL(HAL_EIO); 227185377Ssam } 228185377Ssam 229185377Ssam /* Write the analog registers */ 230189747Ssam if (!ahp->ah_rfHal->setRfRegs(ah, chan, 231189747Ssam IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) { 232185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 233185377Ssam "%s: ar5212SetRfRegs failed\n", __func__); 234185377Ssam FAIL(HAL_EIO); 235185377Ssam } 236185377Ssam 237185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 238187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan)) 239187831Ssam ar5416SetDeltaSlope(ah, chan); 240185377Ssam 241189747Ssam AH5416(ah)->ah_spurMitigate(ah, chan); 242185377Ssam 243185377Ssam /* Setup board specific options for EEPROM version 3 */ 244203930Srpaulo if (!ah->ah_setBoardValues(ah, chan)) { 245185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 246185377Ssam "%s: error setting board options\n", __func__); 247185377Ssam FAIL(HAL_EIO); 248185377Ssam } 249185377Ssam 250185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 251185377Ssam 252185377Ssam OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 253185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 254185377Ssam | macStaId1 255185377Ssam | AR_STA_ID1_RTS_USE_DEF 256185377Ssam | ahp->ah_staId1Defaults 257185377Ssam ); 258185377Ssam ar5212SetOperatingMode(ah, opmode); 259185377Ssam 260185377Ssam /* Set Venice BSSID mask according to current state */ 261185377Ssam OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 262185377Ssam OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 263185377Ssam 264185377Ssam /* Restore previous led state */ 265221479Sadrian if (AR_SREV_HOWL(ah)) 266221479Sadrian OS_REG_WRITE(ah, AR_MAC_LED, 267221479Sadrian AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ); 268221479Sadrian else 269221479Sadrian OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | 270221479Sadrian saveLedState); 271185377Ssam 272222301Sadrian /* Start TSF2 for generic timer 8-15 */ 273222301Sadrian#ifdef NOTYET 274222301Sadrian if (AR_SREV_KIWI(ah)) 275222301Sadrian ar5416StartTsf2(ah); 276222301Sadrian#endif 277222301Sadrian 278185377Ssam /* Restore previous antenna */ 279185377Ssam OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 280185377Ssam 281185377Ssam /* then our BSSID */ 282185377Ssam OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 283185377Ssam OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 284185377Ssam 285185377Ssam /* Restore bmiss rssi & count thresholds */ 286185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 287185377Ssam 288185377Ssam OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 289185377Ssam 290221766Sadrian /* Restore bmiss rssi & count thresholds */ 291221766Sadrian OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 292221766Sadrian 293187831Ssam if (!ar5212SetChannel(ah, chan)) 294185377Ssam FAIL(HAL_EIO); 295185377Ssam 296185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 297185377Ssam 298185377Ssam /* Set 1:1 QCU to DCU mapping for all queues */ 299185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 300185377Ssam OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 301185377Ssam 302185377Ssam ahp->ah_intrTxqs = 0; 303185377Ssam for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 304219770Sadrian ah->ah_resetTxQueue(ah, i); 305185377Ssam 306185377Ssam ar5416InitIMR(ah, opmode); 307185377Ssam ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 308185377Ssam ar5416InitQoS(ah); 309221617Sadrian /* This may override the AR_DIAG_SW register */ 310185377Ssam ar5416InitUserSettings(ah); 311185377Ssam 312222301Sadrian if (AR_SREV_KIWI_13_OR_LATER(ah)) { 313222301Sadrian /* 314222301Sadrian * Enable ASYNC FIFO 315222301Sadrian * 316222301Sadrian * If Async FIFO is enabled, the following counters change 317222301Sadrian * as MAC now runs at 117 Mhz instead of 88/44MHz when 318222301Sadrian * async FIFO is disabled. 319222301Sadrian * 320222301Sadrian * Overwrite the delay/timeouts initialized in ProcessIni() 321222301Sadrian * above. 322222301Sadrian */ 323222301Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 324222301Sadrian AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 325222301Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 326222301Sadrian AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 327222301Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 328222301Sadrian AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 329222301Sadrian 330222301Sadrian OS_REG_WRITE(ah, AR_TIME_OUT, 331222301Sadrian AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 332222301Sadrian OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 333222301Sadrian 334222301Sadrian OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 335222301Sadrian AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 336222301Sadrian OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 337222301Sadrian AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 338222301Sadrian } 339222301Sadrian 340222301Sadrian if (AR_SREV_KIWI_13_OR_LATER(ah)) { 341222301Sadrian /* Enable AGGWEP to accelerate encryption engine */ 342222301Sadrian OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 343222301Sadrian AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 344222301Sadrian } 345222301Sadrian 346222301Sadrian 347185377Ssam /* 348185377Ssam * disable seq number generation in hw 349185377Ssam */ 350185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 351185377Ssam OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 352185377Ssam 353185377Ssam ar5416InitDMA(ah); 354185377Ssam 355185377Ssam /* 356185377Ssam * program OBS bus to see MAC interrupts 357185377Ssam */ 358185377Ssam OS_REG_WRITE(ah, AR_OBS, 8); 359185377Ssam 360220188Sadrian#ifdef AH_AR5416_INTERRUPT_MITIGATION 361185377Ssam OS_REG_WRITE(ah, AR_MIRT, 0); 362219975Sadrian 363185377Ssam OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 364185377Ssam OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 365219975Sadrian OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 366219975Sadrian OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 367225444Sadrian#endif 368185377Ssam ar5416InitBB(ah, chan); 369185377Ssam 370185377Ssam /* Setup compression registers */ 371185377Ssam ar5212SetCompRegs(ah); /* XXX not needed? */ 372185377Ssam 373185377Ssam /* 374185377Ssam * 5416 baseband will check the per rate power table 375185377Ssam * and select the lower of the two 376185377Ssam */ 377185377Ssam ackTpcPow = 63; 378185377Ssam ctsTpcPow = 63; 379185377Ssam chirpTpcPow = 63; 380185377Ssam powerVal = SM(ackTpcPow, AR_TPC_ACK) | 381185377Ssam SM(ctsTpcPow, AR_TPC_CTS) | 382185377Ssam SM(chirpTpcPow, AR_TPC_CHIRP); 383185377Ssam OS_REG_WRITE(ah, AR_TPC, powerVal); 384185377Ssam 385185377Ssam if (!ar5416InitCal(ah, chan)) 386185377Ssam FAIL(HAL_ESELFTEST); 387185377Ssam 388217882Sadrian ar5416RestoreChainMask(ah); 389217882Sadrian 390185377Ssam AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 391185377Ssam 392187831Ssam if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 393187831Ssam chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 394185377Ssam 395221479Sadrian if (AR_SREV_HOWL(ah)) { 396221479Sadrian /* 397221479Sadrian * Enable the MBSSID block-ack fix for HOWL. 398221479Sadrian * This feature is only supported on Howl 1.4, but it is safe to 399221479Sadrian * set bit 22 of STA_ID1 on other Howl revisions (1.1, 1.2, 1.3), 400221479Sadrian * since bit 22 is unused in those Howl revisions. 401221479Sadrian */ 402221479Sadrian unsigned int reg; 403221479Sadrian reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22)); 404221479Sadrian OS_REG_WRITE(ah,AR_STA_ID1, reg); 405221479Sadrian ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg); 406221479Sadrian } 407221479Sadrian 408185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 409185377Ssam 410185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, 0); 411185377Ssam 412185377Ssam return AH_TRUE; 413185377Ssambad: 414185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 415187611Ssam if (status != AH_NULL) 416185377Ssam *status = ecode; 417185377Ssam return AH_FALSE; 418185377Ssam#undef FAIL 419185377Ssam#undef N 420185377Ssam} 421185377Ssam 422185377Ssam#if 0 423185377Ssam/* 424185377Ssam * This channel change evaluates whether the selected hardware can 425185377Ssam * perform a synthesizer-only channel change (no reset). If the 426185377Ssam * TX is not stopped, or the RFBus cannot be granted in the given 427185377Ssam * time, the function returns false as a reset is necessary 428185377Ssam */ 429185377SsamHAL_BOOL 430187831Ssamar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan) 431185377Ssam{ 432185377Ssam uint32_t ulCount; 433185377Ssam uint32_t data, synthDelay, qnum; 434185377Ssam uint16_t rfXpdGain[4]; 435185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 436185377Ssam HAL_CHANNEL_INTERNAL *ichan; 437185377Ssam 438185377Ssam /* 439185377Ssam * Map public channel to private. 440185377Ssam */ 441185377Ssam ichan = ath_hal_checkchannel(ah, chan); 442185377Ssam 443185377Ssam /* TX must be stopped or RF Bus grant will not work */ 444185377Ssam for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 445185377Ssam if (ar5212NumTxPending(ah, qnum)) { 446185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 447185377Ssam "%s: frames pending on queue %d\n", __func__, qnum); 448185377Ssam return AH_FALSE; 449185377Ssam } 450185377Ssam } 451185377Ssam 452185377Ssam /* 453185377Ssam * Kill last Baseband Rx Frame - Request analog bus grant 454185377Ssam */ 455185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); 456185377Ssam if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { 457185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n", 458185377Ssam __func__); 459185377Ssam return AH_FALSE; 460185377Ssam } 461185377Ssam 462185377Ssam ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ 463185377Ssam 464185377Ssam /* Change the synth */ 465187831Ssam if (!ar5212SetChannel(ah, chan)) 466185377Ssam return AH_FALSE; 467185377Ssam 468185377Ssam /* Setup the transmit power values. */ 469219474Sadrian if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 470185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 471185377Ssam "%s: error init'ing transmit power\n", __func__); 472185377Ssam return AH_FALSE; 473185377Ssam } 474185377Ssam 475185377Ssam /* 476185377Ssam * Wait for the frequency synth to settle (synth goes on 477185377Ssam * via PHY_ACTIVE_EN). Read the phy active delay register. 478185377Ssam * Value is in 100ns increments. 479185377Ssam */ 480185377Ssam data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 481185377Ssam if (IS_CHAN_CCK(ichan)) { 482185377Ssam synthDelay = (4 * data) / 22; 483185377Ssam } else { 484185377Ssam synthDelay = data / 10; 485185377Ssam } 486185377Ssam 487185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 488185377Ssam 489185377Ssam /* Release the RFBus Grant */ 490185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 491185377Ssam 492185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 493187831Ssam if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) { 494187831Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3); 495187831Ssam ar5212SetSpurMitigation(ah, chan); 496187831Ssam ar5416SetDeltaSlope(ah, chan); 497185377Ssam } 498185377Ssam 499185377Ssam /* XXX spur mitigation for Melin */ 500185377Ssam 501187831Ssam if (!IEEE80211_IS_CHAN_DFS(chan)) 502187831Ssam chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 503185377Ssam 504187831Ssam ichan->channel_time = 0; 505225444Sadrian ichan->tsf_last = ar5416GetTsf64(ah); 506187831Ssam ar5212TxEnable(ah, AH_TRUE); 507185377Ssam return AH_TRUE; 508185377Ssam} 509185377Ssam#endif 510185377Ssam 511185377Ssamstatic void 512185377Ssamar5416InitDMA(struct ath_hal *ah) 513185377Ssam{ 514204579Srpaulo struct ath_hal_5212 *ahp = AH5212(ah); 515185377Ssam 516185377Ssam /* 517185377Ssam * set AHB_MODE not to do cacheline prefetches 518185377Ssam */ 519185377Ssam OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 520185377Ssam 521185377Ssam /* 522185377Ssam * let mac dma reads be in 128 byte chunks 523185377Ssam */ 524185377Ssam OS_REG_WRITE(ah, AR_TXCFG, 525185377Ssam (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); 526185377Ssam 527185377Ssam /* 528185377Ssam * let mac dma writes be in 128 byte chunks 529185377Ssam */ 530185377Ssam OS_REG_WRITE(ah, AR_RXCFG, 531185377Ssam (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 532185377Ssam 533204521Srpaulo /* restore TX trigger level */ 534204521Srpaulo OS_REG_WRITE(ah, AR_TXCFG, 535204521Srpaulo (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | 536204579Srpaulo SM(ahp->ah_txTrigLev, AR_FTRIG)); 537185377Ssam 538185377Ssam /* 539185377Ssam * Setup receive FIFO threshold to hold off TX activities 540185377Ssam */ 541185377Ssam OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 542185377Ssam 543185377Ssam /* 544185377Ssam * reduce the number of usable entries in PCU TXBUF to avoid 545185377Ssam * wrap around. 546185377Ssam */ 547220294Sadrian if (AR_SREV_KITE(ah)) 548220294Sadrian /* 549220294Sadrian * For AR9285 the number of Fifos are reduced to half. 550220294Sadrian * So set the usable tx buf size also to half to 551220294Sadrian * avoid data/delimiter underruns 552220294Sadrian */ 553220294Sadrian OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 554220294Sadrian else 555220294Sadrian OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); 556185377Ssam} 557185377Ssam 558185377Ssamstatic void 559187831Ssamar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) 560185377Ssam{ 561185377Ssam uint32_t synthDelay; 562185377Ssam 563185377Ssam /* 564185377Ssam * Wait for the frequency synth to settle (synth goes on 565185377Ssam * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 566185377Ssam * Value is in 100ns increments. 567185377Ssam */ 568185377Ssam synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 569187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 570185377Ssam synthDelay = (4 * synthDelay) / 22; 571185377Ssam } else { 572185377Ssam synthDelay /= 10; 573185377Ssam } 574185377Ssam 575185377Ssam /* Turn on PLL on 5416 */ 576185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", 577187831Ssam __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz"); 578185377Ssam 579185377Ssam /* Activate the PHY (includes baseband activate and synthesizer on) */ 580185377Ssam OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 581185377Ssam 582185377Ssam /* 583185377Ssam * If the AP starts the calibration before the base band timeout 584185380Ssam * completes we could get rx_clear false triggering. Add an 585185380Ssam * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 586185377Ssam * does not happen. 587185377Ssam */ 588187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 589185377Ssam OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 590187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 591185377Ssam OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 592185377Ssam } else { 593185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 594185377Ssam } 595185377Ssam} 596185377Ssam 597185377Ssamstatic void 598185377Ssamar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) 599185377Ssam{ 600185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 601185377Ssam 602185377Ssam /* 603185377Ssam * Setup interrupt handling. Note that ar5212ResetTxQueue 604185377Ssam * manipulates the secondary IMR's as queues are enabled 605185377Ssam * and disabled. This is done with RMW ops to insure the 606185377Ssam * settings we make here are preserved. 607185377Ssam */ 608185377Ssam ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN 609185377Ssam | AR_IMR_RXERR | AR_IMR_RXORN 610185377Ssam | AR_IMR_BCNMISC; 611185377Ssam 612220188Sadrian#ifdef AH_AR5416_INTERRUPT_MITIGATION 613221163Sadrian ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM 614185377Ssam | AR_IMR_TXMINTR | AR_IMR_RXMINTR; 615185377Ssam#else 616221163Sadrian ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK; 617185377Ssam#endif 618221163Sadrian 619185377Ssam if (opmode == HAL_M_HOSTAP) 620185377Ssam ahp->ah_maskReg |= AR_IMR_MIB; 621185377Ssam OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 622221163Sadrian 623221163Sadrian#ifdef ADRIAN_NOTYET 624221163Sadrian /* This is straight from ath9k */ 625221163Sadrian if (! AR_SREV_HOWL(ah)) { 626221163Sadrian OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 627221163Sadrian OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 628221163Sadrian OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 629221163Sadrian } 630221163Sadrian#endif 631221163Sadrian 632185377Ssam /* Enable bus errors that are OR'd to set the HIUERR bit */ 633185377Ssam#if 0 634185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, 635187831Ssam OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); 636185377Ssam#endif 637185377Ssam} 638185377Ssam 639185377Ssamstatic void 640185377Ssamar5416InitQoS(struct ath_hal *ah) 641185377Ssam{ 642185377Ssam /* QoS support */ 643185377Ssam OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 644185377Ssam OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 645185377Ssam 646185377Ssam /* Turn on NOACK Support for QoS packets */ 647185377Ssam OS_REG_WRITE(ah, AR_NOACK, 648185377Ssam SM(2, AR_NOACK_2BIT_VALUE) | 649185377Ssam SM(5, AR_NOACK_BIT_OFFSET) | 650185377Ssam SM(0, AR_NOACK_BYTE_OFFSET)); 651185377Ssam 652185377Ssam /* 653185377Ssam * initialize TXOP for all TIDs 654185377Ssam */ 655185377Ssam OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 656185377Ssam OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 657185377Ssam OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 658185377Ssam OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 659185377Ssam OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 660185377Ssam} 661185377Ssam 662185377Ssamstatic void 663185377Ssamar5416InitUserSettings(struct ath_hal *ah) 664185377Ssam{ 665185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 666185377Ssam 667185377Ssam /* Restore user-specified settings */ 668185377Ssam if (ahp->ah_miscMode != 0) 669219771Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 670185377Ssam if (ahp->ah_sifstime != (u_int) -1) 671185377Ssam ar5212SetSifsTime(ah, ahp->ah_sifstime); 672185377Ssam if (ahp->ah_slottime != (u_int) -1) 673185377Ssam ar5212SetSlotTime(ah, ahp->ah_slottime); 674185377Ssam if (ahp->ah_acktimeout != (u_int) -1) 675185377Ssam ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 676185377Ssam if (ahp->ah_ctstimeout != (u_int) -1) 677185377Ssam ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 678185377Ssam if (AH_PRIVATE(ah)->ah_diagreg != 0) 679185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 680220772Sadrian if (AH5416(ah)->ah_globaltxtimeout != (u_int) -1) 681220772Sadrian ar5416SetGlobalTxTimeout(ah, AH5416(ah)->ah_globaltxtimeout); 682185377Ssam} 683185377Ssam 684219855Sadrianstatic void 685219855Sadrianar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan) 686219855Sadrian{ 687219855Sadrian uint32_t rfMode; 688219855Sadrian 689219855Sadrian if (chan == AH_NULL) 690219855Sadrian return; 691219855Sadrian 692219855Sadrian /* treat channel B as channel G , no B mode suport in owl */ 693219855Sadrian rfMode = IEEE80211_IS_CHAN_CCK(chan) ? 694219855Sadrian AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 695219855Sadrian 696219855Sadrian if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 697219855Sadrian /* phy mode bits for 5GHz channels require Fast Clock */ 698219855Sadrian rfMode |= AR_PHY_MODE_DYNAMIC 699219855Sadrian | AR_PHY_MODE_DYN_CCK_DISABLE; 700219855Sadrian } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { 701219855Sadrian rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ? 702219855Sadrian AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 703219855Sadrian } 704219855Sadrian OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 705219855Sadrian} 706219855Sadrian 707185377Ssam/* 708185377Ssam * Places the hardware into reset and then pulls it out of reset 709185377Ssam */ 710185377SsamHAL_BOOL 711187831Ssamar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 712185377Ssam{ 713187831Ssam OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 714185377Ssam /* 715185377Ssam * Warm reset is optimistic. 716185377Ssam */ 717221875Sadrian if (AR_SREV_MERLIN(ah) && 718185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 719185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 720185377Ssam return AH_FALSE; 721185377Ssam } else { 722185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) 723185377Ssam return AH_FALSE; 724185377Ssam } 725185377Ssam 726185377Ssam /* Bring out of sleep mode (AGAIN) */ 727185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 728185377Ssam return AH_FALSE; 729185377Ssam 730221620Sadrian#ifdef notyet 731221620Sadrian ahp->ah_chipFullSleep = AH_FALSE; 732221620Sadrian#endif 733221620Sadrian 734220990Sadrian AH5416(ah)->ah_initPLL(ah, chan); 735185377Ssam 736185377Ssam /* 737185377Ssam * Perform warm reset before the mode/PLL/turbo registers 738185377Ssam * are changed in order to deactivate the radio. Mode changes 739185377Ssam * with an active radio can result in corrupted shifts to the 740185377Ssam * radio device. 741185377Ssam */ 742221620Sadrian ar5416SetRfMode(ah, chan); 743189747Ssam 744185377Ssam return AH_TRUE; 745185377Ssam} 746185377Ssam 747185377Ssam/* 748185377Ssam * Delta slope coefficient computation. 749185377Ssam * Required for OFDM operation. 750185377Ssam */ 751185377Ssamstatic void 752185377Ssamar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, 753185377Ssam uint32_t *coef_mantissa, uint32_t *coef_exponent) 754185377Ssam{ 755185377Ssam#define COEF_SCALE_S 24 756185377Ssam uint32_t coef_exp, coef_man; 757185377Ssam /* 758185377Ssam * ALGO -> coef_exp = 14-floor(log2(coef)); 759185377Ssam * floor(log2(x)) is the highest set bit position 760185377Ssam */ 761185377Ssam for (coef_exp = 31; coef_exp > 0; coef_exp--) 762185377Ssam if ((coef_scaled >> coef_exp) & 0x1) 763185377Ssam break; 764185377Ssam /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 765185377Ssam HALASSERT(coef_exp); 766185377Ssam coef_exp = 14 - (coef_exp - COEF_SCALE_S); 767185377Ssam 768185377Ssam /* 769185377Ssam * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 770185377Ssam * The coefficient is already shifted up for scaling 771185377Ssam */ 772185377Ssam coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 773185377Ssam 774185377Ssam *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 775185377Ssam *coef_exponent = coef_exp - 16; 776185377Ssam 777185377Ssam#undef COEF_SCALE_S 778185377Ssam} 779185377Ssam 780185377Ssamvoid 781187831Ssamar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 782185377Ssam{ 783185377Ssam#define INIT_CLOCKMHZSCALED 0x64000000 784185377Ssam uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 785188975Ssam uint32_t clockMhzScaled; 786185377Ssam 787185377Ssam CHAN_CENTERS centers; 788185377Ssam 789185377Ssam /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 790185377Ssam /* scale for selected channel bandwidth */ 791188975Ssam clockMhzScaled = INIT_CLOCKMHZSCALED; 792188975Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 793188975Ssam clockMhzScaled <<= 1; 794188975Ssam else if (IEEE80211_IS_CHAN_HALF(chan)) 795188975Ssam clockMhzScaled >>= 1; 796188975Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 797188975Ssam clockMhzScaled >>= 2; 798185377Ssam 799185377Ssam /* 800185377Ssam * ALGO -> coef = 1e8/fcarrier*fclock/40; 801185377Ssam * scaled coef to provide precision for this floating calculation 802185377Ssam */ 803185377Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 804185377Ssam coef_scaled = clockMhzScaled / centers.synth_center; 805187831Ssam 806185377Ssam ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 807185377Ssam 808185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 809185377Ssam AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 810185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 811185377Ssam AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 812187831Ssam 813185377Ssam /* 814185377Ssam * For Short GI, 815185377Ssam * scaled coeff is 9/10 that of normal coeff 816185377Ssam */ 817185377Ssam coef_scaled = (9 * coef_scaled)/10; 818185377Ssam 819185377Ssam ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 820185377Ssam 821185377Ssam /* for short gi */ 822185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 823185377Ssam AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 824185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 825185377Ssam AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 826185377Ssam#undef INIT_CLOCKMHZSCALED 827185377Ssam} 828185377Ssam 829185377Ssam/* 830185377Ssam * Set a limit on the overall output power. Used for dynamic 831185377Ssam * transmit power control and the like. 832185377Ssam * 833185377Ssam * NB: limit is in units of 0.5 dbM. 834185377Ssam */ 835185377SsamHAL_BOOL 836185377Ssamar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 837185377Ssam{ 838185377Ssam uint16_t dummyXpdGains[2]; 839185377Ssam 840185377Ssam AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 841219474Sadrian return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan, 842185377Ssam dummyXpdGains); 843185377Ssam} 844185377Ssam 845185377SsamHAL_BOOL 846187831Ssamar5416GetChipPowerLimits(struct ath_hal *ah, 847187831Ssam struct ieee80211_channel *chan) 848185377Ssam{ 849185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 850185377Ssam int16_t minPower, maxPower; 851185377Ssam 852185377Ssam /* 853185377Ssam * Get Pier table max and min powers. 854185377Ssam */ 855187831Ssam if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 856187831Ssam /* NB: rf code returns 1/4 dBm units, convert */ 857187831Ssam chan->ic_maxpower = maxPower / 2; 858187831Ssam chan->ic_minpower = minPower / 2; 859187831Ssam } else { 860187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 861187831Ssam "%s: no min/max power for %u/0x%x\n", 862187831Ssam __func__, chan->ic_freq, chan->ic_flags); 863187831Ssam chan->ic_maxpower = AR5416_MAX_RATE_POWER; 864187831Ssam chan->ic_minpower = 0; 865185377Ssam } 866187831Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 867187831Ssam "Chan %d: MaxPow = %d MinPow = %d\n", 868187831Ssam chan->ic_freq, chan->ic_maxpower, chan->ic_minpower); 869185377Ssam return AH_TRUE; 870185377Ssam} 871185377Ssam 872185377Ssam/************************************************************** 873220988Sadrian * ar5416WriteTxPowerRateRegisters 874220988Sadrian * 875220988Sadrian * Write the TX power rate registers from the raw values given 876220988Sadrian * in ratesArray[]. 877220988Sadrian * 878220988Sadrian * The CCK and HT40 rate registers are only written if needed. 879220988Sadrian * HT20 and 11g/11a OFDM rate registers are always written. 880220988Sadrian * 881220988Sadrian * The values written are raw values which should be written 882220988Sadrian * to the registers - so it's up to the caller to pre-adjust 883220988Sadrian * them (eg CCK power offset value, or Merlin TX power offset, 884220988Sadrian * etc.) 885220988Sadrian */ 886220988Sadrianvoid 887220988Sadrianar5416WriteTxPowerRateRegisters(struct ath_hal *ah, 888220988Sadrian const struct ieee80211_channel *chan, const int16_t ratesArray[]) 889220988Sadrian{ 890220988Sadrian#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 891220988Sadrian 892220988Sadrian /* Write the OFDM power per rate set */ 893220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 894220988Sadrian POW_SM(ratesArray[rate18mb], 24) 895220988Sadrian | POW_SM(ratesArray[rate12mb], 16) 896220988Sadrian | POW_SM(ratesArray[rate9mb], 8) 897220988Sadrian | POW_SM(ratesArray[rate6mb], 0) 898220988Sadrian ); 899220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 900220988Sadrian POW_SM(ratesArray[rate54mb], 24) 901220988Sadrian | POW_SM(ratesArray[rate48mb], 16) 902220988Sadrian | POW_SM(ratesArray[rate36mb], 8) 903220988Sadrian | POW_SM(ratesArray[rate24mb], 0) 904220988Sadrian ); 905220988Sadrian 906220988Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) { 907220988Sadrian /* Write the CCK power per rate set */ 908220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 909220988Sadrian POW_SM(ratesArray[rate2s], 24) 910220988Sadrian | POW_SM(ratesArray[rate2l], 16) 911220988Sadrian | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 912220988Sadrian | POW_SM(ratesArray[rate1l], 0) 913220988Sadrian ); 914220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 915220988Sadrian POW_SM(ratesArray[rate11s], 24) 916220988Sadrian | POW_SM(ratesArray[rate11l], 16) 917220988Sadrian | POW_SM(ratesArray[rate5_5s], 8) 918220988Sadrian | POW_SM(ratesArray[rate5_5l], 0) 919220988Sadrian ); 920220988Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 921220988Sadrian "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 922220988Sadrian __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 923220988Sadrian OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 924220988Sadrian } 925220988Sadrian 926220988Sadrian /* Write the HT20 power per rate set */ 927220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 928220988Sadrian POW_SM(ratesArray[rateHt20_3], 24) 929220988Sadrian | POW_SM(ratesArray[rateHt20_2], 16) 930220988Sadrian | POW_SM(ratesArray[rateHt20_1], 8) 931220988Sadrian | POW_SM(ratesArray[rateHt20_0], 0) 932220988Sadrian ); 933220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 934220988Sadrian POW_SM(ratesArray[rateHt20_7], 24) 935220988Sadrian | POW_SM(ratesArray[rateHt20_6], 16) 936220988Sadrian | POW_SM(ratesArray[rateHt20_5], 8) 937220988Sadrian | POW_SM(ratesArray[rateHt20_4], 0) 938220988Sadrian ); 939220988Sadrian 940220988Sadrian if (IEEE80211_IS_CHAN_HT40(chan)) { 941220988Sadrian /* Write the HT40 power per rate set */ 942220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 943220988Sadrian POW_SM(ratesArray[rateHt40_3], 24) 944220988Sadrian | POW_SM(ratesArray[rateHt40_2], 16) 945220988Sadrian | POW_SM(ratesArray[rateHt40_1], 8) 946220988Sadrian | POW_SM(ratesArray[rateHt40_0], 0) 947220988Sadrian ); 948220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 949220988Sadrian POW_SM(ratesArray[rateHt40_7], 24) 950220988Sadrian | POW_SM(ratesArray[rateHt40_6], 16) 951220988Sadrian | POW_SM(ratesArray[rateHt40_5], 8) 952220988Sadrian | POW_SM(ratesArray[rateHt40_4], 0) 953220988Sadrian ); 954220988Sadrian /* Write the Dup/Ext 40 power per rate set */ 955220988Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 956220988Sadrian POW_SM(ratesArray[rateExtOfdm], 24) 957220988Sadrian | POW_SM(ratesArray[rateExtCck], 16) 958220988Sadrian | POW_SM(ratesArray[rateDupOfdm], 8) 959220988Sadrian | POW_SM(ratesArray[rateDupCck], 0) 960220988Sadrian ); 961220988Sadrian } 962220988Sadrian} 963220988Sadrian 964220988Sadrian 965220988Sadrian/************************************************************** 966185377Ssam * ar5416SetTransmitPower 967185377Ssam * 968185377Ssam * Set the transmit power in the baseband for the given 969185377Ssam * operating channel and mode. 970185377Ssam */ 971203930SrpauloHAL_BOOL 972187831Ssamar5416SetTransmitPower(struct ath_hal *ah, 973187831Ssam const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 974185377Ssam{ 975185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 976185377Ssam 977185377Ssam MODAL_EEP_HEADER *pModal; 978185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 979185377Ssam int16_t ratesArray[Ar5416RateSize]; 980185377Ssam int16_t txPowerIndexOffset = 0; 981185377Ssam uint8_t ht40PowerIncForPdadc = 2; 982185377Ssam int i; 983185377Ssam 984185377Ssam uint16_t cfgCtl; 985185377Ssam uint16_t powerLimit; 986185377Ssam uint16_t twiceAntennaReduction; 987185377Ssam uint16_t twiceMaxRegulatoryPower; 988185377Ssam int16_t maxPower; 989203882Srpaulo HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 990203882Srpaulo struct ar5416eeprom *pEepData = &ee->ee_base; 991185377Ssam 992185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 993185377Ssam 994185377Ssam /* Setup info for the actual eeprom */ 995191909Ssam OS_MEMZERO(ratesArray, sizeof(ratesArray)); 996187831Ssam cfgCtl = ath_hal_getctl(ah, chan); 997187831Ssam powerLimit = chan->ic_maxregpower * 2; 998187831Ssam twiceAntennaReduction = chan->ic_maxantgain; 999185377Ssam twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 1000203882Srpaulo pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1001185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 1002187831Ssam __func__,chan->ic_freq, cfgCtl ); 1003185377Ssam 1004185377Ssam if (IS_EEP_MINOR_V2(ah)) { 1005203882Srpaulo ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1006185377Ssam } 1007203882Srpaulo 1008203882Srpaulo if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, 1009185377Ssam &ratesArray[0],cfgCtl, 1010185377Ssam twiceAntennaReduction, 1011185377Ssam twiceMaxRegulatoryPower, powerLimit)) { 1012185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1013185377Ssam "%s: unable to set tx power per rate table\n", __func__); 1014185377Ssam return AH_FALSE; 1015185377Ssam } 1016185377Ssam 1017219393Sadrian if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 1018185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 1019185377Ssam __func__); 1020185377Ssam return AH_FALSE; 1021185377Ssam } 1022185377Ssam 1023185377Ssam maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 1024185377Ssam 1025187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1026185377Ssam maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 1027185377Ssam } 1028185377Ssam 1029187831Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 1030185377Ssam maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 1031185377Ssam } 1032185377Ssam 1033185377Ssam ahp->ah_tx6PowerInHalfDbm = maxPower; 1034185377Ssam AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 1035185377Ssam ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 1036185377Ssam 1037185377Ssam /* 1038185377Ssam * txPowerIndexOffset is set by the SetPowerTable() call - 1039185377Ssam * adjust the rate table (0 offset if rates EEPROM not loaded) 1040185377Ssam */ 1041185377Ssam for (i = 0; i < N(ratesArray); i++) { 1042185377Ssam ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1043185377Ssam if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1044185377Ssam ratesArray[i] = AR5416_MAX_RATE_POWER; 1045185377Ssam } 1046185377Ssam 1047185377Ssam#ifdef AH_EEPROM_DUMP 1048219393Sadrian /* 1049219393Sadrian * Dump the rate array whilst it represents the intended dBm*2 1050219393Sadrian * values versus what's being adjusted before being programmed 1051219393Sadrian * in. Keep this in mind if you code up this function and enable 1052219393Sadrian * this debugging; the values won't necessarily be what's being 1053219393Sadrian * programmed into the hardware. 1054219393Sadrian */ 1055185377Ssam ar5416PrintPowerPerRate(ah, ratesArray); 1056185377Ssam#endif 1057185377Ssam 1058219393Sadrian /* 1059219393Sadrian * Merlin and later have a power offset, so subtract 1060219393Sadrian * pwr_table_offset * 2 from each value. The default 1061219393Sadrian * power offset is -5 dBm - ie, a register value of 0 1062219393Sadrian * equates to a TX power of -5 dBm. 1063219393Sadrian */ 1064219393Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1065219393Sadrian int8_t pwr_table_offset; 1066219393Sadrian 1067219393Sadrian (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, 1068219393Sadrian &pwr_table_offset); 1069219393Sadrian /* Underflow power gets clamped at raw value 0 */ 1070219393Sadrian /* Overflow power gets camped at AR5416_MAX_RATE_POWER */ 1071219393Sadrian for (i = 0; i < N(ratesArray); i++) { 1072219393Sadrian /* 1073219393Sadrian * + pwr_table_offset is in dBm 1074219393Sadrian * + ratesArray is in 1/2 dBm 1075219393Sadrian */ 1076219393Sadrian ratesArray[i] -= (pwr_table_offset * 2); 1077219393Sadrian if (ratesArray[i] < 0) 1078219393Sadrian ratesArray[i] = 0; 1079219393Sadrian else if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1080219393Sadrian ratesArray[i] = AR5416_MAX_RATE_POWER; 1081219393Sadrian } 1082219393Sadrian } 1083219393Sadrian 1084219393Sadrian /* 1085219393Sadrian * Adjust rates for OLC where needed 1086219393Sadrian * 1087219393Sadrian * The following CCK rates need adjusting when doing 2.4ghz 1088219393Sadrian * CCK transmission. 1089219393Sadrian * 1090219393Sadrian * + rate2s, rate2l, rate1l, rate11s, rate11l, rate5_5s, rate5_5l 1091219393Sadrian * + rateExtCck, rateDupCck 1092219393Sadrian * 1093219393Sadrian * They're adjusted here regardless. The hardware then gets 1094219393Sadrian * programmed as needed. 5GHz operation doesn't program in CCK 1095219393Sadrian * rates for legacy mode but they seem to be initialised for 1096219393Sadrian * HT40 regardless of channel type. 1097219393Sadrian */ 1098219393Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah) && 1099219393Sadrian ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 1100219393Sadrian int adj[] = { 1101219393Sadrian rate2s, rate2l, rate1l, rate11s, rate11l, 1102219393Sadrian rate5_5s, rate5_5l, rateExtCck, rateDupCck 1103219393Sadrian }; 1104219393Sadrian int cck_ofdm_delta = 2; 1105219393Sadrian int i; 1106219393Sadrian for (i = 0; i < N(adj); i++) { 1107221876Sadrian ratesArray[adj[i]] -= cck_ofdm_delta; 1108221876Sadrian if (ratesArray[adj[i]] < 0) 1109221876Sadrian ratesArray[adj[i]] = 0; 1110219393Sadrian } 1111219393Sadrian } 1112219393Sadrian 1113220988Sadrian /* 1114220988Sadrian * Adjust the HT40 power to meet the correct target TX power 1115220988Sadrian * for 40MHz mode, based on TX power curves that are established 1116220988Sadrian * for 20MHz mode. 1117220988Sadrian * 1118220988Sadrian * XXX handle overflow/too high power level? 1119220988Sadrian */ 1120220988Sadrian if (IEEE80211_IS_CHAN_HT40(chan)) { 1121220988Sadrian ratesArray[rateHt40_0] += ht40PowerIncForPdadc; 1122220988Sadrian ratesArray[rateHt40_1] += ht40PowerIncForPdadc; 1123220988Sadrian ratesArray[rateHt40_2] += ht40PowerIncForPdadc; 1124220988Sadrian ratesArray[rateHt40_3] += ht40PowerIncForPdadc; 1125220988Sadrian ratesArray[rateHt40_4] += ht40PowerIncForPdadc; 1126220988Sadrian ratesArray[rateHt40_5] += ht40PowerIncForPdadc; 1127220988Sadrian ratesArray[rateHt40_6] += ht40PowerIncForPdadc; 1128220988Sadrian ratesArray[rateHt40_7] += ht40PowerIncForPdadc; 1129185377Ssam } 1130185377Ssam 1131220988Sadrian /* Write the TX power rate registers */ 1132220988Sadrian ar5416WriteTxPowerRateRegisters(ah, chan, ratesArray); 1133185377Ssam 1134185377Ssam /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ 1135203882Srpaulo OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1136203882Srpaulo POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1137203882Srpaulo | POW_SM(pModal->pwrDecreaseFor2Chain, 0) 1138203882Srpaulo ); 1139185377Ssam return AH_TRUE; 1140185377Ssam#undef POW_SM 1141185377Ssam#undef N 1142185377Ssam} 1143185377Ssam 1144185377Ssam/* 1145185377Ssam * Exported call to check for a recent gain reading and return 1146185377Ssam * the current state of the thermal calibration gain engine. 1147185377Ssam */ 1148185377SsamHAL_RFGAIN 1149185377Ssamar5416GetRfgain(struct ath_hal *ah) 1150185377Ssam{ 1151185377Ssam return HAL_RFGAIN_INACTIVE; 1152185377Ssam} 1153185377Ssam 1154185377Ssam/* 1155185377Ssam * Places all of hardware into reset 1156185377Ssam */ 1157185377SsamHAL_BOOL 1158185377Ssamar5416Disable(struct ath_hal *ah) 1159185377Ssam{ 1160185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1161185377Ssam return AH_FALSE; 1162221620Sadrian if (! ar5416SetResetReg(ah, HAL_RESET_COLD)) 1163221620Sadrian return AH_FALSE; 1164221620Sadrian 1165221620Sadrian AH5416(ah)->ah_initPLL(ah, AH_NULL); 1166221620Sadrian return AH_TRUE; 1167185377Ssam} 1168185377Ssam 1169185377Ssam/* 1170185377Ssam * Places the PHY and Radio chips into reset. A full reset 1171185377Ssam * must be called to leave this state. The PCI/MAC/PCU are 1172185377Ssam * not placed into reset as we must receive interrupt to 1173185377Ssam * re-enable the hardware. 1174185377Ssam */ 1175185377SsamHAL_BOOL 1176185377Ssamar5416PhyDisable(struct ath_hal *ah) 1177185377Ssam{ 1178221620Sadrian if (! ar5416SetResetReg(ah, HAL_RESET_WARM)) 1179221620Sadrian return AH_FALSE; 1180221620Sadrian 1181221620Sadrian AH5416(ah)->ah_initPLL(ah, AH_NULL); 1182221620Sadrian return AH_TRUE; 1183185377Ssam} 1184185377Ssam 1185185377Ssam/* 1186185377Ssam * Write the given reset bit mask into the reset register 1187185377Ssam */ 1188185377SsamHAL_BOOL 1189185377Ssamar5416SetResetReg(struct ath_hal *ah, uint32_t type) 1190185377Ssam{ 1191185377Ssam switch (type) { 1192185377Ssam case HAL_RESET_POWER_ON: 1193185377Ssam return ar5416SetResetPowerOn(ah); 1194185377Ssam case HAL_RESET_WARM: 1195185377Ssam case HAL_RESET_COLD: 1196185377Ssam return ar5416SetReset(ah, type); 1197185377Ssam default: 1198189747Ssam HALASSERT(AH_FALSE); 1199185377Ssam return AH_FALSE; 1200185377Ssam } 1201185377Ssam} 1202185377Ssam 1203185377Ssamstatic HAL_BOOL 1204185377Ssamar5416SetResetPowerOn(struct ath_hal *ah) 1205185377Ssam{ 1206185377Ssam /* Power On Reset (Hard Reset) */ 1207185377Ssam 1208185377Ssam /* 1209185377Ssam * Set force wake 1210185377Ssam * 1211185377Ssam * If the MAC was running, previously calling 1212185377Ssam * reset will wake up the MAC but it may go back to sleep 1213185377Ssam * before we can start polling. 1214185377Ssam * Set force wake stops that 1215185377Ssam * This must be called before initiating a hard reset. 1216185377Ssam */ 1217185377Ssam OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1218185377Ssam AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1219185377Ssam 1220185377Ssam /* 1221185377Ssam * RTC reset and clear 1222185377Ssam */ 1223221163Sadrian if (! AR_SREV_HOWL(ah)) 1224221163Sadrian OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1225185377Ssam OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1226185377Ssam OS_DELAY(20); 1227208711Srpaulo 1228221163Sadrian if (! AR_SREV_HOWL(ah)) 1229221163Sadrian OS_REG_WRITE(ah, AR_RC, 0); 1230221163Sadrian 1231185377Ssam OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1232185377Ssam 1233185377Ssam /* 1234185377Ssam * Poll till RTC is ON 1235185377Ssam */ 1236185377Ssam if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { 1237185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); 1238185377Ssam return AH_FALSE; 1239185377Ssam } 1240185377Ssam 1241185377Ssam return ar5416SetReset(ah, HAL_RESET_COLD); 1242185377Ssam} 1243185377Ssam 1244185377Ssamstatic HAL_BOOL 1245185377Ssamar5416SetReset(struct ath_hal *ah, int type) 1246185377Ssam{ 1247195426Ssam uint32_t tmpReg, mask; 1248221163Sadrian uint32_t rst_flags; 1249185377Ssam 1250221163Sadrian#ifdef AH_SUPPORT_AR9130 /* Because of the AR9130 specific registers */ 1251221163Sadrian if (AR_SREV_HOWL(ah)) { 1252221163Sadrian HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n"); 1253221163Sadrian uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1254221163Sadrian val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1255221163Sadrian val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1256221163Sadrian OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1257221163Sadrian (void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1258221163Sadrian } 1259221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 1260221163Sadrian 1261185377Ssam /* 1262185377Ssam * Force wake 1263185377Ssam */ 1264185377Ssam OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1265185377Ssam AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1266185377Ssam 1267221163Sadrian#ifdef AH_SUPPORT_AR9130 1268221163Sadrian if (AR_SREV_HOWL(ah)) { 1269221163Sadrian rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1270221163Sadrian AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1271185377Ssam } else { 1272221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 1273221163Sadrian /* 1274221163Sadrian * Reset AHB 1275221163Sadrian */ 1276221163Sadrian tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 1277221163Sadrian if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1278221163Sadrian OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1279221163Sadrian OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); 1280221163Sadrian } else { 1281221163Sadrian OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1282221163Sadrian } 1283221163Sadrian rst_flags = AR_RTC_RC_MAC_WARM; 1284221163Sadrian if (type == HAL_RESET_COLD) 1285221163Sadrian rst_flags |= AR_RTC_RC_MAC_COLD; 1286221163Sadrian#ifdef AH_SUPPORT_AR9130 1287185377Ssam } 1288221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 1289185377Ssam 1290221163Sadrian OS_REG_WRITE(ah, AR_RTC_RC, rst_flags); 1291185377Ssam 1292221479Sadrian if (AR_SREV_HOWL(ah)) 1293221479Sadrian OS_DELAY(10000); 1294221479Sadrian else 1295221479Sadrian OS_DELAY(100); 1296221479Sadrian 1297185377Ssam /* 1298185377Ssam * Clear resets and force wakeup 1299185377Ssam */ 1300185377Ssam OS_REG_WRITE(ah, AR_RTC_RC, 0); 1301185377Ssam if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { 1302185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); 1303185377Ssam return AH_FALSE; 1304185377Ssam } 1305185377Ssam 1306185377Ssam /* Clear AHB reset */ 1307221163Sadrian if (! AR_SREV_HOWL(ah)) 1308221163Sadrian OS_REG_WRITE(ah, AR_RC, 0); 1309185377Ssam 1310221163Sadrian if (AR_SREV_HOWL(ah)) 1311221163Sadrian OS_DELAY(50); 1312221163Sadrian 1313221163Sadrian if (AR_SREV_HOWL(ah)) { 1314221163Sadrian uint32_t mask; 1315221163Sadrian mask = OS_REG_READ(ah, AR_CFG); 1316221163Sadrian if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1317221163Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 1318221163Sadrian "CFG Byte Swap Set 0x%x\n", mask); 1319221163Sadrian } else { 1320221163Sadrian mask = 1321221163Sadrian INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1322221163Sadrian OS_REG_WRITE(ah, AR_CFG, mask); 1323221163Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 1324221163Sadrian "Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG)); 1325221163Sadrian } 1326221163Sadrian } else { 1327195426Ssam if (type == HAL_RESET_COLD) { 1328195426Ssam if (isBigEndian()) { 1329195426Ssam /* 1330195426Ssam * Set CFG, little-endian for register 1331195426Ssam * and descriptor accesses. 1332195426Ssam */ 1333195426Ssam mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1334185377Ssam#ifndef AH_NEED_DESC_SWAP 1335195426Ssam mask |= AR_CFG_SWTD; 1336185377Ssam#endif 1337195426Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1338195426Ssam "%s Applying descriptor swap\n", __func__); 1339195426Ssam OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1340195426Ssam } else 1341195426Ssam OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1342185377Ssam } 1343221163Sadrian } 1344185377Ssam 1345185377Ssam return AH_TRUE; 1346185377Ssam} 1347185377Ssam 1348217879Sadrianvoid 1349217879Sadrianar5416InitChainMasks(struct ath_hal *ah) 1350217879Sadrian{ 1351221616Sadrian int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1352221616Sadrian 1353221701Sadrian /* Flip this for this chainmask regardless of chip */ 1354221701Sadrian if (rx_chainmask == 0x5) 1355221616Sadrian OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1356221616Sadrian 1357221616Sadrian /* 1358221616Sadrian * Workaround for OWL 1.0 calibration failure; enable multi-chain; 1359221616Sadrian * then set true mask after calibration. 1360221616Sadrian */ 1361221616Sadrian if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1362221616Sadrian OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1363221616Sadrian OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1364221616Sadrian } else { 1365221616Sadrian OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1366221616Sadrian OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1367221616Sadrian } 1368217879Sadrian OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); 1369221163Sadrian 1370221616Sadrian if (AH5416(ah)->ah_tx_chainmask == 0x5) 1371221616Sadrian OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1372221616Sadrian 1373221163Sadrian if (AR_SREV_HOWL(ah)) { 1374221163Sadrian OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1375221163Sadrian OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1376221163Sadrian } 1377217879Sadrian} 1378217879Sadrian 1379221616Sadrian/* 1380221616Sadrian * Work-around for Owl 1.0 calibration failure. 1381221616Sadrian * 1382221616Sadrian * ar5416InitChainMasks sets the RX chainmask to 0x7 if it's Owl 1.0 1383221616Sadrian * due to init calibration failures. ar5416RestoreChainMask restores 1384221616Sadrian * these registers to the correct setting. 1385221616Sadrian */ 1386217882Sadrianvoid 1387217882Sadrianar5416RestoreChainMask(struct ath_hal *ah) 1388217882Sadrian{ 1389217882Sadrian int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1390217882Sadrian 1391221616Sadrian if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1392217882Sadrian OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1393217882Sadrian OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1394217882Sadrian } 1395217882Sadrian} 1396217882Sadrian 1397217930Sadrian/* 1398217930Sadrian * Update the chainmask based on the current channel configuration. 1399217930Sadrian * 1400217930Sadrian * XXX ath9k checks bluetooth co-existence here 1401217930Sadrian * XXX ath9k checks whether the current state is "off-channel". 1402217930Sadrian * XXX ath9k sticks the hardware into 1x1 mode for legacy; 1403217930Sadrian * we're going to leave multi-RX on for multi-path cancellation. 1404217930Sadrian */ 1405217930Sadrianstatic void 1406217930Sadrianar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht) 1407217930Sadrian{ 1408217930Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 1409217930Sadrian HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 1410217882Sadrian 1411217930Sadrian if (is_ht) { 1412217930Sadrian AH5416(ah)->ah_tx_chainmask = pCap->halTxChainMask; 1413217930Sadrian } else { 1414217930Sadrian AH5416(ah)->ah_tx_chainmask = 1; 1415217930Sadrian } 1416217930Sadrian AH5416(ah)->ah_rx_chainmask = pCap->halRxChainMask; 1417220598Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "TX chainmask: 0x%x; RX chainmask: 0x%x\n", 1418217930Sadrian AH5416(ah)->ah_tx_chainmask, 1419217930Sadrian AH5416(ah)->ah_rx_chainmask); 1420217930Sadrian} 1421217930Sadrian 1422220990Sadrianvoid 1423187831Ssamar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1424185377Ssam{ 1425224243Sadrian uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1426224243Sadrian if (chan != AH_NULL) { 1427224243Sadrian if (IEEE80211_IS_CHAN_HALF(chan)) 1428224243Sadrian pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1429224243Sadrian else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1430224243Sadrian pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1431185377Ssam 1432224243Sadrian if (IEEE80211_IS_CHAN_5GHZ(chan)) 1433224243Sadrian pll |= SM(0xa, AR_RTC_PLL_DIV); 1434224243Sadrian else 1435185377Ssam pll |= SM(0xb, AR_RTC_PLL_DIV); 1436224243Sadrian } else 1437224243Sadrian pll |= SM(0xb, AR_RTC_PLL_DIV); 1438224243Sadrian 1439185377Ssam OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1440185377Ssam 1441185377Ssam /* TODO: 1442185377Ssam * For multi-band owl, switch between bands by reiniting the PLL. 1443185377Ssam */ 1444185377Ssam 1445185377Ssam OS_DELAY(RTC_PLL_SETTLE_DELAY); 1446185377Ssam 1447185377Ssam OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1448185377Ssam} 1449185377Ssam 1450218420Sadrianstatic void 1451218420Sadrianar5416SetDefGainValues(struct ath_hal *ah, 1452218420Sadrian const MODAL_EEP_HEADER *pModal, 1453218420Sadrian const struct ar5416eeprom *eep, 1454218420Sadrian uint8_t txRxAttenLocal, int regChainOffset, int i) 1455218420Sadrian{ 1456218420Sadrian if (IS_EEP_MINOR_V3(ah)) { 1457218420Sadrian txRxAttenLocal = pModal->txRxAttenCh[i]; 1458218420Sadrian 1459221875Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1460218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1461218420Sadrian AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 1462218420Sadrian pModal->bswMargin[i]); 1463218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1464218420Sadrian AR_PHY_GAIN_2GHZ_XATTEN1_DB, 1465218420Sadrian pModal->bswAtten[i]); 1466218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1467218420Sadrian AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1468218420Sadrian pModal->xatten2Margin[i]); 1469218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1470218420Sadrian AR_PHY_GAIN_2GHZ_XATTEN2_DB, 1471218420Sadrian pModal->xatten2Db[i]); 1472218420Sadrian } else { 1473219854Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1474219854Sadrian AR_PHY_GAIN_2GHZ_BSW_MARGIN, 1475219854Sadrian pModal->bswMargin[i]); 1476219854Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1477219854Sadrian AR_PHY_GAIN_2GHZ_BSW_ATTEN, 1478219854Sadrian pModal->bswAtten[i]); 1479218420Sadrian } 1480218420Sadrian } 1481218420Sadrian 1482221875Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1483218420Sadrian OS_REG_RMW_FIELD(ah, 1484218420Sadrian AR_PHY_RXGAIN + regChainOffset, 1485218420Sadrian AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1486218420Sadrian OS_REG_RMW_FIELD(ah, 1487218420Sadrian AR_PHY_RXGAIN + regChainOffset, 1488218420Sadrian AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); 1489218420Sadrian } else { 1490219854Sadrian OS_REG_RMW_FIELD(ah, 1491218420Sadrian AR_PHY_RXGAIN + regChainOffset, 1492219854Sadrian AR_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1493219854Sadrian OS_REG_RMW_FIELD(ah, 1494218420Sadrian AR_PHY_GAIN_2GHZ + regChainOffset, 1495219854Sadrian AR_PHY_GAIN_2GHZ_RXTX_MARGIN, pModal->rxTxMarginCh[i]); 1496218420Sadrian } 1497218420Sadrian} 1498218420Sadrian 1499219393Sadrian/* 1500219393Sadrian * Get the register chain offset for the given chain. 1501219393Sadrian * 1502219393Sadrian * Take into account the register chain swapping with AR5416 v2.0. 1503219393Sadrian * 1504219393Sadrian * XXX make sure that the reg chain swapping is only done for 1505219393Sadrian * XXX AR5416 v2.0 or greater, and not later chips? 1506219393Sadrian */ 1507219393Sadrianint 1508219393Sadrianar5416GetRegChainOffset(struct ath_hal *ah, int i) 1509219393Sadrian{ 1510219393Sadrian int regChainOffset; 1511218420Sadrian 1512221574Sadrian if (AR_SREV_5416_V20_OR_LATER(ah) && 1513219393Sadrian (AH5416(ah)->ah_rx_chainmask == 0x5 || 1514219393Sadrian AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1515219393Sadrian /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1516219393Sadrian * only chains 0 and 2 populated 1517219393Sadrian */ 1518219393Sadrian regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1519219393Sadrian } else { 1520219393Sadrian regChainOffset = i * 0x1000; 1521219393Sadrian } 1522218420Sadrian 1523219393Sadrian return regChainOffset; 1524219393Sadrian} 1525219393Sadrian 1526185377Ssam/* 1527185377Ssam * Read EEPROM header info and program the device for correct operation 1528185377Ssam * given the channel value. 1529185377Ssam */ 1530203930SrpauloHAL_BOOL 1531187831Ssamar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1532185377Ssam{ 1533203882Srpaulo const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1534203882Srpaulo const struct ar5416eeprom *eep = &ee->ee_base; 1535185377Ssam const MODAL_EEP_HEADER *pModal; 1536203882Srpaulo int i, regChainOffset; 1537185377Ssam uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 1538185377Ssam 1539185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1540203882Srpaulo pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1541185377Ssam 1542187831Ssam /* NB: workaround for eeprom versions <= 14.2 */ 1543187831Ssam txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44; 1544185377Ssam 1545203882Srpaulo OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 1546185377Ssam for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1547203882Srpaulo if (AR_SREV_MERLIN(ah)) { 1548203882Srpaulo if (i >= 2) break; 1549203882Srpaulo } 1550219393Sadrian regChainOffset = ar5416GetRegChainOffset(ah, i); 1551185377Ssam 1552203882Srpaulo OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 1553218420Sadrian 1554185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 1555185377Ssam (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 1556185377Ssam ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1557203882Srpaulo SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1558203882Srpaulo SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1559185377Ssam 1560185377Ssam /* 1561221875Sadrian * Large signal upgrade, 1562221875Sadrian * If 14.3 or later EEPROM, use 1563221875Sadrian * txRxAttenLocal = pModal->txRxAttenCh[i] 1564221875Sadrian * else txRxAttenLocal is fixed value above. 1565185377Ssam */ 1566185377Ssam 1567221574Sadrian if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) 1568218420Sadrian ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1569203159Srpaulo 1570185377Ssam } 1571185377Ssam 1572221875Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1573218420Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1574218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1575218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); 1576218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1); 1577218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1); 1578218420Sadrian } else { 1579218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob); 1580218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db); 1581218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1); 1582218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1); 1583218420Sadrian } 1584218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); 1585220955Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, 1586220955Sadrian !!(pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)); 1587220955Sadrian OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, 1588220955Sadrian !!(pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)); 1589218420Sadrian } 1590218420Sadrian 1591203882Srpaulo OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 1592203882Srpaulo OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 1593218420Sadrian 1594221875Sadrian if (! AR_SREV_MERLIN_10_OR_LATER(ah)) 1595218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 1596218420Sadrian 1597185377Ssam OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 1598203882Srpaulo SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 1599203882Srpaulo | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 1600203882Srpaulo | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 1601203882Srpaulo | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1602185377Ssam 1603221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1604221875Sadrian pModal->txEndToRxOn); 1605185377Ssam 1606185377Ssam if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1607185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1608203882Srpaulo pModal->thresh62); 1609185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1610203882Srpaulo pModal->thresh62); 1611185377Ssam } else { 1612185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 1613203882Srpaulo pModal->thresh62); 1614219860Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, 1615203882Srpaulo pModal->thresh62); 1616185377Ssam } 1617185377Ssam 1618185377Ssam /* Minor Version Specific application */ 1619185377Ssam if (IS_EEP_MINOR_V2(ah)) { 1620221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 1621221875Sadrian pModal->txFrameToDataStart); 1622221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 1623221875Sadrian pModal->txFrameToPaOn); 1624185377Ssam } 1625218420Sadrian 1626218420Sadrian if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan)) 1627185377Ssam /* Overwrite switch settling with HT40 value */ 1628221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1629221875Sadrian pModal->swSettleHt40); 1630218420Sadrian 1631218420Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19) 1632218420Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits); 1633218420Sadrian 1634218420Sadrian if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) { 1635218420Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) 1636221875Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1637221875Sadrian eep->baseEepHeader.dacLpMode); 1638218420Sadrian else if (eep->baseEepHeader.dacHiPwrMode_5G) 1639218420Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 1640218420Sadrian else 1641221875Sadrian OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1642221875Sadrian eep->baseEepHeader.dacLpMode); 1643218420Sadrian 1644221875Sadrian OS_DELAY(100); 1645221875Sadrian 1646221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, 1647221875Sadrian pModal->miscBits >> 2); 1648221875Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, 1649221875Sadrian eep->baseEepHeader.desiredScaleCCK); 1650185377Ssam } 1651218420Sadrian 1652185377Ssam return AH_TRUE; 1653185377Ssam} 1654185377Ssam 1655185377Ssam/* 1656185377Ssam * Helper functions common for AP/CB/XB 1657185377Ssam */ 1658185377Ssam 1659185377Ssam/* 1660221834Sadrian * Set the target power array "ratesArray" from the 1661221834Sadrian * given set of target powers. 1662221834Sadrian * 1663221834Sadrian * This is used by the various chipset/EEPROM TX power 1664221834Sadrian * setup routines. 1665221834Sadrian */ 1666221834Sadrianvoid 1667221834Sadrianar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, 1668221834Sadrian const struct ieee80211_channel *chan, 1669221834Sadrian int16_t *ratesArray, 1670221834Sadrian const CAL_TARGET_POWER_LEG *targetPowerCck, 1671221834Sadrian const CAL_TARGET_POWER_LEG *targetPowerCckExt, 1672221834Sadrian const CAL_TARGET_POWER_LEG *targetPowerOfdm, 1673221834Sadrian const CAL_TARGET_POWER_LEG *targetPowerOfdmExt, 1674221834Sadrian const CAL_TARGET_POWER_HT *targetPowerHt20, 1675221834Sadrian const CAL_TARGET_POWER_HT *targetPowerHt40) 1676221834Sadrian{ 1677221834Sadrian#define N(a) (sizeof(a)/sizeof(a[0])) 1678221834Sadrian int i; 1679221834Sadrian 1680221834Sadrian /* Blank the rates array, to be consistent */ 1681221834Sadrian for (i = 0; i < Ar5416RateSize; i++) 1682221834Sadrian ratesArray[i] = 0; 1683221834Sadrian 1684221834Sadrian /* Set rates Array from collected data */ 1685221834Sadrian ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1686221834Sadrian ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm->tPow2x[0]; 1687221834Sadrian ratesArray[rate36mb] = targetPowerOfdm->tPow2x[1]; 1688221834Sadrian ratesArray[rate48mb] = targetPowerOfdm->tPow2x[2]; 1689221834Sadrian ratesArray[rate54mb] = targetPowerOfdm->tPow2x[3]; 1690221834Sadrian ratesArray[rateXr] = targetPowerOfdm->tPow2x[0]; 1691221834Sadrian 1692221834Sadrian for (i = 0; i < N(targetPowerHt20->tPow2x); i++) { 1693221834Sadrian ratesArray[rateHt20_0 + i] = targetPowerHt20->tPow2x[i]; 1694221834Sadrian } 1695221834Sadrian 1696221834Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1697221834Sadrian ratesArray[rate1l] = targetPowerCck->tPow2x[0]; 1698221834Sadrian ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck->tPow2x[1]; 1699221834Sadrian ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck->tPow2x[2]; 1700221834Sadrian ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck->tPow2x[3]; 1701221834Sadrian } 1702221834Sadrian if (IEEE80211_IS_CHAN_HT40(chan)) { 1703221834Sadrian for (i = 0; i < N(targetPowerHt40->tPow2x); i++) { 1704221834Sadrian ratesArray[rateHt40_0 + i] = targetPowerHt40->tPow2x[i]; 1705221834Sadrian } 1706221834Sadrian ratesArray[rateDupOfdm] = targetPowerHt40->tPow2x[0]; 1707221834Sadrian ratesArray[rateDupCck] = targetPowerHt40->tPow2x[0]; 1708221834Sadrian ratesArray[rateExtOfdm] = targetPowerOfdmExt->tPow2x[0]; 1709221834Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1710221834Sadrian ratesArray[rateExtCck] = targetPowerCckExt->tPow2x[0]; 1711221834Sadrian } 1712221834Sadrian } 1713221834Sadrian#undef N 1714221834Sadrian} 1715221834Sadrian 1716221834Sadrian/* 1717185377Ssam * ar5416SetPowerPerRateTable 1718185377Ssam * 1719185377Ssam * Sets the transmit power in the baseband for the given 1720185377Ssam * operating channel and mode. 1721185377Ssam */ 1722203882Srpaulostatic HAL_BOOL 1723185377Ssamar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1724187831Ssam const struct ieee80211_channel *chan, 1725185377Ssam int16_t *ratesArray, uint16_t cfgCtl, 1726185377Ssam uint16_t AntennaReduction, 1727185377Ssam uint16_t twiceMaxRegulatoryPower, 1728185377Ssam uint16_t powerLimit) 1729185377Ssam{ 1730185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 1731185377Ssam/* Local defines to distinguish between extension and control CTL's */ 1732185377Ssam#define EXT_ADDITIVE (0x8000) 1733185377Ssam#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 1734185377Ssam#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 1735185377Ssam#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 1736185377Ssam 1737185377Ssam uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1738185377Ssam int i; 1739185377Ssam int16_t twiceLargestAntenna; 1740185377Ssam CAL_CTL_DATA *rep; 1741185377Ssam CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 1742185377Ssam CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 1743185377Ssam CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 1744185377Ssam int16_t scaledPower, minCtlPower; 1745185377Ssam 1746185377Ssam#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 1747185377Ssam#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 1748185377Ssam static const uint16_t ctlModesFor11a[] = { 1749185377Ssam CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1750185377Ssam }; 1751185377Ssam static const uint16_t ctlModesFor11g[] = { 1752185377Ssam CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 1753185377Ssam }; 1754185377Ssam const uint16_t *pCtlMode; 1755185377Ssam uint16_t numCtlModes, ctlMode, freq; 1756185377Ssam CHAN_CENTERS centers; 1757185377Ssam 1758185377Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 1759185377Ssam 1760185377Ssam /* Compute TxPower reduction due to Antenna Gain */ 1761185377Ssam 1762203882Srpaulo twiceLargestAntenna = AH_MAX(AH_MAX( 1763203882Srpaulo pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1764203882Srpaulo pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), 1765203882Srpaulo pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1766185377Ssam#if 0 1767185377Ssam /* Turn it back on if we need to calculate per chain antenna gain reduction */ 1768185377Ssam /* Use only if the expected gain > 6dbi */ 1769185377Ssam /* Chain 0 is always used */ 1770187831Ssam twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0]; 1771185377Ssam 1772185377Ssam /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ 1773185377Ssam if (ahp->ah_tx_chainmask & 0x2) 1774185377Ssam twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1775187831Ssam pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1776185377Ssam 1777185377Ssam if (ahp->ah_tx_chainmask & 0x4) 1778185377Ssam twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1779187831Ssam pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1780185377Ssam#endif 1781185377Ssam twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 1782185377Ssam 1783185377Ssam /* XXX setup for 5212 use (really used?) */ 1784185377Ssam ath_hal_eepromSet(ah, 1785187831Ssam IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, 1786185377Ssam twiceLargestAntenna); 1787185377Ssam 1788185377Ssam /* 1789185377Ssam * scaledPower is the minimum of the user input power level and 1790185377Ssam * the regulatory allowed power level 1791185377Ssam */ 1792185377Ssam scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 1793185377Ssam 1794185377Ssam /* Reduce scaled Power by number of chains active to get to per chain tx power level */ 1795185377Ssam /* TODO: better value than these? */ 1796185377Ssam switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { 1797185377Ssam case 1: 1798185377Ssam break; 1799185377Ssam case 2: 1800203882Srpaulo scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; 1801185377Ssam break; 1802185377Ssam case 3: 1803203882Srpaulo scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; 1804185377Ssam break; 1805185377Ssam default: 1806185377Ssam return AH_FALSE; /* Unsupported number of chains */ 1807185377Ssam } 1808185377Ssam 1809185377Ssam scaledPower = AH_MAX(0, scaledPower); 1810185377Ssam 1811185377Ssam /* Get target powers from EEPROM - our baseline for TX Power */ 1812187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1813185377Ssam /* Setup for CTL modes */ 1814185377Ssam numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 1815185377Ssam pCtlMode = ctlModesFor11g; 1816185377Ssam 1817203882Srpaulo ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1818203882Srpaulo AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 1819203882Srpaulo ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1820203882Srpaulo AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1821203882Srpaulo ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 1822203882Srpaulo AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1823185377Ssam 1824187831Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 1825185377Ssam numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 1826185377Ssam 1827203882Srpaulo ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 1828203882Srpaulo AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1829185377Ssam /* Get target powers for extension channels */ 1830203882Srpaulo ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1831203882Srpaulo AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 1832203882Srpaulo ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1833203882Srpaulo AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1834185377Ssam } 1835185377Ssam } else { 1836185377Ssam /* Setup for CTL modes */ 1837185377Ssam numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ 1838185377Ssam pCtlMode = ctlModesFor11a; 1839185377Ssam 1840203882Srpaulo ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1841185377Ssam AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1842185377Ssam ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, 1843185377Ssam AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1844185377Ssam 1845187831Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 1846185377Ssam numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ 1847185377Ssam 1848185377Ssam ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, 1849185377Ssam AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1850185377Ssam ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1851185377Ssam AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1852185377Ssam } 1853185377Ssam } 1854185377Ssam 1855185377Ssam /* 1856185377Ssam * For MIMO, need to apply regulatory caps individually across dynamically 1857185377Ssam * running modes: CCK, OFDM, HT20, HT40 1858185377Ssam * 1859185377Ssam * The outer loop walks through each possible applicable runtime mode. 1860185377Ssam * The inner loop walks through each ctlIndex entry in EEPROM. 1861185377Ssam * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 1862185377Ssam * 1863185377Ssam */ 1864185377Ssam for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1865185377Ssam HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 1866187831Ssam (pCtlMode[ctlMode] == CTL_2GHT40); 1867185377Ssam if (isHt40CtlMode) { 1868185377Ssam freq = centers.ctl_center; 1869185377Ssam } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 1870185377Ssam freq = centers.ext_center; 1871185377Ssam } else { 1872185377Ssam freq = centers.ctl_center; 1873185377Ssam } 1874185377Ssam 1875185377Ssam /* walk through each CTL index stored in EEPROM */ 1876203882Srpaulo for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 1877185377Ssam uint16_t twiceMinEdgePower; 1878185377Ssam 1879185377Ssam /* compare test group from regulatory channel list with test mode from pCtlMode list */ 1880203882Srpaulo if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 1881185377Ssam (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 1882203882Srpaulo ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1883203882Srpaulo rep = &(pEepData->ctlData[i]); 1884203882Srpaulo twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 1885203882Srpaulo rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], 1886203882Srpaulo IEEE80211_IS_CHAN_2GHZ(chan)); 1887185377Ssam if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1888185377Ssam /* Find the minimum of all CTL edge powers that apply to this channel */ 1889185377Ssam twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 1890185377Ssam } else { 1891185377Ssam /* specific */ 1892185377Ssam twiceMaxEdgePower = twiceMinEdgePower; 1893185377Ssam break; 1894185377Ssam } 1895185377Ssam } 1896185377Ssam } 1897185377Ssam minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 1898185377Ssam /* Apply ctl mode to correct target power set */ 1899185377Ssam switch(pCtlMode[ctlMode]) { 1900185377Ssam case CTL_11B: 1901185377Ssam for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 1902185377Ssam targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 1903185377Ssam } 1904185377Ssam break; 1905185377Ssam case CTL_11A: 1906185377Ssam case CTL_11G: 1907185377Ssam for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 1908185377Ssam targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 1909185377Ssam } 1910185377Ssam break; 1911185377Ssam case CTL_5GHT20: 1912185377Ssam case CTL_2GHT20: 1913185377Ssam for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1914185377Ssam targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 1915185377Ssam } 1916185377Ssam break; 1917185377Ssam case CTL_11B_EXT: 1918185377Ssam targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 1919185377Ssam break; 1920185377Ssam case CTL_11A_EXT: 1921185377Ssam case CTL_11G_EXT: 1922185377Ssam targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 1923185377Ssam break; 1924185377Ssam case CTL_5GHT40: 1925185377Ssam case CTL_2GHT40: 1926185377Ssam for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1927185377Ssam targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 1928185377Ssam } 1929185377Ssam break; 1930185377Ssam default: 1931185377Ssam return AH_FALSE; 1932185377Ssam break; 1933185377Ssam } 1934185377Ssam } /* end ctl mode checking */ 1935185377Ssam 1936185377Ssam /* Set rates Array from collected data */ 1937221834Sadrian ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, 1938221834Sadrian &targetPowerCck, 1939221834Sadrian &targetPowerCckExt, 1940221834Sadrian &targetPowerOfdm, 1941221834Sadrian &targetPowerOfdmExt, 1942221834Sadrian &targetPowerHt20, 1943221834Sadrian &targetPowerHt40); 1944185377Ssam return AH_TRUE; 1945185377Ssam#undef EXT_ADDITIVE 1946185377Ssam#undef CTL_11A_EXT 1947185377Ssam#undef CTL_11G_EXT 1948185377Ssam#undef CTL_11B_EXT 1949185377Ssam#undef SUB_NUM_CTL_MODES_AT_5G_40 1950185377Ssam#undef SUB_NUM_CTL_MODES_AT_2G_40 1951185377Ssam#undef N 1952185377Ssam} 1953185377Ssam 1954185377Ssam/************************************************************************** 1955185377Ssam * fbin2freq 1956185377Ssam * 1957185377Ssam * Get channel value from binary representation held in eeprom 1958185377Ssam * RETURNS: the frequency in MHz 1959185377Ssam */ 1960185377Ssamstatic uint16_t 1961185377Ssamfbin2freq(uint8_t fbin, HAL_BOOL is2GHz) 1962185377Ssam{ 1963185377Ssam /* 1964185377Ssam * Reserved value 0xFF provides an empty definition both as 1965185377Ssam * an fbin and as a frequency - do not convert 1966185377Ssam */ 1967185377Ssam if (fbin == AR5416_BCHAN_UNUSED) { 1968185377Ssam return fbin; 1969185377Ssam } 1970185377Ssam 1971185377Ssam return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 1972185377Ssam} 1973185377Ssam 1974185377Ssam/* 1975185377Ssam * ar5416GetMaxEdgePower 1976185377Ssam * 1977185377Ssam * Find the maximum conformance test limit for the given channel and CTL info 1978185377Ssam */ 1979220713Sadrianuint16_t 1980203882Srpauloar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) 1981185377Ssam{ 1982185377Ssam uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1983203882Srpaulo int i; 1984185377Ssam 1985185377Ssam /* Get the edge power */ 1986203882Srpaulo for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 1987185377Ssam /* 1988185377Ssam * If there's an exact channel match or an inband flag set 1989185377Ssam * on the lower channel use the given rdEdgePower 1990185377Ssam */ 1991185377Ssam if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 1992185377Ssam twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 1993185377Ssam break; 1994185377Ssam } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { 1995185377Ssam if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 1996185377Ssam twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 1997185377Ssam } 1998185377Ssam /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 1999185377Ssam break; 2000185377Ssam } 2001185377Ssam } 2002185377Ssam HALASSERT(twiceMaxEdgePower > 0); 2003185377Ssam return twiceMaxEdgePower; 2004185377Ssam} 2005185377Ssam 2006185377Ssam/************************************************************** 2007185377Ssam * ar5416GetTargetPowers 2008185377Ssam * 2009185377Ssam * Return the rates of target power for the given target power table 2010185377Ssam * channel, and number of channels 2011185377Ssam */ 2012203930Srpaulovoid 2013187831Ssamar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2014185377Ssam CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, 2015185377Ssam CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, 2016185377Ssam HAL_BOOL isHt40Target) 2017185377Ssam{ 2018185377Ssam uint16_t clo, chi; 2019185377Ssam int i; 2020185377Ssam int matchIndex = -1, lowIndex = -1; 2021185377Ssam uint16_t freq; 2022185377Ssam CHAN_CENTERS centers; 2023185377Ssam 2024185377Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 2025185377Ssam freq = isHt40Target ? centers.synth_center : centers.ctl_center; 2026185377Ssam 2027185377Ssam /* Copy the target powers into the temp channel list */ 2028187831Ssam if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2029185377Ssam matchIndex = 0; 2030185377Ssam } else { 2031185377Ssam for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2032187831Ssam if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2033185377Ssam matchIndex = i; 2034185377Ssam break; 2035187831Ssam } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2036187831Ssam (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2037185377Ssam { 2038185377Ssam lowIndex = i - 1; 2039185377Ssam break; 2040185377Ssam } 2041185377Ssam } 2042185377Ssam if ((matchIndex == -1) && (lowIndex == -1)) { 2043187831Ssam HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2044185377Ssam matchIndex = i - 1; 2045185377Ssam } 2046185377Ssam } 2047185377Ssam 2048185377Ssam if (matchIndex != -1) { 2049185377Ssam OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2050185377Ssam } else { 2051185377Ssam HALASSERT(lowIndex != -1); 2052185377Ssam /* 2053185377Ssam * Get the lower and upper channels, target powers, 2054185377Ssam * and interpolate between them. 2055185377Ssam */ 2056187831Ssam clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2057187831Ssam chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2058185377Ssam 2059185377Ssam for (i = 0; i < numRates; i++) { 2060219586Sadrian pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2061185377Ssam powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2062185377Ssam } 2063185377Ssam } 2064185377Ssam} 2065185377Ssam/************************************************************** 2066185377Ssam * ar5416GetTargetPowersLeg 2067185377Ssam * 2068185377Ssam * Return the four rates of target power for the given target power table 2069185377Ssam * channel, and number of channels 2070185377Ssam */ 2071203930Srpaulovoid 2072185377Ssamar5416GetTargetPowersLeg(struct ath_hal *ah, 2073187831Ssam const struct ieee80211_channel *chan, 2074185377Ssam CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, 2075185377Ssam CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, 2076185377Ssam HAL_BOOL isExtTarget) 2077185377Ssam{ 2078185377Ssam uint16_t clo, chi; 2079185377Ssam int i; 2080185377Ssam int matchIndex = -1, lowIndex = -1; 2081185377Ssam uint16_t freq; 2082185377Ssam CHAN_CENTERS centers; 2083185377Ssam 2084185377Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 2085185377Ssam freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; 2086185377Ssam 2087185377Ssam /* Copy the target powers into the temp channel list */ 2088187831Ssam if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2089185377Ssam matchIndex = 0; 2090185377Ssam } else { 2091185377Ssam for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2092187831Ssam if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2093185377Ssam matchIndex = i; 2094185377Ssam break; 2095187831Ssam } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2096187831Ssam (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2097185377Ssam { 2098185377Ssam lowIndex = i - 1; 2099185377Ssam break; 2100185377Ssam } 2101185377Ssam } 2102185377Ssam if ((matchIndex == -1) && (lowIndex == -1)) { 2103187831Ssam HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2104185377Ssam matchIndex = i - 1; 2105185377Ssam } 2106185377Ssam } 2107185377Ssam 2108185377Ssam if (matchIndex != -1) { 2109185377Ssam OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2110185377Ssam } else { 2111185377Ssam HALASSERT(lowIndex != -1); 2112185377Ssam /* 2113185377Ssam * Get the lower and upper channels, target powers, 2114185377Ssam * and interpolate between them. 2115185377Ssam */ 2116187831Ssam clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2117187831Ssam chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2118185377Ssam 2119185377Ssam for (i = 0; i < numRates; i++) { 2120219586Sadrian pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2121185377Ssam powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2122185377Ssam } 2123185377Ssam } 2124185377Ssam} 2125185377Ssam 2126219393Sadrian/* 2127219393Sadrian * Set the gain boundaries for the given radio chain. 2128219393Sadrian * 2129219393Sadrian * The gain boundaries tell the hardware at what point in the 2130219393Sadrian * PDADC array to "switch over" from one PD gain setting 2131219393Sadrian * to another. There's also a gain overlap between two 2132219393Sadrian * PDADC array gain curves where there's valid PD values 2133219393Sadrian * for 2 gain settings. 2134219393Sadrian * 2135219393Sadrian * The hardware uses the gain overlap and gain boundaries 2136219393Sadrian * to determine which gain curve to use for the given 2137219393Sadrian * target TX power. 2138219393Sadrian */ 2139219393Sadrianvoid 2140219585Sadrianar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, 2141219393Sadrian uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[]) 2142219393Sadrian{ 2143219585Sadrian int regChainOffset; 2144219585Sadrian 2145219585Sadrian regChainOffset = ar5416GetRegChainOffset(ah, i); 2146219585Sadrian 2147219585Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d," 2148219585Sadrian " gainBoundaries: %d, %d, %d, %d\n", __func__, i, pdGainOverlap_t2, 2149219585Sadrian gainBoundaries[0], gainBoundaries[1], gainBoundaries[2], 2150219585Sadrian gainBoundaries[3]); 2151219393Sadrian OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 2152219393Sadrian SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 2153219393Sadrian SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 2154219393Sadrian SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 2155219393Sadrian SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 2156219393Sadrian SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 2157219393Sadrian} 2158219393Sadrian 2159219393Sadrian/* 2160219393Sadrian * Get the gain values and the number of gain levels given 2161219393Sadrian * in xpdMask. 2162219393Sadrian * 2163219393Sadrian * The EEPROM xpdMask determines which power detector gain 2164219393Sadrian * levels were used during calibration. Each of these mask 2165219393Sadrian * bits maps to a fixed gain level in hardware. 2166219393Sadrian */ 2167219393Sadrianuint16_t 2168219393Sadrianar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask, 2169219393Sadrian uint16_t xpdGainValues[]) 2170219393Sadrian{ 2171219393Sadrian int i; 2172219393Sadrian uint16_t numXpdGain = 0; 2173219393Sadrian 2174219393Sadrian for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 2175219393Sadrian if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 2176219393Sadrian if (numXpdGain >= AR5416_NUM_PD_GAINS) { 2177219393Sadrian HALASSERT(0); 2178219393Sadrian break; 2179219393Sadrian } 2180219393Sadrian xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 2181219393Sadrian numXpdGain++; 2182219393Sadrian } 2183219393Sadrian } 2184219393Sadrian return numXpdGain; 2185219393Sadrian} 2186219393Sadrian 2187219393Sadrian/* 2188219393Sadrian * Write the detector gain and biases. 2189219393Sadrian * 2190219393Sadrian * There are four power detector gain levels. The xpdMask in the EEPROM 2191219393Sadrian * determines which power detector gain levels have TX power calibration 2192219393Sadrian * data associated with them. This function writes the number of 2193219393Sadrian * PD gain levels and their values into the hardware. 2194219393Sadrian * 2195219393Sadrian * This is valid for all TX chains - the calibration data itself however 2196219393Sadrian * will likely differ per-chain. 2197219393Sadrian */ 2198219393Sadrianvoid 2199219393Sadrianar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, 2200219393Sadrian uint16_t xpdGainValues[]) 2201219393Sadrian{ 2202219585Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d," 2203219585Sadrian " xpdGainValues: %d, %d, %d\n", __func__, numXpdGain, 2204219585Sadrian xpdGainValues[0], xpdGainValues[1], xpdGainValues[2]); 2205219585Sadrian 2206219393Sadrian OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 2207219393Sadrian ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | 2208219393Sadrian AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 2209219393Sadrian SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | 2210219393Sadrian SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 2211219393Sadrian SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | 2212219393Sadrian SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); 2213219393Sadrian} 2214219393Sadrian 2215219393Sadrian/* 2216219585Sadrian * Write the PDADC array to the given radio chain i. 2217219393Sadrian * 2218219393Sadrian * The 32 PDADC registers are written without any care about 2219219393Sadrian * their contents - so if various chips treat values as "special", 2220219393Sadrian * this routine will not care. 2221219393Sadrian */ 2222219393Sadrianvoid 2223219585Sadrianar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[]) 2224219393Sadrian{ 2225219585Sadrian int regOffset, regChainOffset; 2226219393Sadrian int j; 2227219393Sadrian int reg32; 2228219393Sadrian 2229219585Sadrian regChainOffset = ar5416GetRegChainOffset(ah, i); 2230219393Sadrian regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 2231219393Sadrian 2232219393Sadrian for (j = 0; j < 32; j++) { 2233219393Sadrian reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 2234219393Sadrian ((pdadcValues[4*j + 1] & 0xFF) << 8) | 2235219393Sadrian ((pdadcValues[4*j + 2] & 0xFF) << 16) | 2236219393Sadrian ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 2237219393Sadrian OS_REG_WRITE(ah, regOffset, reg32); 2238219585Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |" 2239219393Sadrian " PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d" 2240219585Sadrian " Value %3d | PDADC %3d Value %3d |\n", 2241219393Sadrian i, 2242219393Sadrian 4*j, pdadcValues[4*j], 2243219393Sadrian 4*j+1, pdadcValues[4*j + 1], 2244219393Sadrian 4*j+2, pdadcValues[4*j + 2], 2245219393Sadrian 4*j+3, pdadcValues[4*j + 3]); 2246219393Sadrian regOffset += 4; 2247219393Sadrian } 2248219393Sadrian} 2249219393Sadrian 2250185377Ssam/************************************************************** 2251185377Ssam * ar5416SetPowerCalTable 2252185377Ssam * 2253185377Ssam * Pull the PDADC piers from cal data and interpolate them across the given 2254185377Ssam * points as well as from the nearest pier(s) to get a power detector 2255185377Ssam * linear voltage to power level table. 2256185377Ssam */ 2257219393SadrianHAL_BOOL 2258187831Ssamar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 2259187831Ssam const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 2260185377Ssam{ 2261203882Srpaulo CAL_DATA_PER_FREQ *pRawDataset; 2262185377Ssam uint8_t *pCalBChans = AH_NULL; 2263185377Ssam uint16_t pdGainOverlap_t2; 2264185377Ssam static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 2265185377Ssam uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 2266219393Sadrian uint16_t numPiers, i; 2267185377Ssam int16_t tMinCalPower; 2268185377Ssam uint16_t numXpdGain, xpdMask; 2269185377Ssam uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 2270219393Sadrian uint32_t regChainOffset; 2271185377Ssam 2272191909Ssam OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 2273185377Ssam 2274203882Srpaulo xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 2275185377Ssam 2276185377Ssam if (IS_EEP_MINOR_V2(ah)) { 2277203882Srpaulo pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 2278185377Ssam } else { 2279185377Ssam pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 2280185377Ssam } 2281185377Ssam 2282187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2283203882Srpaulo pCalBChans = pEepData->calFreqPier2G; 2284203882Srpaulo numPiers = AR5416_NUM_2G_CAL_PIERS; 2285185377Ssam } else { 2286185377Ssam pCalBChans = pEepData->calFreqPier5G; 2287185377Ssam numPiers = AR5416_NUM_5G_CAL_PIERS; 2288185377Ssam } 2289185377Ssam 2290185377Ssam /* Calculate the value of xpdgains from the xpdGain Mask */ 2291219393Sadrian numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues); 2292185377Ssam 2293185377Ssam /* Write the detector gain biases and their number */ 2294219393Sadrian ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 2295185377Ssam 2296185377Ssam for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2297219393Sadrian regChainOffset = ar5416GetRegChainOffset(ah, i); 2298203882Srpaulo 2299203882Srpaulo if (pEepData->baseEepHeader.txMask & (1 << i)) { 2300187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2301203882Srpaulo pRawDataset = pEepData->calPierData2G[i]; 2302185377Ssam } else { 2303185377Ssam pRawDataset = pEepData->calPierData5G[i]; 2304185377Ssam } 2305185377Ssam 2306219393Sadrian /* Fetch the gain boundaries and the PDADC values */ 2307219393Sadrian ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 2308185377Ssam pCalBChans, numPiers, 2309185377Ssam pdGainOverlap_t2, 2310185377Ssam &tMinCalPower, gainBoundaries, 2311185377Ssam pdadcValues, numXpdGain); 2312185377Ssam 2313221574Sadrian if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 2314219585Sadrian ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, 2315219585Sadrian gainBoundaries); 2316185377Ssam } 2317185377Ssam 2318185377Ssam /* Write the power values into the baseband power table */ 2319219585Sadrian ar5416WritePdadcValues(ah, i, pdadcValues); 2320185377Ssam } 2321185377Ssam } 2322185377Ssam *pTxPowerIndexOffset = 0; 2323185377Ssam 2324185377Ssam return AH_TRUE; 2325185377Ssam} 2326185377Ssam 2327185377Ssam/************************************************************** 2328185377Ssam * ar5416GetGainBoundariesAndPdadcs 2329185377Ssam * 2330185377Ssam * Uses the data points read from EEPROM to reconstruct the pdadc power table 2331185377Ssam * Called by ar5416SetPowerCalTable only. 2332185377Ssam */ 2333219393Sadrianvoid 2334185377Ssamar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 2335187831Ssam const struct ieee80211_channel *chan, 2336187831Ssam CAL_DATA_PER_FREQ *pRawDataSet, 2337185377Ssam uint8_t * bChans, uint16_t availPiers, 2338203882Srpaulo uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 2339185377Ssam uint8_t * pPDADCValues, uint16_t numXpdGains) 2340185377Ssam{ 2341185377Ssam 2342185377Ssam int i, j, k; 2343185377Ssam int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 2344185377Ssam uint16_t idxL, idxR, numPiers; /* Pier indexes */ 2345185377Ssam 2346185377Ssam /* filled out Vpd table for all pdGains (chanL) */ 2347185377Ssam static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2348185377Ssam 2349185377Ssam /* filled out Vpd table for all pdGains (chanR) */ 2350185377Ssam static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2351185377Ssam 2352185377Ssam /* filled out Vpd table for all pdGains (interpolated) */ 2353185377Ssam static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2354185377Ssam 2355185377Ssam uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 2356185377Ssam uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; 2357185377Ssam uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; 2358185377Ssam int16_t vpdStep; 2359185377Ssam int16_t tmpVal; 2360185377Ssam uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 2361185377Ssam HAL_BOOL match; 2362185377Ssam int16_t minDelta = 0; 2363185377Ssam CHAN_CENTERS centers; 2364185377Ssam 2365185377Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 2366185377Ssam 2367185377Ssam /* Trim numPiers for the number of populated channel Piers */ 2368185377Ssam for (numPiers = 0; numPiers < availPiers; numPiers++) { 2369185377Ssam if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 2370185377Ssam break; 2371185377Ssam } 2372185377Ssam } 2373185377Ssam 2374185377Ssam /* Find pier indexes around the current channel */ 2375219586Sadrian match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 2376219586Sadrian IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 2377185377Ssam 2378185377Ssam if (match) { 2379185377Ssam /* Directly fill both vpd tables from the matching index */ 2380185377Ssam for (i = 0; i < numXpdGains; i++) { 2381203882Srpaulo minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 2382203882Srpaulo maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 2383219586Sadrian ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], 2384203882Srpaulo pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 2385185377Ssam } 2386185377Ssam } else { 2387185377Ssam for (i = 0; i < numXpdGains; i++) { 2388203882Srpaulo pVpdL = pRawDataSet[idxL].vpdPdg[i]; 2389203882Srpaulo pPwrL = pRawDataSet[idxL].pwrPdg[i]; 2390203882Srpaulo pVpdR = pRawDataSet[idxR].vpdPdg[i]; 2391203882Srpaulo pPwrR = pRawDataSet[idxR].pwrPdg[i]; 2392185377Ssam 2393185377Ssam /* Start Vpd interpolation from the max of the minimum powers */ 2394185377Ssam minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 2395185377Ssam 2396185377Ssam /* End Vpd interpolation from the min of the max powers */ 2397185377Ssam maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 2398185377Ssam HALASSERT(maxPwrT4[i] > minPwrT4[i]); 2399185377Ssam 2400185377Ssam /* Fill pier Vpds */ 2401219586Sadrian ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 2402219586Sadrian ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 2403185377Ssam 2404185377Ssam /* Interpolate the final vpd */ 2405185377Ssam for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 2406219586Sadrian vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 2407219586Sadrian IEEE80211_IS_CHAN_2GHZ(chan)), 2408185377Ssam bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 2409185377Ssam } 2410185377Ssam } 2411185377Ssam } 2412185377Ssam *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 2413185377Ssam 2414185377Ssam k = 0; /* index for the final table */ 2415185377Ssam for (i = 0; i < numXpdGains; i++) { 2416185377Ssam if (i == (numXpdGains - 1)) { 2417185377Ssam pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2418185377Ssam } else { 2419185377Ssam pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2420185377Ssam } 2421185377Ssam 2422185377Ssam pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2423185377Ssam 2424185380Ssam /* NB: only applies to owl 1.0 */ 2425221574Sadrian if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 2426185377Ssam /* 2427185377Ssam * fix the gain delta, but get a delta that can be applied to min to 2428185377Ssam * keep the upper power values accurate, don't think max needs to 2429185377Ssam * be adjusted because should not be at that area of the table? 2430185377Ssam */ 2431185377Ssam minDelta = pPdGainBoundaries[0] - 23; 2432185377Ssam pPdGainBoundaries[0] = 23; 2433185377Ssam } 2434185377Ssam else { 2435185377Ssam minDelta = 0; 2436185377Ssam } 2437185377Ssam 2438185377Ssam /* Find starting index for this pdGain */ 2439185377Ssam if (i == 0) { 2440221876Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) 2441219443Sadrian ss = (int16_t)(0 - (minPwrT4[i] / 2)); 2442219443Sadrian else 2443219443Sadrian ss = 0; /* for the first pdGain, start from index 0 */ 2444185377Ssam } else { 2445185377Ssam /* need overlap entries extrapolated below. */ 2446185377Ssam ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 2447185377Ssam } 2448185377Ssam vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 2449185377Ssam vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2450185377Ssam /* 2451185377Ssam *-ve ss indicates need to extrapolate data below for this pdGain 2452185377Ssam */ 2453185377Ssam while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2454185377Ssam tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 2455185377Ssam pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 2456185377Ssam ss++; 2457185377Ssam } 2458185377Ssam 2459203882Srpaulo sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 2460185377Ssam tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 2461185377Ssam maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 2462185377Ssam 2463185377Ssam while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2464185377Ssam pPDADCValues[k++] = vpdTableI[i][ss++]; 2465185377Ssam } 2466185377Ssam 2467185377Ssam vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 2468185377Ssam vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2469185377Ssam /* 2470185377Ssam * for last gain, pdGainBoundary == Pmax_t2, so will 2471185377Ssam * have to extrapolate 2472185377Ssam */ 2473211307Sadrian if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 2474185377Ssam while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2475185377Ssam tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 2476185377Ssam (ss - maxIndex +1) * vpdStep)); 2477185377Ssam pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 2478185377Ssam ss++; 2479185377Ssam } 2480185377Ssam } /* extrapolated above */ 2481185377Ssam } /* for all pdGainUsed */ 2482185377Ssam 2483185377Ssam /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 2484185377Ssam while (i < AR5416_PD_GAINS_IN_MASK) { 2485185377Ssam pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 2486185377Ssam i++; 2487185377Ssam } 2488185377Ssam 2489185377Ssam while (k < AR5416_NUM_PDADC_VALUES) { 2490185377Ssam pPDADCValues[k] = pPDADCValues[k-1]; 2491185377Ssam k++; 2492185377Ssam } 2493185377Ssam return; 2494185377Ssam} 2495185377Ssam 2496217752Sadrian/* 2497217752Sadrian * The linux ath9k driver and (from what I've been told) the reference 2498217752Sadrian * Atheros driver enables the 11n PHY by default whether or not it's 2499217752Sadrian * configured. 2500217752Sadrian */ 2501185377Ssamstatic void 2502187831Ssamar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) 2503185377Ssam{ 2504185377Ssam uint32_t phymode; 2505217752Sadrian uint32_t enableDacFifo = 0; 2506185377Ssam HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ 2507185377Ssam 2508217752Sadrian if (AR_SREV_KITE_10_OR_LATER(ah)) 2509217752Sadrian enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO); 2510185377Ssam 2511185377Ssam /* Enable 11n HT, 20 MHz */ 2512185377Ssam phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 2513217752Sadrian | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 2514185377Ssam 2515185377Ssam /* Configure baseband for dynamic 20/40 operation */ 2516187831Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 2517217752Sadrian phymode |= AR_PHY_FC_DYN2040_EN; 2518185377Ssam 2519185377Ssam /* Configure control (primary) channel at +-10MHz */ 2520187831Ssam if (IEEE80211_IS_CHAN_HT40U(chan)) 2521185377Ssam phymode |= AR_PHY_FC_DYN2040_PRI_CH; 2522185377Ssam#if 0 2523185377Ssam /* Configure 20/25 spacing */ 2524185377Ssam if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) 2525185377Ssam phymode |= AR_PHY_FC_DYN2040_EXT_CH; 2526185377Ssam#endif 2527185377Ssam macmode = HAL_HT_MACMODE_2040; 2528185377Ssam } else 2529185377Ssam macmode = HAL_HT_MACMODE_20; 2530185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); 2531185377Ssam 2532185377Ssam /* Configure MAC for 20/40 operation */ 2533185377Ssam ar5416Set11nMac2040(ah, macmode); 2534185377Ssam 2535185377Ssam /* global transmit timeout (25 TUs default)*/ 2536185377Ssam /* XXX - put this elsewhere??? */ 2537185377Ssam OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; 2538185377Ssam 2539185377Ssam /* carrier sense timeout */ 2540185377Ssam OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); 2541218690Sadrian OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 2542185377Ssam} 2543185377Ssam 2544185377Ssamvoid 2545185377Ssamar5416GetChannelCenters(struct ath_hal *ah, 2546187831Ssam const struct ieee80211_channel *chan, CHAN_CENTERS *centers) 2547185377Ssam{ 2548187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 2549187831Ssam 2550187831Ssam centers->ctl_center = freq; 2551187831Ssam centers->synth_center = freq; 2552185377Ssam /* 2553185377Ssam * In 20/40 phy mode, the center frequency is 2554185377Ssam * "between" the control and extension channels. 2555185377Ssam */ 2556187831Ssam if (IEEE80211_IS_CHAN_HT40U(chan)) { 2557185377Ssam centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; 2558185377Ssam centers->ext_center = 2559185377Ssam centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; 2560187831Ssam } else if (IEEE80211_IS_CHAN_HT40D(chan)) { 2561185377Ssam centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; 2562185377Ssam centers->ext_center = 2563185377Ssam centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; 2564185377Ssam } else { 2565187831Ssam centers->ext_center = freq; 2566185377Ssam } 2567185377Ssam} 2568219218Sadrian 2569219218Sadrian/* 2570219218Sadrian * Override the INI vals being programmed. 2571219218Sadrian */ 2572219218Sadrianstatic void 2573219218Sadrianar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 2574219218Sadrian{ 2575219218Sadrian uint32_t val; 2576219218Sadrian 2577219218Sadrian /* 2578219218Sadrian * Set the RX_ABORT and RX_DIS and clear if off only after 2579219218Sadrian * RXE is set for MAC. This prevents frames with corrupted 2580219218Sadrian * descriptor status. 2581219218Sadrian */ 2582219218Sadrian OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 2583219218Sadrian 2584221618Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2585221618Sadrian val = OS_REG_READ(ah, AR_PCU_MISC_MODE2); 2586221617Sadrian val &= (~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE); 2587221618Sadrian if (!AR_SREV_9271(ah)) 2588221618Sadrian val &= ~AR_PCU_MISC_MODE2_HWWAR1; 2589219218Sadrian 2590222300Sadrian if (AR_SREV_KIWI_11_OR_LATER(ah)) 2591221618Sadrian val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 2592219218Sadrian 2593221618Sadrian OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 2594221618Sadrian } 2595219218Sadrian 2596219218Sadrian /* 2597219218Sadrian * Disable RIFS search on some chips to avoid baseband 2598219218Sadrian * hang issues. 2599219218Sadrian */ 2600221535Sadrian if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) 2601221878Sadrian (void) ar5416SetRifsDelay(ah, chan, AH_FALSE); 2602221574Sadrian 2603221574Sadrian if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah)) 2604221574Sadrian return; 2605221574Sadrian 2606221574Sadrian /* 2607221574Sadrian * Disable BB clock gating 2608221574Sadrian * Necessary to avoid issues on AR5416 2.0 2609221574Sadrian */ 2610221574Sadrian OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 2611219218Sadrian} 2612219863Sadrian 2613219863Sadrianstruct ini { 2614219863Sadrian uint32_t *data; /* NB: !const */ 2615219863Sadrian int rows, cols; 2616219863Sadrian}; 2617219863Sadrian 2618219863Sadrian/* 2619219863Sadrian * Override XPA bias level based on operating frequency. 2620219863Sadrian * This is a v14 EEPROM specific thing for the AR9160. 2621219863Sadrian */ 2622219863Sadrianvoid 2623219863Sadrianar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan) 2624219863Sadrian{ 2625219863Sadrian#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 2626219863Sadrian MODAL_EEP_HEADER *pModal; 2627219863Sadrian HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 2628219863Sadrian struct ar5416eeprom *eep = &ee->ee_base; 2629219863Sadrian uint8_t biaslevel; 2630219863Sadrian 2631219863Sadrian if (! AR_SREV_SOWL(ah)) 2632219863Sadrian return; 2633219863Sadrian 2634219863Sadrian if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7) 2635219863Sadrian return; 2636219863Sadrian 2637219863Sadrian pModal = &(eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]); 2638219863Sadrian 2639219863Sadrian if (pModal->xpaBiasLvl != 0xff) 2640219863Sadrian biaslevel = pModal->xpaBiasLvl; 2641219863Sadrian else { 2642219863Sadrian uint16_t resetFreqBin, freqBin, freqCount = 0; 2643219863Sadrian CHAN_CENTERS centers; 2644219863Sadrian 2645219863Sadrian ar5416GetChannelCenters(ah, chan, ¢ers); 2646219863Sadrian 2647219863Sadrian resetFreqBin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)); 2648219863Sadrian freqBin = XPA_LVL_FREQ(0) & 0xff; 2649219863Sadrian biaslevel = (uint8_t) (XPA_LVL_FREQ(0) >> 14); 2650219863Sadrian 2651219863Sadrian freqCount++; 2652219863Sadrian 2653219863Sadrian while (freqCount < 3) { 2654219863Sadrian if (XPA_LVL_FREQ(freqCount) == 0x0) 2655219863Sadrian break; 2656219863Sadrian 2657219863Sadrian freqBin = XPA_LVL_FREQ(freqCount) & 0xff; 2658219863Sadrian if (resetFreqBin >= freqBin) 2659219863Sadrian biaslevel = (uint8_t)(XPA_LVL_FREQ(freqCount) >> 14); 2660219863Sadrian else 2661219863Sadrian break; 2662219863Sadrian freqCount++; 2663219863Sadrian } 2664219863Sadrian } 2665219863Sadrian 2666219863Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n", 2667219863Sadrian __func__, biaslevel); 2668219863Sadrian 2669219863Sadrian /* 2670219863Sadrian * This is a dirty workaround for the const initval data, 2671219863Sadrian * which will upset multiple AR9160's on the same board. 2672219863Sadrian * 2673219863Sadrian * The HAL should likely just have a private copy of the addac 2674219863Sadrian * data per instance. 2675219863Sadrian */ 2676219863Sadrian if (IEEE80211_IS_CHAN_2GHZ(chan)) 2677219863Sadrian HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) = 2678219863Sadrian (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3; 2679219863Sadrian else 2680219863Sadrian HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) = 2681219863Sadrian (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6; 2682219863Sadrian#undef XPA_LVL_FREQ 2683219863Sadrian} 2684219863Sadrian 2685220738Sadrianstatic void 2686220738Sadrianar5416MarkPhyInactive(struct ath_hal *ah) 2687220738Sadrian{ 2688220738Sadrian OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2689220738Sadrian} 2690