ar5212_keycache.c revision 185377
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5212_keycache.c,v 1.4 2008/11/10 04:08:03 sam Exp $ 18 */ 19#include "opt_ah.h" 20 21#ifdef AH_SUPPORT_AR5212 22 23#include "ah.h" 24#include "ah_internal.h" 25 26#include "ar5212/ar5212.h" 27#include "ar5212/ar5212reg.h" 28#include "ar5212/ar5212desc.h" 29 30/* 31 * Note: The key cache hardware requires that each double-word 32 * pair be written in even/odd order (since the destination is 33 * a 64-bit register). Don't reorder the writes in this code 34 * w/o considering this! 35 */ 36#define KEY_XOR 0xaa 37 38#define IS_MIC_ENABLED(ah) \ 39 (AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) 40 41/* 42 * Return the size of the hardware key cache. 43 */ 44uint32_t 45ar5212GetKeyCacheSize(struct ath_hal *ah) 46{ 47 return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize; 48} 49 50/* 51 * Return true if the specific key cache entry is valid. 52 */ 53HAL_BOOL 54ar5212IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry) 55{ 56 if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) { 57 uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 58 if (val & AR_KEYTABLE_VALID) 59 return AH_TRUE; 60 } 61 return AH_FALSE; 62} 63 64/* 65 * Clear the specified key cache entry and any associated MIC entry. 66 */ 67HAL_BOOL 68ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry) 69{ 70 uint32_t keyType; 71 72 if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) { 73 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 74 __func__, entry); 75 return AH_FALSE; 76 } 77 keyType = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 78 79 /* XXX why not clear key type/valid bit first? */ 80 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 81 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 82 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 83 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 84 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 85 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 86 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 87 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 88 if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) { 89 uint16_t micentry = entry+64; /* MIC goes at slot+64 */ 90 91 HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize); 92 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 93 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 94 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 95 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 96 /* NB: key type and MAC are known to be ok */ 97 } 98 return AH_TRUE; 99} 100 101/* 102 * Sets the mac part of the specified key cache entry (and any 103 * associated MIC entry) and mark them valid. 104 */ 105HAL_BOOL 106ar5212SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) 107{ 108 uint32_t macHi, macLo; 109 110 if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) { 111 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 112 __func__, entry); 113 return AH_FALSE; 114 } 115 /* 116 * Set MAC address -- shifted right by 1. MacLo is 117 * the 4 MSBs, and MacHi is the 2 LSBs. 118 */ 119 if (mac != AH_NULL) { 120 macHi = (mac[5] << 8) | mac[4]; 121 macLo = (mac[3] << 24)| (mac[2] << 16) 122 | (mac[1] << 8) | mac[0]; 123 macLo >>= 1; 124 macLo |= (macHi & 1) << 31; /* carry */ 125 macHi >>= 1; 126 } else { 127 macLo = macHi = 0; 128 } 129 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 130 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 131 return AH_TRUE; 132} 133 134/* 135 * Sets the contents of the specified key cache entry 136 * and any associated MIC entry. 137 */ 138HAL_BOOL 139ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 140 const HAL_KEYVAL *k, const uint8_t *mac, 141 int xorKey) 142{ 143 struct ath_hal_5212 *ahp = AH5212(ah); 144 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 145 uint32_t key0, key1, key2, key3, key4; 146 uint32_t keyType; 147 uint32_t xorMask = xorKey ? 148 (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0; 149 150 if (entry >= pCap->halKeyCacheSize) { 151 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 152 __func__, entry); 153 return AH_FALSE; 154 } 155 switch (k->kv_type) { 156 case HAL_CIPHER_AES_OCB: 157 keyType = AR_KEYTABLE_TYPE_AES; 158 break; 159 case HAL_CIPHER_AES_CCM: 160 if (!pCap->halCipherAesCcmSupport) { 161 HALDEBUG(ah, HAL_DEBUG_ANY, 162 "%s: AES-CCM not supported by mac rev 0x%x\n", 163 __func__, AH_PRIVATE(ah)->ah_macRev); 164 return AH_FALSE; 165 } 166 keyType = AR_KEYTABLE_TYPE_CCM; 167 break; 168 case HAL_CIPHER_TKIP: 169 keyType = AR_KEYTABLE_TYPE_TKIP; 170 if (IS_MIC_ENABLED(ah) && entry+64 >= pCap->halKeyCacheSize) { 171 HALDEBUG(ah, HAL_DEBUG_ANY, 172 "%s: entry %u inappropriate for TKIP\n", 173 __func__, entry); 174 return AH_FALSE; 175 } 176 break; 177 case HAL_CIPHER_WEP: 178 if (k->kv_len < 40 / NBBY) { 179 HALDEBUG(ah, HAL_DEBUG_ANY, 180 "%s: WEP key length %u too small\n", 181 __func__, k->kv_len); 182 return AH_FALSE; 183 } 184 if (k->kv_len <= 40 / NBBY) 185 keyType = AR_KEYTABLE_TYPE_40; 186 else if (k->kv_len <= 104 / NBBY) 187 keyType = AR_KEYTABLE_TYPE_104; 188 else 189 keyType = AR_KEYTABLE_TYPE_128; 190 break; 191 case HAL_CIPHER_CLR: 192 keyType = AR_KEYTABLE_TYPE_CLR; 193 break; 194 default: 195 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n", 196 __func__, k->kv_type); 197 return AH_FALSE; 198 } 199 200 key0 = LE_READ_4(k->kv_val+0) ^ xorMask; 201 key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff; 202 key2 = LE_READ_4(k->kv_val+6) ^ xorMask; 203 key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff; 204 key4 = LE_READ_4(k->kv_val+12) ^ xorMask; 205 if (k->kv_len <= 104 / NBBY) 206 key4 &= 0xff; 207 208 /* 209 * Note: key cache hardware requires that each double-word 210 * pair be written in even/odd order (since the destination is 211 * a 64-bit register). Don't reorder these writes w/o 212 * considering this! 213 */ 214 if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) { 215 uint16_t micentry = entry+64; /* MIC goes at slot+64 */ 216 uint32_t mic0, mic1, mic2, mic3, mic4; 217 218 /* 219 * Invalidate the encrypt/decrypt key until the MIC 220 * key is installed so pending rx frames will fail 221 * with decrypt errors rather than a MIC error. 222 */ 223 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 224 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 225 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 226 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 227 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 228 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 229 (void) ar5212SetKeyCacheEntryMac(ah, entry, mac); 230 231 232 /* 233 * Write MIC entry according to new or old key layout. 234 * The MISC_MODE register is assumed already set so 235 * these writes will be handled properly (happens on 236 * attach and at every reset). 237 */ 238 /* RX mic */ 239 mic0 = LE_READ_4(k->kv_mic+0); 240 mic2 = LE_READ_4(k->kv_mic+4); 241 if (ahp->ah_miscMode & AR_MISC_MODE_MIC_NEW_LOC_ENABLE) { 242 /* 243 * Both RX and TX mic values can be combined into 244 * one cache slot entry: 245 * 8*N + 800 31:0 RX Michael key 0 246 * 8*N + 804 15:0 TX Michael key 0 [31:16] 247 * 8*N + 808 31:0 RX Michael key 1 248 * 8*N + 80C 15:0 TX Michael key 0 [15:0] 249 * 8*N + 810 31:0 TX Michael key 1 250 * 8*N + 814 15:0 reserved 251 * 8*N + 818 31:0 reserved 252 * 8*N + 81C 14:0 reserved 253 * 15 key valid == 0 254 */ 255 /* TX mic */ 256 mic1 = LE_READ_2(k->kv_txmic+2) & 0xffff; 257 mic3 = LE_READ_2(k->kv_txmic+0) & 0xffff; 258 mic4 = LE_READ_4(k->kv_txmic+4); 259 } else { 260 mic1 = mic3 = mic4 = 0; 261 } 262 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 263 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 264 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 265 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 266 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 267 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 268 AR_KEYTABLE_TYPE_CLR); 269 /* NB: MIC key is not marked valid and has no MAC address */ 270 OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 271 OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 272 273 /* correct intentionally corrupted key */ 274 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 275 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 276 } else { 277 OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 278 OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 279 OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 280 OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 281 OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 282 OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 283 284 (void) ar5212SetKeyCacheEntryMac(ah, entry, mac); 285 } 286 return AH_TRUE; 287} 288#endif /* AH_SUPPORT_AR5212 */ 289