ar5211_keycache.c revision 185377
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185377Ssam * $Id: ar5211_keycache.c,v 1.4 2008/11/10 04:08:02 sam Exp $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#ifdef AH_SUPPORT_AR5211 22185377Ssam 23185377Ssam#include "ah.h" 24185377Ssam#include "ah_internal.h" 25185377Ssam 26185377Ssam#include "ar5211/ar5211.h" 27185377Ssam#include "ar5211/ar5211reg.h" 28185377Ssam 29185377Ssam/* 30185377Ssam * Chips-specific key cache routines. 31185377Ssam */ 32185377Ssam 33185377Ssam#define AR_KEYTABLE_SIZE 128 34185377Ssam#define KEY_XOR 0xaa 35185377Ssam 36185377Ssam/* 37185377Ssam * Return the size of the hardware key cache. 38185377Ssam */ 39185377Ssamuint32_t 40185377Ssamar5211GetKeyCacheSize(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam return AR_KEYTABLE_SIZE; 43185377Ssam} 44185377Ssam 45185377Ssam/* 46185377Ssam * Return true if the specific key cache entry is valid. 47185377Ssam */ 48185377SsamHAL_BOOL 49185377Ssamar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry) 50185377Ssam{ 51185377Ssam if (entry < AR_KEYTABLE_SIZE) { 52185377Ssam uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 53185377Ssam if (val & AR_KEYTABLE_VALID) 54185377Ssam return AH_TRUE; 55185377Ssam } 56185377Ssam return AH_FALSE; 57185377Ssam} 58185377Ssam 59185377Ssam/* 60185377Ssam * Clear the specified key cache entry 61185377Ssam */ 62185377SsamHAL_BOOL 63185377Ssamar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry) 64185377Ssam{ 65185377Ssam if (entry < AR_KEYTABLE_SIZE) { 66185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 67185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 68185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 69185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 70185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 71185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0); 72185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 73185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 74185377Ssam return AH_TRUE; 75185377Ssam } 76185377Ssam return AH_FALSE; 77185377Ssam} 78185377Ssam 79185377Ssam/* 80185377Ssam * Sets the mac part of the specified key cache entry and mark it valid. 81185377Ssam */ 82185377SsamHAL_BOOL 83185377Ssamar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) 84185377Ssam{ 85185377Ssam uint32_t macHi, macLo; 86185377Ssam 87185377Ssam if (entry >= AR_KEYTABLE_SIZE) { 88185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 89185377Ssam __func__, entry); 90185377Ssam return AH_FALSE; 91185377Ssam } 92185377Ssam 93185377Ssam /* 94185377Ssam * Set MAC address -- shifted right by 1. MacLo is 95185377Ssam * the 4 MSBs, and MacHi is the 2 LSBs. 96185377Ssam */ 97185377Ssam if (mac != AH_NULL) { 98185377Ssam macHi = (mac[5] << 8) | mac[4]; 99185377Ssam macLo = (mac[3] << 24)| (mac[2] << 16) 100185377Ssam | (mac[1] << 8) | mac[0]; 101185377Ssam macLo >>= 1; 102185377Ssam macLo |= (macHi & 1) << 31; /* carry */ 103185377Ssam macHi >>= 1; 104185377Ssam } else { 105185377Ssam macLo = macHi = 0; 106185377Ssam } 107185377Ssam 108185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 109185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 110185377Ssam return AH_TRUE; 111185377Ssam} 112185377Ssam 113185377Ssam/* 114185377Ssam * Sets the contents of the specified key cache entry. 115185377Ssam */ 116185377SsamHAL_BOOL 117185377Ssamar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 118185377Ssam const HAL_KEYVAL *k, const uint8_t *mac, 119185377Ssam int xorKey) 120185377Ssam{ 121185377Ssam uint32_t key0, key1, key2, key3, key4; 122185377Ssam uint32_t keyType; 123185377Ssam uint32_t xorMask= xorKey ? 124185377Ssam (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0; 125185377Ssam 126185377Ssam if (entry >= AR_KEYTABLE_SIZE) { 127185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 128185377Ssam __func__, entry); 129185377Ssam return AH_FALSE; 130185377Ssam } 131185377Ssam switch (k->kv_type) { 132185377Ssam case HAL_CIPHER_AES_OCB: 133185377Ssam keyType = AR_KEYTABLE_TYPE_AES; 134185377Ssam break; 135185377Ssam case HAL_CIPHER_WEP: 136185377Ssam if (k->kv_len < 40 / NBBY) { 137185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 138185377Ssam "%s: WEP key length %u too small\n", 139185377Ssam __func__, k->kv_len); 140185377Ssam return AH_FALSE; 141185377Ssam } 142185377Ssam if (k->kv_len <= 40 / NBBY) 143185377Ssam keyType = AR_KEYTABLE_TYPE_40; 144185377Ssam else if (k->kv_len <= 104 / NBBY) 145185377Ssam keyType = AR_KEYTABLE_TYPE_104; 146185377Ssam else 147185377Ssam keyType = AR_KEYTABLE_TYPE_128; 148185377Ssam break; 149185377Ssam case HAL_CIPHER_CLR: 150185377Ssam keyType = AR_KEYTABLE_TYPE_CLR; 151185377Ssam break; 152185377Ssam default: 153185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n", 154185377Ssam __func__, k->kv_type); 155185377Ssam return AH_FALSE; 156185377Ssam } 157185377Ssam 158185377Ssam key0 = LE_READ_4(k->kv_val+0) ^ xorMask; 159185377Ssam key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff; 160185377Ssam key2 = LE_READ_4(k->kv_val+6) ^ xorMask; 161185377Ssam key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff; 162185377Ssam key4 = LE_READ_4(k->kv_val+12) ^ xorMask; 163185377Ssam if (k->kv_len <= 104 / NBBY) 164185377Ssam key4 &= 0xff; 165185377Ssam 166185377Ssam 167185377Ssam /* 168185377Ssam * Note: WEP key cache hardware requires that each double-word 169185377Ssam * pair be written in even/odd order (since the destination is 170185377Ssam * a 64-bit register). Don't reorder these writes w/o 171185377Ssam * understanding this! 172185377Ssam */ 173185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 174185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 175185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 176185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 177185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 178185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 179185377Ssam return ar5211SetKeyCacheEntryMac(ah, entry, mac); 180185377Ssam} 181185377Ssam#endif /* AH_SUPPORT_AR5211 */ 182