1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam 24185377Ssam#include "ar5211/ar5211.h" 25185377Ssam#include "ar5211/ar5211reg.h" 26185377Ssam 27185377Ssam/* 28185377Ssam * Chips-specific key cache routines. 29185377Ssam */ 30185377Ssam 31185377Ssam#define AR_KEYTABLE_SIZE 128 32185377Ssam#define KEY_XOR 0xaa 33185377Ssam 34185377Ssam/* 35185377Ssam * Return the size of the hardware key cache. 36185377Ssam */ 37185377Ssamuint32_t 38185377Ssamar5211GetKeyCacheSize(struct ath_hal *ah) 39185377Ssam{ 40185377Ssam return AR_KEYTABLE_SIZE; 41185377Ssam} 42185377Ssam 43185377Ssam/* 44185377Ssam * Return true if the specific key cache entry is valid. 45185377Ssam */ 46185377SsamHAL_BOOL 47185377Ssamar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry) 48185377Ssam{ 49185377Ssam if (entry < AR_KEYTABLE_SIZE) { 50185377Ssam uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 51185377Ssam if (val & AR_KEYTABLE_VALID) 52185377Ssam return AH_TRUE; 53185377Ssam } 54185377Ssam return AH_FALSE; 55185377Ssam} 56185377Ssam 57185377Ssam/* 58185377Ssam * Clear the specified key cache entry 59185377Ssam */ 60185377SsamHAL_BOOL 61185377Ssamar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry) 62185377Ssam{ 63185377Ssam if (entry < AR_KEYTABLE_SIZE) { 64185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 65185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 66185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 67185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 68185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 69185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0); 70185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 71185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 72185377Ssam return AH_TRUE; 73185377Ssam } 74185377Ssam return AH_FALSE; 75185377Ssam} 76185377Ssam 77185377Ssam/* 78185377Ssam * Sets the mac part of the specified key cache entry and mark it valid. 79185377Ssam */ 80185377SsamHAL_BOOL 81185377Ssamar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) 82185377Ssam{ 83185377Ssam uint32_t macHi, macLo; 84185377Ssam 85185377Ssam if (entry >= AR_KEYTABLE_SIZE) { 86185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 87185377Ssam __func__, entry); 88185377Ssam return AH_FALSE; 89185377Ssam } 90185377Ssam 91185377Ssam /* 92185377Ssam * Set MAC address -- shifted right by 1. MacLo is 93185377Ssam * the 4 MSBs, and MacHi is the 2 LSBs. 94185377Ssam */ 95185377Ssam if (mac != AH_NULL) { 96185377Ssam macHi = (mac[5] << 8) | mac[4]; 97185377Ssam macLo = (mac[3] << 24)| (mac[2] << 16) 98185377Ssam | (mac[1] << 8) | mac[0]; 99185377Ssam macLo >>= 1; 100185377Ssam macLo |= (macHi & 1) << 31; /* carry */ 101185377Ssam macHi >>= 1; 102185377Ssam } else { 103185377Ssam macLo = macHi = 0; 104185377Ssam } 105185377Ssam 106185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 107185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 108185377Ssam return AH_TRUE; 109185377Ssam} 110185377Ssam 111185377Ssam/* 112185377Ssam * Sets the contents of the specified key cache entry. 113185377Ssam */ 114185377SsamHAL_BOOL 115185377Ssamar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 116185377Ssam const HAL_KEYVAL *k, const uint8_t *mac, 117185377Ssam int xorKey) 118185377Ssam{ 119185377Ssam uint32_t key0, key1, key2, key3, key4; 120185377Ssam uint32_t keyType; 121185377Ssam uint32_t xorMask= xorKey ? 122185377Ssam (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0; 123185377Ssam 124185377Ssam if (entry >= AR_KEYTABLE_SIZE) { 125185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n", 126185377Ssam __func__, entry); 127185377Ssam return AH_FALSE; 128185377Ssam } 129185377Ssam switch (k->kv_type) { 130185377Ssam case HAL_CIPHER_AES_OCB: 131185377Ssam keyType = AR_KEYTABLE_TYPE_AES; 132185377Ssam break; 133185377Ssam case HAL_CIPHER_WEP: 134185377Ssam if (k->kv_len < 40 / NBBY) { 135185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 136185377Ssam "%s: WEP key length %u too small\n", 137185377Ssam __func__, k->kv_len); 138185377Ssam return AH_FALSE; 139185377Ssam } 140185377Ssam if (k->kv_len <= 40 / NBBY) 141185377Ssam keyType = AR_KEYTABLE_TYPE_40; 142185377Ssam else if (k->kv_len <= 104 / NBBY) 143185377Ssam keyType = AR_KEYTABLE_TYPE_104; 144185377Ssam else 145185377Ssam keyType = AR_KEYTABLE_TYPE_128; 146185377Ssam break; 147185377Ssam case HAL_CIPHER_CLR: 148185377Ssam keyType = AR_KEYTABLE_TYPE_CLR; 149185377Ssam break; 150185377Ssam default: 151185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n", 152185377Ssam __func__, k->kv_type); 153185377Ssam return AH_FALSE; 154185377Ssam } 155185377Ssam 156185377Ssam key0 = LE_READ_4(k->kv_val+0) ^ xorMask; 157185377Ssam key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff; 158185377Ssam key2 = LE_READ_4(k->kv_val+6) ^ xorMask; 159185377Ssam key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff; 160185377Ssam key4 = LE_READ_4(k->kv_val+12) ^ xorMask; 161185377Ssam if (k->kv_len <= 104 / NBBY) 162185377Ssam key4 &= 0xff; 163185377Ssam 164185377Ssam 165185377Ssam /* 166185377Ssam * Note: WEP key cache hardware requires that each double-word 167185377Ssam * pair be written in even/odd order (since the destination is 168185377Ssam * a 64-bit register). Don't reorder these writes w/o 169185377Ssam * understanding this! 170185377Ssam */ 171185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 172185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 173185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 174185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 175185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 176185377Ssam OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 177185377Ssam return ar5211SetKeyCacheEntryMac(ah, entry, mac); 178185377Ssam} 179