1185377Ssam/*
2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3185377Ssam * Copyright (c) 2002-2004 Atheros Communications, Inc.
4185377Ssam *
5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any
6185377Ssam * purpose with or without fee is hereby granted, provided that the above
7185377Ssam * copyright notice and this permission notice appear in all copies.
8185377Ssam *
9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16185377Ssam *
17187831Ssam * $FreeBSD$
18185377Ssam */
19185377Ssam#ifndef _ATH_AR5210_H_
20185377Ssam#define _ATH_AR5210_H_
21185377Ssam
22185377Ssam#define	AR5210_MAGIC	0x19980124
23185377Ssam
24185377Ssam#if 0
25185377Ssam/*
26185377Ssam * RTS_ENABLE includes LONG_PKT because they essentially
27185377Ssam * imply the same thing, and are set or not set together
28185377Ssam * for this chip
29185377Ssam */
30185377Ssam#define AR5210_TXD_CTRL_A_HDR_LEN(_val)         (((_val)      ) & 0x0003f)
31185377Ssam#define AR5210_TXD_CTRL_A_TX_RATE(_val)         (((_val) <<  6) & 0x003c0)
32185377Ssam#define AR5210_TXD_CTRL_A_RTS_ENABLE            (                 0x00c00)
33185377Ssam#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34185377Ssam#define AR5210_TXD_CTRL_A_ANT_MODE(_val)        (((_val) << 13) & 0x02000)
35185377Ssam#define AR5210_TXD_CTRL_A_PKT_TYPE(_val)        (((_val) << 14) & 0x1c000)
36185377Ssam#define AR5210_TXD_CTRL_A_INT_REQ               (                 0x20000)
37185377Ssam#define AR5210_TXD_CTRL_A_KEY_VALID             (                 0x40000)
38185377Ssam#define AR5210_TXD_CTRL_B_KEY_ID(_val)          (((_val)      ) & 0x0003f)
39185377Ssam#define AR5210_TXD_CTRL_B_RTS_DURATION(_val)    (((_val) <<  6) & 0x7ffc0)
40185377Ssam#endif
41185377Ssam
42185377Ssam#define INIT_CONFIG_STATUS              0x00000000
43185377Ssam#define INIT_ACKTOPS                    0x00000008
44185377Ssam#define INIT_BCON_CNTRL_REG             0x00000000
45185377Ssam#define INIT_SLOT_TIME                  0x00000168
46185377Ssam#define INIT_SLOT_TIME_TURBO            0x000001e0 /* More aggressive turbo slot timing = 6 us */
47185377Ssam#define INIT_ACK_CTS_TIMEOUT            0x04000400
48185377Ssam#define INIT_ACK_CTS_TIMEOUT_TURBO      0x08000800
49185377Ssam
50185377Ssam#define INIT_USEC                       0x27
51185377Ssam#define INIT_USEC_TURBO                 0x4f
52185377Ssam#define INIT_USEC_32                    0x1f
53185377Ssam#define INIT_TX_LATENCY                 0x36
54185377Ssam#define INIT_RX_LATENCY                 0x1D
55185377Ssam#define INIT_TRANSMIT_LATENCY \
56185377Ssam	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
57185377Ssam	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
58185377Ssam	 (INIT_USEC_32 << 7) | INIT_USEC )
59185377Ssam#define INIT_TRANSMIT_LATENCY_TURBO  \
60185377Ssam	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
61185377Ssam	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
62185377Ssam	 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
63185377Ssam
64185377Ssam#define INIT_SIFS                       0x230 /* = 16 us - 2 us */
65185377Ssam#define INIT_SIFS_TURBO                 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
66185377Ssam
67185377Ssam/*
68185377Ssam * Various fifo fill before Tx start, in 64-byte units
69185377Ssam * i.e. put the frame in the air while still DMAing
70185377Ssam */
71185377Ssam#define MIN_TX_FIFO_THRESHOLD           0x1
72185377Ssam#define MAX_TX_FIFO_THRESHOLD           ((IEEE80211_MAX_LEN / 64) + 1)
73185377Ssam
74185377Ssam#define INIT_NEXT_CFP_START             0xffffffff
75185377Ssam
76185377Ssam#define INIT_BEACON_PERIOD              0xffff
77185377Ssam#define INIT_BEACON_EN                  0 /* this should be set by AP only when it's ready */
78185377Ssam#define INIT_BEACON_CONTROL \
79185377Ssam	((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
80185377Ssam	 (INIT_TIM_OFFSET<<16)  | INIT_BEACON_PERIOD)
81185377Ssam
82185377Ssam#define INIT_RSSI_THR                   0x00000700 /* Missed beacon counter initialized to max value of 7 */
83185377Ssam#define INIT_ProgIFS                    0x398      /* PIFS - 2us */
84185377Ssam#define INIT_ProgIFS_TURBO              0x3C0
85185377Ssam#define INIT_EIFS                       0xd70
86185377Ssam#define INIT_EIFS_TURBO                 0x1ae0
87185377Ssam#define INIT_CARR_SENSE_EN              1
88185377Ssam#define INIT_PROTO_TIME_CNTRL           ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
89185377Ssam                                          (INIT_ProgIFS) )
90185377Ssam#define INIT_PROTO_TIME_CNTRL_TURBO     ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
91185377Ssam                                          (INIT_ProgIFS_TURBO) )
92185377Ssam
93185380Ssam#define	AR5210_MAX_RATE_POWER	60
94185377Ssam
95185377Ssam#undef HAL_NUM_TX_QUEUES	/* from ah.h */
96185377Ssam#define	HAL_NUM_TX_QUEUES	3
97185377Ssam
98185377Ssamstruct ath_hal_5210 {
99185377Ssam	struct ath_hal_private ah_priv;	/* base definitions */
100185377Ssam
101185377Ssam	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
102185377Ssam	/*
103185377Ssam	 * Runtime state.
104185377Ssam	 */
105185377Ssam	uint32_t	ah_maskReg;		/* shadow of IMR+IER regs */
106185377Ssam	uint32_t	ah_txOkInterruptMask;
107185377Ssam	uint32_t	ah_txErrInterruptMask;
108185377Ssam	uint32_t	ah_txDescInterruptMask;
109185377Ssam	uint32_t	ah_txEolInterruptMask;
110185377Ssam	uint32_t	ah_txUrnInterruptMask;
111185377Ssam	HAL_POWER_MODE	ah_powerMode;
112185377Ssam	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
113185377Ssam	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
114185377Ssam	/*
115185377Ssam	 * Station mode support.
116185377Ssam	 */
117185377Ssam	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
118185377Ssam	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
119185377Ssam
120185377Ssam	u_int		ah_sifstime;		/* user-specified sifs time */
121185377Ssam	u_int		ah_slottime;		/* user-specified slot time */
122185377Ssam	u_int		ah_acktimeout;		/* user-specified ack timeout */
123185377Ssam	u_int		ah_ctstimeout;		/* user-specified cts timeout */
124185377Ssam};
125185377Ssam#define	AH5210(ah)	((struct ath_hal_5210 *)(ah))
126185377Ssam
127185377Ssamstruct ath_hal;
128185377Ssam
129185406Ssamextern	void ar5210Detach(struct ath_hal *ah);
130185377Ssamextern	HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
131187831Ssam		struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *);
132185377Ssamextern	void ar5210SetPCUConfig(struct ath_hal *);
133185377Ssamextern	HAL_BOOL ar5210PhyDisable(struct ath_hal *);
134185377Ssamextern	HAL_BOOL ar5210Disable(struct ath_hal *);
135187831Ssamextern	HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);
136187831Ssamextern	HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
137187831Ssamextern	HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
138185380Ssam		u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
139187831Ssamextern	HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
140185377Ssamextern	int16_t ar5210GetNoiseFloor(struct ath_hal *);
141185377Ssamextern	int16_t ar5210GetNfAdjust(struct ath_hal *,
142185377Ssam		const HAL_CHANNEL_INTERNAL *);
143185377Ssamextern	HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
144187831Ssamextern	HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,
145187831Ssam		const struct ieee80211_channel *);
146185377Ssamextern	HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
147185377Ssamextern	HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
148185377Ssam
149185377Ssamextern  HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
150185377Ssam		const HAL_TXQ_INFO *qInfo);
151185377Ssamextern	HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
152185377Ssam		HAL_TXQ_INFO *qInfo);
153185377Ssamextern	int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
154185377Ssam		const HAL_TXQ_INFO *qInfo);
155185377Ssamextern	HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
156185377Ssamextern	HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
157185377Ssamextern	uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
158185377Ssamextern	HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
159185377Ssamextern	HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
160185377Ssamextern	uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
161185377Ssamextern	HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
162185377Ssamextern	HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
163185377Ssamextern	HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
164185377Ssam		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
165185377Ssam		u_int txRate0, u_int txRetries0,
166185377Ssam		u_int keyIx, u_int antMode, u_int flags,
167185377Ssam		u_int rtsctsRate, u_int rtsctsDuration,
168185377Ssam                u_int compicvLen, u_int compivLen, u_int comp);
169185377Ssamextern	HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
170185377Ssam		u_int txRate1, u_int txRetries1,
171185377Ssam		u_int txRate2, u_int txRetries2,
172185377Ssam		u_int txRate3, u_int txRetries3);
173185377Ssamextern	HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
174185377Ssam		u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
175185377Ssam		const struct ath_desc *ds0);
176185377Ssamextern	HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
177185377Ssam		struct ath_desc *, struct ath_tx_status *);
178185377Ssamextern  void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
179185377Ssamextern  void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
180217621Sadrianextern	HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,
181217621Sadrian		const struct ath_desc *, int *rates, int *tries);
182185377Ssam
183185377Ssamextern	uint32_t ar5210GetRxDP(struct ath_hal *);
184185377Ssamextern	void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
185185377Ssamextern	void ar5210EnableReceive(struct ath_hal *);
186185377Ssamextern	HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
187185377Ssamextern	void ar5210StartPcuReceive(struct ath_hal *);
188185377Ssamextern	void ar5210StopPcuReceive(struct ath_hal *);
189185377Ssamextern	void ar5210SetMulticastFilter(struct ath_hal *,
190185377Ssam		uint32_t filter0, uint32_t filter1);
191185377Ssamextern	HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
192185377Ssamextern	HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
193185377Ssamextern	uint32_t ar5210GetRxFilter(struct ath_hal *);
194185377Ssamextern	void ar5210SetRxFilter(struct ath_hal *, uint32_t);
195185377Ssamextern	HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
196185377Ssam		uint32_t, u_int flags);
197185377Ssamextern	HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
198185377Ssam		uint32_t, struct ath_desc *, uint64_t,
199185377Ssam		struct ath_rx_status *);
200185377Ssam
201185377Ssamextern	void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
202185377Ssamextern	HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
203185377Ssamextern	void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
204185377Ssamextern	HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
205185377Ssamextern	HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
206185377Ssamextern	HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
207185377Ssamextern	HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
208185377Ssam		uint16_t, HAL_STATUS *);
209185377Ssamextern	u_int ar5210GetWirelessModes(struct ath_hal *ah);
210185377Ssamextern	void ar5210EnableRfKill(struct ath_hal *);
211185377Ssamextern	HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
212188974Ssamextern	HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
213188974Ssam		HAL_GPIO_MUX_TYPE);
214185377Ssamextern	uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
215185377Ssamextern	HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
216185377Ssamextern	void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
217185377Ssamextern	void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
218185377Ssamextern	u_int ar5210GetDefAntenna(struct ath_hal *);
219185377Ssamextern	void ar5210SetDefAntenna(struct ath_hal *, u_int);
220185377Ssamextern	HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
221185377Ssamextern	HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
222185377Ssamextern	void ar5210WriteAssocid(struct ath_hal *,
223185377Ssam		const uint8_t *bssid, uint16_t assocId);
224185377Ssamextern	uint32_t ar5210GetTsf32(struct ath_hal *);
225185377Ssamextern	uint64_t ar5210GetTsf64(struct ath_hal *);
226185377Ssamextern	void ar5210ResetTsf(struct ath_hal *);
227185377Ssamextern	uint32_t ar5210GetRandomSeed(struct ath_hal *);
228185377Ssamextern	HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
229185377Ssamextern	void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
230185377Ssamextern	void ar5210EnableHwEncryption(struct ath_hal *);
231185377Ssamextern	void ar5210DisableHwEncryption(struct ath_hal *);
232185377Ssamextern	HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
233185377Ssamextern	HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
234185377Ssamextern	u_int ar5210GetSifsTime(struct ath_hal *);
235185377Ssamextern	HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
236185377Ssamextern	u_int ar5210GetSlotTime(struct ath_hal *);
237185377Ssamextern	HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
238185377Ssamextern	u_int ar5210GetAckTimeout(struct ath_hal *);
239185377Ssamextern	HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
240185377Ssamextern	u_int ar5210GetAckCTSRate(struct ath_hal *);
241185377Ssamextern	HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
242185377Ssamextern	u_int ar5210GetCTSTimeout(struct ath_hal *);
243185377Ssamextern  HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
244185377Ssamvoid 	ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
245185377Ssamextern	HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
246185377Ssam		uint32_t, uint32_t *);
247185377Ssamextern	HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
248185377Ssam		uint32_t, uint32_t, HAL_STATUS *);
249185377Ssamextern	HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
250185377Ssam		const void *args, uint32_t argsize,
251185377Ssam		void **result, uint32_t *resultsize);
252185377Ssam
253185377Ssamextern	u_int ar5210GetKeyCacheSize(struct ath_hal *);
254185377Ssamextern	HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
255185377Ssamextern	HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
256185377Ssamextern	HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
257185377Ssam                       const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
258185377Ssamextern	HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
259185377Ssam			uint16_t, const uint8_t *);
260185377Ssam
261185377Ssamextern	HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
262185377Ssam		int setChip);
263185377Ssamextern	HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
264185377Ssam
265185377Ssamextern	void ar5210SetBeaconTimers(struct ath_hal *,
266185377Ssam		const HAL_BEACON_TIMERS *);
267185377Ssamextern	void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
268185377Ssamextern	void ar5210SetStaBeaconTimers(struct ath_hal *,
269185377Ssam		const HAL_BEACON_STATE *);
270185377Ssamextern	void ar5210ResetStaBeaconTimers(struct ath_hal *);
271225444Sadrianextern	uint64_t ar5210GetNextTBTT(struct ath_hal *);
272185377Ssam
273185377Ssamextern	HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
274185377Ssamextern	HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
275185377Ssamextern	HAL_INT ar5210GetInterrupts(struct ath_hal *);
276185377Ssamextern	HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
277185377Ssam
278185377Ssamextern	const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
279185377Ssam
280185377Ssamextern	HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
281217684Sadrianextern	void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *);
282217684Sadrianextern	void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
283187831Ssam		const struct ieee80211_channel *);
284185377Ssamextern	void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
285185377Ssam#endif /* _ATH_AR5210_H_ */
286