1219442Sadrian/* 2219442Sadrian * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3219442Sadrian * Copyright (c) 2005-2006 Atheros Communications, Inc. 4219442Sadrian * All rights reserved. 5219442Sadrian * 6219442Sadrian * Permission to use, copy, modify, and/or distribute this software for any 7219442Sadrian * purpose with or without fee is hereby granted, provided that the above 8219442Sadrian * copyright notice and this permission notice appear in all copies. 9219442Sadrian * 10219442Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11219442Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12219442Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13219442Sadrian * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14219442Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15219442Sadrian * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16219442Sadrian * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17219442Sadrian * 18219442Sadrian * $FreeBSD$ 19219442Sadrian */ 20219442Sadrian 21219442Sadrian#ifndef __AH_REGDOMAIN_FREQBANDS_H__ 22219442Sadrian#define __AH_REGDOMAIN_FREQBANDS_H__ 23219442Sadrian 24219442Sadrian#define AFTER(x) ((x)+1) 25219442Sadrian 26219442Sadrian/* 27219442Sadrian * Frequency band collections are defined using bitmasks. Each bit 28219442Sadrian * in a mask is the index of an entry in one of the following tables. 29219442Sadrian * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 30219442Sadrian * vectors must be enlarged or the tables split somehow (e.g. split 31219442Sadrian * 1/2 and 1/4 rate channels into a separate table). 32219442Sadrian * 33219442Sadrian * Beware of ordering; the indices are defined relative to the preceding 34219442Sadrian * entry so if things get off there will be confusion. A good way to 35219442Sadrian * check the indices is to collect them in a switch statement in a stub 36219442Sadrian * function so the compiler checks for duplicates. 37219442Sadrian */ 38219442Sadrian 39219442Sadrian/* 40219442Sadrian * 5GHz 11A channel tags 41219442Sadrian */ 42219442Sadrianstatic REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { 43219442Sadrian { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 44219442Sadrian#define F1_4915_4925 0 45219442Sadrian { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 46219442Sadrian#define F1_4935_4945 AFTER(F1_4915_4925) 47219442Sadrian { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 48219442Sadrian#define F1_4920_4980 AFTER(F1_4935_4945) 49219442Sadrian { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC }, 50219442Sadrian#define F1_4942_4987 AFTER(F1_4920_4980) 51219442Sadrian { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC }, 52219442Sadrian#define F1_4945_4985 AFTER(F1_4942_4987) 53219442Sadrian { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC }, 54219442Sadrian#define F1_4950_4980 AFTER(F1_4945_4985) 55219442Sadrian { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 56219442Sadrian#define F1_5035_5040 AFTER(F1_4950_4980) 57219442Sadrian { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 58219442Sadrian#define F1_5040_5080 AFTER(F1_5035_5040) 59219442Sadrian { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 60219442Sadrian#define F1_5055_5055 AFTER(F1_5040_5080) 61219442Sadrian 62219442Sadrian { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 63219442Sadrian#define F1_5120_5240 AFTER(F1_5055_5055) 64219442Sadrian { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 65219442Sadrian#define F2_5120_5240 AFTER(F1_5120_5240) 66219442Sadrian { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 67219442Sadrian#define F3_5120_5240 AFTER(F2_5120_5240) 68219442Sadrian 69219442Sadrian { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 70219442Sadrian#define F1_5170_5230 AFTER(F3_5120_5240) 71219442Sadrian { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 72219442Sadrian#define F2_5170_5230 AFTER(F1_5170_5230) 73219442Sadrian 74219442Sadrian { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 75219442Sadrian#define F1_5180_5240 AFTER(F2_5170_5230) 76219442Sadrian { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC }, 77219442Sadrian#define F2_5180_5240 AFTER(F1_5180_5240) 78219442Sadrian { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 79219442Sadrian#define F3_5180_5240 AFTER(F2_5180_5240) 80219442Sadrian { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 81219442Sadrian#define F4_5180_5240 AFTER(F3_5180_5240) 82219442Sadrian { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 83219442Sadrian#define F5_5180_5240 AFTER(F4_5180_5240) 84219442Sadrian { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC }, 85219442Sadrian#define F6_5180_5240 AFTER(F5_5180_5240) 86219442Sadrian { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC }, 87219442Sadrian#define F7_5180_5240 AFTER(F6_5180_5240) 88219442Sadrian { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC }, 89219442Sadrian#define F8_5180_5240 AFTER(F7_5180_5240) 90219442Sadrian { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 91219442Sadrian 92219442Sadrian#define F1_5180_5320 AFTER(F8_5180_5240) 93219442Sadrian { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI }, 94219442Sadrian 95219442Sadrian#define F1_5240_5280 AFTER(F1_5180_5320) 96219442Sadrian { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 97219442Sadrian 98219442Sadrian#define F1_5260_5280 AFTER(F1_5240_5280) 99219442Sadrian { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 100219442Sadrian 101219442Sadrian#define F1_5260_5320 AFTER(F1_5260_5280) 102219442Sadrian { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 }, 103219442Sadrian#define F2_5260_5320 AFTER(F1_5260_5320) 104219442Sadrian 105219442Sadrian { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 106219442Sadrian#define F3_5260_5320 AFTER(F2_5260_5320) 107219442Sadrian { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 108219442Sadrian#define F4_5260_5320 AFTER(F3_5260_5320) 109219442Sadrian { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 110219442Sadrian#define F5_5260_5320 AFTER(F4_5260_5320) 111219442Sadrian { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 112219442Sadrian#define F6_5260_5320 AFTER(F5_5260_5320) 113219442Sadrian { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 114219442Sadrian#define F7_5260_5320 AFTER(F6_5260_5320) 115219442Sadrian { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 116219442Sadrian#define F8_5260_5320 AFTER(F7_5260_5320) 117219442Sadrian 118219442Sadrian { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 119219442Sadrian#define F1_5260_5700 AFTER(F8_5260_5320) 120219442Sadrian { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 121219442Sadrian#define F2_5260_5700 AFTER(F1_5260_5700) 122219442Sadrian { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 123219442Sadrian#define F3_5260_5700 AFTER(F2_5260_5700) 124219442Sadrian 125219442Sadrian { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 126219442Sadrian#define F1_5280_5320 AFTER(F3_5260_5700) 127219442Sadrian 128219442Sadrian { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 129219442Sadrian#define F1_5500_5620 AFTER(F1_5280_5320) 130219442Sadrian 131219442Sadrian { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 132219442Sadrian#define F1_5500_5700 AFTER(F1_5500_5620) 133219442Sadrian { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 134219442Sadrian#define F2_5500_5700 AFTER(F1_5500_5700) 135219442Sadrian { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 136219442Sadrian#define F3_5500_5700 AFTER(F2_5500_5700) 137219442Sadrian { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC }, 138219442Sadrian#define F4_5500_5700 AFTER(F3_5500_5700) 139219442Sadrian 140219442Sadrian { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN }, 141219442Sadrian#define F1_5745_5805 AFTER(F4_5500_5700) 142219442Sadrian { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 143219442Sadrian#define F2_5745_5805 AFTER(F1_5745_5805) 144219442Sadrian { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 145219442Sadrian#define F3_5745_5805 AFTER(F2_5745_5805) 146219442Sadrian { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 147219442Sadrian#define F1_5745_5825 AFTER(F3_5745_5805) 148219442Sadrian { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN }, 149219442Sadrian#define F2_5745_5825 AFTER(F1_5745_5825) 150219442Sadrian { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN }, 151219442Sadrian#define F3_5745_5825 AFTER(F2_5745_5825) 152219442Sadrian { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 153219442Sadrian#define F4_5745_5825 AFTER(F3_5745_5825) 154219442Sadrian { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 155219442Sadrian#define F5_5745_5825 AFTER(F4_5745_5825) 156219442Sadrian { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 157219442Sadrian#define F6_5745_5825 AFTER(F5_5745_5825) 158219442Sadrian { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 159219442Sadrian#define F7_5745_5825 AFTER(F6_5745_5825) 160219442Sadrian { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 161219442Sadrian#define F8_5745_5825 AFTER(F7_5745_5825) 162219442Sadrian { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN }, 163219442Sadrian#define F9_5745_5825 AFTER(F8_5745_5825) 164219442Sadrian { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN }, 165219442Sadrian#define F10_5745_5825 AFTER(F9_5745_5825) 166219442Sadrian 167219442Sadrian /* 168219442Sadrian * Below are the world roaming channels 169219442Sadrian * All WWR domains have no power limit, instead use the card's CTL 170219442Sadrian * or max power settings. 171219442Sadrian */ 172219442Sadrian { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 173219442Sadrian#define W1_4920_4980 AFTER(F10_5745_5825) 174219442Sadrian { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 175219442Sadrian#define W1_5040_5080 AFTER(W1_4920_4980) 176219442Sadrian { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 177219442Sadrian#define W1_5170_5230 AFTER(W1_5040_5080) 178219442Sadrian { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 179219442Sadrian#define W1_5180_5240 AFTER(W1_5170_5230) 180219442Sadrian { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 181219442Sadrian#define W1_5260_5320 AFTER(W1_5180_5240) 182219442Sadrian { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 183219442Sadrian#define W1_5745_5825 AFTER(W1_5260_5320) 184219442Sadrian { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 185219442Sadrian#define W1_5500_5700 AFTER(W1_5745_5825) 186219442Sadrian { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 187219442Sadrian#define W2_5260_5320 AFTER(W1_5500_5700) 188219442Sadrian { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 189219442Sadrian#define W2_5180_5240 AFTER(W2_5260_5320) 190219442Sadrian { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 191219442Sadrian#define W2_5825_5825 AFTER(W2_5180_5240) 192219442Sadrian}; 193219442Sadrian 194219442Sadrian/* 195219442Sadrian * 5GHz Turbo (dynamic & static) tags 196219442Sadrian */ 197219442Sadrianstatic REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { 198219442Sadrian { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 199219442Sadrian#define T1_5130_5210 0 200219442Sadrian { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 201219442Sadrian#define T1_5250_5330 AFTER(T1_5130_5210) 202219442Sadrian { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 203219442Sadrian#define T1_5370_5490 AFTER(T1_5250_5330) 204219442Sadrian { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 205219442Sadrian#define T1_5530_5650 AFTER(T1_5370_5490) 206219442Sadrian 207219442Sadrian { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 208219442Sadrian#define T1_5150_5190 AFTER(T1_5530_5650) 209219442Sadrian { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 210219442Sadrian#define T1_5230_5310 AFTER(T1_5150_5190) 211219442Sadrian { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 212219442Sadrian#define T1_5350_5470 AFTER(T1_5230_5310) 213219442Sadrian { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 214219442Sadrian#define T1_5510_5670 AFTER(T1_5350_5470) 215219442Sadrian 216219442Sadrian { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 217219442Sadrian#define T1_5200_5240 AFTER(T1_5510_5670) 218219442Sadrian { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN }, 219219442Sadrian#define T2_5200_5240 AFTER(T1_5200_5240) 220219442Sadrian { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 221219442Sadrian#define T1_5210_5210 AFTER(T2_5200_5240) 222219442Sadrian { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN }, 223219442Sadrian#define T2_5210_5210 AFTER(T1_5210_5210) 224219442Sadrian 225219442Sadrian { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 226219442Sadrian#define T1_5280_5280 AFTER(T2_5210_5210) 227219442Sadrian { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 228219442Sadrian#define T2_5280_5280 AFTER(T1_5280_5280) 229219442Sadrian { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 230219442Sadrian#define T1_5250_5250 AFTER(T2_5280_5280) 231219442Sadrian { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 232219442Sadrian#define T1_5290_5290 AFTER(T1_5250_5250) 233219442Sadrian { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 234219442Sadrian#define T1_5250_5290 AFTER(T1_5290_5290) 235219442Sadrian { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 236219442Sadrian#define T2_5250_5290 AFTER(T1_5250_5290) 237219442Sadrian 238219442Sadrian { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 239219442Sadrian#define T1_5540_5660 AFTER(T2_5250_5290) 240219442Sadrian { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN }, 241219442Sadrian#define T1_5760_5800 AFTER(T1_5540_5660) 242219442Sadrian { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 243219442Sadrian#define T2_5760_5800 AFTER(T1_5760_5800) 244219442Sadrian 245219442Sadrian { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 246219442Sadrian#define T1_5765_5805 AFTER(T2_5760_5800) 247219442Sadrian 248219442Sadrian /* 249219442Sadrian * Below are the WWR frequencies 250219442Sadrian */ 251219442Sadrian { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 252219442Sadrian#define WT1_5210_5250 AFTER(T1_5765_5805) 253219442Sadrian { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 254219442Sadrian#define WT1_5290_5290 AFTER(WT1_5210_5250) 255219442Sadrian { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 256219442Sadrian#define WT1_5540_5660 AFTER(WT1_5290_5290) 257219442Sadrian { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR }, 258219442Sadrian#define WT1_5760_5800 AFTER(WT1_5540_5660) 259219442Sadrian}; 260219442Sadrian 261219442Sadrian/* 262219442Sadrian * 2GHz 11b channel tags 263219442Sadrian */ 264219442Sadrianstatic REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { 265219442Sadrian { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 266219442Sadrian#define F1_2312_2372 0 267219442Sadrian { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 268219442Sadrian#define F2_2312_2372 AFTER(F1_2312_2372) 269219442Sadrian 270219442Sadrian { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 271219442Sadrian#define F1_2412_2472 AFTER(F2_2312_2372) 272219442Sadrian { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 273219442Sadrian#define F2_2412_2472 AFTER(F1_2412_2472) 274219442Sadrian { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 275219442Sadrian#define F3_2412_2472 AFTER(F2_2412_2472) 276219442Sadrian 277219442Sadrian { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 278219442Sadrian#define F1_2412_2462 AFTER(F3_2412_2472) 279219442Sadrian { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 280219442Sadrian#define F2_2412_2462 AFTER(F1_2412_2462) 281219442Sadrian 282219442Sadrian { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 283219442Sadrian#define F1_2432_2442 AFTER(F2_2412_2462) 284219442Sadrian 285219442Sadrian { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 286219442Sadrian#define F1_2457_2472 AFTER(F1_2432_2442) 287219442Sadrian 288219442Sadrian { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 289219442Sadrian#define F1_2467_2472 AFTER(F1_2457_2472) 290219442Sadrian 291219442Sadrian { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 292219442Sadrian#define F1_2484_2484 AFTER(F1_2467_2472) 293219442Sadrian { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2 }, 294219442Sadrian#define F2_2484_2484 AFTER(F1_2484_2484) 295219442Sadrian 296219442Sadrian { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 297219442Sadrian#define F1_2512_2732 AFTER(F2_2484_2484) 298219442Sadrian 299219442Sadrian /* 300219442Sadrian * WWR have powers opened up to 20dBm. 301219442Sadrian * Limits should often come from CTL/Max powers 302219442Sadrian */ 303219442Sadrian { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 304219442Sadrian#define W1_2312_2372 AFTER(F1_2512_2732) 305219442Sadrian { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 306219442Sadrian#define W1_2412_2412 AFTER(W1_2312_2372) 307219442Sadrian { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 308219442Sadrian#define W1_2417_2432 AFTER(W1_2412_2412) 309219442Sadrian { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 310219442Sadrian#define W1_2437_2442 AFTER(W1_2417_2432) 311219442Sadrian { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 312219442Sadrian#define W1_2447_2457 AFTER(W1_2437_2442) 313219442Sadrian { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 314219442Sadrian#define W1_2462_2462 AFTER(W1_2447_2457) 315219442Sadrian { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 316219442Sadrian#define W1_2467_2467 AFTER(W1_2462_2462) 317219442Sadrian { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 318219442Sadrian#define W2_2467_2467 AFTER(W1_2467_2467) 319219442Sadrian { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 320219442Sadrian#define W1_2472_2472 AFTER(W2_2467_2467) 321219442Sadrian { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 322219442Sadrian#define W2_2472_2472 AFTER(W1_2472_2472) 323219442Sadrian { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 324219442Sadrian#define W1_2484_2484 AFTER(W2_2472_2472) 325219442Sadrian { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 326219442Sadrian#define W2_2484_2484 AFTER(W1_2484_2484) 327219442Sadrian}; 328219442Sadrian 329219442Sadrian/* 330219442Sadrian * 2GHz 11g channel tags 331219442Sadrian */ 332219442Sadrianstatic REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { 333219442Sadrian { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 334219442Sadrian#define G1_2312_2372 0 335219442Sadrian { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 336219442Sadrian#define G2_2312_2372 AFTER(G1_2312_2372) 337219442Sadrian { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 338219442Sadrian#define G3_2312_2372 AFTER(G2_2312_2372) 339219442Sadrian { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 340219442Sadrian#define G4_2312_2372 AFTER(G3_2312_2372) 341219442Sadrian 342219442Sadrian { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 343219442Sadrian#define G1_2412_2472 AFTER(G4_2312_2372) 344219442Sadrian { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 345219442Sadrian#define G2_2412_2472 AFTER(G1_2412_2472) 346219442Sadrian { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 347219442Sadrian#define G3_2412_2472 AFTER(G2_2412_2472) 348219442Sadrian { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 349219442Sadrian#define G4_2412_2472 AFTER(G3_2412_2472) 350219442Sadrian { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 351219442Sadrian#define G5_2412_2472 AFTER(G4_2412_2472) 352219442Sadrian 353219442Sadrian { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 354219442Sadrian#define G1_2412_2462 AFTER(G5_2412_2472) 355219442Sadrian { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 356219442Sadrian#define G2_2412_2462 AFTER(G1_2412_2462) 357219442Sadrian { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN }, 358219442Sadrian#define G3_2412_2462 AFTER(G2_2412_2462) 359219442Sadrian { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN }, 360219442Sadrian#define G4_2412_2462 AFTER(G3_2412_2462) 361219442Sadrian 362219442Sadrian { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 363219442Sadrian#define G1_2432_2442 AFTER(G4_2412_2462) 364219442Sadrian 365219442Sadrian { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 366219442Sadrian#define G1_2457_2472 AFTER(G1_2432_2442) 367219442Sadrian 368219442Sadrian { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 369219442Sadrian#define G1_2512_2732 AFTER(G1_2457_2472) 370219442Sadrian { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 371219442Sadrian#define G2_2512_2732 AFTER(G1_2512_2732) 372219442Sadrian { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 373219442Sadrian#define G3_2512_2732 AFTER(G2_2512_2732) 374219442Sadrian 375219442Sadrian { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 376219442Sadrian#define G1_2467_2472 AFTER(G3_2512_2732) 377219442Sadrian 378219442Sadrian /* 379219442Sadrian * WWR open up the power to 20dBm 380219442Sadrian */ 381219442Sadrian { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 382219442Sadrian#define WG1_2312_2372 AFTER(G1_2467_2472) 383219442Sadrian { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 384219442Sadrian#define WG1_2412_2412 AFTER(WG1_2312_2372) 385219442Sadrian { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 386219442Sadrian#define WG1_2417_2432 AFTER(WG1_2412_2412) 387219442Sadrian { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 388219442Sadrian#define WG1_2437_2442 AFTER(WG1_2417_2432) 389219442Sadrian { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 390219442Sadrian#define WG1_2447_2457 AFTER(WG1_2437_2442) 391219442Sadrian { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 392219442Sadrian#define WG1_2462_2462 AFTER(WG1_2447_2457) 393219442Sadrian { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 394219442Sadrian#define WG1_2467_2467 AFTER(WG1_2462_2462) 395219442Sadrian { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 396219442Sadrian#define WG2_2467_2467 AFTER(WG1_2467_2467) 397219442Sadrian { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 398219442Sadrian#define WG1_2472_2472 AFTER(WG2_2467_2467) 399219442Sadrian { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 400219442Sadrian#define WG2_2472_2472 AFTER(WG1_2472_2472) 401219442Sadrian}; 402219442Sadrian 403219442Sadrian/* 404219442Sadrian * 2GHz Dynamic turbo tags 405219442Sadrian */ 406219442Sadrianstatic REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { 407219442Sadrian { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 408219442Sadrian#define T1_2312_2372 0 409219442Sadrian { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 410219442Sadrian#define T1_2437_2437 AFTER(T1_2312_2372) 411219442Sadrian { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN }, 412219442Sadrian#define T2_2437_2437 AFTER(T1_2437_2437) 413219442Sadrian { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR }, 414219442Sadrian#define T3_2437_2437 AFTER(T2_2437_2437) 415219442Sadrian { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 416219442Sadrian#define T1_2512_2732 AFTER(T3_2437_2437) 417219442Sadrian}; 418219442Sadrian 419219442Sadrian#endif 420