1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _ATH_AH_H_ 21185377Ssam#define _ATH_AH_H_ 22185377Ssam/* 23185377Ssam * Atheros Hardware Access Layer 24185377Ssam * 25185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26185377Ssam * structure for use with the device. Hardware-related operations that 27185377Ssam * follow must call back into the HAL through interface, supplying the 28185377Ssam * reference as the first parameter. 29185377Ssam */ 30185377Ssam 31185377Ssam#include "ah_osdep.h" 32185377Ssam 33185377Ssam/* 34220442Sadrian * The maximum number of TX/RX chains supported. 35220442Sadrian * This is intended to be used by various statistics gathering operations 36220442Sadrian * (NF, RSSI, EVM). 37220442Sadrian */ 38220442Sadrian#define AH_MIMO_MAX_CHAINS 3 39220442Sadrian#define AH_MIMO_MAX_EVM_PILOTS 6 40220442Sadrian 41220442Sadrian/* 42185377Ssam * __ahdecl is analogous to _cdecl; it defines the calling 43185377Ssam * convention used within the HAL. For most systems this 44185377Ssam * can just default to be empty and the compiler will (should) 45185377Ssam * use _cdecl. For systems where _cdecl is not compatible this 46185377Ssam * must be defined. See linux/ah_osdep.h for an example. 47185377Ssam */ 48185377Ssam#ifndef __ahdecl 49185377Ssam#define __ahdecl 50185377Ssam#endif 51185377Ssam 52185377Ssam/* 53185377Ssam * Status codes that may be returned by the HAL. Note that 54185377Ssam * interfaces that return a status code set it only when an 55185377Ssam * error occurs--i.e. you cannot check it for success. 56185377Ssam */ 57185377Ssamtypedef enum { 58185377Ssam HAL_OK = 0, /* No error */ 59185377Ssam HAL_ENXIO = 1, /* No hardware present */ 60185377Ssam HAL_ENOMEM = 2, /* Memory allocation failed */ 61185377Ssam HAL_EIO = 3, /* Hardware didn't respond as expected */ 62185377Ssam HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63185377Ssam HAL_EEVERSION = 5, /* EEPROM version invalid */ 64185377Ssam HAL_EELOCKED = 6, /* EEPROM unreadable */ 65185377Ssam HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66185377Ssam HAL_EEREAD = 8, /* EEPROM read problem */ 67185377Ssam HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68185377Ssam HAL_EESIZE = 10, /* EEPROM size not supported */ 69185377Ssam HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70185377Ssam HAL_EINVAL = 12, /* Invalid parameter to function */ 71185377Ssam HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72185377Ssam HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73185377Ssam HAL_EINPROGRESS = 15, /* Operation incomplete */ 74187831Ssam HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75187831Ssam HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76185377Ssam} HAL_STATUS; 77185377Ssam 78185377Ssamtypedef enum { 79185377Ssam AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 80185377Ssam AH_TRUE = 1, 81185377Ssam} HAL_BOOL; 82185377Ssam 83185377Ssamtypedef enum { 84185377Ssam HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 85185377Ssam HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 86185377Ssam HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 87185377Ssam HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 88185377Ssam HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 89185377Ssam HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 90185377Ssam HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 91185377Ssam HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 92185377Ssam HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 93185377Ssam HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 94185377Ssam HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 95185377Ssam HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 96185377Ssam HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 97185377Ssam HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 98185377Ssam HAL_CAP_TXPOW = 15, /* global tx power limit */ 99185377Ssam HAL_CAP_TPC = 16, /* per-packet tx power control */ 100185377Ssam HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 101185377Ssam HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 102185377Ssam HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 103185377Ssam HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 104185377Ssam /* 21 was HAL_CAP_XR */ 105185377Ssam HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 106185380Ssam /* 23 was HAL_CAP_CHAN_HALFRATE */ 107185380Ssam /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 108185377Ssam HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 109185377Ssam HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 110185377Ssam HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 111185377Ssam HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 112221581Sadrian 113221603Sadrian HAL_CAP_HT = 30, /* hardware can support HT */ 114221603Sadrian HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 115221603Sadrian HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 116221603Sadrian HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 117221603Sadrian HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 118221603Sadrian HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 119221581Sadrian 120221603Sadrian HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 121221581Sadrian 122221603Sadrian HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 123221603Sadrian HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 124222584Sadrian HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 125222584Sadrian HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 126222584Sadrian HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 127221603Sadrian 128221603Sadrian HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 129221603Sadrian automatically after waking up to receive TIM */ 130221603Sadrian HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 131221603Sadrian HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 132221603Sadrian HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 133221603Sadrian 134221603Sadrian HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 135221603Sadrian 136221603Sadrian HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 137221603Sadrian 138221603Sadrian HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 139222584Sadrian HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 140221603Sadrian 141221581Sadrian /* The following are private to the FreeBSD HAL (224 onward) */ 142221581Sadrian 143221603Sadrian HAL_CAP_INTMIT = 229, /* interference mitigation */ 144221603Sadrian HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 145221603Sadrian HAL_CAP_BB_HANG = 235, /* can baseband hang */ 146221603Sadrian HAL_CAP_MAC_HANG = 236, /* can MAC hang */ 147221603Sadrian HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 148221603Sadrian HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 149221603Sadrian HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 150221603Sadrian HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 151225444Sadrian HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 152185377Ssam} HAL_CAPABILITY_TYPE; 153185377Ssam 154185377Ssam/* 155185377Ssam * "States" for setting the LED. These correspond to 156185377Ssam * the possible 802.11 operational states and there may 157185377Ssam * be a many-to-one mapping between these states and the 158185377Ssam * actual hardware state for the LED's (i.e. the hardware 159185377Ssam * may have fewer states). 160185377Ssam */ 161185377Ssamtypedef enum { 162185377Ssam HAL_LED_INIT = 0, 163185377Ssam HAL_LED_SCAN = 1, 164185377Ssam HAL_LED_AUTH = 2, 165185377Ssam HAL_LED_ASSOC = 3, 166185377Ssam HAL_LED_RUN = 4 167185377Ssam} HAL_LED_STATE; 168185377Ssam 169185377Ssam/* 170185377Ssam * Transmit queue types/numbers. These are used to tag 171185377Ssam * each transmit queue in the hardware and to identify a set 172185377Ssam * of transmit queues for operations such as start/stop dma. 173185377Ssam */ 174185377Ssamtypedef enum { 175185377Ssam HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 176185377Ssam HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 177185377Ssam HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 178185377Ssam HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 179185377Ssam HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 180219790Sadrian HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 181185377Ssam} HAL_TX_QUEUE; 182185377Ssam 183185377Ssam#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 184185377Ssam 185185377Ssam/* 186185377Ssam * Transmit queue subtype. These map directly to 187185377Ssam * WME Access Categories (except for UPSD). Refer 188185377Ssam * to Table 5 of the WME spec. 189185377Ssam */ 190185377Ssamtypedef enum { 191185377Ssam HAL_WME_AC_BK = 0, /* background access category */ 192185377Ssam HAL_WME_AC_BE = 1, /* best effort access category*/ 193185377Ssam HAL_WME_AC_VI = 2, /* video access category */ 194185377Ssam HAL_WME_AC_VO = 3, /* voice access category */ 195185377Ssam HAL_WME_UPSD = 4, /* uplink power save */ 196185377Ssam} HAL_TX_QUEUE_SUBTYPE; 197185377Ssam 198185377Ssam/* 199185377Ssam * Transmit queue flags that control various 200185377Ssam * operational parameters. 201185377Ssam */ 202185377Ssamtypedef enum { 203185377Ssam /* 204185377Ssam * Per queue interrupt enables. When set the associated 205185377Ssam * interrupt may be delivered for packets sent through 206185377Ssam * the queue. Without these enabled no interrupts will 207185377Ssam * be delivered for transmits through the queue. 208185377Ssam */ 209185377Ssam HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 210185377Ssam HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 211185377Ssam HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 212185377Ssam HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 213185377Ssam HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 214185377Ssam /* 215185377Ssam * Enable hardware compression for packets sent through 216185377Ssam * the queue. The compression buffer must be setup and 217185377Ssam * packets must have a key entry marked in the tx descriptor. 218185377Ssam */ 219185377Ssam HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 220185377Ssam /* 221185377Ssam * Disable queue when veol is hit or ready time expires. 222185377Ssam * By default the queue is disabled only on reaching the 223185377Ssam * physical end of queue (i.e. a null link ptr in the 224185377Ssam * descriptor chain). 225185377Ssam */ 226185377Ssam HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 227185377Ssam /* 228185377Ssam * Schedule frames on delivery of a DBA (DMA Beacon Alert) 229185377Ssam * event. Frames will be transmitted only when this timer 230185377Ssam * fires, e.g to transmit a beacon in ap or adhoc modes. 231185377Ssam */ 232185377Ssam HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 233185377Ssam /* 234185377Ssam * Each transmit queue has a counter that is incremented 235185377Ssam * each time the queue is enabled and decremented when 236185377Ssam * the list of frames to transmit is traversed (or when 237185377Ssam * the ready time for the queue expires). This counter 238185377Ssam * must be non-zero for frames to be scheduled for 239185377Ssam * transmission. The following controls disable bumping 240185377Ssam * this counter under certain conditions. Typically this 241185377Ssam * is used to gate frames based on the contents of another 242185377Ssam * queue (e.g. CAB traffic may only follow a beacon frame). 243185377Ssam * These are meaningful only when frames are scheduled 244185377Ssam * with a non-ASAP policy (e.g. DBA-gated). 245185377Ssam */ 246185377Ssam HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 247185377Ssam HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 248185377Ssam 249185377Ssam /* 250185377Ssam * Fragment burst backoff policy. Normally the no backoff 251185377Ssam * is done after a successful transmission, the next fragment 252185377Ssam * is sent at SIFS. If this flag is set backoff is done 253185377Ssam * after each fragment, regardless whether it was ack'd or 254185377Ssam * not, after the backoff count reaches zero a normal channel 255185377Ssam * access procedure is done before the next transmit (i.e. 256185377Ssam * wait AIFS instead of SIFS). 257185377Ssam */ 258185377Ssam HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 259185377Ssam /* 260185377Ssam * Disable post-tx backoff following each frame. 261185377Ssam */ 262185377Ssam HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 263185377Ssam /* 264185377Ssam * DCU arbiter lockout control. This controls how 265185377Ssam * lower priority tx queues are handled with respect to 266185377Ssam * to a specific queue when multiple queues have frames 267185377Ssam * to send. No lockout means lower priority queues arbitrate 268185377Ssam * concurrently with this queue. Intra-frame lockout 269185377Ssam * means lower priority queues are locked out until the 270185377Ssam * current frame transmits (e.g. including backoffs and bursting). 271185377Ssam * Global lockout means nothing lower can arbitrary so 272185377Ssam * long as there is traffic activity on this queue (frames, 273185377Ssam * backoff, etc). 274185377Ssam */ 275185377Ssam HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 276185377Ssam HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 277185377Ssam 278185377Ssam HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 279185377Ssam HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 280185377Ssam} HAL_TX_QUEUE_FLAGS; 281185377Ssam 282185377Ssamtypedef struct { 283185377Ssam uint32_t tqi_ver; /* hal TXQ version */ 284185377Ssam HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 285185377Ssam HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 286185377Ssam uint32_t tqi_priority; /* (not used) */ 287185377Ssam uint32_t tqi_aifs; /* aifs */ 288185377Ssam uint32_t tqi_cwmin; /* cwMin */ 289185377Ssam uint32_t tqi_cwmax; /* cwMax */ 290185377Ssam uint16_t tqi_shretry; /* rts retry limit */ 291185377Ssam uint16_t tqi_lgretry; /* long retry limit (not used)*/ 292185377Ssam uint32_t tqi_cbrPeriod; /* CBR period (us) */ 293185377Ssam uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 294185377Ssam uint32_t tqi_burstTime; /* max burst duration (us) */ 295185377Ssam uint32_t tqi_readyTime; /* frame schedule time (us) */ 296185377Ssam uint32_t tqi_compBuf; /* comp buffer phys addr */ 297185377Ssam} HAL_TXQ_INFO; 298185377Ssam 299185377Ssam#define HAL_TQI_NONVAL 0xffff 300185377Ssam 301185377Ssam/* token to use for aifs, cwmin, cwmax */ 302185377Ssam#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 303185377Ssam 304185377Ssam/* compression definitions */ 305185377Ssam#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 306185377Ssam#define HAL_COMP_BUF_ALIGN_SIZE 512 307185377Ssam 308185377Ssam/* 309185377Ssam * Transmit packet types. This belongs in ah_desc.h, but 310185377Ssam * is here so we can give a proper type to various parameters 311185377Ssam * (and not require everyone include the file). 312185377Ssam * 313185377Ssam * NB: These values are intentionally assigned for 314185377Ssam * direct use when setting up h/w descriptors. 315185377Ssam */ 316185377Ssamtypedef enum { 317185377Ssam HAL_PKT_TYPE_NORMAL = 0, 318185377Ssam HAL_PKT_TYPE_ATIM = 1, 319185377Ssam HAL_PKT_TYPE_PSPOLL = 2, 320185377Ssam HAL_PKT_TYPE_BEACON = 3, 321185377Ssam HAL_PKT_TYPE_PROBE_RESP = 4, 322185377Ssam HAL_PKT_TYPE_CHIRP = 5, 323185377Ssam HAL_PKT_TYPE_GRP_POLL = 6, 324185377Ssam HAL_PKT_TYPE_AMPDU = 7, 325185377Ssam} HAL_PKT_TYPE; 326185377Ssam 327185377Ssam/* Rx Filter Frame Types */ 328185377Ssamtypedef enum { 329220022Sadrian /* 330220022Sadrian * These bits correspond to AR_RX_FILTER for all chips. 331220022Sadrian * Not all bits are supported by all chips. 332220022Sadrian */ 333185377Ssam HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 334185377Ssam HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 335185377Ssam HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 336185377Ssam HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 337185377Ssam HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 338185377Ssam HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 339185377Ssam HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 340220025Sadrian HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 341185377Ssam HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 342220022Sadrian HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 343220025Sadrian HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 344220022Sadrian HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 345220022Sadrian HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 346220022Sadrian /* Allow all mcast/bcast frames */ 347220022Sadrian 348220022Sadrian /* 349220022Sadrian * Magic RX filter flags that aren't targetting hardware bits 350220022Sadrian * but instead the HAL sets individual bits - eg PHYERR will result 351220022Sadrian * in OFDM/CCK timing error frames being received. 352220022Sadrian */ 353220022Sadrian HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 354185377Ssam} HAL_RX_FILTER; 355185377Ssam 356185377Ssamtypedef enum { 357185377Ssam HAL_PM_AWAKE = 0, 358185377Ssam HAL_PM_FULL_SLEEP = 1, 359185377Ssam HAL_PM_NETWORK_SLEEP = 2, 360185377Ssam HAL_PM_UNDEFINED = 3 361185377Ssam} HAL_POWER_MODE; 362185377Ssam 363185377Ssam/* 364185377Ssam * NOTE WELL: 365185377Ssam * These are mapped to take advantage of the common locations for many of 366185377Ssam * the bits on all of the currently supported MAC chips. This is to make 367185377Ssam * the ISR as efficient as possible, while still abstracting HW differences. 368185377Ssam * When new hardware breaks this commonality this enumerated type, as well 369185377Ssam * as the HAL functions using it, must be modified. All values are directly 370185377Ssam * mapped unless commented otherwise. 371185377Ssam */ 372185377Ssamtypedef enum { 373185377Ssam HAL_INT_RX = 0x00000001, /* Non-common mapping */ 374185377Ssam HAL_INT_RXDESC = 0x00000002, 375185377Ssam HAL_INT_RXNOFRM = 0x00000008, 376185377Ssam HAL_INT_RXEOL = 0x00000010, 377185377Ssam HAL_INT_RXORN = 0x00000020, 378185377Ssam HAL_INT_TX = 0x00000040, /* Non-common mapping */ 379185377Ssam HAL_INT_TXDESC = 0x00000080, 380208711Srpaulo HAL_INT_TIM_TIMER= 0x00000100, 381185377Ssam HAL_INT_TXURN = 0x00000800, 382185377Ssam HAL_INT_MIB = 0x00001000, 383185377Ssam HAL_INT_RXPHY = 0x00004000, 384185377Ssam HAL_INT_RXKCM = 0x00008000, 385185377Ssam HAL_INT_SWBA = 0x00010000, 386185377Ssam HAL_INT_BMISS = 0x00040000, 387192401Ssam HAL_INT_BNR = 0x00100000, 388185377Ssam HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 389185377Ssam HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 390185377Ssam HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 391185377Ssam HAL_INT_GPIO = 0x01000000, 392185377Ssam HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 393185377Ssam HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 394192400Ssam HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 395185377Ssam HAL_INT_CST = 0x10000000, /* Non-common mapping */ 396185377Ssam HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 397185377Ssam HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 398185377Ssam#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 399185377Ssam HAL_INT_BMISC = HAL_INT_TIM 400185377Ssam | HAL_INT_DTIM 401185377Ssam | HAL_INT_DTIMSYNC 402192400Ssam | HAL_INT_CABEND 403192400Ssam | HAL_INT_TBTT, 404185377Ssam 405185377Ssam /* Interrupt bits that map directly to ISR/IMR bits */ 406185377Ssam HAL_INT_COMMON = HAL_INT_RXNOFRM 407185377Ssam | HAL_INT_RXDESC 408185377Ssam | HAL_INT_RXEOL 409185377Ssam | HAL_INT_RXORN 410192396Ssam | HAL_INT_TXDESC 411185377Ssam | HAL_INT_TXURN 412185377Ssam | HAL_INT_MIB 413185377Ssam | HAL_INT_RXPHY 414185377Ssam | HAL_INT_RXKCM 415185377Ssam | HAL_INT_SWBA 416185377Ssam | HAL_INT_BMISS 417192397Ssam | HAL_INT_BNR 418185377Ssam | HAL_INT_GPIO, 419185377Ssam} HAL_INT; 420185377Ssam 421185377Ssamtypedef enum { 422188974Ssam HAL_GPIO_MUX_OUTPUT = 0, 423188974Ssam HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 424188974Ssam HAL_GPIO_MUX_PCIE_POWER_LED = 2, 425188974Ssam HAL_GPIO_MUX_TX_FRAME = 3, 426188974Ssam HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 427188974Ssam HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 428188974Ssam HAL_GPIO_MUX_MAC_POWER_LED = 6 429188974Ssam} HAL_GPIO_MUX_TYPE; 430188974Ssam 431188974Ssamtypedef enum { 432188974Ssam HAL_GPIO_INTR_LOW = 0, 433188974Ssam HAL_GPIO_INTR_HIGH = 1, 434188974Ssam HAL_GPIO_INTR_DISABLE = 2 435188974Ssam} HAL_GPIO_INTR_TYPE; 436188974Ssam 437188974Ssamtypedef enum { 438185377Ssam HAL_RFGAIN_INACTIVE = 0, 439185377Ssam HAL_RFGAIN_READ_REQUESTED = 1, 440185377Ssam HAL_RFGAIN_NEED_CHANGE = 2 441185377Ssam} HAL_RFGAIN; 442185377Ssam 443187831Ssamtypedef uint16_t HAL_CTRY_CODE; /* country code */ 444187831Ssamtypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 445185377Ssam 446185377Ssam#define HAL_ANTENNA_MIN_MODE 0 447185377Ssam#define HAL_ANTENNA_FIXED_A 1 448185377Ssam#define HAL_ANTENNA_FIXED_B 2 449185377Ssam#define HAL_ANTENNA_MAX_MODE 3 450185377Ssam 451185377Ssamtypedef struct { 452185377Ssam uint32_t ackrcv_bad; 453185377Ssam uint32_t rts_bad; 454185377Ssam uint32_t rts_good; 455185377Ssam uint32_t fcs_bad; 456185377Ssam uint32_t beacons; 457185377Ssam} HAL_MIB_STATS; 458185377Ssam 459185377Ssamenum { 460185377Ssam HAL_MODE_11A = 0x001, /* 11a channels */ 461185377Ssam HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 462185377Ssam HAL_MODE_11B = 0x004, /* 11b channels */ 463185377Ssam HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 464185377Ssam#ifdef notdef 465185377Ssam HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 466185377Ssam#else 467185377Ssam HAL_MODE_11G = 0x008, /* XXX historical */ 468185377Ssam#endif 469185377Ssam HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 470185377Ssam HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 471185380Ssam HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 472185380Ssam HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 473185380Ssam HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 474185380Ssam HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 475185377Ssam HAL_MODE_11NG_HT20 = 0x008000, 476185377Ssam HAL_MODE_11NA_HT20 = 0x010000, 477185377Ssam HAL_MODE_11NG_HT40PLUS = 0x020000, 478185377Ssam HAL_MODE_11NG_HT40MINUS = 0x040000, 479185377Ssam HAL_MODE_11NA_HT40PLUS = 0x080000, 480185377Ssam HAL_MODE_11NA_HT40MINUS = 0x100000, 481185377Ssam HAL_MODE_ALL = 0xffffff 482185377Ssam}; 483185377Ssam 484185377Ssamtypedef struct { 485185377Ssam int rateCount; /* NB: for proper padding */ 486185377Ssam uint8_t rateCodeToIndex[144]; /* back mapping */ 487185377Ssam struct { 488188770Ssam uint8_t valid; /* valid for rate control use */ 489188770Ssam uint8_t phy; /* CCK/OFDM/XR */ 490185377Ssam uint32_t rateKbps; /* transfer rate in kbs */ 491185377Ssam uint8_t rateCode; /* rate for h/w descriptors */ 492185377Ssam uint8_t shortPreamble; /* mask for enabling short 493185377Ssam * preamble in CCK rate code */ 494185377Ssam uint8_t dot11Rate; /* value for supported rates 495185377Ssam * info element of MLME */ 496185377Ssam uint8_t controlRate; /* index of next lower basic 497185377Ssam * rate; used for dur. calcs */ 498185377Ssam uint16_t lpAckDuration; /* long preamble ACK duration */ 499185377Ssam uint16_t spAckDuration; /* short preamble ACK duration*/ 500185377Ssam } info[32]; 501185377Ssam} HAL_RATE_TABLE; 502185377Ssam 503185377Ssamtypedef struct { 504185377Ssam u_int rs_count; /* number of valid entries */ 505185377Ssam uint8_t rs_rates[32]; /* rates */ 506185377Ssam} HAL_RATE_SET; 507185377Ssam 508185377Ssam/* 509185377Ssam * 802.11n specific structures and enums 510185377Ssam */ 511185377Ssamtypedef enum { 512185377Ssam HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 513185377Ssam HAL_CHAINTYPE_RX = 2, /* RX chain type */ 514185377Ssam} HAL_CHAIN_TYPE; 515185377Ssam 516185377Ssamtypedef struct { 517185377Ssam u_int Tries; 518185377Ssam u_int Rate; 519185377Ssam u_int PktDuration; 520185377Ssam u_int ChSel; 521185377Ssam u_int RateFlags; 522185377Ssam#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 523185377Ssam#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 524185377Ssam#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 525185377Ssam} HAL_11N_RATE_SERIES; 526185377Ssam 527185377Ssamtypedef enum { 528185377Ssam HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 529185377Ssam HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 530185377Ssam} HAL_HT_MACMODE; 531185377Ssam 532185377Ssamtypedef enum { 533185377Ssam HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 534185377Ssam HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 535185377Ssam} HAL_HT_PHYMODE; 536185377Ssam 537185377Ssamtypedef enum { 538185377Ssam HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 539185377Ssam HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 540185377Ssam} HAL_HT_EXTPROTSPACING; 541185377Ssam 542185377Ssam 543185377Ssamtypedef enum { 544185377Ssam HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 545185377Ssam HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 546185377Ssam} HAL_HT_RXCLEAR; 547185377Ssam 548185377Ssam/* 549185377Ssam * Antenna switch control. By default antenna selection 550185377Ssam * enables multiple (2) antenna use. To force use of the 551185377Ssam * A or B antenna only specify a fixed setting. Fixing 552185377Ssam * the antenna will also disable any diversity support. 553185377Ssam */ 554185377Ssamtypedef enum { 555185377Ssam HAL_ANT_VARIABLE = 0, /* variable by programming */ 556185377Ssam HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 557185377Ssam HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 558185377Ssam} HAL_ANT_SETTING; 559185377Ssam 560185377Ssamtypedef enum { 561185377Ssam HAL_M_STA = 1, /* infrastructure station */ 562185377Ssam HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 563185377Ssam HAL_M_HOSTAP = 6, /* Software Access Point */ 564185377Ssam HAL_M_MONITOR = 8 /* Monitor mode */ 565185377Ssam} HAL_OPMODE; 566185377Ssam 567185377Ssamtypedef struct { 568185377Ssam uint8_t kv_type; /* one of HAL_CIPHER */ 569185377Ssam uint8_t kv_pad; 570185377Ssam uint16_t kv_len; /* length in bits */ 571185377Ssam uint8_t kv_val[16]; /* enough for 128-bit keys */ 572185377Ssam uint8_t kv_mic[8]; /* TKIP MIC key */ 573185377Ssam uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 574185377Ssam} HAL_KEYVAL; 575185377Ssam 576185377Ssamtypedef enum { 577185377Ssam HAL_CIPHER_WEP = 0, 578185377Ssam HAL_CIPHER_AES_OCB = 1, 579185377Ssam HAL_CIPHER_AES_CCM = 2, 580185377Ssam HAL_CIPHER_CKIP = 3, 581185377Ssam HAL_CIPHER_TKIP = 4, 582185377Ssam HAL_CIPHER_CLR = 5, /* no encryption */ 583185377Ssam 584185377Ssam HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 585185377Ssam} HAL_CIPHER; 586185377Ssam 587185377Ssamenum { 588185377Ssam HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 589185377Ssam HAL_SLOT_TIME_9 = 9, 590185377Ssam HAL_SLOT_TIME_20 = 20, 591185377Ssam}; 592185377Ssam 593185377Ssam/* 594185377Ssam * Per-station beacon timer state. Note that the specified 595185377Ssam * beacon interval (given in TU's) can also include flags 596185377Ssam * to force a TSF reset and to enable the beacon xmit logic. 597185377Ssam * If bs_cfpmaxduration is non-zero the hardware is setup to 598185377Ssam * coexist with a PCF-capable AP. 599185377Ssam */ 600185377Ssamtypedef struct { 601185377Ssam uint32_t bs_nexttbtt; /* next beacon in TU */ 602185377Ssam uint32_t bs_nextdtim; /* next DTIM in TU */ 603185377Ssam uint32_t bs_intval; /* beacon interval+flags */ 604185377Ssam#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 605185377Ssam#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 606185377Ssam#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 607185377Ssam uint32_t bs_dtimperiod; 608185377Ssam uint16_t bs_cfpperiod; /* CFP period in TU */ 609185377Ssam uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 610185377Ssam uint32_t bs_cfpnext; /* next CFP in TU */ 611185377Ssam uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 612185377Ssam uint16_t bs_bmissthreshold; /* beacon miss threshold */ 613185377Ssam uint32_t bs_sleepduration; /* max sleep duration */ 614185377Ssam} HAL_BEACON_STATE; 615185377Ssam 616185377Ssam/* 617185377Ssam * Like HAL_BEACON_STATE but for non-station mode setup. 618185377Ssam * NB: see above flag definitions for bt_intval. 619185377Ssam */ 620185377Ssamtypedef struct { 621185377Ssam uint32_t bt_intval; /* beacon interval+flags */ 622185377Ssam uint32_t bt_nexttbtt; /* next beacon in TU */ 623185377Ssam uint32_t bt_nextatim; /* next ATIM in TU */ 624185377Ssam uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 625185377Ssam uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 626185377Ssam uint32_t bt_flags; /* timer enables */ 627185377Ssam#define HAL_BEACON_TBTT_EN 0x00000001 628185377Ssam#define HAL_BEACON_DBA_EN 0x00000002 629185377Ssam#define HAL_BEACON_SWBA_EN 0x00000004 630185377Ssam} HAL_BEACON_TIMERS; 631185377Ssam 632185377Ssam/* 633185377Ssam * Per-node statistics maintained by the driver for use in 634185377Ssam * optimizing signal quality and other operational aspects. 635185377Ssam */ 636185377Ssamtypedef struct { 637185377Ssam uint32_t ns_avgbrssi; /* average beacon rssi */ 638185377Ssam uint32_t ns_avgrssi; /* average data rssi */ 639185377Ssam uint32_t ns_avgtxrssi; /* average tx rssi */ 640185377Ssam} HAL_NODE_STATS; 641185377Ssam 642185377Ssam#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 643185377Ssam 644185377Ssamstruct ath_desc; 645185377Ssamstruct ath_tx_status; 646185377Ssamstruct ath_rx_status; 647187831Ssamstruct ieee80211_channel; 648185377Ssam 649185377Ssam/* 650219773Sadrian * This is a channel survey sample entry. 651219773Sadrian * 652219773Sadrian * The AR5212 ANI routines fill these samples. The ANI code then uses it 653219773Sadrian * when calculating listen time; it is also exported via a diagnostic 654219773Sadrian * API. 655219773Sadrian */ 656219773Sadriantypedef struct { 657219773Sadrian uint32_t seq_num; 658219773Sadrian uint32_t tx_busy; 659219773Sadrian uint32_t rx_busy; 660219773Sadrian uint32_t chan_busy; 661219773Sadrian uint32_t cycle_count; 662219773Sadrian} HAL_SURVEY_SAMPLE; 663219773Sadrian 664219773Sadrian/* 665219773Sadrian * This provides 3.2 seconds of sample space given an 666219773Sadrian * ANI time of 1/10th of a second. This may not be enough! 667219773Sadrian */ 668219773Sadrian#define CHANNEL_SURVEY_SAMPLE_COUNT 32 669219773Sadrian 670219773Sadriantypedef struct { 671219773Sadrian HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 672219773Sadrian uint32_t cur_sample; /* current sample in sequence */ 673219773Sadrian uint32_t cur_seq; /* current sequence number */ 674219773Sadrian} HAL_CHANNEL_SURVEY; 675219773Sadrian 676219773Sadrian/* 677222277Sadrian * ANI commands. 678222277Sadrian * 679222277Sadrian * These are used both internally and externally via the diagnostic 680222277Sadrian * API. 681222277Sadrian * 682222277Sadrian * Note that this is NOT the ANI commands being used via the INTMIT 683222277Sadrian * capability - that has a different mapping for some reason. 684222277Sadrian */ 685222277Sadriantypedef enum { 686222277Sadrian HAL_ANI_PRESENT = 0, /* is ANI support present */ 687222277Sadrian HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 688222277Sadrian HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 689222277Sadrian HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 690222277Sadrian HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 691222277Sadrian HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 692222277Sadrian HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 693222277Sadrian HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 694222277Sadrian} HAL_ANI_CMD; 695222277Sadrian 696222277Sadrian/* 697222277Sadrian * This is the layout of the ANI INTMIT capability. 698222277Sadrian * 699222277Sadrian * Notice that the command values differ to HAL_ANI_CMD. 700222277Sadrian */ 701222277Sadriantypedef enum { 702222277Sadrian HAL_CAP_INTMIT_PRESENT = 0, 703222277Sadrian HAL_CAP_INTMIT_ENABLE = 1, 704222277Sadrian HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 705222277Sadrian HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 706222277Sadrian HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 707222277Sadrian HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 708222277Sadrian HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 709222277Sadrian} HAL_CAP_INTMIT_CMD; 710222277Sadrian 711222584Sadriantypedef struct { 712222584Sadrian int32_t pe_firpwr; /* FIR pwr out threshold */ 713222584Sadrian int32_t pe_rrssi; /* Radar rssi thresh */ 714222584Sadrian int32_t pe_height; /* Pulse height thresh */ 715222584Sadrian int32_t pe_prssi; /* Pulse rssi thresh */ 716222584Sadrian int32_t pe_inband; /* Inband thresh */ 717222584Sadrian 718222584Sadrian /* The following params are only for AR5413 and later */ 719222584Sadrian u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 720222584Sadrian u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 721222584Sadrian u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 722224244Sadrian int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 723224244Sadrian int32_t pe_blockradar; /* 724222584Sadrian * Enable to block radar check if pkt detect is done via OFDM 725222584Sadrian * weak signal detect or pkt is detected immediately after tx 726222584Sadrian * to rx transition 727222584Sadrian */ 728224244Sadrian int32_t pe_enmaxrssi; /* 729222584Sadrian * Enable to use the max rssi instead of the last rssi during 730222584Sadrian * fine gain changes for radar detection 731222584Sadrian */ 732224244Sadrian int32_t pe_extchannel; /* Enable DFS on ext channel */ 733224244Sadrian int32_t pe_enabled; /* Whether radar detection is enabled */ 734222584Sadrian} HAL_PHYERR_PARAM; 735222584Sadrian 736222584Sadrian#define HAL_PHYERR_PARAM_NOVAL 65535 737222584Sadrian#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 738222584Sadrian 739224716Sadrian/* 740224716Sadrian * DFS operating mode flags. 741224716Sadrian */ 742224716Sadriantypedef enum { 743224716Sadrian HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 744224716Sadrian HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 745224716Sadrian HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 746224716Sadrian HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 747224716Sadrian} HAL_DFS_DOMAIN; 748222584Sadrian 749222277Sadrian/* 750222644Sadrian * Flag for setting QUIET period 751222644Sadrian */ 752222644Sadriantypedef enum { 753222644Sadrian HAL_QUIET_DISABLE = 0x0, 754222644Sadrian HAL_QUIET_ENABLE = 0x1, 755222644Sadrian HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 756222644Sadrian HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 757222644Sadrian} HAL_QUIET_FLAG; 758222644Sadrian 759222815Sadrian#define HAL_DFS_EVENT_PRICH 0x0000001 760224539Sadrian#define HAL_DFS_EVENT_EXTCH 0x0000002 761224539Sadrian#define HAL_DFS_EVENT_EXTEARLY 0x0000004 762224539Sadrian#define HAL_DFS_EVENT_ISDC 0x0000008 763222815Sadrian 764224633Sadrianstruct hal_dfs_event { 765222815Sadrian uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 766222815Sadrian uint32_t re_ts; /* Original 15 bit recv timestamp */ 767222815Sadrian uint8_t re_rssi; /* rssi of radar event */ 768222815Sadrian uint8_t re_dur; /* duration of radar pulse */ 769222815Sadrian uint32_t re_flags; /* Flags (see above) */ 770222815Sadrian}; 771224633Sadriantypedef struct hal_dfs_event HAL_DFS_EVENT; 772222815Sadrian 773223459Sadriantypedef struct 774223459Sadrian{ 775223459Sadrian int ah_debug; /* only used if AH_DEBUG is defined */ 776223459Sadrian int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 777223459Sadrian 778223459Sadrian /* NB: these are deprecated; they exist for now for compatibility */ 779223459Sadrian int ah_dma_beacon_response_time;/* in TU's */ 780223459Sadrian int ah_sw_beacon_response_time; /* in TU's */ 781223459Sadrian int ah_additional_swba_backoff; /* in TU's */ 782224633Sadrian} HAL_OPS_CONFIG; 783223459Sadrian 784222644Sadrian/* 785185377Ssam * Hardware Access Layer (HAL) API. 786185377Ssam * 787185377Ssam * Clients of the HAL call ath_hal_attach to obtain a reference to an 788185377Ssam * ath_hal structure for use with the device. Hardware-related operations 789185377Ssam * that follow must call back into the HAL through interface, supplying 790185377Ssam * the reference as the first parameter. Note that before using the 791185377Ssam * reference returned by ath_hal_attach the caller should verify the 792185377Ssam * ABI version number. 793185377Ssam */ 794185377Ssamstruct ath_hal { 795185377Ssam uint32_t ah_magic; /* consistency check magic number */ 796185377Ssam uint16_t ah_devid; /* PCI device ID */ 797185377Ssam uint16_t ah_subvendorid; /* PCI subvendor ID */ 798185377Ssam HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 799185377Ssam HAL_BUS_TAG ah_st; /* params for register r+w */ 800185377Ssam HAL_BUS_HANDLE ah_sh; 801185377Ssam HAL_CTRY_CODE ah_countryCode; 802185377Ssam 803185377Ssam uint32_t ah_macVersion; /* MAC version id */ 804185377Ssam uint16_t ah_macRev; /* MAC revision */ 805185377Ssam uint16_t ah_phyRev; /* PHY revision */ 806185377Ssam /* NB: when only one radio is present the rev is in 5Ghz */ 807185377Ssam uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 808185377Ssam uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 809185377Ssam 810217624Sadrian uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 811217624Sadrian 812223459Sadrian HAL_OPS_CONFIG ah_config; 813185377Ssam const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 814185377Ssam u_int mode); 815185377Ssam void __ahdecl(*ah_detach)(struct ath_hal*); 816185377Ssam 817185377Ssam /* Reset functions */ 818185377Ssam HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 819187831Ssam struct ieee80211_channel *, 820187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status); 821185377Ssam HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 822185377Ssam HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 823188979Ssam void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 824188979Ssam void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 825185377Ssam void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 826187831Ssam HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 827187831Ssam struct ieee80211_channel *, HAL_BOOL *); 828187831Ssam HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 829187831Ssam struct ieee80211_channel *, u_int chainMask, 830187831Ssam HAL_BOOL longCal, HAL_BOOL *isCalDone); 831187831Ssam HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 832187831Ssam const struct ieee80211_channel *); 833203930Srpaulo HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 834203930Srpaulo const struct ieee80211_channel *, uint16_t *); 835185377Ssam HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 836203930Srpaulo HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 837203930Srpaulo const struct ieee80211_channel *); 838185377Ssam 839185377Ssam /* Transmit functions */ 840185377Ssam HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 841185377Ssam HAL_BOOL incTrigLevel); 842185377Ssam int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 843185377Ssam const HAL_TXQ_INFO *qInfo); 844185377Ssam HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 845185377Ssam const HAL_TXQ_INFO *qInfo); 846185377Ssam HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 847185377Ssam HAL_TXQ_INFO *qInfo); 848185377Ssam HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 849185377Ssam HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 850185377Ssam uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 851185377Ssam HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 852185377Ssam uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 853185377Ssam HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 854185377Ssam HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 855185377Ssam HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 856185377Ssam u_int pktLen, u_int hdrLen, 857185377Ssam HAL_PKT_TYPE type, u_int txPower, 858185377Ssam u_int txRate0, u_int txTries0, 859185377Ssam u_int keyIx, u_int antMode, u_int flags, 860185377Ssam u_int rtsctsRate, u_int rtsctsDuration, 861185377Ssam u_int compicvLen, u_int compivLen, 862185377Ssam u_int comp); 863185377Ssam HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 864185377Ssam u_int txRate1, u_int txTries1, 865185377Ssam u_int txRate2, u_int txTries2, 866185377Ssam u_int txRate3, u_int txTries3); 867185377Ssam HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 868185377Ssam u_int segLen, HAL_BOOL firstSeg, 869185377Ssam HAL_BOOL lastSeg, const struct ath_desc *); 870185377Ssam HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 871185377Ssam struct ath_desc *, struct ath_tx_status *); 872185377Ssam void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 873185377Ssam void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 874217621Sadrian HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 875217621Sadrian const struct ath_desc *ds, int *rates, int *tries); 876185377Ssam 877185377Ssam /* Receive Functions */ 878185377Ssam uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 879185377Ssam void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 880185377Ssam void __ahdecl(*ah_enableReceive)(struct ath_hal*); 881185377Ssam HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 882185377Ssam void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 883185377Ssam void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 884185377Ssam void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 885185377Ssam uint32_t filter0, uint32_t filter1); 886185377Ssam HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 887185377Ssam uint32_t index); 888185377Ssam HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 889185377Ssam uint32_t index); 890185377Ssam uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 891185377Ssam void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 892185377Ssam HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 893185377Ssam uint32_t size, u_int flags); 894185377Ssam HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 895185377Ssam struct ath_desc *, uint32_t phyAddr, 896185377Ssam struct ath_desc *next, uint64_t tsf, 897185377Ssam struct ath_rx_status *); 898185377Ssam void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 899187831Ssam const HAL_NODE_STATS *, 900187831Ssam const struct ieee80211_channel *); 901217684Sadrian void __ahdecl(*ah_aniPoll)(struct ath_hal *, 902217684Sadrian const struct ieee80211_channel *); 903185377Ssam void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 904185377Ssam const HAL_NODE_STATS *); 905220600Sadrian void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 906220600Sadrian struct ath_rx_status *, 907220600Sadrian unsigned long, int); 908185377Ssam 909185377Ssam /* Misc Functions */ 910185377Ssam HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 911185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 912185377Ssam uint32_t *result); 913185377Ssam HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 914185377Ssam HAL_CAPABILITY_TYPE, uint32_t capability, 915185377Ssam uint32_t setting, HAL_STATUS *); 916185377Ssam HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 917185377Ssam const void *args, uint32_t argsize, 918185377Ssam void **result, uint32_t *resultsize); 919185377Ssam void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 920185377Ssam HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 921185377Ssam void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 922185377Ssam HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 923185377Ssam HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 924185377Ssam uint16_t, HAL_STATUS *); 925185377Ssam void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 926185377Ssam void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 927185377Ssam const uint8_t *bssid, uint16_t assocId); 928188974Ssam HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 929188974Ssam uint32_t gpio, HAL_GPIO_MUX_TYPE); 930185377Ssam HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 931185377Ssam uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 932185377Ssam HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 933185377Ssam uint32_t gpio, uint32_t val); 934185377Ssam void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 935185377Ssam uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 936185377Ssam uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 937185377Ssam void __ahdecl(*ah_resetTsf)(struct ath_hal*); 938185377Ssam HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 939185377Ssam void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 940185377Ssam HAL_MIB_STATS*); 941185377Ssam HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 942185377Ssam u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 943185377Ssam void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 944185377Ssam HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 945185377Ssam HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 946185377Ssam HAL_ANT_SETTING); 947185377Ssam HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 948185377Ssam u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 949185377Ssam HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 950185377Ssam u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 951185377Ssam HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 952185377Ssam u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 953185377Ssam HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 954185377Ssam u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 955185377Ssam HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 956185377Ssam u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 957185377Ssam HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 958185377Ssam void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 959222644Sadrian HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 960222644Sadrian uint32_t duration, uint32_t nextStart, 961222644Sadrian HAL_QUIET_FLAG flag); 962185377Ssam 963222584Sadrian /* DFS functions */ 964222584Sadrian void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 965222584Sadrian HAL_PHYERR_PARAM *pe); 966222584Sadrian void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 967222584Sadrian HAL_PHYERR_PARAM *pe); 968222815Sadrian HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 969222815Sadrian struct ath_rx_status *rxs, uint64_t fulltsf, 970222815Sadrian const char *buf, HAL_DFS_EVENT *event); 971224709Sadrian HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 972222584Sadrian 973185377Ssam /* Key Cache Functions */ 974185377Ssam uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 975185377Ssam HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 976185377Ssam HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 977185377Ssam uint16_t); 978185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 979185377Ssam uint16_t, const HAL_KEYVAL *, 980185377Ssam const uint8_t *, int); 981185377Ssam HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 982185377Ssam uint16_t, const uint8_t *); 983185377Ssam 984185377Ssam /* Power Management Functions */ 985185377Ssam HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 986185377Ssam HAL_POWER_MODE mode, int setChip); 987185377Ssam HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 988187831Ssam int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 989187831Ssam const struct ieee80211_channel *); 990185377Ssam 991185377Ssam /* Beacon Management Functions */ 992185377Ssam void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 993185377Ssam const HAL_BEACON_TIMERS *); 994185377Ssam /* NB: deprecated, use ah_setBeaconTimers instead */ 995185377Ssam void __ahdecl(*ah_beaconInit)(struct ath_hal *, 996185377Ssam uint32_t nexttbtt, uint32_t intval); 997185377Ssam void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 998185377Ssam const HAL_BEACON_STATE *); 999185377Ssam void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1000225444Sadrian uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1001185377Ssam 1002218066Sadrian /* 802.11n Functions */ 1003218066Sadrian HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1004218066Sadrian struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1005218066Sadrian u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1006218066Sadrian HAL_BOOL); 1007218066Sadrian HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1008218066Sadrian struct ath_desc *, u_int, u_int, u_int, 1009218066Sadrian u_int, u_int, u_int, u_int, u_int); 1010218066Sadrian HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1011218066Sadrian struct ath_desc *, const struct ath_desc *); 1012218066Sadrian void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1013218066Sadrian struct ath_desc *, u_int, u_int, 1014218066Sadrian HAL_11N_RATE_SERIES [], u_int, u_int); 1015218066Sadrian void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1016218066Sadrian struct ath_desc *, u_int); 1017218066Sadrian void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1018218066Sadrian struct ath_desc *); 1019218066Sadrian void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1020218066Sadrian struct ath_desc *, u_int); 1021218066Sadrian uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1022218066Sadrian void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1023218066Sadrian HAL_HT_MACMODE); 1024218066Sadrian HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1025218066Sadrian void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1026218066Sadrian HAL_HT_RXCLEAR); 1027218066Sadrian 1028185377Ssam /* Interrupt functions */ 1029185377Ssam HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1030185377Ssam HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1031185377Ssam HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1032185377Ssam HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1033185377Ssam}; 1034185377Ssam 1035185377Ssam/* 1036185377Ssam * Check the PCI vendor ID and device ID against Atheros' values 1037185377Ssam * and return a printable description for any Atheros hardware. 1038185377Ssam * AH_NULL is returned if the ID's do not describe Atheros hardware. 1039185377Ssam */ 1040185377Ssamextern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1041185377Ssam 1042185377Ssam/* 1043185377Ssam * Attach the HAL for use with the specified device. The device is 1044185377Ssam * defined by the PCI device ID. The caller provides an opaque pointer 1045185377Ssam * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1046185377Ssam * HAL state block for later use. Hardware register accesses are done 1047185377Ssam * using the specified bus tag and handle. On successful return a 1048185377Ssam * reference to a state block is returned that must be supplied in all 1049185377Ssam * subsequent HAL calls. Storage associated with this reference is 1050185377Ssam * dynamically allocated and must be freed by calling the ah_detach 1051185377Ssam * method when the client is done. If the attach operation fails a 1052185377Ssam * null (AH_NULL) reference will be returned and a status code will 1053185377Ssam * be returned if the status parameter is non-zero. 1054185377Ssam */ 1055185377Ssamextern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1056217624Sadrian HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1057185377Ssam 1058188968Ssamextern const char *ath_hal_mac_name(struct ath_hal *); 1059188968Ssamextern const char *ath_hal_rf_name(struct ath_hal *); 1060188968Ssam 1061185377Ssam/* 1062187831Ssam * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1063187831Ssam * request a set of channels for a particular country code and/or 1064187831Ssam * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1065187831Ssam * this list is constructed according to the contents of the EEPROM. 1066187831Ssam * ath_hal_getchannels acts similarly but does not alter the operating 1067187831Ssam * state; this can be used to collect information for a particular 1068187831Ssam * regulatory configuration. Finally ath_hal_set_channels installs a 1069187831Ssam * channel list constructed outside the driver. The HAL will adopt the 1070187831Ssam * channel list and setup internal state according to the specified 1071187831Ssam * regulatory configuration (e.g. conformance test limits). 1072185377Ssam * 1073187831Ssam * For all interfaces the channel list is returned in the supplied array. 1074187831Ssam * maxchans defines the maximum size of this array. nchans contains the 1075187831Ssam * actual number of channels returned. If a problem occurred then a 1076187831Ssam * status code != HAL_OK is returned. 1077185377Ssam */ 1078187831Ssamstruct ieee80211_channel; 1079185377Ssam 1080185377Ssam/* 1081187831Ssam * Return a list of channels according to the specified regulatory. 1082185377Ssam */ 1083187831Ssamextern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1084187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1085187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1086187831Ssam HAL_BOOL enableExtendedChannels); 1087185377Ssam 1088185377Ssam/* 1089187831Ssam * Return a list of channels and install it as the current operating 1090187831Ssam * regulatory list. 1091185377Ssam */ 1092187831Ssamextern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1093187831Ssam struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1094187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1095187831Ssam HAL_BOOL enableExtendedChannels); 1096185377Ssam 1097185377Ssam/* 1098187831Ssam * Install the list of channels as the current operating regulatory 1099187831Ssam * and setup related state according to the country code and sku. 1100185377Ssam */ 1101187831Ssamextern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1102187831Ssam struct ieee80211_channel *chans, int nchans, 1103187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1104185377Ssam 1105185377Ssam/* 1106220443Sadrian * Fetch the ctl/ext noise floor values reported by a MIMO 1107220443Sadrian * radio. Returns 1 for valid results, 0 for invalid channel. 1108220443Sadrian */ 1109220443Sadrianextern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1110220444Sadrian const struct ieee80211_channel *chan, int16_t *nf_ctl, 1111220444Sadrian int16_t *nf_ext); 1112220443Sadrian 1113220443Sadrian/* 1114187831Ssam * Calibrate noise floor data following a channel scan or similar. 1115187831Ssam * This must be called prior retrieving noise floor data. 1116185377Ssam */ 1117187831Ssamextern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1118185377Ssam 1119185377Ssam/* 1120187831Ssam * Return bit mask of wireless modes supported by the hardware. 1121185377Ssam */ 1122187831Ssamextern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1123185377Ssam 1124185377Ssam/* 1125218011Sadrian * Calculate the packet TX time for a legacy or 11n frame 1126185377Ssam */ 1127218011Sadrianextern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1128218011Sadrian const HAL_RATE_TABLE *rates, uint32_t frameLen, 1129218011Sadrian uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1130218011Sadrian 1131218011Sadrian/* 1132218011Sadrian * Calculate the duration of an 11n frame. 1133218011Sadrian */ 1134218011Sadrianextern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1135218011Sadrian int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1136218011Sadrian 1137218011Sadrian/* 1138218011Sadrian * Calculate the transmit duration of a legacy frame. 1139218011Sadrian */ 1140187831Ssamextern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1141187831Ssam const HAL_RATE_TABLE *rates, uint32_t frameLen, 1142187831Ssam uint16_t rateix, HAL_BOOL shortPreamble); 1143225444Sadrian 1144225444Sadrian/* 1145225444Sadrian * Adjust the TSF. 1146225444Sadrian */ 1147225444Sadrianextern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1148225444Sadrian 1149225444Sadrian/* 1150225444Sadrian * Enable or disable CCA. 1151225444Sadrian */ 1152225444Sadrianvoid __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1153225444Sadrian 1154225444Sadrian/* 1155225444Sadrian * Get CCA setting. 1156225444Sadrian */ 1157225444Sadrianint __ahdecl ath_hal_getcca(struct ath_hal *ah); 1158225444Sadrian 1159185377Ssam#endif /* _ATH_AH_H_ */ 1160