1162413Ssam/*- 2178354Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3162413Ssam * All rights reserved. 4162413Ssam * 5162413Ssam * Redistribution and use in source and binary forms, with or without 6162413Ssam * modification, are permitted provided that the following conditions 7162413Ssam * are met: 8162413Ssam * 1. Redistributions of source code must retain the above copyright 9162413Ssam * notice, this list of conditions and the following disclaimer, 10162413Ssam * without modification. 11162413Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12162413Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13162413Ssam * redistribution must be conditioned upon including a substantially 14162413Ssam * similar Disclaimer requirement for further binary redistribution. 15162413Ssam * 16162413Ssam * NO WARRANTY 17162413Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18162413Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19162413Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20162413Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21162413Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22162413Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23162413Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24162413Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25162413Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26162413Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27162413Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28162413Ssam * 29162413Ssam * $FreeBSD$ 30162413Ssam */ 31162413Ssam#ifndef _ATH_AH_OSDEP_H_ 32162413Ssam#define _ATH_AH_OSDEP_H_ 33162413Ssam/* 34162413Ssam * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35162413Ssam */ 36185522Ssam#include <sys/cdefs.h> 37162413Ssam#include <sys/param.h> 38162413Ssam#include <sys/systm.h> 39162413Ssam#include <sys/endian.h> 40185522Ssam#include <sys/linker_set.h> 41162413Ssam 42162413Ssam#include <machine/bus.h> 43162413Ssam 44162413Ssam/* 45185522Ssam * Bus i/o type definitions. 46185522Ssam */ 47185522Ssamtypedef void *HAL_SOFTC; 48185522Ssamtypedef bus_space_tag_t HAL_BUS_TAG; 49185522Ssamtypedef bus_space_handle_t HAL_BUS_HANDLE; 50185522Ssam 51185522Ssam/* 52185522Ssam * Linker set writearounds for chip and RF backend registration. 53185522Ssam */ 54185522Ssam#define OS_DATA_SET(set, item) DATA_SET(set, item) 55185522Ssam#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 56185522Ssam#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 57185522Ssam 58185522Ssam/* 59162413Ssam * Delay n microseconds. 60162413Ssam */ 61191909Ssam#define OS_DELAY(_n) DELAY(_n) 62162413Ssam 63162413Ssam#define OS_INLINE __inline 64191909Ssam#define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 65191909Ssam#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 66162413Ssam 67162413Ssam#define abs(_a) __builtin_abs(_a) 68162413Ssam 69162413Ssamstruct ath_hal; 70162413Ssam 71162413Ssam/* 72195418Ssam * The hardware registers are native little-endian byte order. 73195418Ssam * Big-endian hosts are handled by enabling hardware byte-swap 74195418Ssam * of register reads and writes at reset. But the PCI clock 75195418Ssam * domain registers are not byte swapped! Thus, on big-endian 76195418Ssam * platforms we have to explicitly byte-swap those registers. 77195418Ssam * OS_REG_UNSWAPPED identifies the registers that need special handling. 78195418Ssam */ 79195418Ssam#if _BYTE_ORDER == _BIG_ENDIAN 80195418Ssam#define OS_REG_UNSWAPPED(_reg) \ 81195418Ssam (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 82195418Ssam ((_reg) >= 0x7000 && (_reg) < 0x8000)) 83195418Ssam#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 84195418Ssam#define OS_REG_UNSWAPPED(_reg) (0) 85195418Ssam#endif /* _BYTE_ORDER */ 86195418Ssam 87195418Ssam/* 88162413Ssam * Register read/write operations are either handled through 89162413Ssam * platform-dependent routines (or when debugging is enabled 90162413Ssam * with AH_DEBUG); or they are inline expanded using the macros 91195418Ssam * defined below. 92162413Ssam */ 93162413Ssam#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) 94162413Ssam#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 95162413Ssam#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 96162413Ssam 97162413Ssamextern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 98162413Ssamextern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 99162413Ssam#else 100162413Ssam/* 101162413Ssam * The hardware registers are native little-endian byte order. 102162413Ssam * Big-endian hosts are handled by enabling hardware byte-swap 103162413Ssam * of register reads and writes at reset. But the PCI clock 104162413Ssam * domain registers are not byte swapped! Thus, on big-endian 105162413Ssam * platforms we have to explicitly byte-swap those registers. 106162413Ssam * Most of this code is collapsed at compile time because the 107162413Ssam * register values are constants. 108162413Ssam */ 109162413Ssam#if _BYTE_ORDER == _BIG_ENDIAN 110162413Ssam#define OS_REG_WRITE(_ah, _reg, _val) do { \ 111179467Ssam if (OS_REG_UNSWAPPED(_reg)) \ 112162413Ssam bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 113162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 114162413Ssam else \ 115162413Ssam bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 116162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 117162413Ssam} while (0) 118162413Ssam#define OS_REG_READ(_ah, _reg) \ 119179467Ssam (OS_REG_UNSWAPPED(_reg) ? \ 120162413Ssam bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 121162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \ 122162413Ssam bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 123162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg))) 124162413Ssam#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 125162413Ssam#define OS_REG_WRITE(_ah, _reg, _val) \ 126162413Ssam bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 127162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) 128162413Ssam#define OS_REG_READ(_ah, _reg) \ 129162413Ssam bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 130162413Ssam (bus_space_handle_t)(_ah)->ah_sh, (_reg)) 131162413Ssam#endif /* _BYTE_ORDER */ 132162413Ssam#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ 133162413Ssam 134162413Ssam#ifdef AH_DEBUG_ALQ 135162413Ssamextern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 136162413Ssam#else 137162413Ssam#define OS_MARK(_ah, _id, _v) 138162413Ssam#endif 139162413Ssam 140162413Ssam#endif /* _ATH_AH_OSDEP_H_ */ 141