ata-dma.c revision 95533
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 95533 2002-04-26 22:48:23Z mike $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/bio.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <pci/pcivar.h> 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <dev/ata/ata-all.h> 44 45/* prototypes */ 46static void ata_dmacreate(struct ata_device *, int, int); 47static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); 48static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int); 49static void cyrix_timing(struct ata_device *, int, int); 50static void promise_timing(struct ata_device *, int, int); 51static void hpt_timing(struct ata_device *, int, int); 52static int hpt_cable80(struct ata_device *); 53 54/* misc defines */ 55#define ATAPI_DEVICE(atadev) \ 56 ((atadev->unit == ATA_MASTER && \ 57 atadev->channel->devices & ATA_ATAPI_MASTER) || \ 58 (atadev->unit == ATA_SLAVE && \ 59 atadev->channel->devices & ATA_ATAPI_SLAVE)) 60 61#define MAXSEGSZ PAGE_SIZE 62#define MAXTABSZ PAGE_SIZE 63#define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) 64 65struct ata_dc_cb_args { 66 bus_addr_t maddr; 67 int error; 68}; 69 70static void 71ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 72{ 73 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; 74 75 if (!(cba->error = error)) 76 cba->maddr = segs[0].ds_addr; 77} 78 79int 80ata_dmaalloc(struct ata_device *atadev) 81{ 82 struct ata_channel *ch; 83 struct ata_dc_cb_args ccba; 84 struct ata_dmastate *ds; 85 int error; 86 87 ch = atadev->channel; 88 ds = &atadev->dmastate; 89 if (!ds->cdmatag) { 90 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE, 91 BUS_SPACE_MAXADDR_32BIT, 92 BUS_SPACE_MAXADDR, NULL, NULL, 93 MAXTABSZ, 1, MAXTABSZ, 94 BUS_DMA_ALLOCNOW, &ds->cdmatag))) 95 return error; 96 } 97 if (!ds->ddmatag) { 98 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0, 99 BUS_SPACE_MAXADDR_32BIT, 100 BUS_SPACE_MAXADDR, NULL, NULL, 101 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, 102 BUS_DMA_ALLOCNOW, &ds->ddmatag))) 103 return error; 104 } 105 if (!ds->mdmatab) { 106 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0, 107 &ds->cdmamap))) 108 return error; 109 110 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab, 111 MAXTABSZ, ata_dmasetupc_cb, &ccba, 112 0)) != 0 || ccba.error != 0) { 113 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 114 return error; 115 } 116 ds->mdmatab = ccba.maddr; 117 } 118 if (!ds->ddmamap) { 119 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0) 120 return error; 121 } 122 return 0; 123} 124 125void 126ata_dmafree(struct ata_device *atadev) 127{ 128 struct ata_dmastate *ds; 129 130 ds = &atadev->dmastate; 131 if (ds->mdmatab) { 132 bus_dmamap_unload(ds->cdmatag, ds->cdmamap); 133 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 134 ds->mdmatab = 0; 135 ds->cdmamap = NULL; 136 ds->dmatab = NULL; 137 } 138 if (ds->ddmamap) { 139 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap); 140 ds->ddmamap = NULL; 141 } 142 if (ds->cdmatag) { 143 bus_dma_tag_destroy(ds->cdmatag); 144 ds->cdmatag = NULL; 145 } 146 if (ds->ddmatag) { 147 bus_dma_tag_destroy(ds->ddmatag); 148 ds->ddmatag = NULL; 149 } 150} 151 152void 153ata_dmafreetags(struct ata_channel *ch) 154{ 155 156 if (ch->dmatag) { 157 bus_dma_tag_destroy(ch->dmatag); 158 ch->dmatag = NULL; 159 } 160} 161 162static void 163ata_dmacreate(struct ata_device *atadev, int apiomode, int mode) 164{ 165 166 atadev->mode = mode; 167 if (!atadev->channel->dmatag) { 168 if (bus_dma_tag_create(NULL, 1, 0, 169 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 170 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, 171 BUS_SPACE_MAXSIZE_32BIT, 0, 172 &atadev->channel->dmatag)) { 173 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n"); 174 ata_dmainit(atadev, apiomode, -1, -1); 175 } 176 } 177} 178 179void 180ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode) 181{ 182 device_t parent = device_get_parent(atadev->channel->dev); 183 int chiptype = atadev->channel->chiptype; 184 int chiprev = pci_get_revid(parent); 185 int channel = atadev->channel->unit; 186 int device = ATA_DEV(atadev->unit); 187 int devno = (channel << 1) + device; 188 int error; 189 190 /* set our most pessimistic default mode */ 191 atadev->mode = ATA_PIO; 192 193 if (!atadev->channel->r_bmio) 194 return; 195 196 /* if simplex controller, only allow DMA on primary channel */ 197 if (channel == 1) { 198 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT, 199 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 200 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 201 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 202 ATA_BMSTAT_DMA_SIMPLEX) { 203 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 204 return; 205 } 206 } 207 208 /* DMA engine address alignment is usually 1 word (2 bytes) */ 209 atadev->channel->alignment = 0x1; 210 211#if 1 212 if (udmamode > 2 && !atadev->param->hwres_cblid) { 213 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 214 udmamode = 2; 215 } 216#endif 217 switch (chiptype) { 218 219 case 0x248a8086: /* Intel ICH3 mobile */ 220 case 0x248b8086: /* Intel ICH3 */ 221 case 0x244a8086: /* Intel ICH2 mobile */ 222 case 0x244b8086: /* Intel ICH2 */ 223 if (udmamode >= 5) { 224 int32_t mask48, new48; 225 int16_t word54; 226 227 word54 = pci_read_config(parent, 0x54, 2); 228 if (word54 & (0x10 << devno)) { 229 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 230 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 231 if (bootverbose) 232 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 233 (error) ? "failed" : "success"); 234 if (!error) { 235 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 236 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 237 pci_write_config(parent, 0x48, 238 (pci_read_config(parent, 0x48, 4) & 239 ~mask48) | new48, 4); 240 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 241 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 242 return; 243 } 244 } 245 } 246 /* make sure eventual ATA100 mode from the BIOS is disabled */ 247 pci_write_config(parent, 0x54, 248 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 249 /* FALLTHROUGH */ 250 251 case 0x24118086: /* Intel ICH */ 252 case 0x76018086: /* Intel ICH */ 253 if (udmamode >= 4) { 254 int32_t mask48, new48; 255 int16_t word54; 256 257 word54 = pci_read_config(parent, 0x54, 2); 258 if (word54 & (0x10 << devno)) { 259 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 260 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 261 if (bootverbose) 262 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 263 (error) ? "failed" : "success"); 264 if (!error) { 265 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 266 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 267 pci_write_config(parent, 0x48, 268 (pci_read_config(parent, 0x48, 4) & 269 ~mask48) | new48, 4); 270 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 271 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 272 return; 273 } 274 } 275 } 276 /* make sure eventual ATA66 mode from the BIOS is disabled */ 277 pci_write_config(parent, 0x54, 278 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 279 /* FALLTHROUGH */ 280 281 case 0x71118086: /* Intel PIIX4 */ 282 case 0x84CA8086: /* Intel PIIX4 */ 283 case 0x71998086: /* Intel PIIX4e */ 284 case 0x24218086: /* Intel ICH0 */ 285 if (udmamode >= 2) { 286 int32_t mask48, new48; 287 288 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 289 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 290 if (bootverbose) 291 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 292 (error) ? "failed" : "success"); 293 if (!error) { 294 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 295 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 296 pci_write_config(parent, 0x48, 297 (pci_read_config(parent, 0x48, 4) & 298 ~mask48) | new48, 4); 299 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 300 return; 301 } 302 } 303 /* make sure eventual ATA33 mode from the BIOS is disabled */ 304 pci_write_config(parent, 0x48, 305 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 306 /* FALLTHROUGH */ 307 308 case 0x70108086: /* Intel PIIX3 */ 309 if (wdmamode >= 2 && apiomode >= 4) { 310 int32_t mask40, new40, mask44, new44; 311 312 /* if SITRE not set doit for both channels */ 313 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){ 314 new40 = pci_read_config(parent, 0x40, 4); 315 new44 = pci_read_config(parent, 0x44, 4); 316 if (!(new40 & 0x00004000)) { 317 new44 &= ~0x0000000f; 318 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 319 } 320 if (!(new40 & 0x40000000)) { 321 new44 &= ~0x000000f0; 322 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 323 } 324 new40 |= 0x40004000; 325 pci_write_config(parent, 0x40, new40, 4); 326 pci_write_config(parent, 0x44, new44, 4); 327 } 328 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 329 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 330 if (bootverbose) 331 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 332 (error) ? "failed" : "success"); 333 if (!error) { 334 if (device == ATA_MASTER) { 335 mask40 = 0x0000330f; 336 new40 = 0x00002307; 337 mask44 = 0; 338 new44 = 0; 339 } 340 else { 341 mask40 = 0x000000f0; 342 new40 = 0x00000070; 343 mask44 = 0x0000000f; 344 new44 = 0x0000000b; 345 } 346 if (channel) { 347 mask40 <<= 16; 348 new40 <<= 16; 349 mask44 <<= 4; 350 new44 <<= 4; 351 } 352 pci_write_config(parent, 0x40, 353 (pci_read_config(parent, 0x40, 4) & ~mask40)| 354 new40, 4); 355 pci_write_config(parent, 0x44, 356 (pci_read_config(parent, 0x44, 4) & ~mask44)| 357 new44, 4); 358 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 359 return; 360 } 361 } 362 /* we could set PIO mode timings, but we assume the BIOS did that */ 363 break; 364 365 case 0x12308086: /* Intel PIIX */ 366 if (wdmamode >= 2 && apiomode >= 4) { 367 int32_t word40; 368 369 word40 = pci_read_config(parent, 0x40, 4); 370 word40 >>= channel * 16; 371 372 /* Check for timing config usable for DMA on controller */ 373 if (!((word40 & 0x3300) == 0x2300 && 374 ((word40 >> (device ? 4 : 0)) & 1) == 1)) 375 break; 376 377 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 378 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 379 if (bootverbose) 380 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 381 (error) ? "failed" : "success"); 382 if (!error) { 383 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 384 return; 385 } 386 } 387 break; 388 389 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 390 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 391 if (chiprev < 0xc2 && 392 atadev->channel->devices & ATA_ATAPI_MASTER && 393 atadev->channel->devices & ATA_ATAPI_SLAVE) { 394 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 395 break; 396 } 397 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4); 398 if (udmamode >= 5 && chiprev >= 0xc4) { 399 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 400 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 401 if (bootverbose) 402 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 403 (error) ? "failed" : "success"); 404 if (!error) { 405 int32_t word54 = pci_read_config(parent, 0x54, 4); 406 407 pci_write_config(parent, 0x4b, 408 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 409 word54 &= ~(0x000f000f << (devno << 2)); 410 word54 |= (0x000f0005 << (devno << 2)); 411 pci_write_config(parent, 0x54, word54, 4); 412 pci_write_config(parent, 0x53, 413 pci_read_config(parent, 0x53, 1) | 0x03, 1); 414 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 415 return; 416 } 417 } 418 if (udmamode >= 4 && chiprev >= 0xc2) { 419 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 420 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 421 if (bootverbose) 422 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 423 (error) ? "failed" : "success"); 424 if (!error) { 425 int32_t word54 = pci_read_config(parent, 0x54, 4); 426 427 pci_write_config(parent, 0x4b, 428 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 429 word54 &= ~(0x000f000f << (devno << 2)); 430 word54 |= (0x00080005 << (devno << 2)); 431 pci_write_config(parent, 0x54, word54, 4); 432 pci_write_config(parent, 0x53, 433 pci_read_config(parent, 0x53, 1) | 0x03, 1); 434 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 435 return; 436 } 437 } 438 if (udmamode >= 2 && chiprev >= 0x20) { 439 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 440 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 441 if (bootverbose) 442 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 443 (error) ? "failed" : "success"); 444 if (!error) { 445 int32_t word54 = pci_read_config(parent, 0x54, 4); 446 447 word54 &= ~(0x000f000f << (devno << 2)); 448 word54 |= (0x000a0005 << (devno << 2)); 449 pci_write_config(parent, 0x54, word54, 4); 450 pci_write_config(parent, 0x53, 451 pci_read_config(parent, 0x53, 1) | 0x03, 1); 452 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 453 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 454 return; 455 } 456 } 457 458 /* make sure eventual UDMA mode from the BIOS is disabled */ 459 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 460 ~(0x0008 << (devno << 2)), 2); 461 462 if (wdmamode >= 2 && apiomode >= 4) { 463 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 464 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 465 if (bootverbose) 466 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 467 (error) ? "failed" : "success"); 468 if (!error) { 469 pci_write_config(parent, 0x53, 470 pci_read_config(parent, 0x53, 1) | 0x03, 1); 471 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 472 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 473 return; 474 } 475 } 476 pci_write_config(parent, 0x53, 477 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 478 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 479 ATA_PIO0 + apiomode, 480 ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n", 483 (error) ? "failed" : "success", 484 (apiomode >= 0) ? apiomode : 0); 485 if (!error) { 486 int32_t word54 = pci_read_config(parent, 0x54, 4); 487 int32_t timing; 488 489 switch(ATA_PIO0 + apiomode) { 490 case ATA_PIO0: timing = 0x006d0003; 491 case ATA_PIO1: timing = 0x00580002; 492 case ATA_PIO2: timing = 0x00440001; 493 case ATA_PIO3: timing = 0x00330001; 494 case ATA_PIO4: timing = 0x00310001; 495 default: timing = 0x006d0003; 496 } 497 pci_write_config(parent, 0x58 + (channel << 2), timing, 4); 498 word54 &= ~(0x000f000f << (devno << 2)); 499 word54 |= (0x00000004 << (devno << 2)); 500 pci_write_config(parent, 0x54, word54, 4); 501 atadev->mode = ATA_PIO0 + apiomode; 502 return; 503 } 504 break; 505 506 case 0x01bc10de: /* nVIDIA nForce */ 507 case 0x74411022: /* AMD 768 */ 508 case 0x74111022: /* AMD 766 */ 509 case 0x74091022: /* AMD 756 */ 510 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 511 { 512 int via_modes[5][7] = { 513 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 514 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 515 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 516 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 517 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0x00 }}; /* AMD/nVIDIA */ 518 int *reg_val = NULL; 519 char *chip = "VIA"; 520 521 if (ata_find_dev(parent, 0x31471106, 0)) { /* 8233a */ 522 udmamode = imin(udmamode, 6); 523 reg_val = via_modes[3]; 524 } 525 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 526 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 527 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 528 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 529 udmamode = imin(udmamode, 5); 530 reg_val = via_modes[2]; 531 } 532 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 533 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 534 udmamode = imin(udmamode, 4); 535 reg_val = via_modes[1]; 536 } 537 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 538 udmamode = imin(udmamode, 2); 539 reg_val = via_modes[1]; 540 } 541 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 542 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 543 udmamode = imin(udmamode, 2); 544 reg_val = via_modes[0]; 545 } 546 else if (chiptype == 0x74411022 || /* AMD 768 */ 547 chiptype == 0x74111022) { /* AMD 766 */ 548 udmamode = imin(udmamode, 5); 549 reg_val = via_modes[4]; 550 chip = "AMD"; 551 } 552 else if (chiptype == 0x74091022) { /* AMD 756 */ 553 udmamode = imin(udmamode, 4); 554 reg_val = via_modes[4]; 555 chip = "AMD"; 556 } 557 else if (chiptype == 0x01bc10de) { /* nVIDIA */ 558 udmamode = imin(udmamode, 5); 559 reg_val = via_modes[4]; 560 chip = "nVIDIA"; 561 } 562 else 563 udmamode = 0; 564 565 if (udmamode >= 6) { 566 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 567 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 568 if (bootverbose) 569 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n", 570 (error) ? "failed" : "success", chip); 571 if (!error) { 572 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 573 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 574 return; 575 } 576 } 577 if (udmamode >= 5) { 578 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 579 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 580 if (bootverbose) 581 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n", 582 (error) ? "failed" : "success", chip); 583 if (!error) { 584 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 585 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 586 return; 587 } 588 } 589 if (udmamode >= 4) { 590 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 591 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 592 if (bootverbose) 593 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n", 594 (error) ? "failed" : "success", chip); 595 if (!error) { 596 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 597 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 598 return; 599 } 600 } 601 if (udmamode >= 2) { 602 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 603 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 604 if (bootverbose) 605 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n", 606 (error) ? "failed" : "success", chip); 607 if (!error) { 608 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 609 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 610 return; 611 } 612 } 613 if (wdmamode >= 2 && apiomode >= 4) { 614 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 615 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 616 if (bootverbose) 617 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 618 (error) ? "failed" : "success", chip); 619 if (!error) { 620 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 621 pci_write_config(parent, 0x4b - devno, 0x31, 1); 622 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 623 return; 624 } 625 } 626 } 627 /* we could set PIO mode timings, but we assume the BIOS did that */ 628 break; 629 630 case 0x55131039: /* SiS 5591 */ 631 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 632 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 633 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 634 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 635 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 636 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 637 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 638 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 639 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 640 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 641 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 642 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 643 int8_t reg = 0x40 + (devno << 1); 644 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 645 646 if (udmamode >= 5) { 647 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 648 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 649 if (bootverbose) 650 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 651 (error) ? "failed" : "success"); 652 if (!error) { 653 pci_write_config(parent, reg, val | 0x8000, 2); 654 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 655 return; 656 } 657 } 658 if (udmamode >= 4) { 659 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 660 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 661 if (bootverbose) 662 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 663 (error) ? "failed" : "success"); 664 if (!error) { 665 pci_write_config(parent, reg, val | 0x9000, 2); 666 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 667 return; 668 } 669 } 670 if (udmamode >= 2) { 671 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 672 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 673 if (bootverbose) 674 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 675 (error) ? "failed" : "success"); 676 if (!error) { 677 pci_write_config(parent, reg, val | 0xb000, 2); 678 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 679 return; 680 } 681 } 682 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 683 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 684 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 685 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 686 int8_t reg = 0x40 + (devno << 1); 687 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 688 689 if (udmamode >= 4) { 690 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 691 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 692 if (bootverbose) 693 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 694 (error) ? "failed" : "success"); 695 if (!error) { 696 pci_write_config(parent, reg, val | 0x9000, 2); 697 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 698 return; 699 } 700 } 701 if (udmamode >= 2) { 702 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 703 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 704 if (bootverbose) 705 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 706 (error) ? "failed" : "success"); 707 if (!error) { 708 pci_write_config(parent, reg, val | 0xa000, 2); 709 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 710 return; 711 } 712 } 713 } else if (udmamode >= 2 && chiprev > 0xc1) { 714 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 715 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 716 if (bootverbose) 717 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 718 (error) ? "failed" : "success"); 719 if (!error) { 720 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 721 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 722 return; 723 } 724 } 725 if (wdmamode >=2 && apiomode >= 4) { 726 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 727 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 728 if (bootverbose) 729 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 730 (error) ? "failed" : "success"); 731 if (!error) { 732 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 733 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 734 return; 735 } 736 } 737 /* we could set PIO mode timings, but we assume the BIOS did that */ 738 break; 739 740 case 0x06491095: /* CMD 649 ATA100 controller */ 741 if (udmamode >= 5) { 742 u_int8_t umode; 743 744 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 745 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 746 if (bootverbose) 747 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 748 (error) ? "failed" : "success"); 749 if (!error) { 750 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 751 umode &= ~(device ? 0xca : 0x35); 752 umode |= (device ? 0x0a : 0x05); 753 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 754 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 755 return; 756 } 757 } 758 /* FALLTHROUGH */ 759 760 case 0x06481095: /* CMD 648 ATA66 controller */ 761 if (udmamode >= 4) { 762 u_int8_t umode; 763 764 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 765 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 766 if (bootverbose) 767 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 768 (error) ? "failed" : "success"); 769 if (!error) { 770 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 771 umode &= ~(device ? 0xca : 0x35); 772 umode |= (device ? 0x4a : 0x15); 773 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 774 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 775 return; 776 } 777 } 778 if (udmamode >= 2) { 779 u_int8_t umode; 780 781 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 782 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 783 if (bootverbose) 784 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 785 (error) ? "failed" : "success"); 786 if (!error) { 787 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 788 umode &= ~(device ? 0xca : 0x35); 789 umode |= (device ? 0x42 : 0x11); 790 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 791 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 792 return; 793 } 794 } 795 /* make sure eventual UDMA mode from the BIOS is disabled */ 796 pci_write_config(parent, channel ? 0x7b : 0x73, 797 pci_read_config(parent, channel ? 0x7b : 0x73, 1) & 798 ~(device ? 0xca : 0x53), 1); 799 /* FALLTHROUGH */ 800 801 case 0x06461095: /* CMD 646 ATA controller */ 802 if (wdmamode >= 2 && apiomode >= 4) { 803 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 804 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 805 if (bootverbose) 806 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 807 error ? "failed" : "success"); 808 if (!error) { 809 int32_t offset = (devno < 3) ? (devno << 1) : 7; 810 811 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 812 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 813 return; 814 } 815 } 816 /* we could set PIO mode timings, but we assume the BIOS did that */ 817 break; 818 819 case 0xc6931080: /* Cypress 82c693 ATA controller */ 820 if (wdmamode >= 2 && apiomode >= 4) { 821 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 822 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 823 if (bootverbose) 824 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 825 error ? "failed" : "success"); 826 if (!error) { 827 pci_write_config(atadev->channel->dev, 828 channel ? 0x4e:0x4c, 0x2020, 2); 829 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 830 return; 831 } 832 } 833 /* we could set PIO mode timings, but we assume the BIOS did that */ 834 break; 835 836 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 837 atadev->channel->alignment = 0xf; 838 if (udmamode >= 2) { 839 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 840 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 841 if (bootverbose) 842 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 843 (error) ? "failed" : "success"); 844 if (!error) { 845 cyrix_timing(atadev, devno, ATA_UDMA2); 846 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 847 return; 848 } 849 } 850 if (wdmamode >= 2 && apiomode >= 4) { 851 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 852 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 853 if (bootverbose) 854 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 855 (error) ? "failed" : "success"); 856 if (!error) { 857 cyrix_timing(atadev, devno, ATA_WDMA2); 858 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 859 return; 860 } 861 } 862 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 863 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 864 ATA_WAIT_READY); 865 if (bootverbose) 866 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 867 (error) ? "failed" : "success", 868 ata_mode2str(ATA_PIO0 + apiomode)); 869 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode); 870 atadev->mode = ATA_PIO0 + apiomode; 871 return; 872 873 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 874 if (udmamode >= 5 && chiprev >= 0x92) { 875 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 876 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 877 if (bootverbose) 878 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 879 (error) ? "failed" : "success"); 880 if (!error) { 881 u_int16_t reg56; 882 883 pci_write_config(parent, 0x54, 884 pci_read_config(parent, 0x54, 1) | 885 (0x01 << devno), 1); 886 reg56 = pci_read_config(parent, 0x56, 2); 887 reg56 &= ~(0xf << (devno * 4)); 888 reg56 |= (0x5 << (devno * 4)); 889 pci_write_config(parent, 0x56, reg56, 2); 890 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 891 return; 892 } 893 } 894 if (udmamode >= 4) { 895 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 896 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 897 if (bootverbose) 898 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 899 (error) ? "failed" : "success"); 900 if (!error) { 901 u_int16_t reg56; 902 903 pci_write_config(parent, 0x54, 904 pci_read_config(parent, 0x54, 1) | 905 (0x01 << devno), 1); 906 reg56 = pci_read_config(parent, 0x56, 2); 907 reg56 &= ~(0xf << (devno * 4)); 908 reg56 |= (0x4 << (devno * 4)); 909 pci_write_config(parent, 0x56, reg56, 2); 910 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 911 return; 912 } 913 } 914 /* FALLTHROUGH */ 915 916 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 917 if (udmamode >= 2) { 918 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 919 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 920 if (bootverbose) 921 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 922 (error) ? "failed" : "success"); 923 if (!error) { 924 u_int16_t reg56; 925 926 pci_write_config(parent, 0x54, 927 pci_read_config(parent, 0x54, 1) | 928 (0x01 << devno), 1); 929 reg56 = pci_read_config(parent, 0x56, 2); 930 reg56 &= ~(0xf << (devno * 4)); 931 reg56 |= (0x2 << (devno * 4)); 932 pci_write_config(parent, 0x56, reg56, 2); 933 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 934 return; 935 } 936 } 937 if (wdmamode >= 2 && apiomode >= 4) { 938 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 939 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 940 if (bootverbose) 941 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 942 (error) ? "failed" : "success"); 943 if (!error) { 944 int offset = devno ^ 0x01; 945 int word44 = pci_read_config(parent, 0x44, 4); 946 947 pci_write_config(parent, 0x54, 948 pci_read_config(parent, 0x54, 1) & 949 ~(0x01 << devno), 1); 950 word44 &= ~(0xff << (offset << 8)); 951 word44 |= (0x20 << (offset << 8)); 952 pci_write_config(parent, 0x44, 0x20, 4); 953 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 954 return; 955 } 956 } 957 /* we could set PIO mode timings, but we assume the BIOS did that */ 958 break; 959 960 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 961 case 0x5275105a: /* Promise TX2 ATA133 controllers */ 962 case 0x6269105a: /* Promise TX2 ATA133 controllers */ 963 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 964 if (udmamode >= 6 && 965 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 966 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 967 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 968 if (bootverbose) 969 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 970 (error) ? "failed" : "success"); 971 if (!error) { 972 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 973 return; 974 } 975 } 976 /* FALLTHROUGH */ 977 978 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 979 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 980 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 981 if (udmamode >= 5 && 982 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 983 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 984 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 985 if (bootverbose) 986 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 987 (error) ? "failed" : "success"); 988 if (!error) { 989 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 990 return; 991 } 992 } 993 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 994 if (udmamode >= 4 && 995 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 996 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 997 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 998 if (bootverbose) 999 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1000 (error) ? "failed" : "success"); 1001 if (!error) { 1002 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1003 return; 1004 } 1005 } 1006 if (udmamode >= 2) { 1007 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1008 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1009 if (bootverbose) 1010 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 1011 (error) ? "failed" : "success"); 1012 if (!error) { 1013 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1014 return; 1015 } 1016 } 1017 if (wdmamode >= 2 && apiomode >= 4) { 1018 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1019 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1020 if (bootverbose) 1021 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1022 (error) ? "failed" : "success"); 1023 if (!error) { 1024 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1025 return; 1026 } 1027 } 1028 break; 1029 1030 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 1031 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 1032 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 1033 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1034 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1035 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1036 if (bootverbose) 1037 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1038 (error) ? "failed" : "success"); 1039 if (!error) { 1040 promise_timing(atadev, devno, ATA_UDMA5); 1041 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1042 return; 1043 } 1044 } 1045 /* FALLTHROUGH */ 1046 1047 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 1048 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 1049 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1050 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1051 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1052 if (bootverbose) 1053 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1054 (error) ? "failed" : "success"); 1055 if (!error) { 1056 promise_timing(atadev, devno, ATA_UDMA4); 1057 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1058 return; 1059 } 1060 } 1061 /* FALLTHROUGH */ 1062 1063 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 1064 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1065 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1066 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1067 if (bootverbose) 1068 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 1069 (error) ? "failed" : "success"); 1070 if (!error) { 1071 promise_timing(atadev, devno, ATA_UDMA2); 1072 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1073 return; 1074 } 1075 } 1076 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1077 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1078 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1079 if (bootverbose) 1080 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1081 (error) ? "failed" : "success"); 1082 if (!error) { 1083 promise_timing(atadev, devno, ATA_WDMA2); 1084 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1085 return; 1086 } 1087 } 1088 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1089 ATA_PIO0 + apiomode, 1090 ATA_C_F_SETXFER, ATA_WAIT_READY); 1091 if (bootverbose) 1092 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 1093 (error) ? "failed" : "success", 1094 (apiomode >= 0) ? apiomode : 0); 1095 promise_timing(atadev, devno, ATA_PIO0 + apiomode); 1096 atadev->mode = ATA_PIO0 + apiomode; 1097 return; 1098 1099 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 1100 case 0x00051103: /* HighPoint HPT372 controllers */ 1101 case 0x00081103: /* HighPoint HPT374 controllers */ 1102 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) && 1103 ((chiptype == 0x00041103 && chiprev >= 0x05) || 1104 (chiptype == 0x00051103 && chiprev >= 0x01) || 1105 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1106 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1107 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1108 if (bootverbose) 1109 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 1110 (error) ? "failed" : "success"); 1111 if (!error) { 1112 hpt_timing(atadev, devno, ATA_UDMA6); 1113 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1114 return; 1115 } 1116 } 1117 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) && 1118 ((chiptype == 0x00041103 && chiprev >= 0x03) || 1119 (chiptype == 0x00051103 && chiprev >= 0x01) || 1120 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1121 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1122 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1123 if (bootverbose) 1124 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 1125 (error) ? "failed" : "success"); 1126 if (!error) { 1127 hpt_timing(atadev, devno, ATA_UDMA5); 1128 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1129 return; 1130 } 1131 } 1132 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) { 1133 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1134 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1135 if (bootverbose) 1136 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1137 (error) ? "failed" : "success"); 1138 if (!error) { 1139 hpt_timing(atadev, devno, ATA_UDMA4); 1140 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1141 return; 1142 } 1143 } 1144 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1145 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1146 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1147 if (bootverbose) 1148 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1149 (error) ? "failed" : "success"); 1150 if (!error) { 1151 hpt_timing(atadev, devno, ATA_UDMA2); 1152 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1153 return; 1154 } 1155 } 1156 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1157 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1158 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1159 if (bootverbose) 1160 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1161 (error) ? "failed" : "success"); 1162 if (!error) { 1163 hpt_timing(atadev, devno, ATA_WDMA2); 1164 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1165 return; 1166 } 1167 } 1168 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1169 ATA_PIO0 + apiomode, 1170 ATA_C_F_SETXFER, ATA_WAIT_READY); 1171 if (bootverbose) 1172 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1173 (error) ? "failed" : "success", 1174 (apiomode >= 0) ? apiomode : 0); 1175 hpt_timing(atadev, devno, ATA_PIO0 + apiomode); 1176 atadev->mode = ATA_PIO0 + apiomode; 1177 return; 1178 1179 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1180 if (wdmamode >= 0 && 1181 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1182 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) 1183 ata_dmacreate(atadev, apiomode, ATA_DMA); 1184 else 1185 atadev->mode = ATA_PIO; 1186 return; 1187 1188 default: /* unknown controller chip */ 1189 /* better not try generic DMA on ATAPI devices it almost never works */ 1190 if (ATAPI_DEVICE(atadev)) 1191 break; 1192 1193 /* if controller says its setup for DMA take the easy way out */ 1194 /* the downside is we dont know what DMA mode we are in */ 1195 if ((udmamode >= 0 || wdmamode >= 2) && 1196 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1197 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 1198 ata_dmacreate(atadev, apiomode, ATA_DMA); 1199 return; 1200 } 1201 1202 /* well, we have no support for this, but try anyways */ 1203 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) { 1204 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1205 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1206 if (bootverbose) 1207 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1208 (error) ? "failed" : "success"); 1209 if (!error) { 1210 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1211 return; 1212 } 1213 } 1214 } 1215 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1216 ATA_C_F_SETXFER, ATA_WAIT_READY); 1217 if (bootverbose) 1218 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1219 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1220 if (!error) 1221 atadev->mode = ATA_PIO0 + apiomode; 1222 else { 1223 if (bootverbose) 1224 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1225 atadev->mode = ATA_PIO; 1226 } 1227} 1228 1229struct ata_dmasetup_data_cb_args { 1230 struct ata_dmaentry *dmatab; 1231 int error; 1232}; 1233 1234static void 1235ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1236{ 1237 struct ata_dmasetup_data_cb_args *cba = 1238 (struct ata_dmasetup_data_cb_args *)xsc; 1239 bus_size_t cnt; 1240 u_int32_t lastcount; 1241 int i, j; 1242 1243 cba->error = error; 1244 if (error != 0) 1245 return; 1246 lastcount = j = 0; 1247 for (i = 0; i < nsegs; i++) { 1248 /* 1249 * A maximum segment size was specified for bus_dma_tag_create, but 1250 * some busdma code does not seem to honor this, so fix up if needed. 1251 */ 1252 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { 1253 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); 1254 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; 1255 cba->dmatab[j].count = htole32(lastcount); 1256 } 1257 } 1258 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); 1259} 1260 1261int 1262ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) 1263{ 1264 struct ata_channel *ch = atadev->channel; 1265 1266 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1267 ata_prtdev(atadev, "non aligned DMA transfer attempted\n"); 1268 return -1; 1269 } 1270 1271 if (!count) { 1272 ata_prtdev(atadev, "zero length DMA transfer attempted\n"); 1273 return -1; 1274 } 1275 return 0; 1276} 1277 1278int 1279ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir) 1280{ 1281 struct ata_channel *ch = atadev->channel; 1282 struct ata_dmastate *ds = &atadev->dmastate; 1283 struct ata_dmasetup_data_cb_args cba; 1284 1285 if (ds->flags & ATA_DS_ACTIVE) 1286 panic("ata_dmasetup: transfer active on this device!"); 1287 1288 cba.dmatab = ds->dmatab; 1289 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE); 1290 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count, 1291 ata_dmasetupd_cb, &cba, 0) || cba.error) 1292 return -1; 1293 1294 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE); 1295 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD : 1296 BUS_DMASYNC_PREWRITE); 1297 1298 ch->flags |= ATA_DMA_ACTIVE; 1299 ds->flags = ATA_DS_ACTIVE; 1300 if (dir) 1301 ds->flags |= ATA_DS_READ; 1302 1303 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab); 1304 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1305 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1306 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1307 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1308 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1309 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1310 return 0; 1311} 1312 1313int 1314ata_dmadone(struct ata_device *atadev) 1315{ 1316 struct ata_channel *ch; 1317 struct ata_dmastate *ds; 1318 int error; 1319 1320 ch = atadev->channel; 1321 ds = &atadev->dmastate; 1322 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ? 1323 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1324 bus_dmamap_unload(ds->ddmatag, ds->ddmamap); 1325 1326 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1327 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1328 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1329 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1330 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1331 ch->flags &= ~ATA_DMA_ACTIVE; 1332 ds->flags = 0; 1333 return (error & ATA_BMSTAT_MASK); 1334} 1335 1336int 1337ata_dmastatus(struct ata_channel *ch) 1338{ 1339 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1340} 1341 1342static void 1343cyrix_timing(struct ata_device *atadev, int devno, int mode) 1344{ 1345 u_int32_t reg20 = 0x0000e132; 1346 u_int32_t reg24 = 0x00017771; 1347 1348 switch (mode) { 1349 case ATA_PIO0: reg20 = 0x0000e132; break; 1350 case ATA_PIO1: reg20 = 0x00018121; break; 1351 case ATA_PIO2: reg20 = 0x00024020; break; 1352 case ATA_PIO3: reg20 = 0x00032010; break; 1353 case ATA_PIO4: reg20 = 0x00040010; break; 1354 case ATA_WDMA2: reg24 = 0x00002020; break; 1355 case ATA_UDMA2: reg24 = 0x00911030; break; 1356 } 1357 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20); 1358 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24); 1359} 1360 1361static void 1362promise_timing(struct ata_device *atadev, int devno, int mode) 1363{ 1364 u_int32_t timing = 0; 1365 /* XXX: Endianess */ 1366 struct promise_timing { 1367 u_int8_t pa:4; 1368 u_int8_t prefetch:1; 1369 u_int8_t iordy:1; 1370 u_int8_t errdy:1; 1371 u_int8_t syncin:1; 1372 u_int8_t pb:5; 1373 u_int8_t mb:3; 1374 u_int8_t mc:4; 1375 u_int8_t dmaw:1; 1376 u_int8_t dmar:1; 1377 u_int8_t iordyp:1; 1378 u_int8_t dmarqp:1; 1379 u_int8_t reserved:8; 1380 } *t = (struct promise_timing*)&timing; 1381 1382 t->iordy = 1; t->iordyp = 1; 1383 if (mode >= ATA_DMA) { 1384 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1385 } 1386 1387 switch (atadev->channel->chiptype) { 1388 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1389 switch (mode) { 1390 default: 1391 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1392 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1393 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1394 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1395 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1396 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1397 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1398 } 1399 break; 1400 1401 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1402 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1403 case 0x0d30105a: /* Promise OEM ATA 100 */ 1404 switch (mode) { 1405 default: 1406 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1407 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1408 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1409 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1410 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1411 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1412 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1413 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1414 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1415 } 1416 break; 1417 } 1418 pci_write_config(device_get_parent(atadev->channel->dev), 1419 0x60 + (devno << 2), timing, 4); 1420} 1421 1422static void 1423hpt_timing(struct ata_device *atadev, int devno, int mode) 1424{ 1425 device_t parent = device_get_parent(atadev->channel->dev); 1426 u_int32_t chiptype = atadev->channel->chiptype; 1427 int chiprev = pci_get_revid(parent); 1428 u_int32_t timing; 1429 1430 if (chiptype == 0x00081103 && chiprev >= 0x07) { 1431 switch (mode) { /* HPT374 */ 1432 case ATA_PIO0: timing = 0x0ac1f48a; break; 1433 case ATA_PIO1: timing = 0x0ac1f465; break; 1434 case ATA_PIO2: timing = 0x0a81f454; break; 1435 case ATA_PIO3: timing = 0x0a81f443; break; 1436 case ATA_PIO4: timing = 0x0a81f442; break; 1437 case ATA_WDMA2: timing = 0x22808242; break; 1438 case ATA_UDMA2: timing = 0x120c8242; break; 1439 case ATA_UDMA4: timing = 0x12ac8242; break; 1440 case ATA_UDMA5: timing = 0x12848242; break; 1441 case ATA_UDMA6: timing = 0x12808242; break; 1442 default: timing = 0x0d029d5e; 1443 } 1444 } 1445 else if ((chiptype == 0x00041103 && chiprev >= 0x05) || 1446 (chiptype == 0x00051103 && chiprev >= 0x01)) { 1447 switch (mode) { /* HPT372 */ 1448 case ATA_PIO0: timing = 0x0d029d5e; break; 1449 case ATA_PIO1: timing = 0x0d029d26; break; 1450 case ATA_PIO2: timing = 0x0c829ca6; break; 1451 case ATA_PIO3: timing = 0x0c829c84; break; 1452 case ATA_PIO4: timing = 0x0c829c62; break; 1453 case ATA_WDMA2: timing = 0x2c829262; break; 1454 case ATA_UDMA2: timing = 0x1c91dc62; break; 1455 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1456 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1457 case ATA_UDMA6: timing = 0x1c81dc62; break; 1458 default: timing = 0x0d029d5e; 1459 } 1460 } 1461 else if (chiptype == 0x00041103 && chiprev >= 0x03) { 1462 switch (mode) { /* HPT370 */ 1463 case ATA_PIO0: timing = 0x06914e57; break; 1464 case ATA_PIO1: timing = 0x06914e43; break; 1465 case ATA_PIO2: timing = 0x06514e33; break; 1466 case ATA_PIO3: timing = 0x06514e22; break; 1467 case ATA_PIO4: timing = 0x06514e21; break; 1468 case ATA_WDMA2: timing = 0x26514e21; break; 1469 case ATA_UDMA2: timing = 0x16494e31; break; 1470 case ATA_UDMA4: timing = 0x16454e31; break; 1471 case ATA_UDMA5: timing = 0x16454e31; break; 1472 default: timing = 0x06514e57; 1473 } 1474 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1475 } 1476 else { /* HPT36[68] */ 1477 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1478 case 0x85: /* 25Mhz */ 1479 switch (mode) { 1480 case ATA_PIO0: timing = 0x40d08585; break; 1481 case ATA_PIO1: timing = 0x40d08572; break; 1482 case ATA_PIO2: timing = 0x40ca8542; break; 1483 case ATA_PIO3: timing = 0x40ca8532; break; 1484 case ATA_PIO4: timing = 0x40ca8521; break; 1485 case ATA_WDMA2: timing = 0x20ca8521; break; 1486 case ATA_UDMA2: timing = 0x10cf8521; break; 1487 case ATA_UDMA4: timing = 0x10c98521; break; 1488 default: timing = 0x01208585; 1489 } 1490 break; 1491 default: 1492 case 0xa7: /* 33MHz */ 1493 switch (mode) { 1494 case ATA_PIO0: timing = 0x40d0a7aa; break; 1495 case ATA_PIO1: timing = 0x40d0a7a3; break; 1496 case ATA_PIO2: timing = 0x40d0a753; break; 1497 case ATA_PIO3: timing = 0x40c8a742; break; 1498 case ATA_PIO4: timing = 0x40c8a731; break; 1499 case ATA_WDMA2: timing = 0x20c8a731; break; 1500 case ATA_UDMA2: timing = 0x10caa731; break; 1501 case ATA_UDMA4: timing = 0x10c9a731; break; 1502 default: timing = 0x0120a7a7; 1503 } 1504 break; 1505 case 0xd9: /* 40Mhz */ 1506 switch (mode) { 1507 case ATA_PIO0: timing = 0x4018d9d9; break; 1508 case ATA_PIO1: timing = 0x4010d9c7; break; 1509 case ATA_PIO2: timing = 0x4010d997; break; 1510 case ATA_PIO3: timing = 0x4010d974; break; 1511 case ATA_PIO4: timing = 0x4008d963; break; 1512 case ATA_WDMA2: timing = 0x2008d943; break; 1513 case ATA_UDMA2: timing = 0x100bd943; break; 1514 case ATA_UDMA4: timing = 0x100fd943; break; 1515 default: timing = 0x0120d9d9; 1516 } 1517 } 1518 } 1519 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1520} 1521 1522static int 1523hpt_cable80(struct ata_device *atadev) 1524{ 1525 device_t parent = device_get_parent(atadev->channel->dev); 1526 u_int8_t reg, val, res; 1527 1528 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) { 1529 reg = atadev->channel->unit ? 0x57 : 0x53; 1530 val = pci_read_config(parent, reg, 1); 1531 pci_write_config(parent, reg, val | 0x80, 1); 1532 } 1533 else { 1534 reg = 0x5b; 1535 val = pci_read_config(parent, reg, 1); 1536 pci_write_config(parent, reg, val & 0xfe, 1); 1537 } 1538 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); 1539 pci_write_config(parent, reg, val, 1); 1540 return !res; 1541} 1542