ata-dma.c revision 66326
1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 66326 2000-09-24 18:19:43Z sos $ 29 */ 30 31#include "pci.h" 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <sys/disk.h> 38#include <sys/devicestat.h> 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#if NPCI > 0 42#include <pci/pcivar.h> 43#endif 44#include <machine/bus.h> 45#include <dev/ata/ata-all.h> 46 47#if NPCI > 0 48 49/* prototypes */ 50static void cyrix_timing(struct ata_softc *, int, int); 51static void promise_timing(struct ata_softc *, int, int); 52static void hpt_timing(struct ata_softc *, int, int); 53 54/* misc defines */ 55#ifdef __alpha__ 56#undef vtophys 57#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 58#endif 59 60void * 61ata_dmaalloc(struct ata_softc *scp, int device) 62{ 63 void *dmatab; 64 65 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 66 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 67 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 68 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 69 free(dmatab, M_DEVBUF); 70 dmatab = NULL; 71 } 72 } 73 return dmatab; 74} 75 76void 77ata_dmainit(struct ata_softc *scp, int device, 78 int apiomode, int wdmamode, int udmamode) 79{ 80 device_t parent = device_get_parent(scp->dev); 81 int devno = (scp->unit << 1) + ATA_DEV(device); 82 int error; 83 84 /* set our most pessimistic default mode */ 85 scp->mode[ATA_DEV(device)] = ATA_PIO; 86 87 if (!scp->bmaddr) 88 return; 89 90 /* if simplex controller, only allow DMA on primary channel */ 91 if (scp->unit == 1) { 92 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 93 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 94 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 95 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 96 return; 97 } 98 } 99 100 /* DMA engine address alignment is usually 1 word (2 bytes) */ 101 scp->alignment = 0x1; 102 103 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 104 ata_printf(scp, device, 105 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 106 udmamode = 2; 107 } 108 109 switch (scp->chiptype) { 110 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on ICH2 chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on ICH%s chip\n", 153 (error) ? "failed" : "success", 154 (scp->chiptype == 0x244b8086) ? "2" : ""); 155 if (!error) { 156 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 157 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 158 pci_write_config(parent, 0x48, 159 (pci_read_config(parent, 0x48, 4) & 160 ~mask48) | new48, 4); 161 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 162 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 163 return; 164 } 165 } 166 } 167 /* make sure eventual ATA66 mode from the BIOS is disabled */ 168 pci_write_config(parent, 0x54, 169 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 170 /* FALLTHROUGH */ 171 172 case 0x71118086: /* Intel PIIX4 */ 173 case 0x71998086: /* Intel PIIX4e */ 174 case 0x24218086: /* Intel ICH0 */ 175 if (udmamode >= 2) { 176 int32_t mask48, new48; 177 178 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 180 if (bootverbose) 181 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 182 (error) ? "failed" : "success", 183 (scp->chiptype == 0x244b8086) ? "ICH2" : 184 (scp->chiptype == 0x24118086) ? "ICH" : 185 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 186 if (!error) { 187 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 188 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 189 pci_write_config(parent, 0x48, 190 (pci_read_config(parent, 0x48, 4) & 191 ~mask48) | new48, 4); 192 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 193 return; 194 } 195 } 196 /* make sure eventual ATA33 mode from the BIOS is disabled */ 197 pci_write_config(parent, 0x48, 198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 199 /* FALLTHROUGH */ 200 201 case 0x70108086: /* Intel PIIX3 */ 202 if (wdmamode >= 2 && apiomode >= 4) { 203 int32_t mask40, new40, mask44, new44; 204 205 /* if SITRE not set doit for both channels */ 206 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 207 new40 = pci_read_config(parent, 0x40, 4); 208 new44 = pci_read_config(parent, 0x44, 4); 209 if (!(new40 & 0x00004000)) { 210 new44 &= ~0x0000000f; 211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 212 } 213 if (!(new40 & 0x40000000)) { 214 new44 &= ~0x000000f0; 215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 216 } 217 new40 |= 0x40004000; 218 pci_write_config(parent, 0x40, new40, 4); 219 pci_write_config(parent, 0x44, new44, 4); 220 } 221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 223 if (bootverbose) 224 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 225 (error) ? "failed" : "success", 226 (scp->chiptype == 0x244b8086) ? "ICH2" : 227 (scp->chiptype == 0x24118086) ? "ICH" : 228 (scp->chiptype == 0x24218086) ? "ICH0" : 229 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 230 if (!error) { 231 if (device == ATA_MASTER) { 232 mask40 = 0x0000330f; 233 new40 = 0x00002307; 234 mask44 = 0; 235 new44 = 0; 236 } 237 else { 238 mask40 = 0x000000f0; 239 new40 = 0x00000070; 240 mask44 = 0x0000000f; 241 new44 = 0x0000000b; 242 } 243 if (scp->unit) { 244 mask40 <<= 16; 245 new40 <<= 16; 246 mask44 <<= 4; 247 new44 <<= 4; 248 } 249 pci_write_config(parent, 0x40, 250 (pci_read_config(parent, 0x40, 4) & ~mask40)| 251 new40, 4); 252 pci_write_config(parent, 0x44, 253 (pci_read_config(parent, 0x44, 4) & ~mask44)| 254 new44, 4); 255 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 256 return; 257 } 258 } 259 /* we could set PIO mode timings, but we assume the BIOS did that */ 260 break; 261 262 case 0x12308086: /* Intel PIIX */ 263 if (wdmamode >= 2 && apiomode >= 4) { 264 int32_t word40; 265 266 word40 = pci_read_config(parent, 0x40, 4); 267 word40 >>= scp->unit * 16; 268 269 /* Check for timing config usable for DMA on controller */ 270 if (!((word40 & 0x3300) == 0x2300 && 271 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 272 break; 273 274 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 275 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 276 if (bootverbose) 277 ata_printf(scp, device, 278 "%s setting WDMA2 on PIIX chip\n", 279 (error) ? "failed" : "success"); 280 if (!error) { 281 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 282 return; 283 } 284 } 285 break; 286 287 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 288 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 289 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 290 ata_printf(scp, device, 291 "Aladdin: two atapi devices on this channel, no DMA\n"); 292 break; 293 } 294 if (udmamode >= 2 && pci_read_config(parent, 0x08, 1) > 0x20) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 298 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA2 on Aladdin chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000a0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->flags |= ATA_ATAPI_DMA_RO; 310 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 311 return; 312 } 313 } 314 if (wdmamode >= 2 && apiomode >= 4) { 315 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 316 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 317 if (bootverbose) 318 ata_printf(scp, device, 319 "%s setting WDMA2 on Aladdin chip\n", 320 (error) ? "failed" : "success"); 321 if (!error) { 322 pci_write_config(parent, 0x53, 323 pci_read_config(parent, 0x53, 1) | 0x03, 1); 324 scp->flags |= ATA_ATAPI_DMA_RO; 325 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 326 return; 327 } 328 } 329 pci_write_config(parent, 0x53, 330 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 331 /* we could set PIO mode timings, but we assume the BIOS did that */ 332 break; 333 334 case 0x74091022: /* AMD 756 */ 335 if (udmamode >= 4) { 336 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 337 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 338 if (bootverbose) 339 ata_printf(scp, device, 340 "%s setting UDMA4 on AMD chip\n", 341 (error) ? "failed" : "success"); 342 if (!error) { 343 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 344 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 345 return; 346 } 347 } 348 goto via_82c586; 349 350 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 351 if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 352 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 353 354 if (udmamode >= 4) { 355 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 356 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 357 if (bootverbose) 358 ata_printf(scp, device, 359 "%s setting UDMA4 on VIA chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 363 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 364 return; 365 } 366 } 367 if (udmamode >= 2) { 368 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 369 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 370 if (bootverbose) 371 ata_printf(scp, device, 372 "%s setting UDMA2 on VIA chip\n", 373 (error) ? "failed" : "success"); 374 if (!error) { 375 pci_write_config(parent, 0x53 - devno, 0xea, 1); 376 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 377 return; 378 } 379 } 380 } 381 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 382 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 383via_82c586: 384 if (udmamode >= 2) { 385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 386 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 387 if (bootverbose) 388 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 389 (error) ? "failed" : "success", 390 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 391 if (!error) { 392 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 393 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 394 return; 395 } 396 } 397 } 398 if (wdmamode >= 2 && apiomode >= 4) { 399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 401 if (bootverbose) 402 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 403 (error) ? "failed" : "success", 404 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 405 if (!error) { 406 pci_write_config(parent, 0x53 - devno, 0x82, 1); 407 pci_write_config(parent, 0x4b - devno, 0x31, 1); 408 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 409 return; 410 } 411 } 412 /* we could set PIO mode timings, but we assume the BIOS did that */ 413 break; 414 415 case 0x55131039: /* SiS 5591 */ 416 if (udmamode >= 2) { 417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 418 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 419 if (bootverbose) 420 ata_printf(scp, device, 421 "%s setting UDMA2 on SiS chip\n", 422 (error) ? "failed" : "success"); 423 if (!error) { 424 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 425 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 426 return; 427 } 428 } 429 if (wdmamode >=2 && apiomode >= 4) { 430 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 431 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 432 if (bootverbose) 433 ata_printf(scp, device, 434 "%s setting WDMA2 on SiS chip\n", 435 (error) ? "failed" : "success"); 436 if (!error) { 437 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 438 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 439 return; 440 } 441 } 442 /* we could set PIO mode timings, but we assume the BIOS did that */ 443 break; 444 445 case 0x06461095: /* CMD 646 ATA controller */ 446 if (wdmamode >= 2 && apiomode >= 4) { 447 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 448 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 449 if (bootverbose) 450 ata_printf(scp, device, 451 "%s setting WDMA2 on CMD646 chip\n", 452 error ? "failed" : "success"); 453 if (!error) { 454 int32_t offset = (devno < 3) ? (devno << 1) : 7; 455 456 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 457 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 458 return; 459 } 460 } 461 /* we could set PIO mode timings, but we assume the BIOS did that */ 462 break; 463 464 case 0xc6931080: /* Cypress 82c693 ATA controller */ 465 if (wdmamode >= 2 && apiomode >= 4) { 466 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 467 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 468 if (bootverbose) 469 ata_printf(scp, device, 470 "%s setting WDMA2 on Cypress chip\n", 471 error ? "failed" : "success"); 472 if (!error) { 473 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 474 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 475 return; 476 } 477 } 478 /* we could set PIO mode timings, but we assume the BIOS did that */ 479 break; 480 481 case 0x01021078: 482 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 483 if (udmamode >= 2) { 484 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 485 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 486 if (bootverbose) 487 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 488 (error) ? "failed" : "success"); 489 if (!error) { 490 cyrix_timing(scp, devno, ATA_UDMA2); 491 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 492 return; 493 } 494 } 495 if (wdmamode >= 2 && apiomode >= 4) { 496 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 497 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 498 if (bootverbose) 499 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 500 (error) ? "failed" : "success"); 501 if (!error) { 502 cyrix_timing(scp, devno, ATA_WDMA2); 503 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 504 return; 505 } 506 } 507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 508 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 509 ATA_WAIT_READY); 510 if (bootverbose) 511 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 512 (error) ? "failed" : "success", 513 ata_mode2str(ata_pio2mode(apiomode))); 514 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 515 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 516 return; 517 518 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 519 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 520 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 521 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 522 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 523 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 524 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 525 break; 526 527 if (udmamode >= 5 && 528 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 529 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 530 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 531 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 532 if (bootverbose) 533 ata_printf(scp, device, 534 "%s setting UDMA5 on Promise chip\n", 535 (error) ? "failed" : "success"); 536 if (!error) { 537 promise_timing(scp, devno, ATA_UDMA5); 538 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 539 return; 540 } 541 } 542 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 543 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 544 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 545 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 546 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 547 if (bootverbose) 548 ata_printf(scp, device, 549 "%s setting UDMA4 on Promise chip\n", 550 (error) ? "failed" : "success"); 551 if (!error) { 552 promise_timing(scp, devno, ATA_UDMA4); 553 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 554 return; 555 } 556 } 557 if (udmamode >= 2) { 558 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 559 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 560 if (bootverbose) 561 ata_printf(scp, device, 562 "%s setting UDMA2 on Promise chip\n", 563 (error) ? "failed" : "success"); 564 if (!error) { 565 promise_timing(scp, devno, ATA_UDMA2); 566 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 567 return; 568 } 569 } 570 if (wdmamode >= 2 && apiomode >= 4) { 571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 572 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 573 if (bootverbose) 574 ata_printf(scp, device, 575 "%s setting WDMA2 on Promise chip\n", 576 (error) ? "failed" : "success"); 577 if (!error) { 578 promise_timing(scp, devno, ATA_WDMA2); 579 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 580 return; 581 } 582 } 583 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 584 ata_pio2mode(apiomode), 585 ATA_C_F_SETXFER, ATA_WAIT_READY); 586 if (bootverbose) 587 ata_printf(scp, device, 588 "%s setting PIO%d on Promise chip\n", 589 (error) ? "failed" : "success", 590 (apiomode >= 0) ? apiomode : 0); 591 promise_timing(scp, devno, ata_pio2mode(apiomode)); 592 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 593 return; 594 595 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 596 /* no ATAPI devices for now */ 597 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 598 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 599 break; 600 601 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 602 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 603 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 604 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 605 if (bootverbose) 606 ata_printf(scp, device, 607 "%s setting UDMA5 on HPT370 chip\n", 608 (error) ? "failed" : "success"); 609 if (!error) { 610 hpt_timing(scp, devno, ATA_UDMA5); 611 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 612 return; 613 } 614 } 615 616 if (udmamode >=4 && 617 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 618 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 619 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 620 if (bootverbose) 621 ata_printf(scp, device, 622 "%s setting UDMA4 on HPT366 chip\n", 623 (error) ? "failed" : "success"); 624 if (!error) { 625 hpt_timing(scp, devno, ATA_UDMA4); 626 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 627 return; 628 } 629 } 630 if (udmamode >= 2) { 631 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 632 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 633 if (bootverbose) 634 ata_printf(scp, device, 635 "%s setting UDMA2 on HPT366 chip\n", 636 (error) ? "failed" : "success"); 637 if (!error) { 638 hpt_timing(scp, devno, ATA_UDMA2); 639 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 640 return; 641 } 642 } 643 if (wdmamode >= 2 && apiomode >= 4) { 644 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 645 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 646 if (bootverbose) 647 ata_printf(scp, device, 648 "%s setting WDMA2 on HPT366 chip\n", 649 (error) ? "failed" : "success"); 650 if (!error) { 651 hpt_timing(scp, devno, ATA_WDMA2); 652 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 653 return; 654 } 655 } 656 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 657 ata_pio2mode(apiomode), 658 ATA_C_F_SETXFER, ATA_WAIT_READY); 659 if (bootverbose) 660 ata_printf(scp, device, "%s setting PIO%d on HPT366 chip\n", 661 (error) ? "failed" : "success", 662 (apiomode >= 0) ? apiomode : 0); 663 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 664 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 665 return; 666 667 default: /* unknown controller chip */ 668 /* better not try generic DMA on ATAPI devices it almost never works */ 669 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 670 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 671 break; 672 673 /* if controller says its setup for DMA take the easy way out */ 674 /* the downside is we dont know what DMA mode we are in */ 675 if ((udmamode >= 0 || wdmamode > 1) && 676 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 677 ((device==ATA_MASTER) ? 678 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 679 scp->mode[ATA_DEV(device)] = ATA_DMA; 680 return; 681 } 682 683 /* well, we have no support for this, but try anyways */ 684 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 685 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 686 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 687 if (bootverbose) 688 ata_printf(scp, device, 689 "%s setting WDMA2 on generic chip\n", 690 (error) ? "failed" : "success"); 691 if (!error) { 692 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 693 return; 694 } 695 } 696 } 697 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 698 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 699 if (bootverbose) 700 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 701 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 702 if (!error) 703 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 704 else { 705 if (bootverbose) 706 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 707 scp->mode[ATA_DEV(device)] = ATA_PIO; 708 } 709} 710 711int 712ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 713 caddr_t data, int32_t count) 714{ 715 u_int32_t dma_count, dma_base; 716 int i = 0; 717 718 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 719 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 720 return -1; 721 } 722 723 if (!count) { 724 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 725 return -1; 726 } 727 728 dma_base = vtophys(data); 729 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 730 data += dma_count; 731 count -= dma_count; 732 733 while (count) { 734 dmatab[i].base = dma_base; 735 dmatab[i].count = (dma_count & 0xffff); 736 i++; 737 if (i >= ATA_DMA_ENTRIES) { 738 ata_printf(scp, device, "too many segments in DMA table\n"); 739 return -1; 740 } 741 dma_base = vtophys(data); 742 dma_count = min(count, PAGE_SIZE); 743 data += min(count, PAGE_SIZE); 744 count -= min(count, PAGE_SIZE); 745 } 746 dmatab[i].base = dma_base; 747 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 748 return 0; 749} 750 751void 752ata_dmastart(struct ata_softc *scp, int device, 753 struct ata_dmaentry *dmatab, int dir) 754{ 755 scp->flags |= ATA_DMA_ACTIVE; 756 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 757 outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 758 outb(scp->bmaddr + ATA_BMSTAT_PORT, 759 (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 760 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 761 outb(scp->bmaddr + ATA_BMCMD_PORT, 762 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 763} 764 765int 766ata_dmadone(struct ata_softc *scp) 767{ 768 outb(scp->bmaddr + ATA_BMCMD_PORT, 769 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 770 scp->flags &= ~ATA_DMA_ACTIVE; 771 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 772} 773 774int 775ata_dmastatus(struct ata_softc *scp) 776{ 777 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 778} 779 780static void 781cyrix_timing(struct ata_softc *scp, int devno, int mode) 782{ 783 u_int32_t reg20 = 0x0000e132; 784 u_int32_t reg24 = 0x00017771; 785 786 switch (mode) { 787 case ATA_PIO0: reg20 = 0x0000e132; break; 788 case ATA_PIO1: reg20 = 0x00018121; break; 789 case ATA_PIO2: reg20 = 0x00024020; break; 790 case ATA_PIO3: reg20 = 0x00032010; break; 791 case ATA_PIO4: reg20 = 0x00040010; break; 792 case ATA_WDMA2: reg24 = 0x00002020; break; 793 case ATA_UDMA2: reg24 = 0x00911030; break; 794 } 795 outl(scp->bmaddr + (devno * 8) + 0x20, reg20); 796 outl(scp->bmaddr + (devno * 8) + 0x24, reg24); 797} 798 799static void 800promise_timing(struct ata_softc *scp, int devno, int mode) 801{ 802 u_int32_t timing = 0; 803 struct promise_timing { 804 u_int8_t pa:4; 805 u_int8_t prefetch:1; 806 u_int8_t iordy:1; 807 u_int8_t errdy:1; 808 u_int8_t syncin:1; 809 u_int8_t pb:5; 810 u_int8_t mb:3; 811 u_int8_t mc:4; 812 u_int8_t dmaw:1; 813 u_int8_t dmar:1; 814 u_int8_t iordyp:1; 815 u_int8_t dmarqp:1; 816 u_int8_t reserved:8; 817 } *t = (struct promise_timing*)&timing; 818 819 t->iordy = 1; t->iordyp = 1; 820 if (mode >= ATA_DMA) { 821 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 822 } 823 824 switch (scp->chiptype) { 825 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 826 switch (mode) { 827 default: 828 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 829 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 830 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 831 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 832 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 833 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 834 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 835 } 836 break; 837 838 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 839 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 840 case 0x0d30105a: /* Promise OEM ATA 100 */ 841 switch (mode) { 842 default: 843 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 844 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 845 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 846 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 847 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 848 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 849 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 850 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 851 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 852 } 853 break; 854 } 855 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 856} 857 858static void 859hpt_timing(struct ata_softc *scp, int devno, int mode) 860{ 861 device_t parent = device_get_parent(scp->dev); 862 u_int32_t timing; 863 864 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 865 switch (mode) { 866 case ATA_PIO0: timing = 0x06914e57; break; 867 case ATA_PIO1: timing = 0x06914e43; break; 868 case ATA_PIO2: timing = 0x06514e33; break; 869 case ATA_PIO3: timing = 0x06514e22; break; 870 case ATA_PIO4: timing = 0x06514e21; break; 871 case ATA_WDMA2: timing = 0x26514e21; break; 872 case ATA_UDMA2: timing = 0x16494e31; break; 873 case ATA_UDMA4: timing = 0x16454e31; break; 874 case ATA_UDMA5: timing = 0x16454e31; break; 875 default: timing = 0x06514e57; 876 } 877 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 878 pci_write_config(parent, 0x5b, 0x22, 1); 879 } 880 else { /* HPT36[68] */ 881 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 882 case 0x85: /* 25Mhz */ 883 switch (mode) { 884 case ATA_PIO0: timing = 0xc0d08585; break; 885 case ATA_PIO1: timing = 0xc0d08572; break; 886 case ATA_PIO2: timing = 0xc0ca8542; break; 887 case ATA_PIO3: timing = 0xc0ca8532; break; 888 case ATA_PIO4: timing = 0xc0ca8521; break; 889 case ATA_WDMA2: timing = 0xa0ca8521; break; 890 case ATA_UDMA2: timing = 0x90cf8521; break; 891 case ATA_UDMA4: timing = 0x90c98521; break; 892 default: timing = 0x01208585; 893 } 894 break; 895 default: 896 case 0xa7: /* 33MHz */ 897 switch (mode) { 898 case ATA_PIO0: timing = 0xc0d0a7aa; break; 899 case ATA_PIO1: timing = 0xc0d0a7a3; break; 900 case ATA_PIO2: timing = 0xc0d0a753; break; 901 case ATA_PIO3: timing = 0xc0c8a742; break; 902 case ATA_PIO4: timing = 0xc0c8a731; break; 903 case ATA_WDMA2: timing = 0xa0c8a731; break; 904 case ATA_UDMA2: timing = 0x90caa731; break; 905 case ATA_UDMA4: timing = 0x90c9a731; break; 906 default: timing = 0x0120a7a7; 907 } 908 break; 909 case 0xd9: /* 40Mhz */ 910 switch (mode) { 911 case ATA_PIO0: timing = 0xc018d9d9; break; 912 case ATA_PIO1: timing = 0xc010d9c7; break; 913 case ATA_PIO2: timing = 0xc010d997; break; 914 case ATA_PIO3: timing = 0xc010d974; break; 915 case ATA_PIO4: timing = 0xc008d963; break; 916 case ATA_WDMA2: timing = 0xa008d943; break; 917 case ATA_UDMA2: timing = 0x900bd943; break; 918 case ATA_UDMA4: timing = 0x900fd943; break; 919 default: timing = 0x0120d9d9; 920 } 921 } 922 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 923 } 924} 925 926#else /* NPCI > 0 */ 927 928void 929ata_dmainit(struct ata_softc *scp, int device, 930 int piomode, int wdmamode, int udmamode) 931{ 932} 933 934int 935ata_dmasetup(struct ata_softc *scp, int device, 936 int8_t *data, int32_t count, int flags) 937{ 938 return -1; 939} 940 941void 942ata_dmastart(struct ata_softc *scp) 943{ 944} 945 946int 947ata_dmadone(struct ata_softc *scp) 948{ 949 return -1; 950} 951 952int 953ata_dmastatus(struct ata_softc *scp) 954{ 955 return -1; 956} 957 958#endif /* NPCI > 0 */ 959