ata-dma.c revision 108931
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 108931 2003-01-08 10:03:31Z sos $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/endian.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <pci/pcivar.h> 38#include <machine/bus.h> 39#include <sys/rman.h> 40#include <dev/ata/ata-all.h> 41 42/* prototypes */ 43static void ata_dmacreate(struct ata_device *, int, int); 44static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); 45static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int); 46static void cyrix_timing(struct ata_device *, int, int); 47static void promise_timing(struct ata_device *, int, int); 48static void hpt_timing(struct ata_device *, int, int); 49static int hpt_cable80(struct ata_device *); 50 51/* misc defines */ 52#define ATAPI_DEVICE(atadev) \ 53 ((atadev->unit == ATA_MASTER && \ 54 atadev->channel->devices & ATA_ATAPI_MASTER) || \ 55 (atadev->unit == ATA_SLAVE && \ 56 atadev->channel->devices & ATA_ATAPI_SLAVE)) 57 58#define MAXSEGSZ PAGE_SIZE 59#define MAXTABSZ PAGE_SIZE 60#define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) 61 62struct ata_dc_cb_args { 63 bus_addr_t maddr; 64 int error; 65}; 66 67static void 68ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 69{ 70 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; 71 72 if (!(cba->error = error)) 73 cba->maddr = segs[0].ds_addr; 74} 75 76int 77ata_dmaalloc(struct ata_device *atadev) 78{ 79 struct ata_channel *ch; 80 struct ata_dc_cb_args ccba; 81 struct ata_dmastate *ds; 82 int error; 83 84 ch = atadev->channel; 85 ds = &atadev->dmastate; 86 if (!ds->cdmatag) { 87 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE, 88 BUS_SPACE_MAXADDR_32BIT, 89 BUS_SPACE_MAXADDR, NULL, NULL, 90 MAXTABSZ, 1, MAXTABSZ, 91 BUS_DMA_ALLOCNOW, &ds->cdmatag))) 92 return error; 93 } 94 if (!ds->ddmatag) { 95 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0, 96 BUS_SPACE_MAXADDR_32BIT, 97 BUS_SPACE_MAXADDR, NULL, NULL, 98 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, 99 BUS_DMA_ALLOCNOW, &ds->ddmatag))) 100 return error; 101 } 102 if (!ds->mdmatab) { 103 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0, 104 &ds->cdmamap))) 105 return error; 106 107 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab, 108 MAXTABSZ, ata_dmasetupc_cb, &ccba, 109 0)) != 0 || ccba.error != 0) { 110 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 111 return error; 112 } 113 ds->mdmatab = ccba.maddr; 114 } 115 if (!ds->ddmamap) { 116 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0) 117 return error; 118 } 119 return 0; 120} 121 122void 123ata_dmafree(struct ata_device *atadev) 124{ 125 struct ata_dmastate *ds; 126 127 ds = &atadev->dmastate; 128 if (ds->mdmatab) { 129 bus_dmamap_unload(ds->cdmatag, ds->cdmamap); 130 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 131 ds->mdmatab = 0; 132 ds->cdmamap = NULL; 133 ds->dmatab = NULL; 134 } 135 if (ds->ddmamap) { 136 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap); 137 ds->ddmamap = NULL; 138 } 139 if (ds->cdmatag) { 140 bus_dma_tag_destroy(ds->cdmatag); 141 ds->cdmatag = NULL; 142 } 143 if (ds->ddmatag) { 144 bus_dma_tag_destroy(ds->ddmatag); 145 ds->ddmatag = NULL; 146 } 147} 148 149void 150ata_dmafreetags(struct ata_channel *ch) 151{ 152 153 if (ch->dmatag) { 154 bus_dma_tag_destroy(ch->dmatag); 155 ch->dmatag = NULL; 156 } 157} 158 159static void 160ata_dmacreate(struct ata_device *atadev, int apiomode, int mode) 161{ 162 163 atadev->mode = mode; 164 if (!atadev->channel->dmatag) { 165 if (bus_dma_tag_create(NULL, 1, 0, 166 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 167 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, 168 BUS_SPACE_MAXSIZE_32BIT, 0, 169 &atadev->channel->dmatag)) { 170 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n"); 171 ata_dmainit(atadev, apiomode, -1, -1); 172 } 173 } 174} 175 176void 177ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode) 178{ 179 device_t parent = device_get_parent(atadev->channel->dev); 180 int chiptype = atadev->channel->chiptype; 181 int chiprev = pci_get_revid(parent); 182 int channel = atadev->channel->unit; 183 int device = ATA_DEV(atadev->unit); 184 int devno = (channel << 1) + device; 185 int error; 186 187 /* set our most pessimistic default mode */ 188 atadev->mode = ATA_PIO; 189 190 if (!atadev->channel->r_bmio) 191 return; 192 193 /* if simplex controller, only allow DMA on primary channel */ 194 if (channel == 1) { 195 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT, 196 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 197 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 198 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 199 ATA_BMSTAT_DMA_SIMPLEX) { 200 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 201 return; 202 } 203 } 204 205 /* DMA engine address alignment is usually 1 word (2 bytes) */ 206 atadev->channel->alignment = 0x1; 207 208#if 1 209 if (udmamode > 2 && !atadev->param->hwres_cblid) { 210 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 211 udmamode = 2; 212 } 213#endif 214 switch (chiptype) { 215 216 case 0x24cb8086: /* Intel ICH4 */ 217 case 0x248a8086: /* Intel ICH3 mobile */ 218 case 0x248b8086: /* Intel ICH3 */ 219 case 0x244a8086: /* Intel ICH2 mobile */ 220 case 0x244b8086: /* Intel ICH2 */ 221 if (udmamode >= 5) { 222 int32_t mask48, new48; 223 int16_t word54; 224 225 word54 = pci_read_config(parent, 0x54, 2); 226 if (word54 & (0x10 << devno)) { 227 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 228 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 229 if (bootverbose) 230 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 231 (error) ? "failed" : "success"); 232 if (!error) { 233 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 234 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 235 pci_write_config(parent, 0x48, 236 (pci_read_config(parent, 0x48, 4) & 237 ~mask48) | new48, 4); 238 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 239 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 240 return; 241 } 242 } 243 } 244 /* make sure eventual ATA100 mode from the BIOS is disabled */ 245 pci_write_config(parent, 0x54, 246 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 247 /* FALLTHROUGH */ 248 249 case 0x24118086: /* Intel ICH */ 250 case 0x76018086: /* Intel ICH */ 251 if (udmamode >= 4) { 252 int32_t mask48, new48; 253 int16_t word54; 254 255 word54 = pci_read_config(parent, 0x54, 2); 256 if (word54 & (0x10 << devno)) { 257 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 259 if (bootverbose) 260 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 261 (error) ? "failed" : "success"); 262 if (!error) { 263 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 264 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 265 pci_write_config(parent, 0x48, 266 (pci_read_config(parent, 0x48, 4) & 267 ~mask48) | new48, 4); 268 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 269 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 270 return; 271 } 272 } 273 } 274 /* make sure eventual ATA66 mode from the BIOS is disabled */ 275 pci_write_config(parent, 0x54, 276 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 277 /* FALLTHROUGH */ 278 279 case 0x71118086: /* Intel PIIX4 */ 280 case 0x84CA8086: /* Intel PIIX4 */ 281 case 0x71998086: /* Intel PIIX4e */ 282 case 0x24218086: /* Intel ICH0 */ 283 if (udmamode >= 2) { 284 int32_t mask48, new48; 285 286 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 287 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 288 if (bootverbose) 289 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 290 (error) ? "failed" : "success"); 291 if (!error) { 292 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 293 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 294 pci_write_config(parent, 0x48, 295 (pci_read_config(parent, 0x48, 4) & 296 ~mask48) | new48, 4); 297 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 298 return; 299 } 300 } 301 /* make sure eventual ATA33 mode from the BIOS is disabled */ 302 pci_write_config(parent, 0x48, 303 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 304 /* FALLTHROUGH */ 305 306 case 0x70108086: /* Intel PIIX3 */ 307 if (wdmamode >= 2 && apiomode >= 4) { 308 int32_t mask40, new40, mask44, new44; 309 310 /* if SITRE not set doit for both channels */ 311 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){ 312 new40 = pci_read_config(parent, 0x40, 4); 313 new44 = pci_read_config(parent, 0x44, 4); 314 if (!(new40 & 0x00004000)) { 315 new44 &= ~0x0000000f; 316 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 317 } 318 if (!(new40 & 0x40000000)) { 319 new44 &= ~0x000000f0; 320 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 321 } 322 new40 |= 0x40004000; 323 pci_write_config(parent, 0x40, new40, 4); 324 pci_write_config(parent, 0x44, new44, 4); 325 } 326 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 327 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 328 if (bootverbose) 329 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 330 (error) ? "failed" : "success"); 331 if (!error) { 332 if (device == ATA_MASTER) { 333 mask40 = 0x0000330f; 334 new40 = 0x00002307; 335 mask44 = 0; 336 new44 = 0; 337 } 338 else { 339 mask40 = 0x000000f0; 340 new40 = 0x00000070; 341 mask44 = 0x0000000f; 342 new44 = 0x0000000b; 343 } 344 if (channel) { 345 mask40 <<= 16; 346 new40 <<= 16; 347 mask44 <<= 4; 348 new44 <<= 4; 349 } 350 pci_write_config(parent, 0x40, 351 (pci_read_config(parent, 0x40, 4) & ~mask40)| 352 new40, 4); 353 pci_write_config(parent, 0x44, 354 (pci_read_config(parent, 0x44, 4) & ~mask44)| 355 new44, 4); 356 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 357 return; 358 } 359 } 360 /* we could set PIO mode timings, but we assume the BIOS did that */ 361 break; 362 363 case 0x12308086: /* Intel PIIX */ 364 if (wdmamode >= 2 && apiomode >= 4) { 365 int32_t word40; 366 367 word40 = pci_read_config(parent, 0x40, 4); 368 word40 >>= channel * 16; 369 370 /* Check for timing config usable for DMA on controller */ 371 if (!((word40 & 0x3300) == 0x2300 && 372 ((word40 >> (device ? 4 : 0)) & 1) == 1)) 373 break; 374 375 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 376 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 377 if (bootverbose) 378 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 379 (error) ? "failed" : "success"); 380 if (!error) { 381 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 382 return; 383 } 384 } 385 break; 386 387 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 388 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 389 if (chiprev < 0xc2 && 390 atadev->channel->devices & ATA_ATAPI_MASTER && 391 atadev->channel->devices & ATA_ATAPI_SLAVE) { 392 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 393 break; 394 } 395 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4); 396 if (udmamode >= 5 && chiprev >= 0xc4) { 397 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 398 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 399 if (bootverbose) 400 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 401 (error) ? "failed" : "success"); 402 if (!error) { 403 int32_t word54 = pci_read_config(parent, 0x54, 4); 404 405 pci_write_config(parent, 0x4b, 406 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 407 word54 &= ~(0x000f000f << (devno << 2)); 408 word54 |= (0x000f0005 << (devno << 2)); 409 pci_write_config(parent, 0x54, word54, 4); 410 pci_write_config(parent, 0x53, 411 pci_read_config(parent, 0x53, 1) | 0x03, 1); 412 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 413 return; 414 } 415 } 416 if (udmamode >= 4 && chiprev >= 0xc2) { 417 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 418 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 419 if (bootverbose) 420 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 421 (error) ? "failed" : "success"); 422 if (!error) { 423 int32_t word54 = pci_read_config(parent, 0x54, 4); 424 425 pci_write_config(parent, 0x4b, 426 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 427 word54 &= ~(0x000f000f << (devno << 2)); 428 word54 |= (0x00080005 << (devno << 2)); 429 pci_write_config(parent, 0x54, word54, 4); 430 pci_write_config(parent, 0x53, 431 pci_read_config(parent, 0x53, 1) | 0x03, 1); 432 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 433 return; 434 } 435 } 436 if (udmamode >= 2 && chiprev >= 0x20) { 437 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 438 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 439 if (bootverbose) 440 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 441 (error) ? "failed" : "success"); 442 if (!error) { 443 int32_t word54 = pci_read_config(parent, 0x54, 4); 444 445 word54 &= ~(0x000f000f << (devno << 2)); 446 word54 |= (0x000a0005 << (devno << 2)); 447 pci_write_config(parent, 0x54, word54, 4); 448 pci_write_config(parent, 0x53, 449 pci_read_config(parent, 0x53, 1) | 0x03, 1); 450 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 451 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 452 return; 453 } 454 } 455 456 /* make sure eventual UDMA mode from the BIOS is disabled */ 457 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 458 ~(0x0008 << (devno << 2)), 2); 459 460 if (wdmamode >= 2 && apiomode >= 4) { 461 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 462 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 463 if (bootverbose) 464 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 465 (error) ? "failed" : "success"); 466 if (!error) { 467 pci_write_config(parent, 0x53, 468 pci_read_config(parent, 0x53, 1) | 0x03, 1); 469 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 470 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 471 return; 472 } 473 } 474 pci_write_config(parent, 0x53, 475 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 476 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 477 ATA_PIO0 + apiomode, 478 ATA_C_F_SETXFER, ATA_WAIT_READY); 479 if (bootverbose) 480 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n", 481 (error) ? "failed" : "success", 482 (apiomode >= 0) ? apiomode : 0); 483 if (!error) { 484 int32_t word54 = pci_read_config(parent, 0x54, 4); 485 int32_t timing; 486 487 switch(ATA_PIO0 + apiomode) { 488 case ATA_PIO0: timing = 0x006d0003; 489 case ATA_PIO1: timing = 0x00580002; 490 case ATA_PIO2: timing = 0x00440001; 491 case ATA_PIO3: timing = 0x00330001; 492 case ATA_PIO4: timing = 0x00310001; 493 default: timing = 0x006d0003; 494 } 495 pci_write_config(parent, 0x58 + (channel << 2), timing, 4); 496 word54 &= ~(0x000f000f << (devno << 2)); 497 word54 |= (0x00000004 << (devno << 2)); 498 pci_write_config(parent, 0x54, word54, 4); 499 atadev->mode = ATA_PIO0 + apiomode; 500 return; 501 } 502 break; 503 504 case 0x01bc10de: /* nVIDIA nForce */ 505 case 0x74411022: /* AMD 768 */ 506 case 0x74111022: /* AMD 766 */ 507 case 0x74091022: /* AMD 756 */ 508 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */ 509 { 510 int via_modes[5][7] = { 511 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 512 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 513 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 514 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 515 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0x00 }}; /* AMD/nVIDIA */ 516 int *reg_val = NULL; 517 char *chip = "VIA"; 518 519 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */ 520 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */ 521 udmamode = imin(udmamode, 6); 522 reg_val = via_modes[3]; 523 } 524 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 525 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 526 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 527 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 528 udmamode = imin(udmamode, 5); 529 reg_val = via_modes[2]; 530 } 531 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 532 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 533 udmamode = imin(udmamode, 4); 534 reg_val = via_modes[1]; 535 } 536 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 537 udmamode = imin(udmamode, 2); 538 reg_val = via_modes[1]; 539 } 540 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 541 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 542 udmamode = imin(udmamode, 2); 543 reg_val = via_modes[0]; 544 } 545 else if (chiptype == 0x74411022 || /* AMD 768 */ 546 chiptype == 0x74111022) { /* AMD 766 */ 547 udmamode = imin(udmamode, 5); 548 reg_val = via_modes[4]; 549 chip = "AMD"; 550 } 551 else if (chiptype == 0x74091022) { /* AMD 756 */ 552 udmamode = imin(udmamode, 4); 553 reg_val = via_modes[4]; 554 chip = "AMD"; 555 } 556 else if (chiptype == 0x01bc10de) { /* nVIDIA */ 557 udmamode = imin(udmamode, 5); 558 reg_val = via_modes[4]; 559 chip = "nVIDIA"; 560 } 561 else 562 udmamode = 0; 563 564 if (udmamode >= 6) { 565 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 566 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 567 if (bootverbose) 568 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n", 569 (error) ? "failed" : "success", chip); 570 if (!error) { 571 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 572 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 573 return; 574 } 575 } 576 if (udmamode >= 5) { 577 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 578 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 579 if (bootverbose) 580 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n", 581 (error) ? "failed" : "success", chip); 582 if (!error) { 583 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 584 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 585 return; 586 } 587 } 588 if (udmamode >= 4) { 589 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 590 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n", 593 (error) ? "failed" : "success", chip); 594 if (!error) { 595 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 596 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 597 return; 598 } 599 } 600 if (udmamode >= 2) { 601 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 602 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 603 if (bootverbose) 604 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n", 605 (error) ? "failed" : "success", chip); 606 if (!error) { 607 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 608 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 609 return; 610 } 611 } 612 if (wdmamode >= 2 && apiomode >= 4) { 613 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 614 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 615 if (bootverbose) 616 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 617 (error) ? "failed" : "success", chip); 618 if (!error) { 619 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 620 pci_write_config(parent, 0x4b - devno, 0x31, 1); 621 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 622 return; 623 } 624 } 625 } 626 /* we could set PIO mode timings, but we assume the BIOS did that */ 627 break; 628 629 case 0x55131039: /* SiS 5591 */ 630 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 631 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 632 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 633 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 634 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 635 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 636 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 637 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 638 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 639 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 640 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 641 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 642 int8_t reg = 0x40 + (devno << 1); 643 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 644 645 if (udmamode >= 5) { 646 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 647 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 648 if (bootverbose) 649 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 650 (error) ? "failed" : "success"); 651 if (!error) { 652 pci_write_config(parent, reg, val | 0x8000, 2); 653 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 654 return; 655 } 656 } 657 if (udmamode >= 4) { 658 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 659 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 660 if (bootverbose) 661 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 662 (error) ? "failed" : "success"); 663 if (!error) { 664 pci_write_config(parent, reg, val | 0x9000, 2); 665 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 666 return; 667 } 668 } 669 if (udmamode >= 2) { 670 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 671 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 672 if (bootverbose) 673 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 674 (error) ? "failed" : "success"); 675 if (!error) { 676 pci_write_config(parent, reg, val | 0xb000, 2); 677 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 678 return; 679 } 680 } 681 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 682 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 683 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 684 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 685 int8_t reg = 0x40 + (devno << 1); 686 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 687 688 if (udmamode >= 4) { 689 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 690 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 691 if (bootverbose) 692 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 693 (error) ? "failed" : "success"); 694 if (!error) { 695 pci_write_config(parent, reg, val | 0x9000, 2); 696 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 697 return; 698 } 699 } 700 if (udmamode >= 2) { 701 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 702 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 703 if (bootverbose) 704 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 705 (error) ? "failed" : "success"); 706 if (!error) { 707 pci_write_config(parent, reg, val | 0xa000, 2); 708 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 709 return; 710 } 711 } 712 } else if (udmamode >= 2 && chiprev > 0xc1) { 713 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 714 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 715 if (bootverbose) 716 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 717 (error) ? "failed" : "success"); 718 if (!error) { 719 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 720 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 721 return; 722 } 723 } 724 if (wdmamode >=2 && apiomode >= 4) { 725 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 726 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 727 if (bootverbose) 728 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 729 (error) ? "failed" : "success"); 730 if (!error) { 731 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 732 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 733 return; 734 } 735 } 736 /* we could set PIO mode timings, but we assume the BIOS did that */ 737 break; 738 739 case 0x06801095: /* Sil 0680 ATA133 controller */ 740 { 741 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10); 742 u_int8_t uval = pci_read_config(parent, ureg, 1); 743 u_int8_t mreg = channel ? 0x84 : 0x80; 744 u_int8_t mask = device ? 0x30 : 0x03; 745 u_int8_t mode = pci_read_config(parent, mreg, 1); 746 747 /* enable UDMA mode */ 748 pci_write_config(parent, mreg, 749 (mode & ~mask) | (device ? 0x30 : 0x03), 1); 750 if (udmamode >= 6) { 751 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 752 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 753 if (bootverbose) 754 ata_prtdev(atadev, "%s setting UDMA6 on Sil chip\n", 755 (error) ? "failed" : "success"); 756 if (!error) { 757 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1); 758 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 759 return; 760 } 761 } 762 if (udmamode >= 5) { 763 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 764 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 765 if (bootverbose) 766 ata_prtdev(atadev, "%s setting UDMA5 on Sil chip\n", 767 (error) ? "failed" : "success"); 768 if (!error) { 769 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1); 770 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 771 return; 772 } 773 } 774 if (udmamode >= 4) { 775 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 776 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 777 if (bootverbose) 778 ata_prtdev(atadev, "%s setting UDMA4 on Sil chip\n", 779 (error) ? "failed" : "success"); 780 if (!error) { 781 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1); 782 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 783 return; 784 } 785 } 786 if (udmamode >= 2) { 787 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 788 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 789 if (bootverbose) 790 ata_prtdev(atadev, "%s setting UDMA2 on Sil chip\n", 791 (error) ? "failed" : "success"); 792 if (!error) { 793 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1); 794 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 795 return; 796 } 797 } 798 799 /* disable UDMA mode and enable WDMA mode */ 800 pci_write_config(parent, mreg, 801 (mode & ~mask) | (device ? 0x20 : 0x02), 1); 802 if (wdmamode >= 2 && apiomode >= 4) { 803 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 804 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 805 if (bootverbose) 806 ata_prtdev(atadev, "%s setting WDMA2 on Sil chip\n", 807 (error) ? "failed" : "success"); 808 if (!error) { 809 pci_write_config(parent, ureg - 0x4, 0x10c1, 2); 810 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 811 return; 812 } 813 } 814 815 /* restore PIO mode */ 816 pci_write_config(parent, mreg, mode, 1); 817 } 818 /* we could set PIO mode timings, but we assume the BIOS did that */ 819 break; 820 821 case 0x06491095: /* CMD 649 ATA100 controller */ 822 if (udmamode >= 5) { 823 u_int8_t umode; 824 825 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 826 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 827 if (bootverbose) 828 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 829 (error) ? "failed" : "success"); 830 if (!error) { 831 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 832 umode &= ~(device ? 0xca : 0x35); 833 umode |= (device ? 0x0a : 0x05); 834 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 835 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 836 return; 837 } 838 } 839 /* FALLTHROUGH */ 840 841 case 0x06481095: /* CMD 648 ATA66 controller */ 842 if (udmamode >= 4) { 843 u_int8_t umode; 844 845 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 846 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 847 if (bootverbose) 848 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 849 (error) ? "failed" : "success"); 850 if (!error) { 851 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 852 umode &= ~(device ? 0xca : 0x35); 853 umode |= (device ? 0x4a : 0x15); 854 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 855 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 856 return; 857 } 858 } 859 if (udmamode >= 2) { 860 u_int8_t umode; 861 862 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 863 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 864 if (bootverbose) 865 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 866 (error) ? "failed" : "success"); 867 if (!error) { 868 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 869 umode &= ~(device ? 0xca : 0x35); 870 umode |= (device ? 0x42 : 0x11); 871 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 872 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 873 return; 874 } 875 } 876 /* make sure eventual UDMA mode from the BIOS is disabled */ 877 pci_write_config(parent, channel ? 0x7b : 0x73, 878 pci_read_config(parent, channel ? 0x7b : 0x73, 1) & 879 ~(device ? 0xca : 0x53), 1); 880 /* FALLTHROUGH */ 881 882 case 0x06461095: /* CMD 646 ATA controller */ 883 if (wdmamode >= 2 && apiomode >= 4) { 884 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 885 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 886 if (bootverbose) 887 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 888 error ? "failed" : "success"); 889 if (!error) { 890 int32_t offset = (devno < 3) ? (devno << 1) : 7; 891 892 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 893 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 894 return; 895 } 896 } 897 /* we could set PIO mode timings, but we assume the BIOS did that */ 898 break; 899 900 case 0xc6931080: /* Cypress 82c693 ATA controller */ 901 if (wdmamode >= 2 && apiomode >= 4) { 902 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 903 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 904 if (bootverbose) 905 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 906 error ? "failed" : "success"); 907 if (!error) { 908 pci_write_config(atadev->channel->dev, 909 channel ? 0x4e:0x4c, 0x2020, 2); 910 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 911 return; 912 } 913 } 914 /* we could set PIO mode timings, but we assume the BIOS did that */ 915 break; 916 917 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 918 atadev->channel->alignment = 0xf; 919 if (udmamode >= 2) { 920 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 921 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 922 if (bootverbose) 923 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 924 (error) ? "failed" : "success"); 925 if (!error) { 926 cyrix_timing(atadev, devno, ATA_UDMA2); 927 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 928 return; 929 } 930 } 931 if (wdmamode >= 2 && apiomode >= 4) { 932 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 933 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 934 if (bootverbose) 935 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 936 (error) ? "failed" : "success"); 937 if (!error) { 938 cyrix_timing(atadev, devno, ATA_WDMA2); 939 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 940 return; 941 } 942 } 943 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 944 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 945 ATA_WAIT_READY); 946 if (bootverbose) 947 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 948 (error) ? "failed" : "success", 949 ata_mode2str(ATA_PIO0 + apiomode)); 950 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode); 951 atadev->mode = ATA_PIO0 + apiomode; 952 return; 953 954 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 955 if (udmamode >= 5 && chiprev >= 0x92) { 956 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 957 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 958 if (bootverbose) 959 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 960 (error) ? "failed" : "success"); 961 if (!error) { 962 u_int16_t reg56; 963 964 pci_write_config(parent, 0x54, 965 pci_read_config(parent, 0x54, 1) | 966 (0x01 << devno), 1); 967 reg56 = pci_read_config(parent, 0x56, 2); 968 reg56 &= ~(0xf << (devno * 4)); 969 reg56 |= (0x5 << (devno * 4)); 970 pci_write_config(parent, 0x56, reg56, 2); 971 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 972 return; 973 } 974 } 975 if (udmamode >= 4) { 976 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 977 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 978 if (bootverbose) 979 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 980 (error) ? "failed" : "success"); 981 if (!error) { 982 u_int16_t reg56; 983 984 pci_write_config(parent, 0x54, 985 pci_read_config(parent, 0x54, 1) | 986 (0x01 << devno), 1); 987 reg56 = pci_read_config(parent, 0x56, 2); 988 reg56 &= ~(0xf << (devno * 4)); 989 reg56 |= (0x4 << (devno * 4)); 990 pci_write_config(parent, 0x56, reg56, 2); 991 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 992 return; 993 } 994 } 995 /* FALLTHROUGH */ 996 997 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 998 if (udmamode >= 2) { 999 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1000 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1001 if (bootverbose) 1002 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 1003 (error) ? "failed" : "success"); 1004 if (!error) { 1005 u_int16_t reg56; 1006 1007 pci_write_config(parent, 0x54, 1008 pci_read_config(parent, 0x54, 1) | 1009 (0x01 << devno), 1); 1010 reg56 = pci_read_config(parent, 0x56, 2); 1011 reg56 &= ~(0xf << (devno * 4)); 1012 reg56 |= (0x2 << (devno * 4)); 1013 pci_write_config(parent, 0x56, reg56, 2); 1014 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1015 return; 1016 } 1017 } 1018 if (wdmamode >= 2 && apiomode >= 4) { 1019 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1020 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1021 if (bootverbose) 1022 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 1023 (error) ? "failed" : "success"); 1024 if (!error) { 1025 int offset = devno ^ 0x01; 1026 int word44 = pci_read_config(parent, 0x44, 4); 1027 1028 pci_write_config(parent, 0x54, 1029 pci_read_config(parent, 0x54, 1) & 1030 ~(0x01 << devno), 1); 1031 word44 &= ~(0xff << (offset << 8)); 1032 word44 |= (0x20 << (offset << 8)); 1033 pci_write_config(parent, 0x44, 0x20, 4); 1034 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1035 return; 1036 } 1037 } 1038 /* we could set PIO mode timings, but we assume the BIOS did that */ 1039 break; 1040 1041 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 1042 case 0x5275105a: /* Promise TX2 ATA133 controllers */ 1043 case 0x6269105a: /* Promise TX2 ATA133 controllers */ 1044 case 0x7275105a: /* Promise TX2 ATA133 controllers */ 1045 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1046 if (udmamode >= 6 && 1047 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1048 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1049 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1050 if (bootverbose) 1051 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 1052 (error) ? "failed" : "success"); 1053 if (!error) { 1054 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1055 return; 1056 } 1057 } 1058 /* FALLTHROUGH */ 1059 1060 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 1061 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 1062 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1063 if (udmamode >= 5 && 1064 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1065 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1066 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1067 if (bootverbose) 1068 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1069 (error) ? "failed" : "success"); 1070 if (!error) { 1071 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1072 return; 1073 } 1074 } 1075 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1076 if (udmamode >= 4 && 1077 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1078 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1079 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1080 if (bootverbose) 1081 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1082 (error) ? "failed" : "success"); 1083 if (!error) { 1084 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1085 return; 1086 } 1087 } 1088 if (udmamode >= 2) { 1089 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1090 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1091 if (bootverbose) 1092 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 1093 (error) ? "failed" : "success"); 1094 if (!error) { 1095 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1096 return; 1097 } 1098 } 1099 if (wdmamode >= 2 && apiomode >= 4) { 1100 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1101 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1102 if (bootverbose) 1103 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1104 (error) ? "failed" : "success"); 1105 if (!error) { 1106 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1107 return; 1108 } 1109 } 1110 break; 1111 1112 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 1113 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 1114 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 1115 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1116 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1117 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1118 if (bootverbose) 1119 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1120 (error) ? "failed" : "success"); 1121 if (!error) { 1122 promise_timing(atadev, devno, ATA_UDMA5); 1123 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1124 return; 1125 } 1126 } 1127 /* FALLTHROUGH */ 1128 1129 case 0x0d38105a: /* Promise FastTrak 66 controllers */ 1130 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 1131 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 1132 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1133 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1134 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1135 if (bootverbose) 1136 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1137 (error) ? "failed" : "success"); 1138 if (!error) { 1139 promise_timing(atadev, devno, ATA_UDMA4); 1140 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1141 return; 1142 } 1143 } 1144 /* FALLTHROUGH */ 1145 1146 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 1147 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1148 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1149 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1150 if (bootverbose) 1151 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 1152 (error) ? "failed" : "success"); 1153 if (!error) { 1154 promise_timing(atadev, devno, ATA_UDMA2); 1155 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1156 return; 1157 } 1158 } 1159 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1160 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1161 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1162 if (bootverbose) 1163 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1164 (error) ? "failed" : "success"); 1165 if (!error) { 1166 promise_timing(atadev, devno, ATA_WDMA2); 1167 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1168 return; 1169 } 1170 } 1171 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1172 ATA_PIO0 + apiomode, 1173 ATA_C_F_SETXFER, ATA_WAIT_READY); 1174 if (bootverbose) 1175 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 1176 (error) ? "failed" : "success", 1177 (apiomode >= 0) ? apiomode : 0); 1178 promise_timing(atadev, devno, ATA_PIO0 + apiomode); 1179 atadev->mode = ATA_PIO0 + apiomode; 1180 return; 1181 1182 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 1183 case 0x00051103: /* HighPoint HPT372 controllers */ 1184 case 0x00081103: /* HighPoint HPT374 controllers */ 1185 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) && 1186 ((chiptype == 0x00041103 && chiprev >= 0x05) || 1187 (chiptype == 0x00051103 && chiprev >= 0x01) || 1188 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1189 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1190 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1191 if (bootverbose) 1192 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 1193 (error) ? "failed" : "success"); 1194 if (!error) { 1195 hpt_timing(atadev, devno, ATA_UDMA6); 1196 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1197 return; 1198 } 1199 } 1200 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) && 1201 ((chiptype == 0x00041103 && chiprev >= 0x03) || 1202 (chiptype == 0x00051103 && chiprev >= 0x01) || 1203 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1204 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1205 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1206 if (bootverbose) 1207 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 1208 (error) ? "failed" : "success"); 1209 if (!error) { 1210 hpt_timing(atadev, devno, ATA_UDMA5); 1211 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1212 return; 1213 } 1214 } 1215 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) { 1216 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1217 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1218 if (bootverbose) 1219 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1220 (error) ? "failed" : "success"); 1221 if (!error) { 1222 hpt_timing(atadev, devno, ATA_UDMA4); 1223 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1224 return; 1225 } 1226 } 1227 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1228 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1229 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1230 if (bootverbose) 1231 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1232 (error) ? "failed" : "success"); 1233 if (!error) { 1234 hpt_timing(atadev, devno, ATA_UDMA2); 1235 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1236 return; 1237 } 1238 } 1239 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1240 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1241 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1242 if (bootverbose) 1243 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1244 (error) ? "failed" : "success"); 1245 if (!error) { 1246 hpt_timing(atadev, devno, ATA_WDMA2); 1247 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1248 return; 1249 } 1250 } 1251 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1252 ATA_PIO0 + apiomode, 1253 ATA_C_F_SETXFER, ATA_WAIT_READY); 1254 if (bootverbose) 1255 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1256 (error) ? "failed" : "success", 1257 (apiomode >= 0) ? apiomode : 0); 1258 hpt_timing(atadev, devno, ATA_PIO0 + apiomode); 1259 atadev->mode = ATA_PIO0 + apiomode; 1260 return; 1261 1262 case 0x00091191: /* Acard ATP865R controller */ 1263 case 0x00081191: /* Acard ATP865 controller */ 1264 if (ATAPI_DEVICE(atadev)) 1265 break; 1266 if (udmamode >= 6) { 1267 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1268 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1269 if (bootverbose) 1270 ata_prtdev(atadev, "%s setting up UDMA6 mode on Acard chip\n", 1271 (error) ? "failed" : "success"); 1272 if (!error) { 1273 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1274 1275 reg44 &= ~(0x000f << (devno << 2)); 1276 reg44 |= (0x0007 << (devno << 2)); 1277 pci_write_config(parent, 0x44, reg44, 2); 1278 pci_write_config(parent, 0x4a, 0xa6, 1); 1279 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1280 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1281 return; 1282 } 1283 } 1284 if (udmamode >= 5) { 1285 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1286 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1287 if (bootverbose) 1288 ata_prtdev(atadev, "%s setting up UDMA5 mode on Acard chip\n", 1289 (error) ? "failed" : "success"); 1290 if (!error) { 1291 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1292 1293 reg44 &= ~(0x000f << (devno << 2)); 1294 reg44 |= (0x0006 << (devno << 2)); 1295 pci_write_config(parent, 0x44, reg44, 2); 1296 pci_write_config(parent, 0x4a, 0xa6, 1); 1297 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1298 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1299 return; 1300 } 1301 } 1302 /* FALLTHROUGH */ 1303 1304 case 0x00071191: /* Acard ATP860R controller */ 1305 case 0x00061191: /* Acard ATP860 controller */ 1306 if (ATAPI_DEVICE(atadev)) 1307 break; 1308 if (udmamode >= 4) { 1309 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1310 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1311 if (bootverbose) 1312 ata_prtdev(atadev, "%s setting up UDMA4 mode on Acard chip\n", 1313 (error) ? "failed" : "success"); 1314 if (!error) { 1315 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1316 1317 reg44 &= ~(0x000f << (devno << 2)); 1318 reg44 |= (0x0005 << (devno << 2)); 1319 pci_write_config(parent, 0x44, reg44, 2); 1320 pci_write_config(parent, 0x4a, 0xa6, 1); 1321 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1322 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1323 return; 1324 } 1325 } 1326 if (udmamode >= 2) { 1327 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1328 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1329 if (bootverbose) 1330 ata_prtdev(atadev, "%s setting up UDMA2 mode on Acard chip\n", 1331 (error) ? "failed" : "success"); 1332 if (!error) { 1333 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1334 1335 reg44 &= ~(0x000f << (devno << 2)); 1336 reg44 |= (0x0003 << (devno << 2)); 1337 pci_write_config(parent, 0x44, reg44, 2); 1338 pci_write_config(parent, 0x4a, 0xa6, 1); 1339 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1340 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1341 return; 1342 } 1343 } 1344 if (wdmamode >= 2 && apiomode >= 4) { 1345 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1346 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1347 if (bootverbose) 1348 ata_prtdev(atadev, "%s setting up WDMA2 mode on Acard chip\n", 1349 (error) ? "failed" : "success"); 1350 if (!error) { 1351 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1352 1353 reg44 &= ~(0x000f << (devno << 2)); 1354 pci_write_config(parent, 0x44, reg44, 2); 1355 pci_write_config(parent, 0x4a, 0xa6, 1); 1356 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1357 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1358 return; 1359 } 1360 } 1361 /* we could set PIO mode timings, but we assume the BIOS did that */ 1362 break; 1363 1364 case 0x00051191: /* Acard ATP850UF controller */ 1365 if (ATAPI_DEVICE(atadev)) 1366 break; 1367 if (udmamode >= 2) { 1368 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1369 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1370 if (bootverbose) 1371 ata_prtdev(atadev, "%s setting up UDMA2 mode on Acard chip\n", 1372 (error) ? "failed" : "success"); 1373 if (!error) { 1374 u_int8_t reg54 = pci_read_config(parent, 0x54, 1); 1375 1376 reg54 |= (0x03 << (devno << 1)); 1377 pci_write_config(parent, 0x54, reg54, 1); 1378 pci_write_config(parent, 0x4a, 0xa6, 1); 1379 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 1380 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1381 return; 1382 } 1383 } 1384 if (wdmamode >= 2 && apiomode >= 4) { 1385 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1386 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1387 if (bootverbose) 1388 ata_prtdev(atadev, "%s setting up WDMA2 mode on Acard chip\n", 1389 (error) ? "failed" : "success"); 1390 if (!error) { 1391 u_int8_t reg54 = pci_read_config(parent, 0x54, 1); 1392 1393 reg54 &= ~(0x03 << (devno << 1)); 1394 pci_write_config(parent, 0x54, reg54, 1); 1395 pci_write_config(parent, 0x4a, 0xa6, 1); 1396 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 1397 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1398 return; 1399 } 1400 } 1401 /* we could set PIO mode timings, but we assume the BIOS did that */ 1402 break; 1403 1404 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1405 if (wdmamode >= 0 && 1406 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1407 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) 1408 ata_dmacreate(atadev, apiomode, ATA_DMA); 1409 else 1410 atadev->mode = ATA_PIO; 1411 return; 1412 1413 default: /* unknown controller chip */ 1414 /* better not try generic DMA on ATAPI devices it almost never works */ 1415 if (ATAPI_DEVICE(atadev)) 1416 break; 1417 1418 /* if controller says its setup for DMA take the easy way out */ 1419 /* the downside is we dont know what DMA mode we are in */ 1420 if ((udmamode >= 0 || wdmamode >= 2) && 1421 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1422 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 1423 ata_dmacreate(atadev, apiomode, ATA_DMA); 1424 return; 1425 } 1426 1427 /* well, we have no support for this, but try anyways */ 1428 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) { 1429 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1430 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1431 if (bootverbose) 1432 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1433 (error) ? "failed" : "success"); 1434 if (!error) { 1435 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1436 return; 1437 } 1438 } 1439 } 1440 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1441 ATA_C_F_SETXFER, ATA_WAIT_READY); 1442 if (bootverbose) 1443 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1444 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1445 if (!error) 1446 atadev->mode = ATA_PIO0 + apiomode; 1447 else { 1448 if (bootverbose) 1449 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1450 atadev->mode = ATA_PIO; 1451 } 1452} 1453 1454struct ata_dmasetup_data_cb_args { 1455 struct ata_dmaentry *dmatab; 1456 int error; 1457}; 1458 1459static void 1460ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1461{ 1462 struct ata_dmasetup_data_cb_args *cba = 1463 (struct ata_dmasetup_data_cb_args *)xsc; 1464 bus_size_t cnt; 1465 u_int32_t lastcount; 1466 int i, j; 1467 1468 cba->error = error; 1469 if (error != 0) 1470 return; 1471 lastcount = j = 0; 1472 for (i = 0; i < nsegs; i++) { 1473 /* 1474 * A maximum segment size was specified for bus_dma_tag_create, but 1475 * some busdma code does not seem to honor this, so fix up if needed. 1476 */ 1477 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { 1478 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); 1479 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; 1480 cba->dmatab[j].count = htole32(lastcount); 1481 } 1482 } 1483 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); 1484} 1485 1486int 1487ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) 1488{ 1489 struct ata_channel *ch = atadev->channel; 1490 1491 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1492 ata_prtdev(atadev, "non aligned DMA transfer attempted\n"); 1493 return -1; 1494 } 1495 1496 if (!count) { 1497 ata_prtdev(atadev, "zero length DMA transfer attempted\n"); 1498 return -1; 1499 } 1500 return 0; 1501} 1502 1503int 1504ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir) 1505{ 1506 struct ata_channel *ch = atadev->channel; 1507 struct ata_dmastate *ds = &atadev->dmastate; 1508 struct ata_dmasetup_data_cb_args cba; 1509 1510 if (ds->flags & ATA_DS_ACTIVE) 1511 panic("ata_dmasetup: transfer active on this device!"); 1512 1513 switch(ch->chiptype) { 1514 case 0x0d38105a: /* Promise Fasttrak 66 */ 1515 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1516 case 0x0d30105a: /* Promise OEM ATA 100 */ 1517 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1518 ATA_OUTB(ch->r_bmio, 0x11, 1519 ATA_INB(ch->r_bmio, 0x11) | (atadev->unit ? 0x08 : 0x02)); 1520 1521 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20), 1522 (dir ? 0x05000000 : 0x06000000) | (count >> 1)); 1523 break; 1524 } 1525 1526 cba.dmatab = ds->dmatab; 1527 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE); 1528 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count, 1529 ata_dmasetupd_cb, &cba, 0) || cba.error) 1530 return -1; 1531 1532 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE); 1533 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD : 1534 BUS_DMASYNC_PREWRITE); 1535 1536 ch->flags |= ATA_DMA_ACTIVE; 1537 ds->flags = dir ? (ATA_DS_ACTIVE | ATA_DS_READ) : ATA_DS_ACTIVE; 1538 1539 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab); 1540 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1541 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1542 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1543 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1544 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1545 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1546 return 0; 1547} 1548 1549int 1550ata_dmadone(struct ata_device *atadev) 1551{ 1552 struct ata_channel *ch = atadev->channel; 1553 struct ata_dmastate *ds = &atadev->dmastate; 1554 int error; 1555 1556 switch(ch->chiptype) { 1557 case 0x0d38105a: /* Promise Fasttrak 66 */ 1558 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1559 case 0x0d30105a: /* Promise OEM ATA 100 */ 1560 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1561 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20), 0); 1562 ATA_OUTB(ch->r_bmio, 0x11, 1563 ATA_INB(ch->r_bmio, 0x11) & ~(atadev->unit ? 0x08 : 0x02)); 1564 break; 1565 } 1566 1567 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ? 1568 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1569 bus_dmamap_unload(ds->ddmatag, ds->ddmamap); 1570 1571 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1572 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1573 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1574 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1575 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1576 ch->flags &= ~ATA_DMA_ACTIVE; 1577 ds->flags = 0; 1578 return (error & ATA_BMSTAT_MASK); 1579} 1580 1581int 1582ata_dmastatus(struct ata_channel *ch) 1583{ 1584 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1585} 1586 1587static void 1588cyrix_timing(struct ata_device *atadev, int devno, int mode) 1589{ 1590 u_int32_t reg20 = 0x0000e132; 1591 u_int32_t reg24 = 0x00017771; 1592 1593 switch (mode) { 1594 case ATA_PIO0: reg20 = 0x0000e132; break; 1595 case ATA_PIO1: reg20 = 0x00018121; break; 1596 case ATA_PIO2: reg20 = 0x00024020; break; 1597 case ATA_PIO3: reg20 = 0x00032010; break; 1598 case ATA_PIO4: reg20 = 0x00040010; break; 1599 case ATA_WDMA2: reg24 = 0x00002020; break; 1600 case ATA_UDMA2: reg24 = 0x00911030; break; 1601 } 1602 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20); 1603 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24); 1604} 1605 1606static void 1607promise_timing(struct ata_device *atadev, int devno, int mode) 1608{ 1609 u_int32_t timing = 0; 1610 /* XXX: Endianess */ 1611 struct promise_timing { 1612 u_int8_t pa:4; 1613 u_int8_t prefetch:1; 1614 u_int8_t iordy:1; 1615 u_int8_t errdy:1; 1616 u_int8_t syncin:1; 1617 u_int8_t pb:5; 1618 u_int8_t mb:3; 1619 u_int8_t mc:4; 1620 u_int8_t dmaw:1; 1621 u_int8_t dmar:1; 1622 u_int8_t iordyp:1; 1623 u_int8_t dmarqp:1; 1624 u_int8_t reserved:8; 1625 } *t = (struct promise_timing*)&timing; 1626 1627 t->iordy = 1; t->iordyp = 1; 1628 if (mode >= ATA_DMA) { 1629 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1630 } 1631 1632 switch (atadev->channel->chiptype) { 1633 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1634 switch (mode) { 1635 default: 1636 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1637 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1638 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1639 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1640 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1641 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1642 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1643 } 1644 break; 1645 1646 case 0x0d38105a: /* Promise Fasttrak 66 */ 1647 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1648 case 0x0d30105a: /* Promise OEM ATA 100 */ 1649 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1650 switch (mode) { 1651 default: 1652 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1653 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1654 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1655 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1656 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1657 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1658 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1659 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1660 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1661 } 1662 break; 1663 } 1664 pci_write_config(device_get_parent(atadev->channel->dev), 1665 0x60 + (devno << 2), timing, 4); 1666} 1667 1668static void 1669hpt_timing(struct ata_device *atadev, int devno, int mode) 1670{ 1671 device_t parent = device_get_parent(atadev->channel->dev); 1672 u_int32_t chiptype = atadev->channel->chiptype; 1673 int chiprev = pci_get_revid(parent); 1674 u_int32_t timing; 1675 1676 if (chiptype == 0x00081103 && chiprev >= 0x07) { 1677 switch (mode) { /* HPT374 */ 1678 case ATA_PIO0: timing = 0x0ac1f48a; break; 1679 case ATA_PIO1: timing = 0x0ac1f465; break; 1680 case ATA_PIO2: timing = 0x0a81f454; break; 1681 case ATA_PIO3: timing = 0x0a81f443; break; 1682 case ATA_PIO4: timing = 0x0a81f442; break; 1683 case ATA_WDMA2: timing = 0x22808242; break; 1684 case ATA_UDMA2: timing = 0x120c8242; break; 1685 case ATA_UDMA4: timing = 0x12ac8242; break; 1686 case ATA_UDMA5: timing = 0x12848242; break; 1687 case ATA_UDMA6: timing = 0x12808242; break; 1688 default: timing = 0x0d029d5e; 1689 } 1690 } 1691 else if ((chiptype == 0x00041103 && chiprev >= 0x05) || 1692 (chiptype == 0x00051103 && chiprev >= 0x01)) { 1693 switch (mode) { /* HPT372 */ 1694 case ATA_PIO0: timing = 0x0d029d5e; break; 1695 case ATA_PIO1: timing = 0x0d029d26; break; 1696 case ATA_PIO2: timing = 0x0c829ca6; break; 1697 case ATA_PIO3: timing = 0x0c829c84; break; 1698 case ATA_PIO4: timing = 0x0c829c62; break; 1699 case ATA_WDMA2: timing = 0x2c829262; break; 1700 case ATA_UDMA2: timing = 0x1c91dc62; break; 1701 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1702 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1703 case ATA_UDMA6: timing = 0x1c81dc62; break; 1704 default: timing = 0x0d029d5e; 1705 } 1706 } 1707 else if (chiptype == 0x00041103 && chiprev >= 0x03) { 1708 switch (mode) { /* HPT370 */ 1709 case ATA_PIO0: timing = 0x06914e57; break; 1710 case ATA_PIO1: timing = 0x06914e43; break; 1711 case ATA_PIO2: timing = 0x06514e33; break; 1712 case ATA_PIO3: timing = 0x06514e22; break; 1713 case ATA_PIO4: timing = 0x06514e21; break; 1714 case ATA_WDMA2: timing = 0x26514e21; break; 1715 case ATA_UDMA2: timing = 0x16494e31; break; 1716 case ATA_UDMA4: timing = 0x16454e31; break; 1717 case ATA_UDMA5: timing = 0x16454e31; break; 1718 default: timing = 0x06514e57; 1719 } 1720 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1721 } 1722 else { /* HPT36[68] */ 1723 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1724 case 0x85: /* 25Mhz */ 1725 switch (mode) { 1726 case ATA_PIO0: timing = 0x40d08585; break; 1727 case ATA_PIO1: timing = 0x40d08572; break; 1728 case ATA_PIO2: timing = 0x40ca8542; break; 1729 case ATA_PIO3: timing = 0x40ca8532; break; 1730 case ATA_PIO4: timing = 0x40ca8521; break; 1731 case ATA_WDMA2: timing = 0x20ca8521; break; 1732 case ATA_UDMA2: timing = 0x10cf8521; break; 1733 case ATA_UDMA4: timing = 0x10c98521; break; 1734 default: timing = 0x01208585; 1735 } 1736 break; 1737 default: 1738 case 0xa7: /* 33MHz */ 1739 switch (mode) { 1740 case ATA_PIO0: timing = 0x40d0a7aa; break; 1741 case ATA_PIO1: timing = 0x40d0a7a3; break; 1742 case ATA_PIO2: timing = 0x40d0a753; break; 1743 case ATA_PIO3: timing = 0x40c8a742; break; 1744 case ATA_PIO4: timing = 0x40c8a731; break; 1745 case ATA_WDMA2: timing = 0x20c8a731; break; 1746 case ATA_UDMA2: timing = 0x10caa731; break; 1747 case ATA_UDMA4: timing = 0x10c9a731; break; 1748 default: timing = 0x0120a7a7; 1749 } 1750 break; 1751 case 0xd9: /* 40Mhz */ 1752 switch (mode) { 1753 case ATA_PIO0: timing = 0x4018d9d9; break; 1754 case ATA_PIO1: timing = 0x4010d9c7; break; 1755 case ATA_PIO2: timing = 0x4010d997; break; 1756 case ATA_PIO3: timing = 0x4010d974; break; 1757 case ATA_PIO4: timing = 0x4008d963; break; 1758 case ATA_WDMA2: timing = 0x2008d943; break; 1759 case ATA_UDMA2: timing = 0x100bd943; break; 1760 case ATA_UDMA4: timing = 0x100fd943; break; 1761 default: timing = 0x0120d9d9; 1762 } 1763 } 1764 } 1765 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1766} 1767 1768static int 1769hpt_cable80(struct ata_device *atadev) 1770{ 1771 device_t parent = device_get_parent(atadev->channel->dev); 1772 u_int8_t reg, val, res; 1773 1774 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) { 1775 reg = atadev->channel->unit ? 0x57 : 0x53; 1776 val = pci_read_config(parent, reg, 1); 1777 pci_write_config(parent, reg, val | 0x80, 1); 1778 } 1779 else { 1780 reg = 0x5b; 1781 val = pci_read_config(parent, reg, 1); 1782 pci_write_config(parent, reg, val & 0xfe, 1); 1783 } 1784 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); 1785 pci_write_config(parent, reg, val, 1); 1786 return !res; 1787} 1788