aic7xxx.reg revision 68402
123925Sgibbs/* 223925Sgibbs * Aic7xxx register and scratch ram definitions. 323925Sgibbs * 455581Sgibbs * Copyright (c) 1994-2000 Justin Gibbs. 523925Sgibbs * All rights reserved. 623925Sgibbs * 723925Sgibbs * Redistribution and use in source and binary forms, with or without 823925Sgibbs * modification, are permitted provided that the following conditions 923925Sgibbs * are met: 1023925Sgibbs * 1. Redistributions of source code must retain the above copyright 1126997Sgibbs * notice, this list of conditions, and the following disclaimer, 1254211Sgibbs * without modification. 1339220Sgibbs * 2. The name of the author may not be used to endorse or promote products 1423925Sgibbs * derived from this software without specific prior written permission. 1523925Sgibbs * 1654211Sgibbs * Alternatively, this software may be distributed under the terms of the 1763457Sgibbs * GNU Public License ("GPL"). 1826997Sgibbs * 1923925Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2023925Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2123925Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2223925Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2323925Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2423925Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2523925Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2623925Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2723925Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2823925Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2923925Sgibbs * SUCH DAMAGE. 3023925Sgibbs * 3166647Sgibbs * $Id: //depot/src/aic7xxx/aic7xxx.reg#5 $ 3265942Sgibbs * 3350477Speter * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 68402 2000-11-06 20:05:38Z gibbs $ 3423925Sgibbs */ 3523925Sgibbs 3623925Sgibbs/* 3723925Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 3823925Sgibbs * firmware for the aic7xxx family of SCSI host adapters as well as to generate 3923925Sgibbs * a C header file for use in the kernel portion of the Aic7xxx driver. 4023925Sgibbs * 4123925Sgibbs * All page numbers refer to the Adaptec AIC-7770 Data Book available from 4223925Sgibbs * Adaptec's Technical Documents Department 1-800-934-2766 4323925Sgibbs */ 4423925Sgibbs 4523925Sgibbs/* 4623925Sgibbs * SCSI Sequence Control (p. 3-11). 4723925Sgibbs * Each bit, when set starts a specific SCSI sequence on the bus 4823925Sgibbs */ 4923925Sgibbsregister SCSISEQ { 5023925Sgibbs address 0x000 5123925Sgibbs access_mode RW 5223925Sgibbs bit TEMODE 0x80 5323925Sgibbs bit ENSELO 0x40 5423925Sgibbs bit ENSELI 0x20 5523925Sgibbs bit ENRSELI 0x10 5623925Sgibbs bit ENAUTOATNO 0x08 5723925Sgibbs bit ENAUTOATNI 0x04 5823925Sgibbs bit ENAUTOATNP 0x02 5923925Sgibbs bit SCSIRSTO 0x01 6023925Sgibbs} 6123925Sgibbs 6223925Sgibbs/* 6323925Sgibbs * SCSI Transfer Control 0 Register (pp. 3-13). 6423925Sgibbs * Controls the SCSI module data path. 6523925Sgibbs */ 6623925Sgibbsregister SXFRCTL0 { 6723925Sgibbs address 0x001 6823925Sgibbs access_mode RW 6923925Sgibbs bit DFON 0x80 7023925Sgibbs bit DFPEXP 0x40 7123925Sgibbs bit FAST20 0x20 7223925Sgibbs bit CLRSTCNT 0x10 7323925Sgibbs bit SPIOEN 0x08 7423925Sgibbs bit SCAMEN 0x04 7523925Sgibbs bit CLRCHN 0x02 7623925Sgibbs} 7723925Sgibbs 7823925Sgibbs/* 7923925Sgibbs * SCSI Transfer Control 1 Register (pp. 3-14,15). 8023925Sgibbs * Controls the SCSI module data path. 8123925Sgibbs */ 8223925Sgibbsregister SXFRCTL1 { 8323925Sgibbs address 0x002 8423925Sgibbs access_mode RW 8523925Sgibbs bit BITBUCKET 0x80 8623925Sgibbs bit SWRAPEN 0x40 8723925Sgibbs bit ENSPCHK 0x20 8823925Sgibbs mask STIMESEL 0x18 8923925Sgibbs bit ENSTIMER 0x04 9023925Sgibbs bit ACTNEGEN 0x02 9123925Sgibbs bit STPWEN 0x01 /* Powered Termination */ 9223925Sgibbs} 9323925Sgibbs 9423925Sgibbs/* 9523925Sgibbs * SCSI Control Signal Read Register (p. 3-15). 9623925Sgibbs * Reads the actual state of the SCSI bus pins 9723925Sgibbs */ 9823925Sgibbsregister SCSISIGI { 9923925Sgibbs address 0x003 10023925Sgibbs access_mode RO 10123925Sgibbs bit CDI 0x80 10223925Sgibbs bit IOI 0x40 10323925Sgibbs bit MSGI 0x20 10423925Sgibbs bit ATNI 0x10 10523925Sgibbs bit SELI 0x08 10623925Sgibbs bit BSYI 0x04 10723925Sgibbs bit REQI 0x02 10823925Sgibbs bit ACKI 0x01 10923925Sgibbs/* 11023925Sgibbs * Possible phases in SCSISIGI 11123925Sgibbs */ 11223925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 11323925Sgibbs mask P_DATAOUT 0x00 11423925Sgibbs mask P_DATAIN IOI 11565948Sgibbs mask P_DATAOUT_DT P_DATAOUT|MSGI 11665948Sgibbs mask P_DATAIN_DT P_DATAIN|MSGI 11723925Sgibbs mask P_COMMAND CDI 11823925Sgibbs mask P_MESGOUT CDI|MSGI 11923925Sgibbs mask P_STATUS CDI|IOI 12023925Sgibbs mask P_MESGIN CDI|IOI|MSGI 12123925Sgibbs} 12223925Sgibbs 12323925Sgibbs/* 12423925Sgibbs * SCSI Control Signal Write Register (p. 3-16). 12523925Sgibbs * Writing to this register modifies the control signals on the bus. Only 12623925Sgibbs * those signals that are allowed in the current mode (Initiator/Target) are 12723925Sgibbs * asserted. 12823925Sgibbs */ 12923925Sgibbsregister SCSISIGO { 13023925Sgibbs address 0x003 13123925Sgibbs access_mode WO 13223925Sgibbs bit CDO 0x80 13323925Sgibbs bit IOO 0x40 13423925Sgibbs bit MSGO 0x20 13523925Sgibbs bit ATNO 0x10 13623925Sgibbs bit SELO 0x08 13723925Sgibbs bit BSYO 0x04 13823925Sgibbs bit REQO 0x02 13923925Sgibbs bit ACKO 0x01 14023925Sgibbs/* 14123925Sgibbs * Possible phases to write into SCSISIG0 14223925Sgibbs */ 14323925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 14423925Sgibbs mask P_DATAOUT 0x00 14523925Sgibbs mask P_DATAIN IOI 14623925Sgibbs mask P_COMMAND CDI 14723925Sgibbs mask P_MESGOUT CDI|MSGI 14823925Sgibbs mask P_STATUS CDI|IOI 14923925Sgibbs mask P_MESGIN CDI|IOI|MSGI 15023925Sgibbs} 15123925Sgibbs 15223925Sgibbs/* 15323925Sgibbs * SCSI Rate Control (p. 3-17). 15423925Sgibbs * Contents of this register determine the Synchronous SCSI data transfer 15523925Sgibbs * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 15623925Sgibbs * SOFS (3:0) bits disables synchronous data transfers. Any offset value 15723925Sgibbs * greater than 0 enables synchronous transfers. 15823925Sgibbs */ 15923925Sgibbsregister SCSIRATE { 16023925Sgibbs address 0x004 16123925Sgibbs access_mode RW 16223925Sgibbs bit WIDEXFER 0x80 /* Wide transfer control */ 16355581Sgibbs bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 16455581Sgibbs bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 16523925Sgibbs mask SXFR 0x70 /* Sync transfer rate */ 16655581Sgibbs mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 16723925Sgibbs mask SOFS 0x0f /* Sync offset */ 16823925Sgibbs} 16923925Sgibbs 17023925Sgibbs/* 17123925Sgibbs * SCSI ID (p. 3-18). 17223925Sgibbs * Contains the ID of the board and the current target on the 17323925Sgibbs * selected channel. 17423925Sgibbs */ 17523925Sgibbsregister SCSIID { 17623925Sgibbs address 0x005 17723925Sgibbs access_mode RW 17823925Sgibbs mask TID 0xf0 /* Target ID mask */ 17963457Sgibbs mask TWIN_TID 0x70 18063457Sgibbs bit TWIN_CHNLB 0x80 18123925Sgibbs mask OID 0x0f /* Our ID mask */ 18239220Sgibbs /* 18339220Sgibbs * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 18439220Sgibbs * The aic7890/91 allow an offset of up to 127 transfers in both wide 18539220Sgibbs * and narrow mode. 18639220Sgibbs */ 18739220Sgibbs alias SCSIOFFSET 18839220Sgibbs mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 18923925Sgibbs} 19023925Sgibbs 19123925Sgibbs/* 19223925Sgibbs * SCSI Latched Data (p. 3-19). 19323925Sgibbs * Read/Write latches used to transfer data on the SCSI bus during 19423925Sgibbs * Automatic or Manual PIO mode. SCSIDATH can be used for the 19523925Sgibbs * upper byte of a 16bit wide asynchronouse data phase transfer. 19623925Sgibbs */ 19723925Sgibbsregister SCSIDATL { 19823925Sgibbs address 0x006 19923925Sgibbs access_mode RW 20023925Sgibbs} 20123925Sgibbs 20223925Sgibbsregister SCSIDATH { 20323925Sgibbs address 0x007 20423925Sgibbs access_mode RW 20523925Sgibbs} 20623925Sgibbs 20723925Sgibbs/* 20823925Sgibbs * SCSI Transfer Count (pp. 3-19,20) 20923925Sgibbs * These registers count down the number of bytes transferred 21023925Sgibbs * across the SCSI bus. The counter is decremented only once 21123925Sgibbs * the data has been safely transferred. SDONE in SSTAT0 is 21223925Sgibbs * set when STCNT goes to 0 21323925Sgibbs */ 21423925Sgibbsregister STCNT { 21523925Sgibbs address 0x008 21623925Sgibbs size 3 21723925Sgibbs access_mode RW 21823925Sgibbs} 21923925Sgibbs 22055581Sgibbs/* ALT_MODE register on Ultra160 chips */ 22155581Sgibbsregister OPTIONMODE { 22255581Sgibbs address 0x008 22355581Sgibbs access_mode RW 22455581Sgibbs bit AUTORATEEN 0x80 22555581Sgibbs bit AUTOACKEN 0x40 22655581Sgibbs bit ATNMGMNTEN 0x20 22755581Sgibbs bit BUSFREEREV 0x10 22855581Sgibbs bit EXPPHASEDIS 0x08 22955581Sgibbs bit SCSIDATL_IMGEN 0x04 23055581Sgibbs bit AUTO_MSGOUT_DE 0x02 23155581Sgibbs bit DIS_MSGIN_DUALEDGE 0x01 23255581Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 23355581Sgibbs} 23455581Sgibbs 23555581Sgibbs/* ALT_MODE register on Ultra160 chips */ 23655581Sgibbsregister TARGCRCCNT { 23755581Sgibbs address 0x00a 23855581Sgibbs size 2 23955581Sgibbs access_mode RW 24055581Sgibbs} 24155581Sgibbs 24223925Sgibbs/* 24323925Sgibbs * Clear SCSI Interrupt 0 (p. 3-20) 24423925Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 24523925Sgibbs */ 24623925Sgibbsregister CLRSINT0 { 24723925Sgibbs address 0x00b 24823925Sgibbs access_mode WO 24923925Sgibbs bit CLRSELDO 0x40 25023925Sgibbs bit CLRSELDI 0x20 25123925Sgibbs bit CLRSELINGO 0x10 25223925Sgibbs bit CLRSWRAP 0x08 25323925Sgibbs bit CLRSPIORDY 0x02 25423925Sgibbs} 25523925Sgibbs 25623925Sgibbs/* 25723925Sgibbs * SCSI Status 0 (p. 3-21) 25823925Sgibbs * Contains one set of SCSI Interrupt codes 25923925Sgibbs * These are most likely of interest to the sequencer 26023925Sgibbs */ 26123925Sgibbsregister SSTAT0 { 26223925Sgibbs address 0x00b 26323925Sgibbs access_mode RO 26439220Sgibbs bit TARGET 0x80 /* Board acting as target */ 26539220Sgibbs bit SELDO 0x40 /* Selection Done */ 26639220Sgibbs bit SELDI 0x20 /* Board has been selected */ 26739220Sgibbs bit SELINGO 0x10 /* Selection In Progress */ 26839220Sgibbs bit SWRAP 0x08 /* 24bit counter wrap */ 26939220Sgibbs bit IOERR 0x08 /* LVD Tranceiver mode changed */ 27039220Sgibbs bit SDONE 0x04 /* STCNT = 0x000000 */ 27139220Sgibbs bit SPIORDY 0x02 /* SCSI PIO Ready */ 27239220Sgibbs bit DMADONE 0x01 /* DMA transfer completed */ 27323925Sgibbs} 27423925Sgibbs 27523925Sgibbs/* 27623925Sgibbs * Clear SCSI Interrupt 1 (p. 3-23) 27723925Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 27823925Sgibbs */ 27923925Sgibbsregister CLRSINT1 { 28023925Sgibbs address 0x00c 28123925Sgibbs access_mode WO 28223925Sgibbs bit CLRSELTIMEO 0x80 28323925Sgibbs bit CLRATNO 0x40 28423925Sgibbs bit CLRSCSIRSTI 0x20 28523925Sgibbs bit CLRBUSFREE 0x08 28623925Sgibbs bit CLRSCSIPERR 0x04 28723925Sgibbs bit CLRPHASECHG 0x02 28823925Sgibbs bit CLRREQINIT 0x01 28923925Sgibbs} 29023925Sgibbs 29123925Sgibbs/* 29223925Sgibbs * SCSI Status 1 (p. 3-24) 29323925Sgibbs */ 29423925Sgibbsregister SSTAT1 { 29523925Sgibbs address 0x00c 29623925Sgibbs access_mode RO 29723925Sgibbs bit SELTO 0x80 29823925Sgibbs bit ATNTARG 0x40 29923925Sgibbs bit SCSIRSTI 0x20 30023925Sgibbs bit PHASEMIS 0x10 30123925Sgibbs bit BUSFREE 0x08 30223925Sgibbs bit SCSIPERR 0x04 30323925Sgibbs bit PHASECHG 0x02 30423925Sgibbs bit REQINIT 0x01 30523925Sgibbs} 30623925Sgibbs 30723925Sgibbs/* 30823925Sgibbs * SCSI Status 2 (pp. 3-25,26) 30923925Sgibbs */ 31023925Sgibbsregister SSTAT2 { 31123925Sgibbs address 0x00d 31223925Sgibbs access_mode RO 31323925Sgibbs bit OVERRUN 0x80 31463944Sgibbs bit SHVALID 0x40 /* Shaddow Layer non-zero */ 31539220Sgibbs bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 31665948Sgibbs bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 31765948Sgibbs bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 31865948Sgibbs bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 31965948Sgibbs bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 32023925Sgibbs mask SFCNT 0x1f 32123925Sgibbs} 32223925Sgibbs 32323925Sgibbs/* 32423925Sgibbs * SCSI Status 3 (p. 3-26) 32523925Sgibbs */ 32623925Sgibbsregister SSTAT3 { 32723925Sgibbs address 0x00e 32823925Sgibbs access_mode RO 32923925Sgibbs mask SCSICNT 0xf0 33023925Sgibbs mask OFFCNT 0x0f 33123925Sgibbs} 33223925Sgibbs 33323925Sgibbs/* 33439220Sgibbs * SCSI ID for the aic7890/91 chips 33523925Sgibbs */ 33639220Sgibbsregister SCSIID_ULTRA2 { 33723925Sgibbs address 0x00f 33823925Sgibbs access_mode RW 33939220Sgibbs mask TID 0xf0 /* Target ID mask */ 34039220Sgibbs mask OID 0x0f /* Our ID mask */ 34123925Sgibbs} 34223925Sgibbs 34323925Sgibbs/* 34423925Sgibbs * SCSI Interrupt Mode 1 (p. 3-28) 34523925Sgibbs * Setting any bit will enable the corresponding function 34623925Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 34723925Sgibbs */ 34823925Sgibbsregister SIMODE0 { 34923925Sgibbs address 0x010 35023925Sgibbs access_mode RW 35123925Sgibbs bit ENSELDO 0x40 35223925Sgibbs bit ENSELDI 0x20 35323925Sgibbs bit ENSELINGO 0x10 35423925Sgibbs bit ENSWRAP 0x08 35539220Sgibbs bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 35623925Sgibbs bit ENSDONE 0x04 35723925Sgibbs bit ENSPIORDY 0x02 35823925Sgibbs bit ENDMADONE 0x01 35923925Sgibbs} 36023925Sgibbs 36123925Sgibbs/* 36223925Sgibbs * SCSI Interrupt Mode 1 (pp. 3-28,29) 36323925Sgibbs * Setting any bit will enable the corresponding function 36423925Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 36523925Sgibbs */ 36623925Sgibbsregister SIMODE1 { 36723925Sgibbs address 0x011 36823925Sgibbs access_mode RW 36923925Sgibbs bit ENSELTIMO 0x80 37023925Sgibbs bit ENATNTARG 0x40 37123925Sgibbs bit ENSCSIRST 0x20 37223925Sgibbs bit ENPHASEMIS 0x10 37323925Sgibbs bit ENBUSFREE 0x08 37423925Sgibbs bit ENSCSIPERR 0x04 37523925Sgibbs bit ENPHASECHG 0x02 37623925Sgibbs bit ENREQINIT 0x01 37723925Sgibbs} 37823925Sgibbs 37923925Sgibbs/* 38023925Sgibbs * SCSI Data Bus (High) (p. 3-29) 38123925Sgibbs * This register reads data on the SCSI Data bus directly. 38223925Sgibbs */ 38323925Sgibbsregister SCSIBUSL { 38423925Sgibbs address 0x012 38568087Sgibbs access_mode RW 38623925Sgibbs} 38723925Sgibbs 38823925Sgibbsregister SCSIBUSH { 38923925Sgibbs address 0x013 39068087Sgibbs access_mode RW 39123925Sgibbs} 39223925Sgibbs 39323925Sgibbs/* 39423925Sgibbs * SCSI/Host Address (p. 3-30) 39523925Sgibbs * These registers hold the host address for the byte about to be 39623925Sgibbs * transferred on the SCSI bus. They are counted up in the same 39723925Sgibbs * manner as STCNT is counted down. SHADDR should always be used 39823925Sgibbs * to determine the address of the last byte transferred since HADDR 39923925Sgibbs * can be skewed by write ahead. 40023925Sgibbs */ 40123925Sgibbsregister SHADDR { 40223925Sgibbs address 0x014 40323925Sgibbs size 4 40423925Sgibbs access_mode RO 40523925Sgibbs} 40623925Sgibbs 40723925Sgibbs/* 40823925Sgibbs * Selection Timeout Timer (p. 3-30) 40923925Sgibbs */ 41023925Sgibbsregister SELTIMER { 41123925Sgibbs address 0x018 41223925Sgibbs access_mode RW 41323925Sgibbs bit STAGE6 0x20 41423925Sgibbs bit STAGE5 0x10 41523925Sgibbs bit STAGE4 0x08 41623925Sgibbs bit STAGE3 0x04 41723925Sgibbs bit STAGE2 0x02 41823925Sgibbs bit STAGE1 0x01 41939220Sgibbs alias TARGIDIN 42023925Sgibbs} 42123925Sgibbs 42223925Sgibbs/* 42323925Sgibbs * Selection/Reselection ID (p. 3-31) 42423925Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 42523925Sgibbs * device did not set its own ID. 42623925Sgibbs */ 42723925Sgibbsregister SELID { 42823925Sgibbs address 0x019 42923925Sgibbs access_mode RW 43023925Sgibbs mask SELID_MASK 0xf0 43123925Sgibbs bit ONEBIT 0x08 43223925Sgibbs} 43323925Sgibbs 43455581Sgibbsregister SCAMCTL { 43555581Sgibbs address 0x01a 43655581Sgibbs access_mode RW 43755581Sgibbs bit ENSCAMSELO 0x80 43855581Sgibbs bit CLRSCAMSELID 0x40 43955581Sgibbs bit ALTSTIM 0x20 44055581Sgibbs bit DFLTTID 0x10 44155581Sgibbs mask SCAMLVL 0x03 44255581Sgibbs} 44355581Sgibbs 44423925Sgibbs/* 44539220Sgibbs * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 44639220Sgibbs */ 44739220Sgibbsregister TARGID { 44839220Sgibbs address 0x01b 44939220Sgibbs size 2 45039220Sgibbs access_mode RW 45139220Sgibbs} 45239220Sgibbs 45339220Sgibbs/* 45439220Sgibbs * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 45539220Sgibbs * Indicates if external logic has been attached to the chip to 45639220Sgibbs * perform the tasks of accessing a serial eeprom, testing termination 45739220Sgibbs * strength, and performing cable detection. On the aic7860, most of 45839220Sgibbs * these features are handled on chip, but on the aic7855 an attached 45939220Sgibbs * aic3800 does the grunt work. 46039220Sgibbs */ 46139220Sgibbsregister SPIOCAP { 46239220Sgibbs address 0x01b 46339220Sgibbs access_mode RW 46439220Sgibbs bit SOFT1 0x80 46539220Sgibbs bit SOFT0 0x40 46639220Sgibbs bit SOFTCMDEN 0x20 46739220Sgibbs bit HAS_BRDCTL 0x10 /* External Board control */ 46839220Sgibbs bit SEEPROM 0x08 /* External serial eeprom logic */ 46939220Sgibbs bit EEPROM 0x04 /* Writable external BIOS ROM */ 47039220Sgibbs bit ROM 0x02 /* Logic for accessing external ROM */ 47139220Sgibbs bit SSPIOCPS 0x01 /* Termination and cable detection */ 47239220Sgibbs} 47339220Sgibbs 47444590Sgibbsregister BRDCTL { 47544590Sgibbs address 0x01d 47644590Sgibbs bit BRDDAT7 0x80 47744590Sgibbs bit BRDDAT6 0x40 47844590Sgibbs bit BRDDAT5 0x20 47944590Sgibbs bit BRDSTB 0x10 48044590Sgibbs bit BRDCS 0x08 48144590Sgibbs bit BRDRW 0x04 48244590Sgibbs bit BRDCTL1 0x02 48344590Sgibbs bit BRDCTL0 0x01 48444590Sgibbs /* 7890 Definitions */ 48544590Sgibbs bit BRDDAT4 0x10 48644590Sgibbs bit BRDDAT3 0x08 48744590Sgibbs bit BRDDAT2 0x04 48844590Sgibbs bit BRDRW_ULTRA2 0x02 48944590Sgibbs bit BRDSTB_ULTRA2 0x01 49044590Sgibbs} 49144590Sgibbs 49239220Sgibbs/* 49344590Sgibbs * Serial EEPROM Control (p. 4-92 in 7870 Databook) 49444590Sgibbs * Controls the reading and writing of an external serial 1-bit 49544590Sgibbs * EEPROM Device. In order to access the serial EEPROM, you must 49644590Sgibbs * first set the SEEMS bit that generates a request to the memory 49744590Sgibbs * port for access to the serial EEPROM device. When the memory 49844590Sgibbs * port is not busy servicing another request, it reconfigures 49944590Sgibbs * to allow access to the serial EEPROM. When this happens, SEERDY 50044590Sgibbs * gets set high to verify that the memory port access has been 50144590Sgibbs * granted. 50244590Sgibbs * 50344590Sgibbs * After successful arbitration for the memory port, the SEECS bit of 50444590Sgibbs * the SEECTL register is connected to the chip select. The SEECK, 50544590Sgibbs * SEEDO, and SEEDI are connected to the clock, data out, and data in 50644590Sgibbs * lines respectively. The SEERDY bit of SEECTL is useful in that it 50744590Sgibbs * gives us an 800 nsec timer. After a write to the SEECTL register, 50844590Sgibbs * the SEERDY goes high 800 nsec later. The one exception to this is 50944590Sgibbs * when we first request access to the memory port. The SEERDY goes 51044590Sgibbs * high to signify that access has been granted and, for this case, has 51144590Sgibbs * no implied timing. 51244590Sgibbs * 51344590Sgibbs * See 93cx6.c for detailed information on the protocol necessary to 51444590Sgibbs * read the serial EEPROM. 51544590Sgibbs */ 51644590Sgibbsregister SEECTL { 51744590Sgibbs address 0x01e 51844590Sgibbs bit EXTARBACK 0x80 51944590Sgibbs bit EXTARBREQ 0x40 52044590Sgibbs bit SEEMS 0x20 52144590Sgibbs bit SEERDY 0x10 52244590Sgibbs bit SEECS 0x08 52344590Sgibbs bit SEECK 0x04 52444590Sgibbs bit SEEDO 0x02 52544590Sgibbs bit SEEDI 0x01 52644590Sgibbs} 52744590Sgibbs/* 52823925Sgibbs * SCSI Block Control (p. 3-32) 52923925Sgibbs * Controls Bus type and channel selection. In a twin channel configuration 53023925Sgibbs * addresses 0x00-0x1e are gated to the appropriate channel based on this 53123925Sgibbs * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 53223925Sgibbs * on a wide bus. 53323925Sgibbs */ 53423925Sgibbsregister SBLKCTL { 53523925Sgibbs address 0x01f 53623925Sgibbs access_mode RW 53723925Sgibbs bit DIAGLEDEN 0x80 /* Aic78X0 only */ 53823925Sgibbs bit DIAGLEDON 0x40 /* Aic78X0 only */ 53923925Sgibbs bit AUTOFLUSHDIS 0x20 54023925Sgibbs bit SELBUSB 0x08 54139220Sgibbs bit ENAB40 0x08 /* LVD transceiver active */ 54239220Sgibbs bit ENAB20 0x04 /* SE/HVD transceiver active */ 54323925Sgibbs bit SELWIDE 0x02 54439220Sgibbs bit XCVR 0x01 /* External transceiver active */ 54523925Sgibbs} 54623925Sgibbs 54723925Sgibbs/* 54823925Sgibbs * Sequencer Control (p. 3-33) 54923925Sgibbs * Error detection mode and speed configuration 55023925Sgibbs */ 55123925Sgibbsregister SEQCTL { 55223925Sgibbs address 0x060 55323925Sgibbs access_mode RW 55423925Sgibbs bit PERRORDIS 0x80 55523925Sgibbs bit PAUSEDIS 0x40 55623925Sgibbs bit FAILDIS 0x20 55723925Sgibbs bit FASTMODE 0x10 55823925Sgibbs bit BRKADRINTEN 0x08 55923925Sgibbs bit STEP 0x04 56023925Sgibbs bit SEQRESET 0x02 56123925Sgibbs bit LOADRAM 0x01 56223925Sgibbs} 56323925Sgibbs 56423925Sgibbs/* 56523925Sgibbs * Sequencer RAM Data (p. 3-34) 56623925Sgibbs * Single byte window into the Scratch Ram area starting at the address 56723925Sgibbs * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 56842652Sgibbs * four bytes in succession. The SEQADDRs will increment after the most 56923925Sgibbs * significant byte is written 57023925Sgibbs */ 57123925Sgibbsregister SEQRAM { 57223925Sgibbs address 0x061 57323925Sgibbs access_mode RW 57423925Sgibbs} 57523925Sgibbs 57623925Sgibbs/* 57723925Sgibbs * Sequencer Address Registers (p. 3-35) 57823925Sgibbs * Only the first bit of SEQADDR1 holds addressing information 57923925Sgibbs */ 58023925Sgibbsregister SEQADDR0 { 58123925Sgibbs address 0x062 58223925Sgibbs access_mode RW 58323925Sgibbs} 58423925Sgibbs 58523925Sgibbsregister SEQADDR1 { 58623925Sgibbs address 0x063 58723925Sgibbs access_mode RW 58823925Sgibbs mask SEQADDR1_MASK 0x01 58923925Sgibbs} 59023925Sgibbs 59123925Sgibbs/* 59223925Sgibbs * Accumulator 59323925Sgibbs * We cheat by passing arguments in the Accumulator up to the kernel driver 59423925Sgibbs */ 59523925Sgibbsregister ACCUM { 59623925Sgibbs address 0x064 59723925Sgibbs access_mode RW 59823925Sgibbs accumulator 59923925Sgibbs} 60023925Sgibbs 60123925Sgibbsregister SINDEX { 60223925Sgibbs address 0x065 60323925Sgibbs access_mode RW 60423925Sgibbs sindex 60523925Sgibbs} 60623925Sgibbs 60723925Sgibbsregister DINDEX { 60823925Sgibbs address 0x066 60923925Sgibbs access_mode RW 61023925Sgibbs} 61123925Sgibbs 61223925Sgibbsregister ALLONES { 61323925Sgibbs address 0x069 61423925Sgibbs access_mode RO 61523925Sgibbs allones 61623925Sgibbs} 61723925Sgibbs 61823925Sgibbsregister ALLZEROS { 61923925Sgibbs address 0x06a 62023925Sgibbs access_mode RO 62123925Sgibbs allzeros 62223925Sgibbs} 62323925Sgibbs 62423925Sgibbsregister NONE { 62523925Sgibbs address 0x06a 62623925Sgibbs access_mode WO 62723925Sgibbs none 62823925Sgibbs} 62923925Sgibbs 63023925Sgibbsregister FLAGS { 63123925Sgibbs address 0x06b 63223925Sgibbs access_mode RO 63323925Sgibbs bit ZERO 0x02 63423925Sgibbs bit CARRY 0x01 63523925Sgibbs} 63623925Sgibbs 63723925Sgibbsregister SINDIR { 63823925Sgibbs address 0x06c 63923925Sgibbs access_mode RO 64023925Sgibbs} 64123925Sgibbs 64223925Sgibbsregister DINDIR { 64323925Sgibbs address 0x06d 64423925Sgibbs access_mode WO 64523925Sgibbs} 64623925Sgibbs 64723925Sgibbsregister FUNCTION1 { 64823925Sgibbs address 0x06e 64923925Sgibbs access_mode RW 65023925Sgibbs} 65123925Sgibbs 65223925Sgibbsregister STACK { 65323925Sgibbs address 0x06f 65423925Sgibbs access_mode RO 65523925Sgibbs} 65623925Sgibbs 65723925Sgibbs/* 65823925Sgibbs * Board Control (p. 3-43) 65923925Sgibbs */ 66023925Sgibbsregister BCTL { 66123925Sgibbs address 0x084 66223925Sgibbs access_mode RW 66323925Sgibbs bit ACE 0x08 66423925Sgibbs bit ENABLE 0x01 66523925Sgibbs} 66623925Sgibbs 66723925Sgibbs/* 66823925Sgibbs * On the aic78X0 chips, Board Control is replaced by the DSCommand 66923925Sgibbs * register (p. 4-64) 67023925Sgibbs */ 67144590Sgibbsregister DSCOMMAND0 { 67223925Sgibbs address 0x084 67323925Sgibbs access_mode RW 67423925Sgibbs bit CACHETHEN 0x80 /* Cache Threshold enable */ 67523925Sgibbs bit DPARCKEN 0x40 /* Data Parity Check Enable */ 67623925Sgibbs bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 67723925Sgibbs bit EXTREQLCK 0x10 /* External Request Lock */ 67844590Sgibbs /* aic7890/91/96/97 only */ 67944590Sgibbs bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 68044590Sgibbs bit RAMPS 0x04 /* External SCB RAM Present */ 68144590Sgibbs bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 68244590Sgibbs bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 68323925Sgibbs} 68423925Sgibbs 68523925Sgibbs/* 68623925Sgibbs * Bus On/Off Time (p. 3-44) 68723925Sgibbs */ 68823925Sgibbsregister BUSTIME { 68923925Sgibbs address 0x085 69023925Sgibbs access_mode RW 69123925Sgibbs mask BOFF 0xf0 69223925Sgibbs mask BON 0x0f 69323925Sgibbs} 69423925Sgibbs 69523925Sgibbs/* 69644590Sgibbs * Bus Speed (p. 3-45) aic7770 only 69723925Sgibbs */ 69823925Sgibbsregister BUSSPD { 69923925Sgibbs address 0x086 70023925Sgibbs access_mode RW 70123925Sgibbs mask DFTHRSH 0xc0 70223925Sgibbs mask STBOFF 0x38 70323925Sgibbs mask STBON 0x07 70423925Sgibbs mask DFTHRSH_100 0xc0 70568087Sgibbs mask DFTHRSH_75 0x80 70623925Sgibbs} 70723925Sgibbs 70844590Sgibbs/* aic7850/55/60/70/80/95 only */ 70944590Sgibbsregister DSPCISTATUS { 71044590Sgibbs address 0x086 71144590Sgibbs mask DFTHRSH_100 0xc0 71244590Sgibbs} 71344590Sgibbs 71447158Sgibbs/* aic7890/91/96/97 only */ 71547158Sgibbsregister HS_MAILBOX { 71647158Sgibbs address 0x086 71747158Sgibbs mask HOST_MAILBOX 0xF0 71847158Sgibbs mask SEQ_MAILBOX 0x0F 71958258Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 72047158Sgibbs} 72147158Sgibbs 72247158Sgibbsconst HOST_MAILBOX_SHIFT 4 72347158Sgibbsconst SEQ_MAILBOX_SHIFT 0 72447158Sgibbs 72523925Sgibbs/* 72623925Sgibbs * Host Control (p. 3-47) R/W 72723925Sgibbs * Overall host control of the device. 72823925Sgibbs */ 72923925Sgibbsregister HCNTRL { 73023925Sgibbs address 0x087 73123925Sgibbs access_mode RW 73223925Sgibbs bit POWRDN 0x40 73323925Sgibbs bit SWINT 0x10 73423925Sgibbs bit IRQMS 0x08 73523925Sgibbs bit PAUSE 0x04 73623925Sgibbs bit INTEN 0x02 73723925Sgibbs bit CHIPRST 0x01 73823925Sgibbs bit CHIPRSTACK 0x01 73923925Sgibbs} 74023925Sgibbs 74123925Sgibbs/* 74223925Sgibbs * Host Address (p. 3-48) 74323925Sgibbs * This register contains the address of the byte about 74423925Sgibbs * to be transferred across the host bus. 74523925Sgibbs */ 74623925Sgibbsregister HADDR { 74723925Sgibbs address 0x088 74823925Sgibbs size 4 74923925Sgibbs access_mode RW 75023925Sgibbs} 75123925Sgibbs 75223925Sgibbsregister HCNT { 75323925Sgibbs address 0x08c 75423925Sgibbs size 3 75523925Sgibbs access_mode RW 75623925Sgibbs} 75723925Sgibbs 75823925Sgibbs/* 75923925Sgibbs * SCB Pointer (p. 3-49) 76063457Sgibbs * Gate one of the SCBs into the SCBARRAY window. 76123925Sgibbs */ 76223925Sgibbsregister SCBPTR { 76323925Sgibbs address 0x090 76423925Sgibbs access_mode RW 76523925Sgibbs} 76623925Sgibbs 76723925Sgibbs/* 76823925Sgibbs * Interrupt Status (p. 3-50) 76923925Sgibbs * Status for system interrupts 77023925Sgibbs */ 77123925Sgibbsregister INTSTAT { 77223925Sgibbs address 0x091 77323925Sgibbs access_mode RW 77423925Sgibbs bit BRKADRINT 0x08 77523925Sgibbs bit SCSIINT 0x04 77623925Sgibbs bit CMDCMPLT 0x02 77723925Sgibbs bit SEQINT 0x01 77823925Sgibbs mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 77923925Sgibbs mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 78023925Sgibbs mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 78123925Sgibbs mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 78263457Sgibbs mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 78368087Sgibbs mask RESIDUAL 0x50|SEQINT /* Residual byte count != 0 */ 78468087Sgibbs mask HOST_MSG_LOOP 0x60|SEQINT /* 78541646Sgibbs * The bus is ready for the 78641646Sgibbs * host to perform another 78741646Sgibbs * message transaction. This 78841646Sgibbs * mechanism is used for things 78941646Sgibbs * like sync/wide negotiation 79041646Sgibbs * that require a kernel based 79141646Sgibbs * message state engine. 79223925Sgibbs */ 79368087Sgibbs mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 79468087Sgibbs mask PERR_DETECTED 0x80|SEQINT /* 79557099Sgibbs * Either the phase_lock 79657099Sgibbs * or inb_next routine has 79757099Sgibbs * noticed a parity error. 79857099Sgibbs */ 79968087Sgibbs mask DATA_OVERRUN 0x90|SEQINT /* 80023925Sgibbs * Target attempted to write 80123925Sgibbs * beyond the bounds of its 80223925Sgibbs * command. 80323925Sgibbs */ 80468402Sgibbs mask MKMSG_FAILED 0xa0|SEQINT /* 80568402Sgibbs * Target completed command 80668402Sgibbs * without honoring our ATN 80768402Sgibbs * request to issue a message. 80868087Sgibbs */ 80968087Sgibbs mask SCBPTR_MISMATCH 0xb0|SEQINT /* 81068087Sgibbs * In the SCB paging case, our 81168087Sgibbs * SCBPTR is not the same as 81268087Sgibbs * we originally set prior to 81368087Sgibbs * download of a new scb. 81468087Sgibbs */ 81568087Sgibbs mask SCB_MISMATCH 0xc0|SEQINT /* 81668087Sgibbs * Downloaded SCB's tag does 81768087Sgibbs * not match the entry we 81868087Sgibbs * intended to download. 81968087Sgibbs */ 82068087Sgibbs mask ABORT_QINSCB 0xd0|SEQINT /* 82168087Sgibbs * An SCB was aborted 82268087Sgibbs * during download. 82368087Sgibbs * Informational. 82468087Sgibbs */ 82568087Sgibbs mask NO_FREE_SCB 0xe0|SEQINT /* 82668087Sgibbs * get_free_or_disc_scb failed. 82768087Sgibbs */ 82868087Sgibbs mask OUT_OF_RANGE 0xf0|SEQINT 82923925Sgibbs 83023925Sgibbs mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 83123925Sgibbs mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 83223925Sgibbs} 83323925Sgibbs 83423925Sgibbs/* 83523925Sgibbs * Hard Error (p. 3-53) 83623925Sgibbs * Reporting of catastrophic errors. You usually cannot recover from 83723925Sgibbs * these without a full board reset. 83823925Sgibbs */ 83923925Sgibbsregister ERROR { 84023925Sgibbs address 0x092 84123925Sgibbs access_mode RO 84239220Sgibbs bit CIOPARERR 0x80 /* Ultra2 only */ 84339220Sgibbs bit PCIERRSTAT 0x40 /* PCI only */ 84439220Sgibbs bit MPARERR 0x20 /* PCI only */ 84539220Sgibbs bit DPARERR 0x10 /* PCI only */ 84639220Sgibbs bit SQPARERR 0x08 84723925Sgibbs bit ILLOPCODE 0x04 84823925Sgibbs bit ILLSADDR 0x02 84923925Sgibbs bit ILLHADDR 0x01 85023925Sgibbs} 85123925Sgibbs 85223925Sgibbs/* 85323925Sgibbs * Clear Interrupt Status (p. 3-52) 85423925Sgibbs */ 85523925Sgibbsregister CLRINT { 85623925Sgibbs address 0x092 85723925Sgibbs access_mode WO 85839220Sgibbs bit CLRPARERR 0x10 /* PCI only */ 85923925Sgibbs bit CLRBRKADRINT 0x08 86023925Sgibbs bit CLRSCSIINT 0x04 86123925Sgibbs bit CLRCMDINT 0x02 86223925Sgibbs bit CLRSEQINT 0x01 86323925Sgibbs} 86423925Sgibbs 86523925Sgibbsregister DFCNTRL { 86623925Sgibbs address 0x093 86723925Sgibbs access_mode RW 86839220Sgibbs bit PRELOADEN 0x80 /* aic7890 only */ 86923925Sgibbs bit WIDEODD 0x40 87023925Sgibbs bit SCSIEN 0x20 87123925Sgibbs bit SDMAEN 0x10 87223925Sgibbs bit SDMAENACK 0x10 87323925Sgibbs bit HDMAEN 0x08 87423925Sgibbs bit HDMAENACK 0x08 87523925Sgibbs bit DIRECTION 0x04 87623925Sgibbs bit FIFOFLUSH 0x02 87723925Sgibbs bit FIFORESET 0x01 87823925Sgibbs} 87923925Sgibbs 88023925Sgibbsregister DFSTATUS { 88123925Sgibbs address 0x094 88223925Sgibbs access_mode RO 88339220Sgibbs bit PRELOAD_AVAIL 0x80 88423925Sgibbs bit DWORDEMP 0x20 88523925Sgibbs bit MREQPEND 0x10 88623925Sgibbs bit HDONE 0x08 88723925Sgibbs bit DFTHRESH 0x04 88823925Sgibbs bit FIFOFULL 0x02 88923925Sgibbs bit FIFOEMP 0x01 89023925Sgibbs} 89123925Sgibbs 89241299Sgibbsregister DFWADDR { 89341299Sgibbs address 0x95 89441299Sgibbs access_mode RW 89541299Sgibbs} 89641299Sgibbs 89741299Sgibbsregister DFRADDR { 89841299Sgibbs address 0x97 89941299Sgibbs access_mode RW 90041299Sgibbs} 90141299Sgibbs 90223925Sgibbsregister DFDAT { 90323925Sgibbs address 0x099 90423925Sgibbs access_mode RW 90523925Sgibbs} 90623925Sgibbs 90723925Sgibbs/* 90823925Sgibbs * SCB Auto Increment (p. 3-59) 90923925Sgibbs * Byte offset into the SCB Array and an optional bit to allow auto 91023925Sgibbs * incrementing of the address during download and upload operations 91123925Sgibbs */ 91223925Sgibbsregister SCBCNT { 91323925Sgibbs address 0x09a 91423925Sgibbs access_mode RW 91523925Sgibbs bit SCBAUTO 0x80 91623925Sgibbs mask SCBCNT_MASK 0x1f 91723925Sgibbs} 91823925Sgibbs 91923925Sgibbs/* 92023925Sgibbs * Queue In FIFO (p. 3-60) 92123925Sgibbs * Input queue for queued SCBs (commands that the seqencer has yet to start) 92223925Sgibbs */ 92323925Sgibbsregister QINFIFO { 92423925Sgibbs address 0x09b 92523925Sgibbs access_mode RW 92623925Sgibbs} 92723925Sgibbs 92823925Sgibbs/* 92923925Sgibbs * Queue In Count (p. 3-60) 93023925Sgibbs * Number of queued SCBs 93123925Sgibbs */ 93223925Sgibbsregister QINCNT { 93323925Sgibbs address 0x09c 93423925Sgibbs access_mode RO 93523925Sgibbs} 93623925Sgibbs 93723925Sgibbs/* 93823925Sgibbs * Queue Out FIFO (p. 3-61) 93923925Sgibbs * Queue of SCBs that have completed and await the host 94023925Sgibbs */ 94123925Sgibbsregister QOUTFIFO { 94223925Sgibbs address 0x09d 94323925Sgibbs access_mode WO 94423925Sgibbs} 94523925Sgibbs 94655581Sgibbsregister CRCCONTROL1 { 94755581Sgibbs address 0x09d 94855581Sgibbs access_mode RW 94955581Sgibbs bit CRCONSEEN 0x80 95055581Sgibbs bit CRCVALCHKEN 0x40 95155581Sgibbs bit CRCENDCHKEN 0x20 95255581Sgibbs bit CRCREQCHKEN 0x10 95355581Sgibbs bit TARGCRCENDEN 0x08 95455581Sgibbs bit TARGCRCCNTEN 0x04 95555581Sgibbs} 95655581Sgibbs 95755581Sgibbs 95823925Sgibbs/* 95923925Sgibbs * Queue Out Count (p. 3-61) 96023925Sgibbs * Number of queued SCBs in the Out FIFO 96123925Sgibbs */ 96223925Sgibbsregister QOUTCNT { 96323925Sgibbs address 0x09e 96423925Sgibbs access_mode RO 96523925Sgibbs} 96623925Sgibbs 96755581Sgibbsregister SCSIPHASE { 96855581Sgibbs address 0x09e 96955581Sgibbs access_mode RO 97055581Sgibbs bit STATUS_PHASE 0x20 97155581Sgibbs bit COMMAND_PHASE 0x10 97255581Sgibbs bit MSG_IN_PHASE 0x08 97355581Sgibbs bit MSG_OUT_PHASE 0x04 97455581Sgibbs bit DATA_IN_PHASE 0x02 97555581Sgibbs bit DATA_OUT_PHASE 0x01 97655581Sgibbs} 97755581Sgibbs 97823925Sgibbs/* 97939220Sgibbs * Special Function 98039220Sgibbs */ 98139220Sgibbsregister SFUNCT { 98239220Sgibbs address 0x09f 98339220Sgibbs access_mode RW 98455581Sgibbs bit ALT_MODE 0x80 98539220Sgibbs} 98639220Sgibbs 98739220Sgibbs/* 98823925Sgibbs * SCB Definition (p. 5-4) 98923925Sgibbs */ 99023925Sgibbsscb { 99123925Sgibbs address 0x0a0 99263457Sgibbs SCB_CDB_PTR { 99323925Sgibbs size 4 99463457Sgibbs alias SCB_RESIDUAL_DATACNT 99563457Sgibbs alias SCB_CDB_STORE 99663457Sgibbs alias SCB_TARGET_INFO 99723925Sgibbs } 99863457Sgibbs SCB_RESIDUAL_SGPTR { 99963457Sgibbs size 4 100063457Sgibbs } 100163457Sgibbs SCB_SCSI_STATUS { 100223925Sgibbs size 1 100323925Sgibbs } 100463457Sgibbs SCB_CDB_STORE_PAD { 100523925Sgibbs size 3 100623925Sgibbs } 100723925Sgibbs SCB_DATAPTR { 100823925Sgibbs size 4 100923925Sgibbs } 101023925Sgibbs SCB_DATACNT { 101139220Sgibbs /* 101263457Sgibbs * The last byte is really the high address bits for 101363457Sgibbs * the data address. 101439220Sgibbs */ 101539220Sgibbs size 4 101663457Sgibbs bit SG_LAST_SEG 0x80 /* In the fourth byte */ 101763457Sgibbs mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 101823925Sgibbs } 101963457Sgibbs SCB_SGPTR { 102023925Sgibbs size 4 102163457Sgibbs bit SG_RESID_VALID 0x04 /* In the first byte */ 102263457Sgibbs bit SG_FULL_RESID 0x02 /* In the first byte */ 102363457Sgibbs bit SG_LIST_NULL 0x01 /* In the first byte */ 102423925Sgibbs } 102565948Sgibbs SCB_CONTROL { 102665948Sgibbs size 1 102765948Sgibbs bit TARGET_SCB 0x80 102865948Sgibbs bit DISCENB 0x40 102965948Sgibbs bit TAG_ENB 0x20 103065948Sgibbs bit MK_MESSAGE 0x10 103165948Sgibbs bit ULTRAENB 0x08 103265948Sgibbs bit DISCONNECTED 0x04 103365948Sgibbs mask SCB_TAG_TYPE 0x03 103465948Sgibbs } 103565948Sgibbs SCB_SCSIID { 103665948Sgibbs size 1 103765948Sgibbs bit TWIN_CHNLB 0x80 103865948Sgibbs mask TWIN_TID 0x70 103965948Sgibbs mask TID 0xf0 104065948Sgibbs mask OID 0x0f 104165948Sgibbs } 104265948Sgibbs SCB_LUN { 104365948Sgibbs mask LID 0xff 104465948Sgibbs size 1 104565948Sgibbs } 104623925Sgibbs SCB_TAG { 104723925Sgibbs size 1 104823925Sgibbs } 104965948Sgibbs SCB_CDB_LEN { 105065948Sgibbs size 1 105165948Sgibbs } 105239220Sgibbs SCB_SCSIRATE { 105323925Sgibbs size 1 105423925Sgibbs } 105539220Sgibbs SCB_SCSIOFFSET { 105639220Sgibbs size 1 105739220Sgibbs } 105863457Sgibbs SCB_NEXT { 105963457Sgibbs size 1 106039220Sgibbs } 106165948Sgibbs SCB_64_SPARE { 106239220Sgibbs size 16 106339220Sgibbs } 106465948Sgibbs SCB_64_BTT { 106563457Sgibbs size 16 106623925Sgibbs } 106723925Sgibbs} 106823925Sgibbs 106965948Sgibbsconst SCB_UPLOAD_SIZE 32 107065948Sgibbsconst SCB_DOWNLOAD_SIZE 32 107165948Sgibbsconst SCB_DOWNLOAD_SIZE_64 48 107239220Sgibbs 107323925Sgibbsconst SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 107423925Sgibbs 107523925Sgibbs/* --------------------- AHA-2840-only definitions -------------------- */ 107623925Sgibbs 107723925Sgibbsregister SEECTL_2840 { 107823925Sgibbs address 0x0c0 107923925Sgibbs access_mode RW 108023925Sgibbs bit CS_2840 0x04 108123925Sgibbs bit CK_2840 0x02 108223925Sgibbs bit DO_2840 0x01 108323925Sgibbs} 108423925Sgibbs 108523925Sgibbsregister STATUS_2840 { 108623925Sgibbs address 0x0c1 108723925Sgibbs access_mode RW 108823925Sgibbs bit EEPROM_TF 0x80 108923925Sgibbs mask BIOS_SEL 0x60 109023925Sgibbs mask ADSEL 0x1e 109123925Sgibbs bit DI_2840 0x01 109223925Sgibbs} 109323925Sgibbs 109423925Sgibbs/* --------------------- AIC-7870-only definitions -------------------- */ 109523925Sgibbs 109639220Sgibbsregister CCHADDR { 109739220Sgibbs address 0x0E0 109839220Sgibbs size 8 109939220Sgibbs} 110039220Sgibbs 110139220Sgibbsregister CCHCNT { 110239220Sgibbs address 0x0E8 110339220Sgibbs} 110439220Sgibbs 110539220Sgibbsregister CCSGRAM { 110639220Sgibbs address 0x0E9 110739220Sgibbs} 110839220Sgibbs 110939220Sgibbsregister CCSGADDR { 111039220Sgibbs address 0x0EA 111139220Sgibbs} 111239220Sgibbs 111339220Sgibbsregister CCSGCTL { 111439220Sgibbs address 0x0EB 111539220Sgibbs bit CCSGDONE 0x80 111639220Sgibbs bit CCSGEN 0x08 111763457Sgibbs bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 111839220Sgibbs bit CCSGRESET 0x01 111939220Sgibbs} 112039220Sgibbs 112139220Sgibbsregister CCSCBCNT { 112239220Sgibbs address 0xEF 112339220Sgibbs} 112439220Sgibbs 112539220Sgibbsregister CCSCBCTL { 112639220Sgibbs address 0x0EE 112739220Sgibbs bit CCSCBDONE 0x80 112839220Sgibbs bit ARRDONE 0x40 /* SCB Array prefetch done */ 112939220Sgibbs bit CCARREN 0x10 113039220Sgibbs bit CCSCBEN 0x08 113139220Sgibbs bit CCSCBDIR 0x04 113239220Sgibbs bit CCSCBRESET 0x01 113339220Sgibbs} 113439220Sgibbs 113539220Sgibbsregister CCSCBADDR { 113639220Sgibbs address 0x0ED 113739220Sgibbs} 113839220Sgibbs 113939220Sgibbsregister CCSCBRAM { 114039220Sgibbs address 0xEC 114139220Sgibbs} 114239220Sgibbs 114339220Sgibbs/* 114439220Sgibbs * SCB bank address (7895/7896/97 only) 114539220Sgibbs */ 114639220Sgibbsregister SCBBADDR { 114739220Sgibbs address 0x0F0 114839220Sgibbs access_mode RW 114939220Sgibbs} 115039220Sgibbs 115139220Sgibbsregister CCSCBPTR { 115239220Sgibbs address 0x0F1 115339220Sgibbs} 115439220Sgibbs 115539220Sgibbsregister HNSCB_QOFF { 115639220Sgibbs address 0x0F4 115739220Sgibbs} 115839220Sgibbs 115939220Sgibbsregister SNSCB_QOFF { 116039220Sgibbs address 0x0F6 116139220Sgibbs} 116239220Sgibbs 116339220Sgibbsregister SDSCB_QOFF { 116439220Sgibbs address 0x0F8 116539220Sgibbs} 116639220Sgibbs 116739220Sgibbsregister QOFF_CTLSTA { 116839220Sgibbs address 0x0FA 116939220Sgibbs bit SCB_AVAIL 0x40 117039220Sgibbs bit SNSCB_ROLLOVER 0x20 117139220Sgibbs bit SDSCB_ROLLOVER 0x10 117239220Sgibbs mask SCB_QSIZE 0x07 117339220Sgibbs mask SCB_QSIZE_256 0x06 117439220Sgibbs} 117539220Sgibbs 117639220Sgibbsregister DFF_THRSH { 117739220Sgibbs address 0x0FB 117839220Sgibbs mask WR_DFTHRSH 0x70 117939220Sgibbs mask RD_DFTHRSH 0x07 118039220Sgibbs mask RD_DFTHRSH_MIN 0x00 118139220Sgibbs mask RD_DFTHRSH_25 0x01 118239220Sgibbs mask RD_DFTHRSH_50 0x02 118339220Sgibbs mask RD_DFTHRSH_63 0x03 118439220Sgibbs mask RD_DFTHRSH_75 0x04 118539220Sgibbs mask RD_DFTHRSH_85 0x05 118639220Sgibbs mask RD_DFTHRSH_90 0x06 118739220Sgibbs mask RD_DFTHRSH_MAX 0x07 118839220Sgibbs mask WR_DFTHRSH_MIN 0x00 118939220Sgibbs mask WR_DFTHRSH_25 0x10 119039220Sgibbs mask WR_DFTHRSH_50 0x20 119139220Sgibbs mask WR_DFTHRSH_63 0x30 119239220Sgibbs mask WR_DFTHRSH_75 0x40 119339220Sgibbs mask WR_DFTHRSH_85 0x50 119439220Sgibbs mask WR_DFTHRSH_90 0x60 119539220Sgibbs mask WR_DFTHRSH_MAX 0x70 119639220Sgibbs} 119739220Sgibbs 119863457Sgibbsregister SG_CACHE_PRE { 119963457Sgibbs access_mode WO 120039220Sgibbs address 0x0fc 120163457Sgibbs mask SG_ADDR_MASK 0xf8 120263457Sgibbs bit ODD_SEG 0x04 120339220Sgibbs bit LAST_SEG 0x02 120439220Sgibbs bit LAST_SEG_DONE 0x01 120539220Sgibbs} 120639220Sgibbs 120763457Sgibbsregister SG_CACHE_SHADOW { 120863457Sgibbs access_mode RO 120963457Sgibbs address 0x0fc 121063457Sgibbs mask SG_ADDR_MASK 0xf8 121163457Sgibbs bit ODD_SEG 0x04 121263457Sgibbs bit LAST_SEG 0x02 121363457Sgibbs bit LAST_SEG_DONE 0x01 121463457Sgibbs} 121523925Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 121623925Sgibbs/* These offsets are either to values that are initialized by the board's 121723925Sgibbs * BIOS or are specified by the sequencer code. 121823925Sgibbs * 121923925Sgibbs * The host adapter card (at least the BIOS) uses 20-2f for SCSI 122023925Sgibbs * device information, 32-33 and 5a-5f as well. As it turns out, the 122123925Sgibbs * BIOS trashes 20-2f, writing the synchronous negotiation results 122223925Sgibbs * on top of the BIOS values, so we re-use those for our per-target 122323925Sgibbs * scratchspace (actually a value that can be copied directly into 122423925Sgibbs * SCSIRATE). The kernel driver will enable synchronous negotiation 122523925Sgibbs * for all targets that have a value other than 0 in the lower four 122623925Sgibbs * bits of the target scratch space. This should work regardless of 122723925Sgibbs * whether the bios has been installed. 122823925Sgibbs */ 122923925Sgibbs 123023925Sgibbsscratch_ram { 123123925Sgibbs address 0x020 123223925Sgibbs 123323925Sgibbs /* 123423925Sgibbs * 1 byte per target starting at this address for configuration values 123523925Sgibbs */ 123663457Sgibbs CMDSIZE_TABLE { 123763457Sgibbs alias TARG_SCSIRATE 123863457Sgibbs size 8 123963457Sgibbs } 124063457Sgibbs BUSY_TARGETS { 124168087Sgibbs size 8 124223925Sgibbs } 124339220Sgibbs /* 124468087Sgibbs * Bit vector of targets that have ULTRA enabled as set by 124568087Sgibbs * the BIOS. The Sequencer relies on a per-SCB field to 124668087Sgibbs * control whether to enable Ultra transfers or not. During 124768087Sgibbs * initialization, we read this field and reuse it for 2 124868087Sgibbs * entries in the busy target table. 124968087Sgibbs */ 125068087Sgibbs ULTRA_ENB { 125168087Sgibbs size 2 125268087Sgibbs } 125368087Sgibbs /* 125468087Sgibbs * Bit vector of targets that have disconnection disabled as set by 125568087Sgibbs * the BIOS. The Sequencer relies in a per-SCB field to control the 125668087Sgibbs * disconnect priveldge. During initialization, we read this field 125768087Sgibbs * and reuse it for 2 entries in the busy target table. 125868087Sgibbs */ 125968087Sgibbs DISC_DSB { 126068087Sgibbs size 2 126168087Sgibbs } 126268087Sgibbs BUSY_TARGETS_TAIL { 126368087Sgibbs size 4 126468087Sgibbs } 126568087Sgibbs /* 126666647Sgibbs * Partial transfer past cacheline end to be 126766647Sgibbs * transferred using an extra S/G. 126839220Sgibbs */ 126966647Sgibbs MWI_RESIDUAL { 127066647Sgibbs size 1 127123925Sgibbs } 127223925Sgibbs /* 127366647Sgibbs * SCBID of the next SCB to be started by the controller. 127466647Sgibbs */ 127566647Sgibbs NEXT_QUEUED_SCB { 127666647Sgibbs size 1 127766647Sgibbs } 127866647Sgibbs /* 127939220Sgibbs * Single byte buffer used to designate the type or message 128039220Sgibbs * to send to a target. 128123925Sgibbs */ 128239220Sgibbs MSG_OUT { 128323925Sgibbs size 1 128423925Sgibbs } 128523925Sgibbs /* Parameters for DMA Logic */ 128623925Sgibbs DMAPARAMS { 128723925Sgibbs size 1 128839220Sgibbs bit PRELOADEN 0x80 128923925Sgibbs bit WIDEODD 0x40 129023925Sgibbs bit SCSIEN 0x20 129123925Sgibbs bit SDMAEN 0x10 129223925Sgibbs bit SDMAENACK 0x10 129323925Sgibbs bit HDMAEN 0x08 129423925Sgibbs bit HDMAENACK 0x08 129523925Sgibbs bit DIRECTION 0x04 129623925Sgibbs bit FIFOFLUSH 0x02 129723925Sgibbs bit FIFORESET 0x01 129823925Sgibbs } 129923925Sgibbs SEQ_FLAGS { 130023925Sgibbs size 1 130139220Sgibbs bit IDENTIFY_SEEN 0x80 130263457Sgibbs bit TARGET_CMD_IS_TAGGED 0x40 130339220Sgibbs bit DPHASE 0x20 130439220Sgibbs /* Target flags */ 130539220Sgibbs bit TARG_CMD_PENDING 0x10 130639220Sgibbs bit CMDPHASE_PENDING 0x08 130739220Sgibbs bit DPHASE_PENDING 0x04 130839220Sgibbs bit SPHASE_PENDING 0x02 130939220Sgibbs bit NO_DISCONNECT 0x01 131023925Sgibbs } 131123925Sgibbs /* 131223925Sgibbs * Temporary storage for the 131323925Sgibbs * target/channel/lun of a 131423925Sgibbs * reconnecting target 131523925Sgibbs */ 131663457Sgibbs SAVED_SCSIID { 131723925Sgibbs size 1 131823925Sgibbs } 131963457Sgibbs SAVED_LUN { 132023925Sgibbs size 1 132123925Sgibbs } 132223925Sgibbs /* 132323925Sgibbs * The last bus phase as seen by the sequencer. 132423925Sgibbs */ 132523925Sgibbs LASTPHASE { 132623925Sgibbs size 1 132723925Sgibbs bit CDI 0x80 132823925Sgibbs bit IOI 0x40 132923925Sgibbs bit MSGI 0x20 133023925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 133123925Sgibbs mask P_DATAOUT 0x00 133223925Sgibbs mask P_DATAIN IOI 133323925Sgibbs mask P_COMMAND CDI 133423925Sgibbs mask P_MESGOUT CDI|MSGI 133523925Sgibbs mask P_STATUS CDI|IOI 133623925Sgibbs mask P_MESGIN CDI|IOI|MSGI 133723925Sgibbs mask P_BUSFREE 0x01 133823925Sgibbs } 133923925Sgibbs /* 134039220Sgibbs * head of list of SCBs awaiting 134139220Sgibbs * selection 134223925Sgibbs */ 134339220Sgibbs WAITING_SCBH { 134439220Sgibbs size 1 134523925Sgibbs } 134623925Sgibbs /* 134723925Sgibbs * head of list of SCBs that are 134823925Sgibbs * disconnected. Used for SCB 134923925Sgibbs * paging. 135023925Sgibbs */ 135123925Sgibbs DISCONNECTED_SCBH { 135223925Sgibbs size 1 135323925Sgibbs } 135423925Sgibbs /* 135523925Sgibbs * head of list of SCBs that are 135623925Sgibbs * not in use. Used for SCB paging. 135723925Sgibbs */ 135823925Sgibbs FREE_SCBH { 135923925Sgibbs size 1 136023925Sgibbs } 136139220Sgibbs /* 136239220Sgibbs * Address of the hardware scb array in the host. 136339220Sgibbs */ 136423925Sgibbs HSCB_ADDR { 136523925Sgibbs size 4 136623925Sgibbs } 136739220Sgibbs /* 136863457Sgibbs * Base address of our shared data with the kernel driver in host 136966647Sgibbs * memory. This includes the qoutfifo and target mode 137063457Sgibbs * incoming command queue. 137139220Sgibbs */ 137263457Sgibbs SHARED_DATA_ADDR { 137339220Sgibbs size 4 137439220Sgibbs } 137539220Sgibbs KERNEL_QINPOS { 137623925Sgibbs size 1 137723925Sgibbs } 137839220Sgibbs QINPOS { 137939220Sgibbs size 1 138039220Sgibbs } 138139220Sgibbs QOUTPOS { 138239220Sgibbs size 1 138339220Sgibbs } 138428169Sgibbs /* 138541299Sgibbs * Kernel and sequencer offsets into the queue of 138641299Sgibbs * incoming target mode command descriptors. The 138744507Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 138828169Sgibbs */ 138941299Sgibbs KERNEL_TQINPOS { 139028169Sgibbs size 1 139128169Sgibbs } 139241299Sgibbs TQINPOS { 139341299Sgibbs size 1 139441299Sgibbs } 139523925Sgibbs ARG_1 { 139623925Sgibbs size 1 139741646Sgibbs mask SEND_MSG 0x80 139841646Sgibbs mask SEND_SENSE 0x40 139941646Sgibbs mask SEND_REJ 0x20 140041646Sgibbs mask MSGOUT_PHASEMIS 0x10 140141646Sgibbs mask EXIT_MSG_LOOP 0x08 140241646Sgibbs mask CONT_MSG_LOOP 0x04 140341646Sgibbs mask CONT_TARG_SESSION 0x02 140423925Sgibbs alias RETURN_1 140523925Sgibbs } 140639220Sgibbs ARG_2 { 140739220Sgibbs size 1 140839220Sgibbs alias RETURN_2 140939220Sgibbs } 141039220Sgibbs 141123925Sgibbs /* 141239220Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 141339220Sgibbs */ 141439220Sgibbs LAST_MSG { 141539220Sgibbs size 1 141639220Sgibbs } 141739220Sgibbs 141839220Sgibbs /* 141941646Sgibbs * Interrupt kernel for a message to this target on 142041646Sgibbs * the next transaction. This is usually used for 142141646Sgibbs * negotiation requests. 142241646Sgibbs */ 142341646Sgibbs TARGET_MSG_REQUEST { 142441646Sgibbs size 2 142541646Sgibbs } 142639220Sgibbs 142739220Sgibbs /* 142841816Sgibbs * Sequences the kernel driver has okayed for us. This allows 142941816Sgibbs * the driver to do things like prevent initiator or target 143041816Sgibbs * operations. 143141816Sgibbs */ 143241816Sgibbs SCSISEQ_TEMPLATE { 143341816Sgibbs size 1 143441816Sgibbs bit ENSELO 0x40 143541816Sgibbs bit ENSELI 0x20 143641816Sgibbs bit ENRSELI 0x10 143741816Sgibbs bit ENAUTOATNO 0x08 143841816Sgibbs bit ENAUTOATNI 0x04 143941816Sgibbs bit ENAUTOATNP 0x02 144041816Sgibbs } 144141816Sgibbs 144241816Sgibbs /* 144342652Sgibbs * Track whether the transfer byte count for 144442652Sgibbs * the current data phase is odd. 144542652Sgibbs */ 144642652Sgibbs DATA_COUNT_ODD { 144742652Sgibbs size 1 144842652Sgibbs } 144942652Sgibbs 145042652Sgibbs /* 145142652Sgibbs * The initiator specified tag for this target mode transaction. 145242652Sgibbs */ 145342652Sgibbs INITIATOR_TAG { 145442652Sgibbs size 1 145542652Sgibbs } 145642652Sgibbs 145742652Sgibbs /* 145823925Sgibbs * These are reserved registers in the card's scratch ram. Some of 145923925Sgibbs * the values are specified in the AHA2742 technical reference manual 146023925Sgibbs * and are initialized by the BIOS at boot time. 146123925Sgibbs */ 146223925Sgibbs SCSICONF { 146323925Sgibbs address 0x05a 146423925Sgibbs size 1 146539220Sgibbs bit TERM_ENB 0x80 146623925Sgibbs bit RESET_SCSI 0x40 146754211Sgibbs bit ENSPCHK 0x20 146839220Sgibbs mask HSCSIID 0x07 /* our SCSI ID */ 146939220Sgibbs mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 147023925Sgibbs } 147165953Sgibbs INTDEF { 147265953Sgibbs address 0x05c 147365953Sgibbs size 1 147465953Sgibbs bit EDGE_TRIG 0x80 147565953Sgibbs mask VECTOR 0x0f 147665953Sgibbs } 147723925Sgibbs HOSTCONF { 147823925Sgibbs address 0x05d 147923925Sgibbs size 1 148023925Sgibbs } 148123925Sgibbs HA_274_BIOSCTRL { 148223925Sgibbs address 0x05f 148323925Sgibbs size 1 148423925Sgibbs mask BIOSMODE 0x30 148523925Sgibbs mask BIOSDISABLED 0x30 148623925Sgibbs bit CHANNEL_B_PRIMARY 0x08 148723925Sgibbs } 148839220Sgibbs /* 148939220Sgibbs * Per target SCSI offset values for Ultra2 controllers. 149039220Sgibbs */ 149139220Sgibbs TARG_OFFSET { 149239220Sgibbs address 0x070 149339220Sgibbs size 16 149439220Sgibbs } 149523925Sgibbs} 149623925Sgibbs 149763457Sgibbsconst TID_SHIFT 4 149823925Sgibbsconst SCB_LIST_NULL 0xff 149939220Sgibbsconst TARGET_CMD_CMPLT 0xfe 150023925Sgibbs 150139220Sgibbsconst CCSGADDR_MAX 0x80 150239220Sgibbsconst CCSGRAM_MAXSEGS 16 150323925Sgibbs 150423925Sgibbs/* WDTR Message values */ 150539220Sgibbsconst BUS_8_BIT 0x00 150623925Sgibbsconst BUS_16_BIT 0x01 150723925Sgibbsconst BUS_32_BIT 0x02 150839220Sgibbs 150939220Sgibbs/* Offset maximums */ 151023925Sgibbsconst MAX_OFFSET_8BIT 0x0f 151139220Sgibbsconst MAX_OFFSET_16BIT 0x08 151239220Sgibbsconst MAX_OFFSET_ULTRA2 0x7f 151339220Sgibbsconst HOST_MSG 0xff 151429897Sgibbs 151539220Sgibbs/* Target mode command processing constants */ 151639220Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 151739220Sgibbs 151844507Sgibbsconst STATUS_BUSY 0x08 151963457Sgibbsconst STATUS_QUEUE_FULL 0x28 152063457Sgibbsconst SCB_TARGET_PHASES 0 152163457Sgibbsconst SCB_TARGET_DATA_DIR 1 152263457Sgibbsconst SCB_TARGET_STATUS 2 152363457Sgibbsconst SCB_INITIATOR_TAG 3 152463457Sgibbsconst TARGET_DATA_IN 1 152544507Sgibbs 152629897Sgibbs/* 152729897Sgibbs * Downloaded (kernel inserted) constants 152829897Sgibbs */ 152963457Sgibbs/* Offsets into the SCBID array where different data is stored */ 153063457Sgibbsconst QOUTFIFO_OFFSET download 153163457Sgibbsconst QINFIFO_OFFSET download 153265948Sgibbsconst CACHESIZE_MASK download 153365948Sgibbsconst INVERTED_CACHESIZE_MASK download 153466647Sgibbsconst SG_PREFETCH_CNT download 153566647Sgibbsconst SG_PREFETCH_ALIGN_MASK download 153666647Sgibbsconst SG_PREFETCH_ADDR_MASK download 1537