aic7xxx.reg revision 65942
1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2000 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id$ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 65942 2000-09-16 20:02:28Z gibbs $ 34 */ 35 36/* 37 * This file is processed by the aic7xxx_asm utility for use in assembling 38 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 39 * a C header file for use in the kernel portion of the Aic7xxx driver. 40 * 41 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 42 * Adaptec's Technical Documents Department 1-800-934-2766 43 */ 44 45/* 46 * SCSI Sequence Control (p. 3-11). 47 * Each bit, when set starts a specific SCSI sequence on the bus 48 */ 49register SCSISEQ { 50 address 0x000 51 access_mode RW 52 bit TEMODE 0x80 53 bit ENSELO 0x40 54 bit ENSELI 0x20 55 bit ENRSELI 0x10 56 bit ENAUTOATNO 0x08 57 bit ENAUTOATNI 0x04 58 bit ENAUTOATNP 0x02 59 bit SCSIRSTO 0x01 60} 61 62/* 63 * SCSI Transfer Control 0 Register (pp. 3-13). 64 * Controls the SCSI module data path. 65 */ 66register SXFRCTL0 { 67 address 0x001 68 access_mode RW 69 bit DFON 0x80 70 bit DFPEXP 0x40 71 bit FAST20 0x20 72 bit CLRSTCNT 0x10 73 bit SPIOEN 0x08 74 bit SCAMEN 0x04 75 bit CLRCHN 0x02 76} 77 78/* 79 * SCSI Transfer Control 1 Register (pp. 3-14,15). 80 * Controls the SCSI module data path. 81 */ 82register SXFRCTL1 { 83 address 0x002 84 access_mode RW 85 bit BITBUCKET 0x80 86 bit SWRAPEN 0x40 87 bit ENSPCHK 0x20 88 mask STIMESEL 0x18 89 bit ENSTIMER 0x04 90 bit ACTNEGEN 0x02 91 bit STPWEN 0x01 /* Powered Termination */ 92} 93 94/* 95 * SCSI Control Signal Read Register (p. 3-15). 96 * Reads the actual state of the SCSI bus pins 97 */ 98register SCSISIGI { 99 address 0x003 100 access_mode RO 101 bit CDI 0x80 102 bit IOI 0x40 103 bit MSGI 0x20 104 bit ATNI 0x10 105 bit SELI 0x08 106 bit BSYI 0x04 107 bit REQI 0x02 108 bit ACKI 0x01 109/* 110 * Possible phases in SCSISIGI 111 */ 112 mask PHASE_MASK CDI|IOI|MSGI 113 mask P_DATAOUT 0x00 114 mask P_DATAIN IOI 115 mask P_COMMAND CDI 116 mask P_MESGOUT CDI|MSGI 117 mask P_STATUS CDI|IOI 118 mask P_MESGIN CDI|IOI|MSGI 119} 120 121/* 122 * SCSI Control Signal Write Register (p. 3-16). 123 * Writing to this register modifies the control signals on the bus. Only 124 * those signals that are allowed in the current mode (Initiator/Target) are 125 * asserted. 126 */ 127register SCSISIGO { 128 address 0x003 129 access_mode WO 130 bit CDO 0x80 131 bit IOO 0x40 132 bit MSGO 0x20 133 bit ATNO 0x10 134 bit SELO 0x08 135 bit BSYO 0x04 136 bit REQO 0x02 137 bit ACKO 0x01 138/* 139 * Possible phases to write into SCSISIG0 140 */ 141 mask PHASE_MASK CDI|IOI|MSGI 142 mask P_DATAOUT 0x00 143 mask P_DATAIN IOI 144 mask P_COMMAND CDI 145 mask P_MESGOUT CDI|MSGI 146 mask P_STATUS CDI|IOI 147 mask P_MESGIN CDI|IOI|MSGI 148} 149 150/* 151 * SCSI Rate Control (p. 3-17). 152 * Contents of this register determine the Synchronous SCSI data transfer 153 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 154 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 155 * greater than 0 enables synchronous transfers. 156 */ 157register SCSIRATE { 158 address 0x004 159 access_mode RW 160 bit WIDEXFER 0x80 /* Wide transfer control */ 161 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 162 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 163 mask SXFR 0x70 /* Sync transfer rate */ 164 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 165 mask SOFS 0x0f /* Sync offset */ 166} 167 168/* 169 * SCSI ID (p. 3-18). 170 * Contains the ID of the board and the current target on the 171 * selected channel. 172 */ 173register SCSIID { 174 address 0x005 175 access_mode RW 176 mask TID 0xf0 /* Target ID mask */ 177 mask TWIN_TID 0x70 178 bit TWIN_CHNLB 0x80 179 mask OID 0x0f /* Our ID mask */ 180 /* 181 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 182 * The aic7890/91 allow an offset of up to 127 transfers in both wide 183 * and narrow mode. 184 */ 185 alias SCSIOFFSET 186 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 187} 188 189/* 190 * SCSI Latched Data (p. 3-19). 191 * Read/Write latches used to transfer data on the SCSI bus during 192 * Automatic or Manual PIO mode. SCSIDATH can be used for the 193 * upper byte of a 16bit wide asynchronouse data phase transfer. 194 */ 195register SCSIDATL { 196 address 0x006 197 access_mode RW 198} 199 200register SCSIDATH { 201 address 0x007 202 access_mode RW 203} 204 205/* 206 * SCSI Transfer Count (pp. 3-19,20) 207 * These registers count down the number of bytes transferred 208 * across the SCSI bus. The counter is decremented only once 209 * the data has been safely transferred. SDONE in SSTAT0 is 210 * set when STCNT goes to 0 211 */ 212register STCNT { 213 address 0x008 214 size 3 215 access_mode RW 216} 217 218/* ALT_MODE register on Ultra160 chips */ 219register OPTIONMODE { 220 address 0x008 221 access_mode RW 222 bit AUTORATEEN 0x80 223 bit AUTOACKEN 0x40 224 bit ATNMGMNTEN 0x20 225 bit BUSFREEREV 0x10 226 bit EXPPHASEDIS 0x08 227 bit SCSIDATL_IMGEN 0x04 228 bit AUTO_MSGOUT_DE 0x02 229 bit DIS_MSGIN_DUALEDGE 0x01 230 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 231} 232 233/* ALT_MODE register on Ultra160 chips */ 234register TARGCRCCNT { 235 address 0x00a 236 size 2 237 access_mode RW 238} 239 240/* 241 * Clear SCSI Interrupt 0 (p. 3-20) 242 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 243 */ 244register CLRSINT0 { 245 address 0x00b 246 access_mode WO 247 bit CLRSELDO 0x40 248 bit CLRSELDI 0x20 249 bit CLRSELINGO 0x10 250 bit CLRSWRAP 0x08 251 bit CLRSPIORDY 0x02 252} 253 254/* 255 * SCSI Status 0 (p. 3-21) 256 * Contains one set of SCSI Interrupt codes 257 * These are most likely of interest to the sequencer 258 */ 259register SSTAT0 { 260 address 0x00b 261 access_mode RO 262 bit TARGET 0x80 /* Board acting as target */ 263 bit SELDO 0x40 /* Selection Done */ 264 bit SELDI 0x20 /* Board has been selected */ 265 bit SELINGO 0x10 /* Selection In Progress */ 266 bit SWRAP 0x08 /* 24bit counter wrap */ 267 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 268 bit SDONE 0x04 /* STCNT = 0x000000 */ 269 bit SPIORDY 0x02 /* SCSI PIO Ready */ 270 bit DMADONE 0x01 /* DMA transfer completed */ 271} 272 273/* 274 * Clear SCSI Interrupt 1 (p. 3-23) 275 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 276 */ 277register CLRSINT1 { 278 address 0x00c 279 access_mode WO 280 bit CLRSELTIMEO 0x80 281 bit CLRATNO 0x40 282 bit CLRSCSIRSTI 0x20 283 bit CLRBUSFREE 0x08 284 bit CLRSCSIPERR 0x04 285 bit CLRPHASECHG 0x02 286 bit CLRREQINIT 0x01 287} 288 289/* 290 * SCSI Status 1 (p. 3-24) 291 */ 292register SSTAT1 { 293 address 0x00c 294 access_mode RO 295 bit SELTO 0x80 296 bit ATNTARG 0x40 297 bit SCSIRSTI 0x20 298 bit PHASEMIS 0x10 299 bit BUSFREE 0x08 300 bit SCSIPERR 0x04 301 bit PHASECHG 0x02 302 bit REQINIT 0x01 303} 304 305/* 306 * SCSI Status 2 (pp. 3-25,26) 307 */ 308register SSTAT2 { 309 address 0x00d 310 access_mode RO 311 bit OVERRUN 0x80 312 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 313 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 314 mask SFCNT 0x1f 315} 316 317/* 318 * SCSI Status 3 (p. 3-26) 319 */ 320register SSTAT3 { 321 address 0x00e 322 access_mode RO 323 mask SCSICNT 0xf0 324 mask OFFCNT 0x0f 325} 326 327/* 328 * SCSI ID for the aic7890/91 chips 329 */ 330register SCSIID_ULTRA2 { 331 address 0x00f 332 access_mode RW 333 mask TID 0xf0 /* Target ID mask */ 334 mask OID 0x0f /* Our ID mask */ 335} 336 337/* 338 * SCSI Interrupt Mode 1 (p. 3-28) 339 * Setting any bit will enable the corresponding function 340 * in SIMODE0 to interrupt via the IRQ pin. 341 */ 342register SIMODE0 { 343 address 0x010 344 access_mode RW 345 bit ENSELDO 0x40 346 bit ENSELDI 0x20 347 bit ENSELINGO 0x10 348 bit ENSWRAP 0x08 349 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 350 bit ENSDONE 0x04 351 bit ENSPIORDY 0x02 352 bit ENDMADONE 0x01 353} 354 355/* 356 * SCSI Interrupt Mode 1 (pp. 3-28,29) 357 * Setting any bit will enable the corresponding function 358 * in SIMODE1 to interrupt via the IRQ pin. 359 */ 360register SIMODE1 { 361 address 0x011 362 access_mode RW 363 bit ENSELTIMO 0x80 364 bit ENATNTARG 0x40 365 bit ENSCSIRST 0x20 366 bit ENPHASEMIS 0x10 367 bit ENBUSFREE 0x08 368 bit ENSCSIPERR 0x04 369 bit ENPHASECHG 0x02 370 bit ENREQINIT 0x01 371} 372 373/* 374 * SCSI Data Bus (High) (p. 3-29) 375 * This register reads data on the SCSI Data bus directly. 376 */ 377register SCSIBUSL { 378 address 0x012 379 access_mode RO 380} 381 382register SCSIBUSH { 383 address 0x013 384 access_mode RO 385} 386 387/* 388 * SCSI/Host Address (p. 3-30) 389 * These registers hold the host address for the byte about to be 390 * transferred on the SCSI bus. They are counted up in the same 391 * manner as STCNT is counted down. SHADDR should always be used 392 * to determine the address of the last byte transferred since HADDR 393 * can be skewed by write ahead. 394 */ 395register SHADDR { 396 address 0x014 397 size 4 398 access_mode RO 399} 400 401/* 402 * Selection Timeout Timer (p. 3-30) 403 */ 404register SELTIMER { 405 address 0x018 406 access_mode RW 407 bit STAGE6 0x20 408 bit STAGE5 0x10 409 bit STAGE4 0x08 410 bit STAGE3 0x04 411 bit STAGE2 0x02 412 bit STAGE1 0x01 413 alias TARGIDIN 414} 415 416/* 417 * Selection/Reselection ID (p. 3-31) 418 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 419 * device did not set its own ID. 420 */ 421register SELID { 422 address 0x019 423 access_mode RW 424 mask SELID_MASK 0xf0 425 bit ONEBIT 0x08 426} 427 428register SCAMCTL { 429 address 0x01a 430 access_mode RW 431 bit ENSCAMSELO 0x80 432 bit CLRSCAMSELID 0x40 433 bit ALTSTIM 0x20 434 bit DFLTTID 0x10 435 mask SCAMLVL 0x03 436} 437 438/* 439 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 440 */ 441register TARGID { 442 address 0x01b 443 size 2 444 access_mode RW 445} 446 447/* 448 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 449 * Indicates if external logic has been attached to the chip to 450 * perform the tasks of accessing a serial eeprom, testing termination 451 * strength, and performing cable detection. On the aic7860, most of 452 * these features are handled on chip, but on the aic7855 an attached 453 * aic3800 does the grunt work. 454 */ 455register SPIOCAP { 456 address 0x01b 457 access_mode RW 458 bit SOFT1 0x80 459 bit SOFT0 0x40 460 bit SOFTCMDEN 0x20 461 bit HAS_BRDCTL 0x10 /* External Board control */ 462 bit SEEPROM 0x08 /* External serial eeprom logic */ 463 bit EEPROM 0x04 /* Writable external BIOS ROM */ 464 bit ROM 0x02 /* Logic for accessing external ROM */ 465 bit SSPIOCPS 0x01 /* Termination and cable detection */ 466} 467 468register BRDCTL { 469 address 0x01d 470 bit BRDDAT7 0x80 471 bit BRDDAT6 0x40 472 bit BRDDAT5 0x20 473 bit BRDSTB 0x10 474 bit BRDCS 0x08 475 bit BRDRW 0x04 476 bit BRDCTL1 0x02 477 bit BRDCTL0 0x01 478 /* 7890 Definitions */ 479 bit BRDDAT4 0x10 480 bit BRDDAT3 0x08 481 bit BRDDAT2 0x04 482 bit BRDRW_ULTRA2 0x02 483 bit BRDSTB_ULTRA2 0x01 484} 485 486/* 487 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 488 * Controls the reading and writing of an external serial 1-bit 489 * EEPROM Device. In order to access the serial EEPROM, you must 490 * first set the SEEMS bit that generates a request to the memory 491 * port for access to the serial EEPROM device. When the memory 492 * port is not busy servicing another request, it reconfigures 493 * to allow access to the serial EEPROM. When this happens, SEERDY 494 * gets set high to verify that the memory port access has been 495 * granted. 496 * 497 * After successful arbitration for the memory port, the SEECS bit of 498 * the SEECTL register is connected to the chip select. The SEECK, 499 * SEEDO, and SEEDI are connected to the clock, data out, and data in 500 * lines respectively. The SEERDY bit of SEECTL is useful in that it 501 * gives us an 800 nsec timer. After a write to the SEECTL register, 502 * the SEERDY goes high 800 nsec later. The one exception to this is 503 * when we first request access to the memory port. The SEERDY goes 504 * high to signify that access has been granted and, for this case, has 505 * no implied timing. 506 * 507 * See 93cx6.c for detailed information on the protocol necessary to 508 * read the serial EEPROM. 509 */ 510register SEECTL { 511 address 0x01e 512 bit EXTARBACK 0x80 513 bit EXTARBREQ 0x40 514 bit SEEMS 0x20 515 bit SEERDY 0x10 516 bit SEECS 0x08 517 bit SEECK 0x04 518 bit SEEDO 0x02 519 bit SEEDI 0x01 520} 521/* 522 * SCSI Block Control (p. 3-32) 523 * Controls Bus type and channel selection. In a twin channel configuration 524 * addresses 0x00-0x1e are gated to the appropriate channel based on this 525 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 526 * on a wide bus. 527 */ 528register SBLKCTL { 529 address 0x01f 530 access_mode RW 531 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 532 bit DIAGLEDON 0x40 /* Aic78X0 only */ 533 bit AUTOFLUSHDIS 0x20 534 bit SELBUSB 0x08 535 bit ENAB40 0x08 /* LVD transceiver active */ 536 bit ENAB20 0x04 /* SE/HVD transceiver active */ 537 bit SELWIDE 0x02 538 bit XCVR 0x01 /* External transceiver active */ 539} 540 541/* 542 * Sequencer Control (p. 3-33) 543 * Error detection mode and speed configuration 544 */ 545register SEQCTL { 546 address 0x060 547 access_mode RW 548 bit PERRORDIS 0x80 549 bit PAUSEDIS 0x40 550 bit FAILDIS 0x20 551 bit FASTMODE 0x10 552 bit BRKADRINTEN 0x08 553 bit STEP 0x04 554 bit SEQRESET 0x02 555 bit LOADRAM 0x01 556} 557 558/* 559 * Sequencer RAM Data (p. 3-34) 560 * Single byte window into the Scratch Ram area starting at the address 561 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 562 * four bytes in succession. The SEQADDRs will increment after the most 563 * significant byte is written 564 */ 565register SEQRAM { 566 address 0x061 567 access_mode RW 568} 569 570/* 571 * Sequencer Address Registers (p. 3-35) 572 * Only the first bit of SEQADDR1 holds addressing information 573 */ 574register SEQADDR0 { 575 address 0x062 576 access_mode RW 577} 578 579register SEQADDR1 { 580 address 0x063 581 access_mode RW 582 mask SEQADDR1_MASK 0x01 583} 584 585/* 586 * Accumulator 587 * We cheat by passing arguments in the Accumulator up to the kernel driver 588 */ 589register ACCUM { 590 address 0x064 591 access_mode RW 592 accumulator 593} 594 595register SINDEX { 596 address 0x065 597 access_mode RW 598 sindex 599} 600 601register DINDEX { 602 address 0x066 603 access_mode RW 604} 605 606register ALLONES { 607 address 0x069 608 access_mode RO 609 allones 610} 611 612register ALLZEROS { 613 address 0x06a 614 access_mode RO 615 allzeros 616} 617 618register NONE { 619 address 0x06a 620 access_mode WO 621 none 622} 623 624register FLAGS { 625 address 0x06b 626 access_mode RO 627 bit ZERO 0x02 628 bit CARRY 0x01 629} 630 631register SINDIR { 632 address 0x06c 633 access_mode RO 634} 635 636register DINDIR { 637 address 0x06d 638 access_mode WO 639} 640 641register FUNCTION1 { 642 address 0x06e 643 access_mode RW 644} 645 646register STACK { 647 address 0x06f 648 access_mode RO 649} 650 651/* 652 * Board Control (p. 3-43) 653 */ 654register BCTL { 655 address 0x084 656 access_mode RW 657 bit ACE 0x08 658 bit ENABLE 0x01 659} 660 661/* 662 * On the aic78X0 chips, Board Control is replaced by the DSCommand 663 * register (p. 4-64) 664 */ 665register DSCOMMAND0 { 666 address 0x084 667 access_mode RW 668 bit CACHETHEN 0x80 /* Cache Threshold enable */ 669 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 670 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 671 bit EXTREQLCK 0x10 /* External Request Lock */ 672 /* aic7890/91/96/97 only */ 673 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 674 bit RAMPS 0x04 /* External SCB RAM Present */ 675 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 676 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 677} 678 679/* 680 * Bus On/Off Time (p. 3-44) 681 */ 682register BUSTIME { 683 address 0x085 684 access_mode RW 685 mask BOFF 0xf0 686 mask BON 0x0f 687} 688 689/* 690 * Bus Speed (p. 3-45) aic7770 only 691 */ 692register BUSSPD { 693 address 0x086 694 access_mode RW 695 mask DFTHRSH 0xc0 696 mask STBOFF 0x38 697 mask STBON 0x07 698 mask DFTHRSH_100 0xc0 699} 700 701/* aic7850/55/60/70/80/95 only */ 702register DSPCISTATUS { 703 address 0x086 704 mask DFTHRSH_100 0xc0 705} 706 707/* aic7890/91/96/97 only */ 708register HS_MAILBOX { 709 address 0x086 710 mask HOST_MAILBOX 0xF0 711 mask SEQ_MAILBOX 0x0F 712 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 713} 714 715const HOST_MAILBOX_SHIFT 4 716const SEQ_MAILBOX_SHIFT 0 717 718/* 719 * Host Control (p. 3-47) R/W 720 * Overall host control of the device. 721 */ 722register HCNTRL { 723 address 0x087 724 access_mode RW 725 bit POWRDN 0x40 726 bit SWINT 0x10 727 bit IRQMS 0x08 728 bit PAUSE 0x04 729 bit INTEN 0x02 730 bit CHIPRST 0x01 731 bit CHIPRSTACK 0x01 732} 733 734/* 735 * Host Address (p. 3-48) 736 * This register contains the address of the byte about 737 * to be transferred across the host bus. 738 */ 739register HADDR { 740 address 0x088 741 size 4 742 access_mode RW 743} 744 745register HCNT { 746 address 0x08c 747 size 3 748 access_mode RW 749} 750 751/* 752 * SCB Pointer (p. 3-49) 753 * Gate one of the SCBs into the SCBARRAY window. 754 */ 755register SCBPTR { 756 address 0x090 757 access_mode RW 758} 759 760/* 761 * Interrupt Status (p. 3-50) 762 * Status for system interrupts 763 */ 764register INTSTAT { 765 address 0x091 766 access_mode RW 767 bit BRKADRINT 0x08 768 bit SCSIINT 0x04 769 bit CMDCMPLT 0x02 770 bit SEQINT 0x01 771 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 772 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 773 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 774 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 775 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 776 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 777 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ 778 mask TRACEPOINT2 0x90|SEQINT 779 mask HOST_MSG_LOOP 0xa0|SEQINT /* 780 * The bus is ready for the 781 * host to perform another 782 * message transaction. This 783 * mechanism is used for things 784 * like sync/wide negotiation 785 * that require a kernel based 786 * message state engine. 787 */ 788 mask PERR_DETECTED 0xb0|SEQINT /* 789 * Either the phase_lock 790 * or inb_next routine has 791 * noticed a parity error. 792 */ 793 mask TRACEPOINT 0xd0|SEQINT 794 mask DATA_OVERRUN 0xf0|SEQINT /* 795 * Target attempted to write 796 * beyond the bounds of its 797 * command. 798 */ 799 800 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 801 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 802} 803 804/* 805 * Hard Error (p. 3-53) 806 * Reporting of catastrophic errors. You usually cannot recover from 807 * these without a full board reset. 808 */ 809register ERROR { 810 address 0x092 811 access_mode RO 812 bit CIOPARERR 0x80 /* Ultra2 only */ 813 bit PCIERRSTAT 0x40 /* PCI only */ 814 bit MPARERR 0x20 /* PCI only */ 815 bit DPARERR 0x10 /* PCI only */ 816 bit SQPARERR 0x08 817 bit ILLOPCODE 0x04 818 bit ILLSADDR 0x02 819 bit ILLHADDR 0x01 820} 821 822/* 823 * Clear Interrupt Status (p. 3-52) 824 */ 825register CLRINT { 826 address 0x092 827 access_mode WO 828 bit CLRPARERR 0x10 /* PCI only */ 829 bit CLRBRKADRINT 0x08 830 bit CLRSCSIINT 0x04 831 bit CLRCMDINT 0x02 832 bit CLRSEQINT 0x01 833} 834 835register DFCNTRL { 836 address 0x093 837 access_mode RW 838 bit PRELOADEN 0x80 /* aic7890 only */ 839 bit WIDEODD 0x40 840 bit SCSIEN 0x20 841 bit SDMAEN 0x10 842 bit SDMAENACK 0x10 843 bit HDMAEN 0x08 844 bit HDMAENACK 0x08 845 bit DIRECTION 0x04 846 bit FIFOFLUSH 0x02 847 bit FIFORESET 0x01 848} 849 850register DFSTATUS { 851 address 0x094 852 access_mode RO 853 bit PRELOAD_AVAIL 0x80 854 bit DWORDEMP 0x20 855 bit MREQPEND 0x10 856 bit HDONE 0x08 857 bit DFTHRESH 0x04 858 bit FIFOFULL 0x02 859 bit FIFOEMP 0x01 860} 861 862register DFWADDR { 863 address 0x95 864 access_mode RW 865} 866 867register DFRADDR { 868 address 0x97 869 access_mode RW 870} 871 872register DFDAT { 873 address 0x099 874 access_mode RW 875} 876 877/* 878 * SCB Auto Increment (p. 3-59) 879 * Byte offset into the SCB Array and an optional bit to allow auto 880 * incrementing of the address during download and upload operations 881 */ 882register SCBCNT { 883 address 0x09a 884 access_mode RW 885 bit SCBAUTO 0x80 886 mask SCBCNT_MASK 0x1f 887} 888 889/* 890 * Queue In FIFO (p. 3-60) 891 * Input queue for queued SCBs (commands that the seqencer has yet to start) 892 */ 893register QINFIFO { 894 address 0x09b 895 access_mode RW 896} 897 898/* 899 * Queue In Count (p. 3-60) 900 * Number of queued SCBs 901 */ 902register QINCNT { 903 address 0x09c 904 access_mode RO 905} 906 907/* 908 * Queue Out FIFO (p. 3-61) 909 * Queue of SCBs that have completed and await the host 910 */ 911register QOUTFIFO { 912 address 0x09d 913 access_mode WO 914} 915 916register CRCCONTROL1 { 917 address 0x09d 918 access_mode RW 919 bit CRCONSEEN 0x80 920 bit CRCVALCHKEN 0x40 921 bit CRCENDCHKEN 0x20 922 bit CRCREQCHKEN 0x10 923 bit TARGCRCENDEN 0x08 924 bit TARGCRCCNTEN 0x04 925} 926 927 928/* 929 * Queue Out Count (p. 3-61) 930 * Number of queued SCBs in the Out FIFO 931 */ 932register QOUTCNT { 933 address 0x09e 934 access_mode RO 935} 936 937register SCSIPHASE { 938 address 0x09e 939 access_mode RO 940 bit STATUS_PHASE 0x20 941 bit COMMAND_PHASE 0x10 942 bit MSG_IN_PHASE 0x08 943 bit MSG_OUT_PHASE 0x04 944 bit DATA_IN_PHASE 0x02 945 bit DATA_OUT_PHASE 0x01 946} 947 948/* 949 * Special Function 950 */ 951register SFUNCT { 952 address 0x09f 953 access_mode RW 954 bit ALT_MODE 0x80 955} 956 957/* 958 * SCB Definition (p. 5-4) 959 */ 960scb { 961 address 0x0a0 962 SCB_CONTROL { 963 size 1 964 bit TARGET_SCB 0x80 965 bit DISCENB 0x40 966 bit TAG_ENB 0x20 967 bit MK_MESSAGE 0x10 968 bit ULTRAENB 0x08 969 bit DISCONNECTED 0x04 970 mask SCB_TAG_TYPE 0x03 971 } 972 SCB_SCSIID { 973 size 1 974 bit TWIN_CHNLB 0x80 975 mask TWIN_TID 0x70 976 mask TID 0xf0 977 mask OID 0x0f 978 } 979 SCB_LUN { 980 mask LID 0xff 981 size 1 982 } 983 SCB_CDB_LEN { 984 size 1 985 } 986 SCB_CDB_PTR { 987 size 4 988 alias SCB_RESIDUAL_DATACNT 989 alias SCB_CDB_STORE 990 alias SCB_TARGET_INFO 991 } 992 SCB_RESIDUAL_SGPTR { 993 size 4 994 } 995 SCB_SCSI_STATUS { 996 size 1 997 } 998 SCB_CDB_STORE_PAD { 999 size 3 1000 } 1001 SCB_DATAPTR { 1002 size 4 1003 } 1004 SCB_DATACNT { 1005 /* 1006 * The last byte is really the high address bits for 1007 * the data address. 1008 */ 1009 size 4 1010 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 1011 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1012 } 1013 SCB_SGPTR { 1014 size 4 1015 bit SG_RESID_VALID 0x04 /* In the first byte */ 1016 bit SG_FULL_RESID 0x02 /* In the first byte */ 1017 bit SG_LIST_NULL 0x01 /* In the first byte */ 1018 } 1019 SCB_TAG { 1020 size 1 1021 } 1022 SCB_SCSIRATE { 1023 size 1 1024 } 1025 SCB_SCSIOFFSET { 1026 size 1 1027 } 1028 SCB_NEXT { 1029 size 1 1030 } 1031 SCB_64_BTT { 1032 size 16 1033 } 1034 SCB_64_SPARE { 1035 size 16 1036 } 1037} 1038 1039const SCB_32BYTE_SIZE 30 /* Cards supporting 32byte scbs */ 1040const SCB_64BYTE_SIZE 32 /* Cards supporting 64byte scbs */ 1041 1042const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1043 1044/* --------------------- AHA-2840-only definitions -------------------- */ 1045 1046register SEECTL_2840 { 1047 address 0x0c0 1048 access_mode RW 1049 bit CS_2840 0x04 1050 bit CK_2840 0x02 1051 bit DO_2840 0x01 1052} 1053 1054register STATUS_2840 { 1055 address 0x0c1 1056 access_mode RW 1057 bit EEPROM_TF 0x80 1058 mask BIOS_SEL 0x60 1059 mask ADSEL 0x1e 1060 bit DI_2840 0x01 1061} 1062 1063/* --------------------- AIC-7870-only definitions -------------------- */ 1064 1065register CCHADDR { 1066 address 0x0E0 1067 size 8 1068} 1069 1070register CCHCNT { 1071 address 0x0E8 1072} 1073 1074register CCSGRAM { 1075 address 0x0E9 1076} 1077 1078register CCSGADDR { 1079 address 0x0EA 1080} 1081 1082register CCSGCTL { 1083 address 0x0EB 1084 bit CCSGDONE 0x80 1085 bit CCSGEN 0x08 1086 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1087 bit CCSGRESET 0x01 1088} 1089 1090register CCSCBCNT { 1091 address 0xEF 1092} 1093 1094register CCSCBCTL { 1095 address 0x0EE 1096 bit CCSCBDONE 0x80 1097 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1098 bit CCARREN 0x10 1099 bit CCSCBEN 0x08 1100 bit CCSCBDIR 0x04 1101 bit CCSCBRESET 0x01 1102} 1103 1104register CCSCBADDR { 1105 address 0x0ED 1106} 1107 1108register CCSCBRAM { 1109 address 0xEC 1110} 1111 1112/* 1113 * SCB bank address (7895/7896/97 only) 1114 */ 1115register SCBBADDR { 1116 address 0x0F0 1117 access_mode RW 1118} 1119 1120register CCSCBPTR { 1121 address 0x0F1 1122} 1123 1124register HNSCB_QOFF { 1125 address 0x0F4 1126} 1127 1128register SNSCB_QOFF { 1129 address 0x0F6 1130} 1131 1132register SDSCB_QOFF { 1133 address 0x0F8 1134} 1135 1136register QOFF_CTLSTA { 1137 address 0x0FA 1138 bit SCB_AVAIL 0x40 1139 bit SNSCB_ROLLOVER 0x20 1140 bit SDSCB_ROLLOVER 0x10 1141 mask SCB_QSIZE 0x07 1142 mask SCB_QSIZE_256 0x06 1143} 1144 1145register DFF_THRSH { 1146 address 0x0FB 1147 mask WR_DFTHRSH 0x70 1148 mask RD_DFTHRSH 0x07 1149 mask RD_DFTHRSH_MIN 0x00 1150 mask RD_DFTHRSH_25 0x01 1151 mask RD_DFTHRSH_50 0x02 1152 mask RD_DFTHRSH_63 0x03 1153 mask RD_DFTHRSH_75 0x04 1154 mask RD_DFTHRSH_85 0x05 1155 mask RD_DFTHRSH_90 0x06 1156 mask RD_DFTHRSH_MAX 0x07 1157 mask WR_DFTHRSH_MIN 0x00 1158 mask WR_DFTHRSH_25 0x10 1159 mask WR_DFTHRSH_50 0x20 1160 mask WR_DFTHRSH_63 0x30 1161 mask WR_DFTHRSH_75 0x40 1162 mask WR_DFTHRSH_85 0x50 1163 mask WR_DFTHRSH_90 0x60 1164 mask WR_DFTHRSH_MAX 0x70 1165} 1166 1167register SG_CACHE_PRE { 1168 access_mode WO 1169 address 0x0fc 1170 mask SG_ADDR_MASK 0xf8 1171 bit ODD_SEG 0x04 1172 bit LAST_SEG 0x02 1173 bit LAST_SEG_DONE 0x01 1174} 1175 1176register SG_CACHE_SHADOW { 1177 access_mode RO 1178 address 0x0fc 1179 mask SG_ADDR_MASK 0xf8 1180 bit ODD_SEG 0x04 1181 bit LAST_SEG 0x02 1182 bit LAST_SEG_DONE 0x01 1183} 1184/* ---------------------- Scratch RAM Offsets ------------------------- */ 1185/* These offsets are either to values that are initialized by the board's 1186 * BIOS or are specified by the sequencer code. 1187 * 1188 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1189 * device information, 32-33 and 5a-5f as well. As it turns out, the 1190 * BIOS trashes 20-2f, writing the synchronous negotiation results 1191 * on top of the BIOS values, so we re-use those for our per-target 1192 * scratchspace (actually a value that can be copied directly into 1193 * SCSIRATE). The kernel driver will enable synchronous negotiation 1194 * for all targets that have a value other than 0 in the lower four 1195 * bits of the target scratch space. This should work regardless of 1196 * whether the bios has been installed. 1197 */ 1198 1199scratch_ram { 1200 address 0x020 1201 1202 /* 1203 * 1 byte per target starting at this address for configuration values 1204 */ 1205 CMDSIZE_TABLE { 1206 alias TARG_SCSIRATE 1207 size 8 1208 } 1209 BUSY_TARGETS { 1210 size 16 1211 } 1212 /* 1213 * Bit vector of targets that have ULTRA enabled. 1214 */ 1215 ULTRA_ENB { 1216 size 2 1217 } 1218 /* 1219 * Bit vector of targets that have disconnection disabled. 1220 */ 1221 DISC_DSB { 1222 size 2 1223 } 1224 /* 1225 * Single byte buffer used to designate the type or message 1226 * to send to a target. 1227 */ 1228 MSG_OUT { 1229 size 1 1230 } 1231 /* Parameters for DMA Logic */ 1232 DMAPARAMS { 1233 size 1 1234 bit PRELOADEN 0x80 1235 bit WIDEODD 0x40 1236 bit SCSIEN 0x20 1237 bit SDMAEN 0x10 1238 bit SDMAENACK 0x10 1239 bit HDMAEN 0x08 1240 bit HDMAENACK 0x08 1241 bit DIRECTION 0x04 1242 bit FIFOFLUSH 0x02 1243 bit FIFORESET 0x01 1244 } 1245 SEQ_FLAGS { 1246 size 1 1247 bit IDENTIFY_SEEN 0x80 1248 bit SCBPTR_VALID 0x40 1249 bit TARGET_CMD_IS_TAGGED 0x40 1250 bit DPHASE 0x20 1251 /* Target flags */ 1252 bit TARG_CMD_PENDING 0x10 1253 bit CMDPHASE_PENDING 0x08 1254 bit DPHASE_PENDING 0x04 1255 bit SPHASE_PENDING 0x02 1256 bit NO_DISCONNECT 0x01 1257 } 1258 /* 1259 * Temporary storage for the 1260 * target/channel/lun of a 1261 * reconnecting target 1262 */ 1263 SAVED_SCSIID { 1264 size 1 1265 } 1266 SAVED_LUN { 1267 size 1 1268 } 1269 /* 1270 * The last bus phase as seen by the sequencer. 1271 */ 1272 LASTPHASE { 1273 size 1 1274 bit CDI 0x80 1275 bit IOI 0x40 1276 bit MSGI 0x20 1277 mask PHASE_MASK CDI|IOI|MSGI 1278 mask P_DATAOUT 0x00 1279 mask P_DATAIN IOI 1280 mask P_COMMAND CDI 1281 mask P_MESGOUT CDI|MSGI 1282 mask P_STATUS CDI|IOI 1283 mask P_MESGIN CDI|IOI|MSGI 1284 mask P_BUSFREE 0x01 1285 } 1286 /* 1287 * head of list of SCBs awaiting 1288 * selection 1289 */ 1290 WAITING_SCBH { 1291 size 1 1292 } 1293 /* 1294 * head of list of SCBs that are 1295 * disconnected. Used for SCB 1296 * paging. 1297 */ 1298 DISCONNECTED_SCBH { 1299 size 1 1300 } 1301 /* 1302 * head of list of SCBs that are 1303 * not in use. Used for SCB paging. 1304 */ 1305 FREE_SCBH { 1306 size 1 1307 } 1308 /* 1309 * Address of the hardware scb array in the host. 1310 */ 1311 HSCB_ADDR { 1312 size 4 1313 } 1314 /* 1315 * Base address of our shared data with the kernel driver in host 1316 * memory. This includes the qinfifo, qoutfifo, and target mode 1317 * incoming command queue. 1318 */ 1319 SHARED_DATA_ADDR { 1320 size 4 1321 } 1322 KERNEL_QINPOS { 1323 size 1 1324 } 1325 QINPOS { 1326 size 1 1327 } 1328 QOUTPOS { 1329 size 1 1330 } 1331 /* 1332 * Kernel and sequencer offsets into the queue of 1333 * incoming target mode command descriptors. The 1334 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1335 */ 1336 KERNEL_TQINPOS { 1337 size 1 1338 } 1339 TQINPOS { 1340 size 1 1341 } 1342 ARG_1 { 1343 size 1 1344 mask SEND_MSG 0x80 1345 mask SEND_SENSE 0x40 1346 mask SEND_REJ 0x20 1347 mask MSGOUT_PHASEMIS 0x10 1348 mask EXIT_MSG_LOOP 0x08 1349 mask CONT_MSG_LOOP 0x04 1350 mask CONT_TARG_SESSION 0x02 1351 alias RETURN_1 1352 } 1353 ARG_2 { 1354 size 1 1355 alias RETURN_2 1356 } 1357 1358 /* 1359 * Snapshot of MSG_OUT taken after each message is sent. 1360 */ 1361 LAST_MSG { 1362 size 1 1363 } 1364 1365 /* 1366 * Interrupt kernel for a message to this target on 1367 * the next transaction. This is usually used for 1368 * negotiation requests. 1369 */ 1370 TARGET_MSG_REQUEST { 1371 size 2 1372 } 1373 1374 /* 1375 * Sequences the kernel driver has okayed for us. This allows 1376 * the driver to do things like prevent initiator or target 1377 * operations. 1378 */ 1379 SCSISEQ_TEMPLATE { 1380 size 1 1381 bit ENSELO 0x40 1382 bit ENSELI 0x20 1383 bit ENRSELI 0x10 1384 bit ENAUTOATNO 0x08 1385 bit ENAUTOATNI 0x04 1386 bit ENAUTOATNP 0x02 1387 } 1388 1389 /* 1390 * Track whether the transfer byte count for 1391 * the current data phase is odd. 1392 */ 1393 DATA_COUNT_ODD { 1394 size 1 1395 } 1396 1397 /* 1398 * The initiator specified tag for this target mode transaction. 1399 */ 1400 INITIATOR_TAG { 1401 size 1 1402 } 1403 1404 /* 1405 * These are reserved registers in the card's scratch ram. Some of 1406 * the values are specified in the AHA2742 technical reference manual 1407 * and are initialized by the BIOS at boot time. 1408 */ 1409 SCSICONF { 1410 address 0x05a 1411 size 1 1412 bit TERM_ENB 0x80 1413 bit RESET_SCSI 0x40 1414 bit ENSPCHK 0x20 1415 mask HSCSIID 0x07 /* our SCSI ID */ 1416 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1417 } 1418 HOSTCONF { 1419 address 0x05d 1420 size 1 1421 } 1422 HA_274_BIOSCTRL { 1423 address 0x05f 1424 size 1 1425 mask BIOSMODE 0x30 1426 mask BIOSDISABLED 0x30 1427 bit CHANNEL_B_PRIMARY 0x08 1428 } 1429 /* 1430 * Per target SCSI offset values for Ultra2 controllers. 1431 */ 1432 TARG_OFFSET { 1433 address 0x070 1434 size 16 1435 } 1436} 1437 1438const TID_SHIFT 4 1439const SCB_LIST_NULL 0xff 1440const TARGET_CMD_CMPLT 0xfe 1441 1442const CCSGADDR_MAX 0x80 1443const CCSGRAM_MAXSEGS 16 1444 1445/* WDTR Message values */ 1446const BUS_8_BIT 0x00 1447const BUS_16_BIT 0x01 1448const BUS_32_BIT 0x02 1449 1450/* Offset maximums */ 1451const MAX_OFFSET_8BIT 0x0f 1452const MAX_OFFSET_16BIT 0x08 1453const MAX_OFFSET_ULTRA2 0x7f 1454const HOST_MSG 0xff 1455 1456/* Target mode command processing constants */ 1457const CMD_GROUP_CODE_SHIFT 0x05 1458 1459const STATUS_BUSY 0x08 1460const STATUS_QUEUE_FULL 0x28 1461const SCB_TARGET_PHASES 0 1462const SCB_TARGET_DATA_DIR 1 1463const SCB_TARGET_STATUS 2 1464const SCB_INITIATOR_TAG 3 1465const TARGET_DATA_IN 1 1466 1467/* 1468 * Downloaded (kernel inserted) constants 1469 */ 1470/* Offsets into the SCBID array where different data is stored */ 1471const QOUTFIFO_OFFSET download 1472const QINFIFO_OFFSET download 1473