ahci.h revision 220657
1885Swollman/*- 2885Swollman * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3885Swollman * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 4885Swollman * All rights reserved. 5885Swollman * 6885Swollman * Redistribution and use in source and binary forms, with or without 7885Swollman * modification, are permitted provided that the following conditions 8885Swollman * are met: 9885Swollman * 1. Redistributions of source code must retain the above copyright 10885Swollman * notice, this list of conditions and the following disclaimer, 11885Swollman * without modification, immediately at the beginning of the file. 12885Swollman * 2. Redistributions in binary form must reproduce the above copyright 13885Swollman * notice, this list of conditions and the following disclaimer in the 14885Swollman * documentation and/or other materials provided with the distribution. 15885Swollman * 16885Swollman * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17885Swollman * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18885Swollman * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19885Swollman * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20885Swollman * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21885Swollman * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210625Sdg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23885Swollman * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24885Swollman * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25885Swollman * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26885Swollman * 27885Swollman * $FreeBSD: head/sys/dev/ahci/ahci.h 220657 2011-04-15 16:40:31Z mav $ 28885Swollman */ 29885Swollman 30885Swollman/* ATA register defines */ 3112130Sdg#define ATA_DATA 0 /* (RW) data */ 32885Swollman 33885Swollman#define ATA_FEATURE 1 /* (W) feature */ 342056Swollman#define ATA_F_DMA 0x01 /* enable DMA */ 352056Swollman#define ATA_F_OVL 0x02 /* enable overlap */ 3611332Sswallace 372056Swollman#define ATA_COUNT 2 /* (W) sector count */ 381549Srgrimes 392056Swollman#define ATA_SECTOR 3 /* (RW) sector # */ 402056Swollman#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 412056Swollman#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42885Swollman#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43886Swollman#define ATA_D_LBA 0x40 /* use LBA addressing */ 44885Swollman#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45886Swollman 46886Swollman#define ATA_COMMAND 7 /* (W) command */ 47886Swollman 48886Swollman#define ATA_ERROR 8 /* (R) error */ 49885Swollman#define ATA_E_ILI 0x01 /* illegal length */ 50885Swollman#define ATA_E_NM 0x02 /* no media */ 51885Swollman#define ATA_E_ABORT 0x04 /* command aborted */ 52885Swollman#define ATA_E_MCR 0x08 /* media change request */ 5312130Sdg#define ATA_E_IDNF 0x10 /* ID not found */ 54885Swollman#define ATA_E_MC 0x20 /* media changed */ 55885Swollman#define ATA_E_UNC 0x40 /* uncorrectable data */ 5612130Sdg#define ATA_E_ICRC 0x80 /* UDMA crc error */ 5712130Sdg#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58885Swollman 5912130Sdg#define ATA_IREASON 9 /* (R) interrupt reason */ 60885Swollman#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61885Swollman#define ATA_I_IN 0x02 /* read (1) | write (0) */ 62885Swollman#define ATA_I_RELEASE 0x04 /* released bus (1) */ 63885Swollman#define ATA_I_TAGMASK 0xf8 /* tag mask */ 64885Swollman 65885Swollman#define ATA_STATUS 10 /* (R) status */ 66885Swollman#define ATA_ALTSTAT 11 /* (R) alternate status */ 67885Swollman#define ATA_S_ERROR 0x01 /* error */ 68885Swollman#define ATA_S_INDEX 0x02 /* index */ 69885Swollman#define ATA_S_CORR 0x04 /* data corrected */ 70885Swollman#define ATA_S_DRQ 0x08 /* data request */ 7112130Sdg#define ATA_S_DSC 0x10 /* drive seek completed */ 72885Swollman#define ATA_S_SERVICE 0x10 /* drive needs service */ 73885Swollman#define ATA_S_DWF 0x20 /* drive write fault */ 7412130Sdg#define ATA_S_DMA 0x20 /* DMA ready */ 75885Swollman#define ATA_S_READY 0x40 /* drive ready */ 76885Swollman#define ATA_S_BUSY 0x80 /* busy */ 77885Swollman 78885Swollman#define ATA_CONTROL 12 /* (W) control */ 79885Swollman#define ATA_A_IDS 0x02 /* disable interrupts */ 80885Swollman#define ATA_A_RESET 0x04 /* RESET controller */ 81885Swollman#define ATA_A_4BIT 0x08 /* 4 head bits */ 82885Swollman#define ATA_A_HOB 0x80 /* High Order Byte enable */ 83885Swollman 84885Swollman/* SATA register defines */ 85885Swollman#define ATA_SSTATUS 13 86885Swollman#define ATA_SS_DET_MASK 0x0000000f 87885Swollman#define ATA_SS_DET_NO_DEVICE 0x00000000 88885Swollman#define ATA_SS_DET_DEV_PRESENT 0x00000001 89885Swollman#define ATA_SS_DET_PHY_ONLINE 0x00000003 90885Swollman#define ATA_SS_DET_PHY_OFFLINE 0x00000004 91885Swollman 92885Swollman#define ATA_SS_SPD_MASK 0x000000f0 93885Swollman#define ATA_SS_SPD_NO_SPEED 0x00000000 94885Swollman#define ATA_SS_SPD_GEN1 0x00000010 95885Swollman#define ATA_SS_SPD_GEN2 0x00000020 96885Swollman#define ATA_SS_SPD_GEN3 0x00000040 9712130Sdg 98885Swollman#define ATA_SS_IPM_MASK 0x00000f00 99885Swollman#define ATA_SS_IPM_NO_DEVICE 0x00000000 100885Swollman#define ATA_SS_IPM_ACTIVE 0x00000100 101885Swollman#define ATA_SS_IPM_PARTIAL 0x00000200 102885Swollman#define ATA_SS_IPM_SLUMBER 0x00000600 10312130Sdg 104885Swollman#define ATA_SERROR 14 105885Swollman#define ATA_SE_DATA_CORRECTED 0x00000001 106885Swollman#define ATA_SE_COMM_CORRECTED 0x00000002 107885Swollman#define ATA_SE_DATA_ERR 0x00000100 108885Swollman#define ATA_SE_COMM_ERR 0x00000200 109885Swollman#define ATA_SE_PROT_ERR 0x00000400 110885Swollman#define ATA_SE_HOST_ERR 0x00000800 111885Swollman#define ATA_SE_PHY_CHANGED 0x00010000 112885Swollman#define ATA_SE_PHY_IERROR 0x00020000 113885Swollman#define ATA_SE_COMM_WAKE 0x00040000 114885Swollman#define ATA_SE_DECODE_ERR 0x00080000 115885Swollman#define ATA_SE_PARITY_ERR 0x00100000 116885Swollman#define ATA_SE_CRC_ERR 0x00200000 117885Swollman#define ATA_SE_HANDSHAKE_ERR 0x00400000 118885Swollman#define ATA_SE_LINKSEQ_ERR 0x00800000 119885Swollman#define ATA_SE_TRANSPORT_ERR 0x01000000 120885Swollman#define ATA_SE_UNKNOWN_FIS 0x02000000 12112130Sdg#define ATA_SE_EXCHANGED 0x04000000 12212130Sdg 123885Swollman#define ATA_SCONTROL 15 124885Swollman#define ATA_SC_DET_MASK 0x0000000f 12512130Sdg#define ATA_SC_DET_IDLE 0x00000000 12612130Sdg#define ATA_SC_DET_RESET 0x00000001 127885Swollman#define ATA_SC_DET_DISABLE 0x00000004 12812130Sdg 129885Swollman#define ATA_SC_SPD_MASK 0x000000f0 130885Swollman#define ATA_SC_SPD_NO_SPEED 0x00000000 131885Swollman#define ATA_SC_SPD_SPEED_GEN1 0x00000010 132885Swollman#define ATA_SC_SPD_SPEED_GEN2 0x00000020 13312130Sdg#define ATA_SC_SPD_SPEED_GEN3 0x00000040 134885Swollman 135885Swollman#define ATA_SC_IPM_MASK 0x00000f00 136885Swollman#define ATA_SC_IPM_NONE 0x00000000 137886Swollman#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 138886Swollman#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 139886Swollman 140886Swollman#define ATA_SACTIVE 16 141886Swollman 142886Swollman#define AHCI_MAX_PORTS 32 1432112Swollman#define AHCI_MAX_SLOTS 32 144886Swollman 145/* SATA AHCI v1.0 register defines */ 146#define AHCI_CAP 0x00 147#define AHCI_CAP_NPMASK 0x0000001f 148#define AHCI_CAP_SXS 0x00000020 149#define AHCI_CAP_EMS 0x00000040 150#define AHCI_CAP_CCCS 0x00000080 151#define AHCI_CAP_NCS 0x00001F00 152#define AHCI_CAP_NCS_SHIFT 8 153#define AHCI_CAP_PSC 0x00002000 154#define AHCI_CAP_SSC 0x00004000 155#define AHCI_CAP_PMD 0x00008000 156#define AHCI_CAP_FBSS 0x00010000 157#define AHCI_CAP_SPM 0x00020000 158#define AHCI_CAP_SAM 0x00080000 159#define AHCI_CAP_ISS 0x00F00000 160#define AHCI_CAP_ISS_SHIFT 20 161#define AHCI_CAP_SCLO 0x01000000 162#define AHCI_CAP_SAL 0x02000000 163#define AHCI_CAP_SALP 0x04000000 164#define AHCI_CAP_SSS 0x08000000 165#define AHCI_CAP_SMPS 0x10000000 166#define AHCI_CAP_SSNTF 0x20000000 167#define AHCI_CAP_SNCQ 0x40000000 168#define AHCI_CAP_64BIT 0x80000000 169 170#define AHCI_GHC 0x04 171#define AHCI_GHC_AE 0x80000000 172#define AHCI_GHC_MRSM 0x00000004 173#define AHCI_GHC_IE 0x00000002 174#define AHCI_GHC_HR 0x00000001 175 176#define AHCI_IS 0x08 177#define AHCI_PI 0x0c 178#define AHCI_VS 0x10 179 180#define AHCI_CCCC 0x14 181#define AHCI_CCCC_TV_MASK 0xffff0000 182#define AHCI_CCCC_TV_SHIFT 16 183#define AHCI_CCCC_CC_MASK 0x0000ff00 184#define AHCI_CCCC_CC_SHIFT 8 185#define AHCI_CCCC_INT_MASK 0x000000f8 186#define AHCI_CCCC_INT_SHIFT 3 187#define AHCI_CCCC_EN 0x00000001 188#define AHCI_CCCP 0x18 189 190#define AHCI_EM_LOC 0x1C 191#define AHCI_EM_CTL 0x20 192#define AHCI_EM_MR 0x00000001 193#define AHCI_EM_TM 0x00000100 194#define AHCI_EM_RST 0x00000200 195#define AHCI_EM_LED 0x00010000 196#define AHCI_EM_SAFTE 0x00020000 197#define AHCI_EM_SES2 0x00040000 198#define AHCI_EM_SGPIO 0x00080000 199#define AHCI_EM_SMB 0x01000000 200#define AHCI_EM_XMT 0x02000000 201#define AHCI_EM_ALHD 0x04000000 202#define AHCI_EM_PM 0x08000000 203 204#define AHCI_CAP2 0x24 205#define AHCI_CAP2_BOH 0x00000001 206#define AHCI_CAP2_NVMP 0x00000002 207#define AHCI_CAP2_APST 0x00000004 208 209#define AHCI_OFFSET 0x100 210#define AHCI_STEP 0x80 211 212#define AHCI_P_CLB 0x00 213#define AHCI_P_CLBU 0x04 214#define AHCI_P_FB 0x08 215#define AHCI_P_FBU 0x0c 216#define AHCI_P_IS 0x10 217#define AHCI_P_IE 0x14 218#define AHCI_P_IX_DHR 0x00000001 219#define AHCI_P_IX_PS 0x00000002 220#define AHCI_P_IX_DS 0x00000004 221#define AHCI_P_IX_SDB 0x00000008 222#define AHCI_P_IX_UF 0x00000010 223#define AHCI_P_IX_DP 0x00000020 224#define AHCI_P_IX_PC 0x00000040 225#define AHCI_P_IX_MP 0x00000080 226 227#define AHCI_P_IX_PRC 0x00400000 228#define AHCI_P_IX_IPM 0x00800000 229#define AHCI_P_IX_OF 0x01000000 230#define AHCI_P_IX_INF 0x04000000 231#define AHCI_P_IX_IF 0x08000000 232#define AHCI_P_IX_HBD 0x10000000 233#define AHCI_P_IX_HBF 0x20000000 234#define AHCI_P_IX_TFE 0x40000000 235#define AHCI_P_IX_CPD 0x80000000 236 237#define AHCI_P_CMD 0x18 238#define AHCI_P_CMD_ST 0x00000001 239#define AHCI_P_CMD_SUD 0x00000002 240#define AHCI_P_CMD_POD 0x00000004 241#define AHCI_P_CMD_CLO 0x00000008 242#define AHCI_P_CMD_FRE 0x00000010 243#define AHCI_P_CMD_CCS_MASK 0x00001f00 244#define AHCI_P_CMD_CCS_SHIFT 8 245#define AHCI_P_CMD_ISS 0x00002000 246#define AHCI_P_CMD_FR 0x00004000 247#define AHCI_P_CMD_CR 0x00008000 248#define AHCI_P_CMD_CPS 0x00010000 249#define AHCI_P_CMD_PMA 0x00020000 250#define AHCI_P_CMD_HPCP 0x00040000 251#define AHCI_P_CMD_MPSP 0x00080000 252#define AHCI_P_CMD_CPD 0x00100000 253#define AHCI_P_CMD_ESP 0x00200000 254#define AHCI_P_CMD_FBSCP 0x00400000 255#define AHCI_P_CMD_APSTE 0x00800000 256#define AHCI_P_CMD_ATAPI 0x01000000 257#define AHCI_P_CMD_DLAE 0x02000000 258#define AHCI_P_CMD_ALPE 0x04000000 259#define AHCI_P_CMD_ASP 0x08000000 260#define AHCI_P_CMD_ICC_MASK 0xf0000000 261#define AHCI_P_CMD_NOOP 0x00000000 262#define AHCI_P_CMD_ACTIVE 0x10000000 263#define AHCI_P_CMD_PARTIAL 0x20000000 264#define AHCI_P_CMD_SLUMBER 0x60000000 265 266#define AHCI_P_TFD 0x20 267#define AHCI_P_SIG 0x24 268#define AHCI_P_SSTS 0x28 269#define AHCI_P_SCTL 0x2c 270#define AHCI_P_SERR 0x30 271#define AHCI_P_SACT 0x34 272#define AHCI_P_CI 0x38 273#define AHCI_P_SNTF 0x3C 274#define AHCI_P_FBS 0x40 275#define AHCI_P_FBS_EN 0x00000001 276#define AHCI_P_FBS_DEC 0x00000002 277#define AHCI_P_FBS_SDE 0x00000004 278#define AHCI_P_FBS_DEV 0x00000f00 279#define AHCI_P_FBS_DEV_SHIFT 8 280#define AHCI_P_FBS_ADO 0x0000f000 281#define AHCI_P_FBS_ADO_SHIFT 12 282#define AHCI_P_FBS_DWE 0x000f0000 283#define AHCI_P_FBS_DWE_SHIFT 16 284 285/* Just to be sure, if building as module. */ 286#if MAXPHYS < 512 * 1024 287#undef MAXPHYS 288#define MAXPHYS 512 * 1024 289#endif 290/* Pessimistic prognosis on number of required S/G entries */ 291#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 292/* Command list. 32 commands. First, 1Kbyte aligned. */ 293#define AHCI_CL_OFFSET 0 294#define AHCI_CL_SIZE 32 295/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 296#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 297#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 298/* Total main work area. */ 299#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 300 301struct ahci_dma_prd { 302 u_int64_t dba; 303 u_int32_t reserved; 304 u_int32_t dbc; /* 0 based */ 305#define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 306#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 307#define AHCI_PRD_IPC (1 << 31) 308} __packed; 309 310struct ahci_cmd_tab { 311 u_int8_t cfis[64]; 312 u_int8_t acmd[32]; 313 u_int8_t reserved[32]; 314 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 315} __packed; 316 317struct ahci_cmd_list { 318 u_int16_t cmd_flags; 319#define AHCI_CMD_ATAPI 0x0020 320#define AHCI_CMD_WRITE 0x0040 321#define AHCI_CMD_PREFETCH 0x0080 322#define AHCI_CMD_RESET 0x0100 323#define AHCI_CMD_BIST 0x0200 324#define AHCI_CMD_CLR_BUSY 0x0400 325 326 u_int16_t prd_length; /* PRD entries */ 327 u_int32_t bytecount; 328 u_int64_t cmd_table_phys; /* 128byte aligned */ 329} __packed; 330 331/* misc defines */ 332#define ATA_IRQ_RID 0 333#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 334 335struct ata_dmaslot { 336 bus_dmamap_t data_map; /* data DMA map */ 337 int nsegs; /* Number of segs loaded */ 338}; 339 340/* structure holding DMA related information */ 341struct ata_dma { 342 bus_dma_tag_t work_tag; /* workspace DMA tag */ 343 bus_dmamap_t work_map; /* workspace DMA map */ 344 uint8_t *work; /* workspace */ 345 bus_addr_t work_bus; /* bus address of work */ 346 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 347 bus_dmamap_t rfis_map; /* RFIS list DMA map */ 348 uint8_t *rfis; /* FIS receive area */ 349 bus_addr_t rfis_bus; /* bus address of rfis */ 350 bus_dma_tag_t data_tag; /* data DMA tag */ 351 u_int64_t max_address; /* highest DMA'able address */ 352}; 353 354enum ahci_slot_states { 355 AHCI_SLOT_EMPTY, 356 AHCI_SLOT_LOADING, 357 AHCI_SLOT_RUNNING, 358 AHCI_SLOT_EXECUTING 359}; 360 361struct ahci_slot { 362 device_t dev; /* Device handle */ 363 u_int8_t slot; /* Number of this slot */ 364 enum ahci_slot_states state; /* Slot state */ 365 union ccb *ccb; /* CCB occupying slot */ 366 struct ata_dmaslot dma; /* DMA data of this slot */ 367 struct callout timeout; /* Execution timeout */ 368}; 369 370struct ahci_device { 371 int revision; 372 int mode; 373 u_int bytecount; 374 u_int atapi; 375 u_int tags; 376 u_int caps; 377}; 378 379/* structure describing an ATA channel */ 380struct ahci_channel { 381 device_t dev; /* Device handle */ 382 int unit; /* Physical channel */ 383 struct resource *r_mem; /* Memory of this channel */ 384 struct resource *r_irq; /* Interrupt of this channel */ 385 void *ih; /* Interrupt handle */ 386 struct ata_dma dma; /* DMA data */ 387 struct cam_sim *sim; 388 struct cam_path *path; 389 uint32_t caps; /* Controller capabilities */ 390 uint32_t caps2; /* Controller capabilities */ 391 uint32_t chcaps; /* Channel capabilities */ 392 int quirks; 393 int numslots; /* Number of present slots */ 394 int pm_level; /* power management level */ 395 396 struct ahci_slot slot[AHCI_MAX_SLOTS]; 397 union ccb *hold[AHCI_MAX_SLOTS]; 398 struct mtx mtx; /* state lock */ 399 int devices; /* What is present */ 400 int pm_present; /* PM presence reported */ 401 int fbs_enabled; /* FIS-based switching enabled */ 402 uint32_t oslots; /* Occupied slots */ 403 uint32_t rslots; /* Running slots */ 404 uint32_t aslots; /* Slots with atomic commands */ 405 uint32_t eslots; /* Slots in error */ 406 uint32_t toslots; /* Slots in timeout */ 407 int numrslots; /* Number of running slots */ 408 int numrslotspd[16];/* Number of running slots per dev */ 409 int numtslots; /* Number of tagged slots */ 410 int numtslotspd[16];/* Number of tagged slots per dev */ 411 int numhslots; /* Number of holden slots */ 412 int recoverycmd; /* Our READ LOG active */ 413 int fatalerr; /* Fatal error happend */ 414 int lastslot; /* Last used slot */ 415 int taggedtarget; /* Last tagged target */ 416 int resetting; /* Hard-reset in progress. */ 417 int listening; /* SUD bit is cleared. */ 418 union ccb *frozen; /* Frozen command */ 419 struct callout pm_timer; /* Power management events */ 420 struct callout reset_timer; /* Hard-reset timeout */ 421 422 struct ahci_device user[16]; /* User-specified settings */ 423 struct ahci_device curr[16]; /* Current settings */ 424}; 425 426/* structure describing a AHCI controller */ 427struct ahci_controller { 428 device_t dev; 429 int r_rid; 430 struct resource *r_mem; 431 struct rman sc_iomem; 432 struct ahci_controller_irq { 433 struct ahci_controller *ctlr; 434 struct resource *r_irq; 435 void *handle; 436 int r_irq_rid; 437 int mode; 438#define AHCI_IRQ_MODE_ALL 0 439#define AHCI_IRQ_MODE_AFTER 1 440#define AHCI_IRQ_MODE_ONE 2 441 } irqs[16]; 442 uint32_t caps; /* Controller capabilities */ 443 uint32_t caps2; /* Controller capabilities */ 444 uint32_t capsem; /* Controller capabilities */ 445 int quirks; 446 int numirqs; 447 int channels; 448 int ichannels; 449 int ccc; /* CCC timeout */ 450 int cccv; /* CCC vector */ 451 struct { 452 void (*function)(void *); 453 void *argument; 454 } interrupt[AHCI_MAX_PORTS]; 455}; 456 457enum ahci_err_type { 458 AHCI_ERR_NONE, /* No error */ 459 AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 460 AHCI_ERR_INNOCENT, /* Innocent victim. */ 461 AHCI_ERR_TFE, /* Task File Error. */ 462 AHCI_ERR_SATA, /* SATA error. */ 463 AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 464 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 465 * until READ LOG executed to reveal error. */ 466}; 467 468/* macros to hide busspace uglyness */ 469#define ATA_INB(res, offset) \ 470 bus_read_1((res), (offset)) 471#define ATA_INW(res, offset) \ 472 bus_read_2((res), (offset)) 473#define ATA_INL(res, offset) \ 474 bus_read_4((res), (offset)) 475#define ATA_INSW(res, offset, addr, count) \ 476 bus_read_multi_2((res), (offset), (addr), (count)) 477#define ATA_INSW_STRM(res, offset, addr, count) \ 478 bus_read_multi_stream_2((res), (offset), (addr), (count)) 479#define ATA_INSL(res, offset, addr, count) \ 480 bus_read_multi_4((res), (offset), (addr), (count)) 481#define ATA_INSL_STRM(res, offset, addr, count) \ 482 bus_read_multi_stream_4((res), (offset), (addr), (count)) 483#define ATA_OUTB(res, offset, value) \ 484 bus_write_1((res), (offset), (value)) 485#define ATA_OUTW(res, offset, value) \ 486 bus_write_2((res), (offset), (value)) 487#define ATA_OUTL(res, offset, value) \ 488 bus_write_4((res), (offset), (value)) 489#define ATA_OUTSW(res, offset, addr, count) \ 490 bus_write_multi_2((res), (offset), (addr), (count)) 491#define ATA_OUTSW_STRM(res, offset, addr, count) \ 492 bus_write_multi_stream_2((res), (offset), (addr), (count)) 493#define ATA_OUTSL(res, offset, addr, count) \ 494 bus_write_multi_4((res), (offset), (addr), (count)) 495#define ATA_OUTSL_STRM(res, offset, addr, count) \ 496 bus_write_multi_stream_4((res), (offset), (addr), (count)) 497