ahci.h revision 195534
1195534Sscottl/*- 2195534Sscottl * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3195534Sscottl * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 4195534Sscottl * All rights reserved. 5195534Sscottl * 6195534Sscottl * Redistribution and use in source and binary forms, with or without 7195534Sscottl * modification, are permitted provided that the following conditions 8195534Sscottl * are met: 9195534Sscottl * 1. Redistributions of source code must retain the above copyright 10195534Sscottl * notice, this list of conditions and the following disclaimer, 11195534Sscottl * without modification, immediately at the beginning of the file. 12195534Sscottl * 2. Redistributions in binary form must reproduce the above copyright 13195534Sscottl * notice, this list of conditions and the following disclaimer in the 14195534Sscottl * documentation and/or other materials provided with the distribution. 15195534Sscottl * 16195534Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17195534Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18195534Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19195534Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20195534Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21195534Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22195534Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23195534Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24195534Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25195534Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26195534Sscottl * 27195534Sscottl * $FreeBSD: head/sys/dev/ahci/ahci.h 195534 2009-07-10 08:18:08Z scottl $ 28195534Sscottl */ 29195534Sscottl 30195534Sscottl/* ATA register defines */ 31195534Sscottl#define ATA_DATA 0 /* (RW) data */ 32195534Sscottl 33195534Sscottl#define ATA_FEATURE 1 /* (W) feature */ 34195534Sscottl#define ATA_F_DMA 0x01 /* enable DMA */ 35195534Sscottl#define ATA_F_OVL 0x02 /* enable overlap */ 36195534Sscottl 37195534Sscottl#define ATA_COUNT 2 /* (W) sector count */ 38195534Sscottl 39195534Sscottl#define ATA_SECTOR 3 /* (RW) sector # */ 40195534Sscottl#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41195534Sscottl#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42195534Sscottl#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43195534Sscottl#define ATA_D_LBA 0x40 /* use LBA addressing */ 44195534Sscottl#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45195534Sscottl 46195534Sscottl#define ATA_COMMAND 7 /* (W) command */ 47195534Sscottl 48195534Sscottl#define ATA_ERROR 8 /* (R) error */ 49195534Sscottl#define ATA_E_ILI 0x01 /* illegal length */ 50195534Sscottl#define ATA_E_NM 0x02 /* no media */ 51195534Sscottl#define ATA_E_ABORT 0x04 /* command aborted */ 52195534Sscottl#define ATA_E_MCR 0x08 /* media change request */ 53195534Sscottl#define ATA_E_IDNF 0x10 /* ID not found */ 54195534Sscottl#define ATA_E_MC 0x20 /* media changed */ 55195534Sscottl#define ATA_E_UNC 0x40 /* uncorrectable data */ 56195534Sscottl#define ATA_E_ICRC 0x80 /* UDMA crc error */ 57195534Sscottl#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58195534Sscottl 59195534Sscottl#define ATA_IREASON 9 /* (R) interrupt reason */ 60195534Sscottl#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61195534Sscottl#define ATA_I_IN 0x02 /* read (1) | write (0) */ 62195534Sscottl#define ATA_I_RELEASE 0x04 /* released bus (1) */ 63195534Sscottl#define ATA_I_TAGMASK 0xf8 /* tag mask */ 64195534Sscottl 65195534Sscottl#define ATA_STATUS 10 /* (R) status */ 66195534Sscottl#define ATA_ALTSTAT 11 /* (R) alternate status */ 67195534Sscottl#define ATA_S_ERROR 0x01 /* error */ 68195534Sscottl#define ATA_S_INDEX 0x02 /* index */ 69195534Sscottl#define ATA_S_CORR 0x04 /* data corrected */ 70195534Sscottl#define ATA_S_DRQ 0x08 /* data request */ 71195534Sscottl#define ATA_S_DSC 0x10 /* drive seek completed */ 72195534Sscottl#define ATA_S_SERVICE 0x10 /* drive needs service */ 73195534Sscottl#define ATA_S_DWF 0x20 /* drive write fault */ 74195534Sscottl#define ATA_S_DMA 0x20 /* DMA ready */ 75195534Sscottl#define ATA_S_READY 0x40 /* drive ready */ 76195534Sscottl#define ATA_S_BUSY 0x80 /* busy */ 77195534Sscottl 78195534Sscottl#define ATA_CONTROL 12 /* (W) control */ 79195534Sscottl#define ATA_A_IDS 0x02 /* disable interrupts */ 80195534Sscottl#define ATA_A_RESET 0x04 /* RESET controller */ 81195534Sscottl#define ATA_A_4BIT 0x08 /* 4 head bits */ 82195534Sscottl#define ATA_A_HOB 0x80 /* High Order Byte enable */ 83195534Sscottl 84195534Sscottl/* SATA register defines */ 85195534Sscottl#define ATA_SSTATUS 13 86195534Sscottl#define ATA_SS_DET_MASK 0x0000000f 87195534Sscottl#define ATA_SS_DET_NO_DEVICE 0x00000000 88195534Sscottl#define ATA_SS_DET_DEV_PRESENT 0x00000001 89195534Sscottl#define ATA_SS_DET_PHY_ONLINE 0x00000003 90195534Sscottl#define ATA_SS_DET_PHY_OFFLINE 0x00000004 91195534Sscottl 92195534Sscottl#define ATA_SS_SPD_MASK 0x000000f0 93195534Sscottl#define ATA_SS_SPD_NO_SPEED 0x00000000 94195534Sscottl#define ATA_SS_SPD_GEN1 0x00000010 95195534Sscottl#define ATA_SS_SPD_GEN2 0x00000020 96195534Sscottl#define ATA_SS_SPD_GEN3 0x00000040 97195534Sscottl 98195534Sscottl#define ATA_SS_IPM_MASK 0x00000f00 99195534Sscottl#define ATA_SS_IPM_NO_DEVICE 0x00000000 100195534Sscottl#define ATA_SS_IPM_ACTIVE 0x00000100 101195534Sscottl#define ATA_SS_IPM_PARTIAL 0x00000200 102195534Sscottl#define ATA_SS_IPM_SLUMBER 0x00000600 103195534Sscottl 104195534Sscottl#define ATA_SERROR 14 105195534Sscottl#define ATA_SE_DATA_CORRECTED 0x00000001 106195534Sscottl#define ATA_SE_COMM_CORRECTED 0x00000002 107195534Sscottl#define ATA_SE_DATA_ERR 0x00000100 108195534Sscottl#define ATA_SE_COMM_ERR 0x00000200 109195534Sscottl#define ATA_SE_PROT_ERR 0x00000400 110195534Sscottl#define ATA_SE_HOST_ERR 0x00000800 111195534Sscottl#define ATA_SE_PHY_CHANGED 0x00010000 112195534Sscottl#define ATA_SE_PHY_IERROR 0x00020000 113195534Sscottl#define ATA_SE_COMM_WAKE 0x00040000 114195534Sscottl#define ATA_SE_DECODE_ERR 0x00080000 115195534Sscottl#define ATA_SE_PARITY_ERR 0x00100000 116195534Sscottl#define ATA_SE_CRC_ERR 0x00200000 117195534Sscottl#define ATA_SE_HANDSHAKE_ERR 0x00400000 118195534Sscottl#define ATA_SE_LINKSEQ_ERR 0x00800000 119195534Sscottl#define ATA_SE_TRANSPORT_ERR 0x01000000 120195534Sscottl#define ATA_SE_UNKNOWN_FIS 0x02000000 121195534Sscottl 122195534Sscottl#define ATA_SCONTROL 15 123195534Sscottl#define ATA_SC_DET_MASK 0x0000000f 124195534Sscottl#define ATA_SC_DET_IDLE 0x00000000 125195534Sscottl#define ATA_SC_DET_RESET 0x00000001 126195534Sscottl#define ATA_SC_DET_DISABLE 0x00000004 127195534Sscottl 128195534Sscottl#define ATA_SC_SPD_MASK 0x000000f0 129195534Sscottl#define ATA_SC_SPD_NO_SPEED 0x00000000 130195534Sscottl#define ATA_SC_SPD_SPEED_GEN1 0x00000010 131195534Sscottl#define ATA_SC_SPD_SPEED_GEN2 0x00000020 132195534Sscottl#define ATA_SC_SPD_SPEED_GEN3 0x00000040 133195534Sscottl 134195534Sscottl#define ATA_SC_IPM_MASK 0x00000f00 135195534Sscottl#define ATA_SC_IPM_NONE 0x00000000 136195534Sscottl#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 137195534Sscottl#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 138195534Sscottl 139195534Sscottl#define ATA_SACTIVE 16 140195534Sscottl 141195534Sscottl#define AHCI_MAX_PORTS 32 142195534Sscottl#define AHCI_MAX_SLOTS 32 143195534Sscottl 144195534Sscottl/* SATA AHCI v1.0 register defines */ 145195534Sscottl#define AHCI_CAP 0x00 146195534Sscottl#define AHCI_CAP_NPMASK 0x0000001f 147195534Sscottl#define AHCI_CAP_SXS 0x00000020 148195534Sscottl#define AHCI_CAP_EMS 0x00000040 149195534Sscottl#define AHCI_CAP_CCCS 0x00000080 150195534Sscottl#define AHCI_CAP_NCS 0x00001F00 151195534Sscottl#define AHCI_CAP_NCS_SHIFT 8 152195534Sscottl#define AHCI_CAP_PSC 0x00002000 153195534Sscottl#define AHCI_CAP_SSC 0x00004000 154195534Sscottl#define AHCI_CAP_PMD 0x00008000 155195534Sscottl#define AHCI_CAP_FBSS 0x00010000 156195534Sscottl#define AHCI_CAP_SPM 0x00020000 157195534Sscottl#define AHCI_CAP_SAM 0x00080000 158195534Sscottl#define AHCI_CAP_ISS 0x00F00000 159195534Sscottl#define AHCI_CAP_ISS_SHIFT 20 160195534Sscottl#define AHCI_CAP_SCLO 0x01000000 161195534Sscottl#define AHCI_CAP_SAL 0x02000000 162195534Sscottl#define AHCI_CAP_SALP 0x04000000 163195534Sscottl#define AHCI_CAP_SSS 0x08000000 164195534Sscottl#define AHCI_CAP_SMPS 0x10000000 165195534Sscottl#define AHCI_CAP_SSNTF 0x20000000 166195534Sscottl#define AHCI_CAP_SNCQ 0x40000000 167195534Sscottl#define AHCI_CAP_64BIT 0x80000000 168195534Sscottl 169195534Sscottl#define AHCI_GHC 0x04 170195534Sscottl#define AHCI_GHC_AE 0x80000000 171195534Sscottl#define AHCI_GHC_MRSM 0x00000004 172195534Sscottl#define AHCI_GHC_IE 0x00000002 173195534Sscottl#define AHCI_GHC_HR 0x00000001 174195534Sscottl 175195534Sscottl#define AHCI_IS 0x08 176195534Sscottl#define AHCI_PI 0x0c 177195534Sscottl#define AHCI_VS 0x10 178195534Sscottl 179195534Sscottl#define AHCI_OFFSET 0x100 180195534Sscottl#define AHCI_STEP 0x80 181195534Sscottl 182195534Sscottl#define AHCI_P_CLB 0x00 183195534Sscottl#define AHCI_P_CLBU 0x04 184195534Sscottl#define AHCI_P_FB 0x08 185195534Sscottl#define AHCI_P_FBU 0x0c 186195534Sscottl#define AHCI_P_IS 0x10 187195534Sscottl#define AHCI_P_IE 0x14 188195534Sscottl#define AHCI_P_IX_DHR 0x00000001 189195534Sscottl#define AHCI_P_IX_PS 0x00000002 190195534Sscottl#define AHCI_P_IX_DS 0x00000004 191195534Sscottl#define AHCI_P_IX_SDB 0x00000008 192195534Sscottl#define AHCI_P_IX_UF 0x00000010 193195534Sscottl#define AHCI_P_IX_DP 0x00000020 194195534Sscottl#define AHCI_P_IX_PC 0x00000040 195195534Sscottl#define AHCI_P_IX_DI 0x00000080 196195534Sscottl 197195534Sscottl#define AHCI_P_IX_PRC 0x00400000 198195534Sscottl#define AHCI_P_IX_IPM 0x00800000 199195534Sscottl#define AHCI_P_IX_OF 0x01000000 200195534Sscottl#define AHCI_P_IX_INF 0x04000000 201195534Sscottl#define AHCI_P_IX_IF 0x08000000 202195534Sscottl#define AHCI_P_IX_HBD 0x10000000 203195534Sscottl#define AHCI_P_IX_HBF 0x20000000 204195534Sscottl#define AHCI_P_IX_TFE 0x40000000 205195534Sscottl#define AHCI_P_IX_CPD 0x80000000 206195534Sscottl 207195534Sscottl#define AHCI_P_CMD 0x18 208195534Sscottl#define AHCI_P_CMD_ST 0x00000001 209195534Sscottl#define AHCI_P_CMD_SUD 0x00000002 210195534Sscottl#define AHCI_P_CMD_POD 0x00000004 211195534Sscottl#define AHCI_P_CMD_CLO 0x00000008 212195534Sscottl#define AHCI_P_CMD_FRE 0x00000010 213195534Sscottl#define AHCI_P_CMD_CCS_MASK 0x00001f00 214195534Sscottl#define AHCI_P_CMD_CCS_SHIFT 8 215195534Sscottl#define AHCI_P_CMD_ISS 0x00002000 216195534Sscottl#define AHCI_P_CMD_FR 0x00004000 217195534Sscottl#define AHCI_P_CMD_CR 0x00008000 218195534Sscottl#define AHCI_P_CMD_CPS 0x00010000 219195534Sscottl#define AHCI_P_CMD_PMA 0x00020000 220195534Sscottl#define AHCI_P_CMD_HPCP 0x00040000 221195534Sscottl#define AHCI_P_CMD_ISP 0x00080000 222195534Sscottl#define AHCI_P_CMD_CPD 0x00100000 223195534Sscottl#define AHCI_P_CMD_ATAPI 0x01000000 224195534Sscottl#define AHCI_P_CMD_DLAE 0x02000000 225195534Sscottl#define AHCI_P_CMD_ALPE 0x04000000 226195534Sscottl#define AHCI_P_CMD_ASP 0x08000000 227195534Sscottl#define AHCI_P_CMD_ICC_MASK 0xf0000000 228195534Sscottl#define AHCI_P_CMD_NOOP 0x00000000 229195534Sscottl#define AHCI_P_CMD_ACTIVE 0x10000000 230195534Sscottl#define AHCI_P_CMD_PARTIAL 0x20000000 231195534Sscottl#define AHCI_P_CMD_SLUMBER 0x60000000 232195534Sscottl 233195534Sscottl#define AHCI_P_TFD 0x20 234195534Sscottl#define AHCI_P_SIG 0x24 235195534Sscottl#define AHCI_P_SSTS 0x28 236195534Sscottl#define AHCI_P_SCTL 0x2c 237195534Sscottl#define AHCI_P_SERR 0x30 238195534Sscottl#define AHCI_P_SACT 0x34 239195534Sscottl#define AHCI_P_CI 0x38 240195534Sscottl#define AHCI_P_SNTF 0x3C 241195534Sscottl#define AHCI_P_FBS 0x40 242195534Sscottl 243195534Sscottl/* Just to be sure, if building as module. */ 244195534Sscottl#if MAXPHYS < 512 * 1024 245195534Sscottl#undef MAXPHYS 246195534Sscottl#define MAXPHYS 512 * 1024 247195534Sscottl#endif 248195534Sscottl/* Pessimistic prognosis on number of required S/G entries */ 249195534Sscottl#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 250195534Sscottl/* Command list. 32 commands. First, 1Kbyte aligned. */ 251195534Sscottl#define AHCI_CL_OFFSET 0 252195534Sscottl#define AHCI_CL_SIZE 32 253195534Sscottl/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 254195534Sscottl#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 255195534Sscottl#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 256195534Sscottl/* Total main work area. */ 257195534Sscottl#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 258195534Sscottl 259195534Sscottlstruct ahci_dma_prd { 260195534Sscottl u_int64_t dba; 261195534Sscottl u_int32_t reserved; 262195534Sscottl u_int32_t dbc; /* 0 based */ 263195534Sscottl#define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 264195534Sscottl#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 265195534Sscottl#define AHCI_PRD_IPC (1 << 31) 266195534Sscottl} __packed; 267195534Sscottl 268195534Sscottlstruct ahci_cmd_tab { 269195534Sscottl u_int8_t cfis[64]; 270195534Sscottl u_int8_t acmd[32]; 271195534Sscottl u_int8_t reserved[32]; 272195534Sscottl struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 273195534Sscottl} __packed; 274195534Sscottl 275195534Sscottlstruct ahci_cmd_list { 276195534Sscottl u_int16_t cmd_flags; 277195534Sscottl#define AHCI_CMD_ATAPI 0x0020 278195534Sscottl#define AHCI_CMD_WRITE 0x0040 279195534Sscottl#define AHCI_CMD_PREFETCH 0x0080 280195534Sscottl#define AHCI_CMD_RESET 0x0100 281195534Sscottl#define AHCI_CMD_BIST 0x0200 282195534Sscottl#define AHCI_CMD_CLR_BUSY 0x0400 283195534Sscottl 284195534Sscottl u_int16_t prd_length; /* PRD entries */ 285195534Sscottl u_int32_t bytecount; 286195534Sscottl u_int64_t cmd_table_phys; /* 128byte aligned */ 287195534Sscottl} __packed; 288195534Sscottl 289195534Sscottl/* misc defines */ 290195534Sscottl#define ATA_IRQ_RID 0 291195534Sscottl#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 292195534Sscottl 293195534Sscottlstruct ata_dmaslot { 294195534Sscottl bus_dmamap_t data_map; /* data DMA map */ 295195534Sscottl int nsegs; /* Number of segs loaded */ 296195534Sscottl}; 297195534Sscottl 298195534Sscottl/* structure holding DMA related information */ 299195534Sscottlstruct ata_dma { 300195534Sscottl bus_dma_tag_t work_tag; /* workspace DMA tag */ 301195534Sscottl bus_dmamap_t work_map; /* workspace DMA map */ 302195534Sscottl uint8_t *work; /* workspace */ 303195534Sscottl bus_addr_t work_bus; /* bus address of work */ 304195534Sscottl bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 305195534Sscottl bus_dmamap_t rfis_map; /* RFIS list DMA map */ 306195534Sscottl uint8_t *rfis; /* FIS receive area */ 307195534Sscottl bus_addr_t rfis_bus; /* bus address of rfis */ 308195534Sscottl bus_dma_tag_t data_tag; /* data DMA tag */ 309195534Sscottl u_int64_t max_address; /* highest DMA'able address */ 310195534Sscottl}; 311195534Sscottl 312195534Sscottlenum ahci_slot_states { 313195534Sscottl AHCI_SLOT_EMPTY, 314195534Sscottl AHCI_SLOT_LOADING, 315195534Sscottl AHCI_SLOT_RUNNING, 316195534Sscottl AHCI_SLOT_WAITING 317195534Sscottl}; 318195534Sscottl 319195534Sscottlstruct ahci_slot { 320195534Sscottl device_t dev; /* Device handle */ 321195534Sscottl u_int8_t slot; /* Number of this slot */ 322195534Sscottl enum ahci_slot_states state; /* Slot state */ 323195534Sscottl union ccb *ccb; /* CCB occupying slot */ 324195534Sscottl struct ata_dmaslot dma; /* DMA data of this slot */ 325195534Sscottl struct callout timeout; /* Execution timeout */ 326195534Sscottl}; 327195534Sscottl 328195534Sscottl/* structure describing an ATA channel */ 329195534Sscottlstruct ahci_channel { 330195534Sscottl device_t dev; /* Device handle */ 331195534Sscottl int unit; /* Physical channel */ 332195534Sscottl struct resource *r_mem; /* Memory of this channel */ 333195534Sscottl struct resource *r_irq; /* Interrupt of this channel */ 334195534Sscottl void *ih; /* Interrupt handle */ 335195534Sscottl struct ata_dma dma; /* DMA data */ 336195534Sscottl struct cam_sim *sim; 337195534Sscottl struct cam_path *path; 338195534Sscottl uint32_t caps; /* Controller capabilities */ 339195534Sscottl int numslots; /* Number of present slots */ 340195534Sscottl int pm_level; /* power management level */ 341195534Sscottl int sata_rev; /* Maximum allowed SATA generation */ 342195534Sscottl 343195534Sscottl struct ahci_slot slot[AHCI_MAX_SLOTS]; 344195534Sscottl union ccb *hold[AHCI_MAX_SLOTS]; 345195534Sscottl struct mtx mtx; /* state lock */ 346195534Sscottl int devices; /* What is present */ 347195534Sscottl int pm_present; /* PM presence reported */ 348195534Sscottl uint32_t rslots; /* Running slots */ 349195534Sscottl uint32_t aslots; /* Slots with atomic commands */ 350195534Sscottl int numrslots; /* Number of running slots */ 351195534Sscottl int numtslots; /* Number of tagged slots */ 352195534Sscottl int readlog; /* Our READ LOG active */ 353195534Sscottl int lastslot; /* Last used slot */ 354195534Sscottl int taggedtarget; /* Last tagged target */ 355195534Sscottl union ccb *frozen; /* Frozen command */ 356195534Sscottl}; 357195534Sscottl 358195534Sscottl/* structure describing a AHCI controller */ 359195534Sscottlstruct ahci_controller { 360195534Sscottl device_t dev; 361195534Sscottl int r_rid; 362195534Sscottl struct resource *r_mem; 363195534Sscottl struct rman sc_iomem; 364195534Sscottl struct ahci_controller_irq { 365195534Sscottl struct ahci_controller *ctlr; 366195534Sscottl struct resource *r_irq; 367195534Sscottl void *handle; 368195534Sscottl int r_irq_rid; 369195534Sscottl int mode; 370195534Sscottl#define AHCI_IRQ_MODE_ALL 0 371195534Sscottl#define AHCI_IRQ_MODE_AFTER 1 372195534Sscottl#define AHCI_IRQ_MODE_ONE 2 373195534Sscottl } irqs[16]; 374195534Sscottl int numirqs; 375195534Sscottl int channels; 376195534Sscottl int ichannels; 377195534Sscottl struct { 378195534Sscottl void (*function)(void *); 379195534Sscottl void *argument; 380195534Sscottl } interrupt[AHCI_MAX_PORTS]; 381195534Sscottl}; 382195534Sscottl 383195534Sscottlenum ahci_err_type { 384195534Sscottl AHCI_ERR_NONE, /* No error */ 385195534Sscottl AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 386195534Sscottl AHCI_ERR_INNOCENT, /* Innocent victim. */ 387195534Sscottl AHCI_ERR_TFE, /* Task File Error. */ 388195534Sscottl AHCI_ERR_SATA, /* SATA error. */ 389195534Sscottl AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 390195534Sscottl AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 391195534Sscottl * until READ LOG executed to reveal error. */ 392195534Sscottl}; 393195534Sscottl 394195534Sscottl/* macros to hide busspace uglyness */ 395195534Sscottl#define ATA_INB(res, offset) \ 396195534Sscottl bus_read_1((res), (offset)) 397195534Sscottl#define ATA_INW(res, offset) \ 398195534Sscottl bus_read_2((res), (offset)) 399195534Sscottl#define ATA_INL(res, offset) \ 400195534Sscottl bus_read_4((res), (offset)) 401195534Sscottl#define ATA_INSW(res, offset, addr, count) \ 402195534Sscottl bus_read_multi_2((res), (offset), (addr), (count)) 403195534Sscottl#define ATA_INSW_STRM(res, offset, addr, count) \ 404195534Sscottl bus_read_multi_stream_2((res), (offset), (addr), (count)) 405195534Sscottl#define ATA_INSL(res, offset, addr, count) \ 406195534Sscottl bus_read_multi_4((res), (offset), (addr), (count)) 407195534Sscottl#define ATA_INSL_STRM(res, offset, addr, count) \ 408195534Sscottl bus_read_multi_stream_4((res), (offset), (addr), (count)) 409195534Sscottl#define ATA_OUTB(res, offset, value) \ 410195534Sscottl bus_write_1((res), (offset), (value)) 411195534Sscottl#define ATA_OUTW(res, offset, value) \ 412195534Sscottl bus_write_2((res), (offset), (value)) 413195534Sscottl#define ATA_OUTL(res, offset, value) \ 414195534Sscottl bus_write_4((res), (offset), (value)) 415195534Sscottl#define ATA_OUTSW(res, offset, addr, count) \ 416195534Sscottl bus_write_multi_2((res), (offset), (addr), (count)) 417195534Sscottl#define ATA_OUTSW_STRM(res, offset, addr, count) \ 418195534Sscottl bus_write_multi_stream_2((res), (offset), (addr), (count)) 419195534Sscottl#define ATA_OUTSL(res, offset, addr, count) \ 420195534Sscottl bus_write_multi_4((res), (offset), (addr), (count)) 421195534Sscottl#define ATA_OUTSL_STRM(res, offset, addr, count) \ 422195534Sscottl bus_write_multi_stream_4((res), (offset), (addr), (count)) 423