adwmcode.h revision 225736
1221807Sstas/*- 2221807Sstas * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 3221807Sstas * 4221807Sstas * $FreeBSD: stable/9/sys/dev/advansys/adwmcode.h 139749 2005-01-06 01:43:34Z imp $ 5221807Sstas * 6221807Sstas * Obtained from: 7221807Sstas * 8221807Sstas * Copyright (c) 1995-1999 Advanced System Products, Inc. 9221807Sstas * All Rights Reserved. 10221807Sstas * 11221807Sstas * Redistribution and use in source and binary forms, with or without 12221807Sstas * modification, are permitted provided that redistributions of source 13221807Sstas * code retain the above copyright notice and this comment without 14221807Sstas * modification. 15221807Sstas */ 16221807Sstas 17221807Sstas#ifndef _ADMCODE_H_ 18221807Sstas#define _ADMCODE_H_ 19221807Sstas 20221807Sstasstruct adw_mcode 21221807Sstas{ 22221807Sstas const u_int8_t* mcode_buf; 23221807Sstas const u_int32_t mcode_chksum; 24221807Sstas const u_int16_t mcode_size; 25221807Sstas}; 26221807Sstas 27221807Sstasextern const struct adw_mcode adw_asc3550_mcode_data; 28221807Sstasextern const struct adw_mcode adw_asc38C0800_mcode_data; 29221807Sstas 30221807Sstas/* 31221807Sstas * Fixed LRAM locations of microcode operating variables. 32221807Sstas */ 33221807Sstas#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 34221807Sstas#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 35221807Sstas#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 36221807Sstas#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 37221807Sstas#define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 38221807Sstas#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 39221807Sstas#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 40221807Sstas#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 41221807Sstas#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */ 42221807Sstas#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 43221807Sstas#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 44221807Sstas#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 45221807Sstas#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 46221807Sstas#define ADW_MC_CHIP_TYPE 0x009A 47221807Sstas#define ADW_MC_INTRB_CODE 0x009B 48221807Sstas#define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 49221807Sstas#define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */ 50221807Sstas#define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/ 51221807Sstas#define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /* 52221807Sstas * Host Initiated 53221807Sstas * SCSI Bus Reset. 54221807Sstas */ 55221807Sstas#define ADW_MC_WDTR_ABLE_BIOS_31 0x0120 56221807Sstas#define ADW_MC_WDTR_ABLE 0x009C 57221807Sstas#define ADW_MC_SDTR_ABLE 0x009E 58221807Sstas#define ADW_MC_TAGQNG_ABLE 0x00A0 59221807Sstas#define ADW_MC_DISC_ENABLE 0x00A2 60221807Sstas#define ADW_MC_IDLE_CMD_STATUS 0x00A4 61221807Sstas#define ADW_MC_IDLE_CMD 0x00A6 62221807Sstas#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8 63221807Sstas#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 64221807Sstas#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 65221807Sstas#define ADW_MC_DEFAULT_MEM_CFG 0x00B0 66221807Sstas#define ADW_MC_DEFAULT_SEL_MASK 0x00B2 67221807Sstas#define ADW_MC_RISC_NEXT_READY 0x00B4 68221807Sstas#define ADW_MC_RISC_NEXT_DONE 0x00B5 69221807Sstas#define ADW_MC_SDTR_DONE 0x00B6 70221807Sstas#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 71221807Sstas#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 72221807Sstas#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 73221807Sstas#define ADW_HSHK_CFG_WIDE_XFR 0x8000 74221807Sstas#define ADW_HSHK_CFG_RATE_MASK 0x7F00 75221807Sstas#define ADW_HSHK_CFG_RATE_SHIFT 8 76221807Sstas#define ADW_HSHK_CFG_OFFSET 0x001F 77221807Sstas#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 78221807Sstas#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 79221807Sstas#define ADW_MC_WDTR_DONE 0x0124 80221807Sstas#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 81221807Sstas#define ADW_MC_ICQ 0x0160 82221807Sstas#define ADW_MC_IRQ 0x0164 83221807Sstas 84221807Sstas/* ADW_SCSI_REQ_Q 'cntl' field values */ 85221807Sstas#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */ 86221807Sstas#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 87221807Sstas#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 88221807Sstas#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 89221807Sstas#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */ 90221807Sstas 91221807Sstas#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 92221807Sstas#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 93221807Sstas#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/ 94221807Sstas#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 95221807Sstas#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/ 96221807Sstas/* 97221807Sstas * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or 98221807Sstas * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 99221807Sstas */ 100221807Sstas#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 101221807Sstas#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 102221807Sstas 103struct adw_carrier 104{ 105 u_int32_t carr_offset; /* Carrier byte offset into our array */ 106 u_int32_t carr_ba; /* Carrier Bus Address */ 107 u_int32_t areq_ba; /* SCSI Req Queue Bus Address */ 108 u_int32_t next_ba; 109#define ADW_RQ_DONE 0x00000001 110#define ADW_CQ_STOPPER 0x00000000 111#define ADW_NEXT_BA_MASK 0xFFFFFFF0 112}; 113 114/* 115 * Microcode idle loop commands 116 */ 117typedef enum { 118 ADW_IDLE_CMD_COMPLETED = 0x0000, 119 ADW_IDLE_CMD_STOP_CHIP = 0x0001, 120 ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 121 ADW_IDLE_CMD_SEND_INT = 0x0004, 122 ADW_IDLE_CMD_ABORT = 0x0008, 123 ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 124 ADW_IDLE_CMD_SCSI_RESET_START = 0x0020, 125 ADW_IDLE_CMD_SCSI_RESET_END = 0x0040, 126 ADW_IDLE_CMD_SCSIREQ = 0x0080 127} adw_idle_cmd_t; 128 129typedef enum { 130 ADW_IDLE_CMD_FAILURE = 0x0000, 131 ADW_IDLE_CMD_SUCCESS = 0x0001 132} adw_idle_cmd_status_t; 133 134 135#endif /* _ADMCODE_H_ */ 136