advlib.c revision 18781
118781Sgibbs/* 218781Sgibbs * Low level routines for the Advanced Systems Inc. SCSI controllers chips 318781Sgibbs * 418781Sgibbs * Copyright (c) 1996 Justin T. Gibbs. 518781Sgibbs * All rights reserved. 618781Sgibbs * 718781Sgibbs * Redistribution and use in source and binary forms, with or without 818781Sgibbs * modification, are permitted provided that the following conditions 918781Sgibbs * are met: 1018781Sgibbs * 1. Redistributions of source code must retain the above copyright 1118781Sgibbs * notice immediately at the beginning of the file, without modification, 1218781Sgibbs * this list of conditions, and the following disclaimer. 1318781Sgibbs * 2. Redistributions in binary form must reproduce the above copyright 1418781Sgibbs * notice, this list of conditions and the following disclaimer in the 1518781Sgibbs * documentation and/or other materials provided with the distribution. 1618781Sgibbs * 3. The name of the author may not be used to endorse or promote products 1718781Sgibbs * derived from this software without specific prior written permission. 1818781Sgibbs * 1918781Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2018781Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2118781Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2218781Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2318781Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2418781Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2518781Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2618781Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2718781Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2818781Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2918781Sgibbs * SUCH DAMAGE. 3018781Sgibbs * 3118781Sgibbs * $Id$ 3218781Sgibbs */ 3318781Sgibbs/* 3418781Sgibbs * Ported from: 3518781Sgibbs * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 3618781Sgibbs * 3718781Sgibbs * Copyright (c) 1995-1996 Advanced System Products, Inc. 3818781Sgibbs * All Rights Reserved. 3918781Sgibbs * 4018781Sgibbs * Redistribution and use in source and binary forms, with or without 4118781Sgibbs * modification, are permitted provided that redistributions of source 4218781Sgibbs * code retain the above copyright notice and this comment without 4318781Sgibbs * modification. 4418781Sgibbs */ 4518781Sgibbs 4618781Sgibbs#include <sys/param.h> 4718781Sgibbs#include <sys/systm.h> 4818781Sgibbs 4918781Sgibbs#include <machine/clock.h> 5018781Sgibbs 5118781Sgibbs#include <scsi/scsi_all.h> 5218781Sgibbs#include <scsi/scsi_message.h> 5318781Sgibbs#include <scsi/scsi_disk.h> 5418781Sgibbs 5518781Sgibbs#include <vm/vm.h> 5618781Sgibbs#include <vm/vm_param.h> 5718781Sgibbs#include <vm/pmap.h> 5818781Sgibbs 5918781Sgibbs#include <dev/advansys/advlib.h> 6018781Sgibbs#include <dev/advansys/advmcode.h> 6118781Sgibbs 6218781Sgibbs/* 6318781Sgibbs * Allowable periods in ns 6418781Sgibbs */ 6518781Sgibbsu_int8_t adv_sdtr_period_tbl[] = 6618781Sgibbs{ 6718781Sgibbs 25, 6818781Sgibbs 30, 6918781Sgibbs 35, 7018781Sgibbs 40, 7118781Sgibbs 50, 7218781Sgibbs 60, 7318781Sgibbs 70, 7418781Sgibbs 85 7518781Sgibbs}; 7618781Sgibbs 7718781Sgibbsstruct sdtr_xmsg { 7818781Sgibbs u_int8_t msg_type; 7918781Sgibbs u_int8_t msg_len; 8018781Sgibbs u_int8_t msg_req; 8118781Sgibbs u_int8_t xfer_period; 8218781Sgibbs u_int8_t req_ack_offset; 8318781Sgibbs u_int8_t res; 8418781Sgibbs}; 8518781Sgibbs 8618781Sgibbs/* 8718781Sgibbs * Some of the early PCI adapters have problems with 8818781Sgibbs * async transfers. Instead try to use an offset of 8918781Sgibbs * 1. 9018781Sgibbs */ 9118781Sgibbs#define ASYN_SDTR_DATA_FIX 0x41 9218781Sgibbs 9318781Sgibbs/* LRAM routines */ 9418781Sgibbsstatic void adv_read_lram_16_multi __P((struct adv_softc *adv, u_int16_t s_addr, 9518781Sgibbs u_int16_t *buffer, int count)); 9618781Sgibbsstatic void adv_write_lram_16_multi __P((struct adv_softc *adv, 9718781Sgibbs u_int16_t s_addr, u_int16_t *buffer, 9818781Sgibbs int count)); 9918781Sgibbsstatic void adv_mset_lram_16 __P((struct adv_softc *adv, 10018781Sgibbs u_int16_t s_addr, u_int16_t set_value, 10118781Sgibbs int count)); 10218781Sgibbsstatic u_int32_t adv_msum_lram_16 __P((struct adv_softc *adv, u_int16_t s_addr, int count)); 10318781Sgibbs 10418781Sgibbsstatic int adv_write_and_verify_lram_16 __P((struct adv_softc *adv, 10518781Sgibbs u_int16_t addr, u_int16_t value)); 10618781Sgibbsstatic u_int32_t adv_read_lram_32 __P((struct adv_softc *adv, u_int16_t addr)); 10718781Sgibbs 10818781Sgibbs 10918781Sgibbsstatic void adv_write_lram_32 __P((struct adv_softc *adv, u_int16_t addr, 11018781Sgibbs u_int32_t value)); 11118781Sgibbsstatic void adv_write_lram_32_multi __P((struct adv_softc *adv, u_int16_t s_addr, 11218781Sgibbs u_int32_t *buffer, int count)); 11318781Sgibbs 11418781Sgibbs/* EEPROM routines */ 11518781Sgibbsstatic u_int16_t adv_read_eeprom_16 __P((struct adv_softc *adv, u_int8_t addr)); 11618781Sgibbsstatic u_int16_t adv_write_eeprom_16 __P((struct adv_softc *adv, u_int8_t addr, u_int16_t value)); 11718781Sgibbsstatic int adv_write_eeprom_cmd_reg __P((struct adv_softc *adv, u_int8_t cmd_reg)); 11818781Sgibbsstatic int adv_set_eeprom_config_once __P((struct adv_softc *adv, 11918781Sgibbs struct adv_eeprom_config *eeprom_config)); 12018781Sgibbs 12118781Sgibbs/* Initialization */ 12218781Sgibbsstatic u_int32_t adv_load_microcode __P((struct adv_softc *adv, u_int16_t s_addr, 12318781Sgibbs u_int16_t *mcode_buf, u_int16_t mcode_size)); 12418781Sgibbsstatic void adv_init_lram __P((struct adv_softc *adv)); 12518781Sgibbsstatic int adv_init_microcode_var __P((struct adv_softc *adv)); 12618781Sgibbsstatic void adv_init_qlink_var __P((struct adv_softc *adv)); 12718781Sgibbs 12818781Sgibbs/* Interrupts */ 12918781Sgibbsstatic void adv_disable_interrupt __P((struct adv_softc *adv)); 13018781Sgibbsstatic void adv_enable_interrupt __P((struct adv_softc *adv)); 13118781Sgibbsstatic void adv_toggle_irq_act __P((struct adv_softc *adv)); 13218781Sgibbs 13318781Sgibbs/* Chip Control */ 13418781Sgibbs#if UNUSED 13518781Sgibbsstatic void adv_start_execution __P((struct adv_softc *adv)); 13618781Sgibbs#endif 13718781Sgibbsstatic int adv_start_chip __P((struct adv_softc *adv)); 13818781Sgibbsstatic int adv_stop_chip __P((struct adv_softc *adv)); 13918781Sgibbsstatic void adv_set_chip_ih __P((struct adv_softc *adv, u_int16_t ins_code)); 14018781Sgibbsstatic void adv_set_bank __P((struct adv_softc *adv, u_int8_t bank)); 14118781Sgibbs#if UNUSED 14218781Sgibbsstatic u_int8_t adv_get_chip_scsi_ctrl __P((struct adv_softc *adv)); 14318781Sgibbs#endif 14418781Sgibbs 14518781Sgibbs/* Queue handling and execution */ 14618781Sgibbsstatic int adv_sgcount_to_qcount __P((int sgcount)); 14718781Sgibbsstatic void adv_get_q_info __P((struct adv_softc *adv, u_int16_t s_addr, u_int16_t *inbuf, 14818781Sgibbs int words)); 14918781Sgibbsstatic u_int adv_get_num_free_queues __P((struct adv_softc *adv, u_int8_t n_qs)); 15018781Sgibbsstatic u_int8_t adv_alloc_free_queues __P((struct adv_softc *adv, u_int8_t free_q_head, 15118781Sgibbs u_int8_t n_free_q)); 15218781Sgibbsstatic u_int8_t adv_alloc_free_queue __P((struct adv_softc *adv, u_int8_t free_q_head)); 15318781Sgibbsstatic int adv_send_scsi_queue __P((struct adv_softc *adv, struct adv_scsi_q *scsiq, 15418781Sgibbs u_int8_t n_q_required)); 15518781Sgibbsstatic void adv_put_ready_sg_list_queue __P((struct adv_softc *adv, struct adv_scsi_q *scsiq, 15618781Sgibbs u_int8_t q_no)); 15718781Sgibbsstatic void adv_put_ready_queue __P((struct adv_softc *adv, struct adv_scsi_q *scsiq, u_int8_t q_no)); 15818781Sgibbsstatic void adv_put_scsiq __P((struct adv_softc *adv, u_int16_t s_addr, u_int16_t *buffer, int words)); 15918781Sgibbs 16018781Sgibbs/* SDTR */ 16118781Sgibbsstatic u_int8_t adv_msgout_sdtr __P((struct adv_softc *adv, u_int8_t sdtr_period, u_int8_t sdtr_offset)); 16218781Sgibbsstatic u_int8_t adv_get_card_sync_setting __P((u_int8_t period, u_int8_t offset)); 16318781Sgibbsstatic void adv_set_chip_sdtr __P((struct adv_softc *adv, u_int8_t sdtr_data, 16418781Sgibbs u_int8_t tid_no)); 16518781Sgibbs 16618781Sgibbs 16718781Sgibbs/* Exported Function first */ 16818781Sgibbs 16918781Sgibbsu_int8_t 17018781Sgibbsadv_read_lram_8(adv, addr) 17118781Sgibbs struct adv_softc *adv; 17218781Sgibbs u_int16_t addr; 17318781Sgibbs 17418781Sgibbs{ 17518781Sgibbs u_int8_t byte_data; 17618781Sgibbs u_int16_t word_data; 17718781Sgibbs 17818781Sgibbs /* 17918781Sgibbs * LRAM is accessed on 16bit boundaries. 18018781Sgibbs */ 18118781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr & 0xFFFE); 18218781Sgibbs word_data = ADV_INW(adv, ADV_LRAM_DATA); 18318781Sgibbs if (addr & 1) { 18418781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 18518781Sgibbs byte_data = (u_int8_t)(word_data & 0xFF); 18618781Sgibbs#else 18718781Sgibbs byte_data = (u_int8_t)((word_data >> 8) & 0xFF); 18818781Sgibbs#endif 18918781Sgibbs } else { 19018781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 19118781Sgibbs byte_data = (u_int8_t)((word_data >> 8) & 0xFF); 19218781Sgibbs#else 19318781Sgibbs byte_data = (u_int8_t)(word_data & 0xFF); 19418781Sgibbs#endif 19518781Sgibbs } 19618781Sgibbs return (byte_data); 19718781Sgibbs} 19818781Sgibbs 19918781Sgibbsvoid 20018781Sgibbsadv_write_lram_8(adv, addr, value) 20118781Sgibbs struct adv_softc *adv; 20218781Sgibbs u_int16_t addr; 20318781Sgibbs u_int8_t value; 20418781Sgibbs{ 20518781Sgibbs u_int16_t word_data; 20618781Sgibbs 20718781Sgibbs word_data = adv_read_lram_16(adv, addr & 0xFFFE); 20818781Sgibbs if (addr & 1) { 20918781Sgibbs word_data &= 0x00FF; 21018781Sgibbs word_data |= (((u_int8_t)value << 8) & 0xFF00); 21118781Sgibbs } else { 21218781Sgibbs word_data &= 0xFF00; 21318781Sgibbs word_data |= ((u_int8_t)value & 0x00FF); 21418781Sgibbs } 21518781Sgibbs adv_write_lram_16(adv, addr & 0xFFFE, word_data); 21618781Sgibbs} 21718781Sgibbs 21818781Sgibbs 21918781Sgibbsu_int16_t 22018781Sgibbsadv_read_lram_16(adv, addr) 22118781Sgibbs struct adv_softc *adv; 22218781Sgibbs u_int16_t addr; 22318781Sgibbs{ 22418781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 22518781Sgibbs return (ADV_INW(adv, ADV_LRAM_DATA)); 22618781Sgibbs} 22718781Sgibbs 22818781Sgibbsvoid 22918781Sgibbsadv_write_lram_16(adv, addr, value) 23018781Sgibbs struct adv_softc *adv; 23118781Sgibbs u_int16_t addr; 23218781Sgibbs u_int16_t value; 23318781Sgibbs{ 23418781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 23518781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, value); 23618781Sgibbs} 23718781Sgibbs 23818781Sgibbs 23918781Sgibbs/* 24018781Sgibbs * Return the fully qualified board type for the adapter. 24118781Sgibbs * The chip_revision must be set before this function is called. 24218781Sgibbs */ 24318781Sgibbsvoid 24418781Sgibbsadv_get_board_type(adv) 24518781Sgibbs struct adv_softc *adv; 24618781Sgibbs{ 24718781Sgibbs if ((adv->chip_version >= ADV_CHIP_MIN_VER_VL) && 24818781Sgibbs (adv->chip_version <= ADV_CHIP_MAX_VER_VL)) { 24918781Sgibbs if (((adv->iobase & 0x0C30) == 0x0C30) || 25018781Sgibbs ((adv->iobase & 0x0C50) == 0x0C50)) { 25118781Sgibbs adv->type = ADV_EISA; 25218781Sgibbs } else 25318781Sgibbs adv->type = ADV_VL; 25418781Sgibbs } else if ((adv->chip_version >= ADV_CHIP_MIN_VER_ISA) && 25518781Sgibbs (adv->chip_version <= ADV_CHIP_MAX_VER_ISA)) { 25618781Sgibbs if (adv->chip_version >= ADV_CHIP_MIN_VER_ISA_PNP) { 25718781Sgibbs adv->type = ADV_ISAPNP; 25818781Sgibbs } else 25918781Sgibbs adv->type = ADV_ISA; 26018781Sgibbs } else if ((adv->chip_version >= ADV_CHIP_MIN_VER_PCI) && 26118781Sgibbs (adv->chip_version <= ADV_CHIP_MAX_VER_PCI)) { 26218781Sgibbs adv->type = ADV_PCI; 26318781Sgibbs } else 26418781Sgibbs panic("adv_get_board_type: Unknown board type encountered"); 26518781Sgibbs} 26618781Sgibbs 26718781Sgibbsu_int16_t 26818781Sgibbsadv_get_eeprom_config(adv, eeprom_config) 26918781Sgibbs struct adv_softc *adv; 27018781Sgibbs struct adv_eeprom_config *eeprom_config; 27118781Sgibbs{ 27218781Sgibbs u_int16_t sum; 27318781Sgibbs u_int16_t *wbuf; 27418781Sgibbs u_int8_t cfg_beg; 27518781Sgibbs u_int8_t cfg_end; 27618781Sgibbs u_int8_t s_addr; 27718781Sgibbs 27818781Sgibbs wbuf = (u_int16_t *)eeprom_config; 27918781Sgibbs sum = 0; 28018781Sgibbs 28118781Sgibbs for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 28218781Sgibbs *wbuf = adv_read_eeprom_16(adv, s_addr); 28318781Sgibbs sum += *wbuf; 28418781Sgibbs } 28518781Sgibbs 28618781Sgibbs if (adv->type & ADV_VL) { 28718781Sgibbs cfg_beg = ADV_EEPROM_CFG_BEG_VL; 28818781Sgibbs cfg_end = ADV_EEPROM_MAX_ADDR_VL; 28918781Sgibbs } else { 29018781Sgibbs cfg_beg = ADV_EEPROM_CFG_BEG; 29118781Sgibbs cfg_end = ADV_EEPROM_MAX_ADDR; 29218781Sgibbs } 29318781Sgibbs 29418781Sgibbs for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 29518781Sgibbs *wbuf = adv_read_eeprom_16(adv, s_addr); 29618781Sgibbs sum += *wbuf; 29718781Sgibbs#if ADV_DEBUG_EEPROM 29818781Sgibbs printf("Addr 0x%x: 0x%04x\n", s_addr, *wbuf); 29918781Sgibbs#endif 30018781Sgibbs } 30118781Sgibbs *wbuf = adv_read_eeprom_16(adv, s_addr); 30218781Sgibbs return (sum); 30318781Sgibbs} 30418781Sgibbs 30518781Sgibbsint 30618781Sgibbsadv_set_eeprom_config(adv, eeprom_config) 30718781Sgibbs struct adv_softc *adv; 30818781Sgibbs struct adv_eeprom_config *eeprom_config; 30918781Sgibbs{ 31018781Sgibbs int retry; 31118781Sgibbs 31218781Sgibbs retry = 0; 31318781Sgibbs while (1) { 31418781Sgibbs if (adv_set_eeprom_config_once(adv, eeprom_config) == 0) { 31518781Sgibbs break; 31618781Sgibbs } 31718781Sgibbs if (++retry > ADV_EEPROM_MAX_RETRY) { 31818781Sgibbs break; 31918781Sgibbs } 32018781Sgibbs } 32118781Sgibbs return (retry > ADV_EEPROM_MAX_RETRY); 32218781Sgibbs} 32318781Sgibbs 32418781Sgibbsint 32518781Sgibbsadv_reset_chip_and_scsi_bus(adv) 32618781Sgibbs struct adv_softc *adv; 32718781Sgibbs{ 32818781Sgibbs adv_stop_chip(adv); 32918781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_SCSI_RESET | ADV_CC_HALT); 33018781Sgibbs DELAY(200 * 1000); 33118781Sgibbs 33218781Sgibbs adv_set_chip_ih(adv, ADV_INS_RFLAG_WTM); 33318781Sgibbs adv_set_chip_ih(adv, ADV_INS_HALT); 33418781Sgibbs 33518781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_HALT); 33618781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT); 33718781Sgibbs DELAY(200 * 1000); 33818781Sgibbs return (adv_is_chip_halted(adv)); 33918781Sgibbs} 34018781Sgibbs 34118781Sgibbsint 34218781Sgibbsadv_test_external_lram(adv) 34318781Sgibbs struct adv_softc* adv; 34418781Sgibbs{ 34518781Sgibbs u_int16_t q_addr; 34618781Sgibbs u_int16_t saved_value; 34718781Sgibbs int success; 34818781Sgibbs 34918781Sgibbs success = 0; 35018781Sgibbs 35118781Sgibbs /* XXX Why 241? */ 35218781Sgibbs q_addr = ADV_QNO_TO_QADDR(241); 35318781Sgibbs saved_value = adv_read_lram_16(adv, q_addr); 35418781Sgibbs if (adv_write_and_verify_lram_16(adv, q_addr, 0x55AA) == 0) { 35518781Sgibbs success = 1; 35618781Sgibbs adv_write_lram_16(adv, q_addr, saved_value); 35718781Sgibbs } 35818781Sgibbs return (success); 35918781Sgibbs} 36018781Sgibbs 36118781Sgibbs 36218781Sgibbsint 36318781Sgibbsadv_init_lram_and_mcode(adv) 36418781Sgibbs struct adv_softc *adv; 36518781Sgibbs{ 36618781Sgibbs u_int32_t retval; 36718781Sgibbs adv_disable_interrupt(adv); 36818781Sgibbs 36918781Sgibbs adv_init_lram(adv); 37018781Sgibbs 37118781Sgibbs retval = adv_load_microcode(adv, 0, (u_int16_t *)adv_mcode, adv_mcode_size); 37218781Sgibbs if (retval != adv_mcode_chksum) { 37318781Sgibbs printf("adv%d: Microcode download failed checksum!\n", 37418781Sgibbs adv->unit); 37518781Sgibbs return (1); 37618781Sgibbs } 37718781Sgibbs 37818781Sgibbs if (adv_init_microcode_var(adv) != 0) 37918781Sgibbs return (1); 38018781Sgibbs 38118781Sgibbs adv_enable_interrupt(adv); 38218781Sgibbs return (0); 38318781Sgibbs} 38418781Sgibbs 38518781Sgibbsu_int8_t 38618781Sgibbsadv_get_chip_irq(adv) 38718781Sgibbs struct adv_softc *adv; 38818781Sgibbs{ 38918781Sgibbs u_int16_t cfg_lsw; 39018781Sgibbs u_int8_t chip_irq; 39118781Sgibbs 39218781Sgibbs cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW); 39318781Sgibbs 39418781Sgibbs if ((adv->type & ADV_VL) != 0) { 39518781Sgibbs chip_irq = (u_int8_t)(((cfg_lsw >> 2) & 0x07)); 39618781Sgibbs if ((chip_irq == 0) || 39718781Sgibbs (chip_irq == 4) || 39818781Sgibbs (chip_irq == 7)) { 39918781Sgibbs return (0); 40018781Sgibbs } 40118781Sgibbs return (chip_irq + (ADV_MIN_IRQ_NO - 1)); 40218781Sgibbs } 40318781Sgibbs chip_irq = (u_int8_t)(((cfg_lsw >> 2) & 0x03)); 40418781Sgibbs if (chip_irq == 3) 40518781Sgibbs chip_irq += 2; 40618781Sgibbs return (chip_irq + ADV_MIN_IRQ_NO); 40718781Sgibbs} 40818781Sgibbs 40918781Sgibbsu_int8_t 41018781Sgibbsadv_set_chip_irq(adv, irq_no) 41118781Sgibbs struct adv_softc *adv; 41218781Sgibbs u_int8_t irq_no; 41318781Sgibbs{ 41418781Sgibbs u_int16_t cfg_lsw; 41518781Sgibbs 41618781Sgibbs if ((adv->type & ADV_VL) != 0) { 41718781Sgibbs if (irq_no != 0) { 41818781Sgibbs if ((irq_no < ADV_MIN_IRQ_NO) || (irq_no > ADV_MAX_IRQ_NO)) { 41918781Sgibbs irq_no = 0; 42018781Sgibbs } else { 42118781Sgibbs irq_no -= ADV_MIN_IRQ_NO - 1; 42218781Sgibbs } 42318781Sgibbs } 42418781Sgibbs cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE3; 42518781Sgibbs cfg_lsw |= 0x0010; 42618781Sgibbs ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw); 42718781Sgibbs adv_toggle_irq_act(adv); 42818781Sgibbs 42918781Sgibbs cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE0; 43018781Sgibbs cfg_lsw |= (irq_no & 0x07) << 2; 43118781Sgibbs ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw); 43218781Sgibbs adv_toggle_irq_act(adv); 43318781Sgibbs } else if ((adv->type & ADV_ISA) != 0) { 43418781Sgibbs if (irq_no == 15) 43518781Sgibbs irq_no -= 2; 43618781Sgibbs irq_no -= ADV_MIN_IRQ_NO; 43718781Sgibbs cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFF3; 43818781Sgibbs cfg_lsw |= (irq_no & 0x03) << 2; 43918781Sgibbs ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw); 44018781Sgibbs } 44118781Sgibbs return (adv_get_chip_irq(adv)); 44218781Sgibbs} 44318781Sgibbs 44418781Sgibbsint 44518781Sgibbsadv_execute_scsi_queue(adv, scsiq) 44618781Sgibbs struct adv_softc *adv; 44718781Sgibbs struct adv_scsi_q *scsiq; 44818781Sgibbs{ 44918781Sgibbs int retval; 45018781Sgibbs u_int n_q_required; 45118781Sgibbs int s; 45218781Sgibbs u_int32_t addr; 45318781Sgibbs u_int8_t sg_entry_cnt; 45418781Sgibbs u_int8_t target_ix; 45518781Sgibbs u_int8_t sg_entry_cnt_minus_one; 45618781Sgibbs u_int8_t tid_no; 45718781Sgibbs u_int8_t sdtr_data; 45818781Sgibbs u_int32_t *p_data_addr; 45918781Sgibbs u_int32_t *p_data_bcount; 46018781Sgibbs 46118781Sgibbs scsiq->q1.q_no = 0; 46218781Sgibbs retval = 1; /* Default to error case */ 46318781Sgibbs target_ix = scsiq->q2.target_ix; 46418781Sgibbs tid_no = ADV_TIX_TO_TID(target_ix); 46518781Sgibbs 46618781Sgibbs n_q_required = 1; 46718781Sgibbs 46818781Sgibbs s = splbio(); 46918781Sgibbs if (scsiq->cdbptr->opcode == REQUEST_SENSE) { 47018781Sgibbs if (((adv->initiate_sdtr & scsiq->q1.target_id) != 0) 47118781Sgibbs && ((adv->sdtr_done & scsiq->q1.target_id) != 0)) { 47218781Sgibbs int sdtr_index; 47318781Sgibbs 47418781Sgibbs sdtr_data = adv_read_lram_8(adv, ADVV_SDTR_DATA_BEG + tid_no); 47518781Sgibbs sdtr_index = (sdtr_data >> 4); 47618781Sgibbs adv_msgout_sdtr(adv, adv_sdtr_period_tbl[sdtr_index], 47718781Sgibbs (sdtr_data & ADV_SYN_MAX_OFFSET)); 47818781Sgibbs scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); 47918781Sgibbs } 48018781Sgibbs } 48118781Sgibbs 48218781Sgibbs if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 48318781Sgibbs sg_entry_cnt = scsiq->sg_head->entry_cnt; 48418781Sgibbs sg_entry_cnt_minus_one = sg_entry_cnt - 1; 48518781Sgibbs 48618781Sgibbs#ifdef DIAGNOSTIC 48718781Sgibbs if (sg_entry_cnt <= 1) 48818781Sgibbs panic("adv_execute_scsi_queue: Queue with QC_SG_HEAD set but %d segs.", sg_entry_cnt); 48918781Sgibbs 49018781Sgibbs if (sg_entry_cnt > ADV_MAX_SG_LIST) 49118781Sgibbs panic("adv_execute_scsi_queue: Queue with too many segs."); 49218781Sgibbs 49318781Sgibbs if (adv->type & (ADV_ISA | ADV_VL | ADV_EISA)) { 49418781Sgibbs for (i = 0; i < sg_entry_cnt_minus_one; i++) { 49518781Sgibbs addr = scsiq->sg_head->sg_list[i].addr + 49618781Sgibbs scsiq->sg_head->sg_list[i].bytes; 49718781Sgibbs 49818781Sgibbs if ((addr & 0x0003) != 0) 49918781Sgibbs panic("adv_execute_scsi_queue: SG with odd address or byte count"); 50018781Sgibbs } 50118781Sgibbs } 50218781Sgibbs#endif 50318781Sgibbs p_data_addr = &scsiq->sg_head->sg_list[sg_entry_cnt_minus_one].addr; 50418781Sgibbs p_data_bcount = &scsiq->sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 50518781Sgibbs 50618781Sgibbs n_q_required = adv_sgcount_to_qcount(sg_entry_cnt); 50718781Sgibbs scsiq->sg_head->queue_cnt = n_q_required - 1; 50818781Sgibbs } else { 50918781Sgibbs p_data_addr = &scsiq->q1.data_addr; 51018781Sgibbs p_data_bcount = &scsiq->q1.data_cnt; 51118781Sgibbs n_q_required = 1; 51218781Sgibbs } 51318781Sgibbs 51418781Sgibbs if (adv->bug_fix_control & ADV_BUG_FIX_ADD_ONE_BYTE) { 51518781Sgibbs addr = *p_data_addr + *p_data_bcount; 51618781Sgibbs if ((addr & 0x0003) != 0) { 51718781Sgibbs /* 51818781Sgibbs * XXX Is this extra test (the one on data_cnt) really only supposed to apply 51918781Sgibbs * to the non SG case or was it a bug due to code duplication? 52018781Sgibbs */ 52118781Sgibbs if ((scsiq->q1.cntl & QC_SG_HEAD) != 0 || (scsiq->q1.data_cnt & 0x01FF) == 0) { 52218781Sgibbs if ((scsiq->cdbptr->opcode == READ_COMMAND) || 52318781Sgibbs (scsiq->cdbptr->opcode == READ_BIG)) { 52418781Sgibbs if ((scsiq->q2.tag_code & ADV_TAG_FLAG_ADD_ONE_BYTE) == 0) { 52518781Sgibbs (*p_data_bcount)++; 52618781Sgibbs scsiq->q2.tag_code |= ADV_TAG_FLAG_ADD_ONE_BYTE; 52718781Sgibbs } 52818781Sgibbs } 52918781Sgibbs 53018781Sgibbs } 53118781Sgibbs } 53218781Sgibbs } 53318781Sgibbs 53418781Sgibbs if ((adv_get_num_free_queues(adv, n_q_required) >= n_q_required) 53518781Sgibbs || ((scsiq->q1.cntl & QC_URGENT) != 0)) 53618781Sgibbs retval = adv_send_scsi_queue(adv, scsiq, n_q_required); 53718781Sgibbs 53818781Sgibbs splx(s); 53918781Sgibbs return (retval); 54018781Sgibbs} 54118781Sgibbs 54218781Sgibbs 54318781Sgibbsu_int8_t 54418781Sgibbsadv_copy_lram_doneq(adv, q_addr, scsiq, max_dma_count) 54518781Sgibbs struct adv_softc *adv; 54618781Sgibbs u_int16_t q_addr; 54718781Sgibbs struct adv_q_done_info *scsiq; 54818781Sgibbs u_int32_t max_dma_count; 54918781Sgibbs{ 55018781Sgibbs u_int16_t val; 55118781Sgibbs u_int8_t sg_queue_cnt; 55218781Sgibbs 55318781Sgibbs adv_get_q_info(adv, q_addr + ADV_SCSIQ_DONE_INFO_BEG, 55418781Sgibbs (u_int16_t *)scsiq, 55518781Sgibbs (sizeof(scsiq->d2) + sizeof(scsiq->d3)) / 2); 55618781Sgibbs 55718781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 55818781Sgibbs adv_adj_endian_qdone_info(scsiq); 55918781Sgibbs#endif 56018781Sgibbs 56118781Sgibbs val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_STATUS); 56218781Sgibbs scsiq->q_status = val & 0xFF; 56318781Sgibbs scsiq->q_no = (val >> 8) & 0XFF; 56418781Sgibbs 56518781Sgibbs val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_CNTL); 56618781Sgibbs scsiq->cntl = val & 0xFF; 56718781Sgibbs sg_queue_cnt = (val >> 8) & 0xFF; 56818781Sgibbs 56918781Sgibbs val = adv_read_lram_16(adv,q_addr + ADV_SCSIQ_B_SENSE_LEN); 57018781Sgibbs scsiq->sense_len = val & 0xFF; 57118781Sgibbs scsiq->user_def = (val >> 8) & 0xFF; 57218781Sgibbs 57318781Sgibbs scsiq->remain_bytes = adv_read_lram_32(adv, 57418781Sgibbs q_addr + ADV_SCSIQ_DW_REMAIN_XFER_CNT); 57518781Sgibbs /* 57618781Sgibbs * XXX Is this just a safeguard or will the counter really 57718781Sgibbs * have bogus upper bits? 57818781Sgibbs */ 57918781Sgibbs scsiq->remain_bytes &= max_dma_count; 58018781Sgibbs 58118781Sgibbs return (sg_queue_cnt); 58218781Sgibbs} 58318781Sgibbs 58418781Sgibbsint 58518781Sgibbsadv_stop_execution(adv) 58618781Sgibbs struct adv_softc *adv; 58718781Sgibbs{ 58818781Sgibbs int count; 58918781Sgibbs 59018781Sgibbs count = 0; 59118781Sgibbs if (adv_read_lram_8(adv, ADV_STOP_CODE_B) == 0) { 59218781Sgibbs adv_write_lram_8(adv, ADV_STOP_CODE_B, 59318781Sgibbs ADV_STOP_REQ_RISC_STOP); 59418781Sgibbs do { 59518781Sgibbs if (adv_read_lram_8(adv, ADV_STOP_CODE_B) & 59618781Sgibbs ADV_STOP_ACK_RISC_STOP) { 59718781Sgibbs return (1); 59818781Sgibbs } 59918781Sgibbs DELAY(1000); 60018781Sgibbs } while (count++ < 20); 60118781Sgibbs } 60218781Sgibbs return (0); 60318781Sgibbs} 60418781Sgibbs 60518781Sgibbsint 60618781Sgibbsadv_is_chip_halted(adv) 60718781Sgibbs struct adv_softc *adv; 60818781Sgibbs{ 60918781Sgibbs if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0) { 61018781Sgibbs if ((ADV_INB(adv, ADV_CHIP_CTRL) & ADV_CC_HALT) != 0) { 61118781Sgibbs return (1); 61218781Sgibbs } 61318781Sgibbs } 61418781Sgibbs return (0); 61518781Sgibbs} 61618781Sgibbs 61718781Sgibbs/* 61818781Sgibbs * XXX The numeric constants and the loops in this routine 61918781Sgibbs * need to be documented. 62018781Sgibbs */ 62118781Sgibbsvoid 62218781Sgibbsadv_ack_interrupt(adv) 62318781Sgibbs struct adv_softc *adv; 62418781Sgibbs{ 62518781Sgibbs u_int8_t host_flag; 62618781Sgibbs u_int8_t risc_flag; 62718781Sgibbs int loop; 62818781Sgibbs 62918781Sgibbs loop = 0; 63018781Sgibbs do { 63118781Sgibbs risc_flag = adv_read_lram_8(adv, ADVV_RISC_FLAG_B); 63218781Sgibbs if (loop++ > 0x7FFF) { 63318781Sgibbs break; 63418781Sgibbs } 63518781Sgibbs } while ((risc_flag & ADV_RISC_FLAG_GEN_INT) != 0); 63618781Sgibbs 63718781Sgibbs host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B); 63818781Sgibbs adv_write_lram_8(adv, ADVV_HOST_FLAG_B, 63918781Sgibbs host_flag | ADV_HOST_FLAG_ACK_INT); 64018781Sgibbs 64118781Sgibbs ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK); 64218781Sgibbs loop = 0; 64318781Sgibbs while (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_INT_PENDING) { 64418781Sgibbs ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK); 64518781Sgibbs if (loop++ > 3) { 64618781Sgibbs break; 64718781Sgibbs } 64818781Sgibbs } 64918781Sgibbs 65018781Sgibbs adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag); 65118781Sgibbs} 65218781Sgibbs 65318781Sgibbs/* 65418781Sgibbs * Handle all conditions that may halt the chip waiting 65518781Sgibbs * for us to intervene. 65618781Sgibbs */ 65718781Sgibbsvoid 65818781Sgibbsadv_isr_chip_halted(adv) 65918781Sgibbs struct adv_softc *adv; 66018781Sgibbs{ 66118781Sgibbs u_int16_t int_halt_code; 66218781Sgibbs u_int8_t halt_qp; 66318781Sgibbs u_int16_t halt_q_addr; 66418781Sgibbs u_int8_t target_ix; 66518781Sgibbs u_int8_t q_cntl; 66618781Sgibbs u_int8_t tid_no; 66718781Sgibbs target_bit_vector target_id; 66818781Sgibbs target_bit_vector scsi_busy; 66918781Sgibbs u_int8_t asyn_sdtr; 67018781Sgibbs u_int8_t sdtr_data; 67118781Sgibbs 67218781Sgibbs int_halt_code = adv_read_lram_16(adv, ADVV_HALTCODE_W); 67318781Sgibbs halt_qp = adv_read_lram_8(adv, ADVV_CURCDB_B); 67418781Sgibbs halt_q_addr = ADV_QNO_TO_QADDR(halt_qp); 67518781Sgibbs target_ix = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TARGET_IX); 67618781Sgibbs q_cntl = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL); 67718781Sgibbs tid_no = ADV_TIX_TO_TID(target_ix); 67818781Sgibbs target_id = ADV_TID_TO_TARGET_ID(tid_no); 67918781Sgibbs if (adv->needs_async_bug_fix & target_id) 68018781Sgibbs asyn_sdtr = ASYN_SDTR_DATA_FIX; 68118781Sgibbs else 68218781Sgibbs asyn_sdtr = 0; 68318781Sgibbs if (int_halt_code == ADV_HALT_EXTMSG_IN) { 68418781Sgibbs struct sdtr_xmsg sdtr_xmsg; 68518781Sgibbs int sdtr_accept; 68618781Sgibbs 68718781Sgibbs adv_read_lram_16_multi(adv, ADVV_MSGIN_BEG, 68818781Sgibbs (u_int16_t *) &sdtr_xmsg, 68918781Sgibbs sizeof(sdtr_xmsg) >> 1); 69018781Sgibbs if ((sdtr_xmsg.msg_type == MSG_EXTENDED) && 69118781Sgibbs (sdtr_xmsg.msg_len == MSG_EXT_SDTR_LEN)) { 69218781Sgibbs sdtr_accept = TRUE; 69318781Sgibbs if (sdtr_xmsg.msg_req == MSG_EXT_SDTR) { 69418781Sgibbs if (sdtr_xmsg.req_ack_offset > ADV_SYN_MAX_OFFSET) { 69518781Sgibbs 69618781Sgibbs sdtr_accept = FALSE; 69718781Sgibbs sdtr_xmsg.req_ack_offset = ADV_SYN_MAX_OFFSET; 69818781Sgibbs } 69918781Sgibbs sdtr_data = adv_get_card_sync_setting(sdtr_xmsg.xfer_period, 70018781Sgibbs sdtr_xmsg.req_ack_offset); 70118781Sgibbs if (sdtr_xmsg.req_ack_offset == 0) { 70218781Sgibbs q_cntl &= ~QC_MSG_OUT; 70318781Sgibbs adv->initiate_sdtr &= ~target_id; 70418781Sgibbs adv->sdtr_done &= ~target_id; 70518781Sgibbs adv_set_chip_sdtr(adv, asyn_sdtr, tid_no); 70618781Sgibbs } else if (sdtr_data == 0) { 70718781Sgibbs q_cntl |= QC_MSG_OUT; 70818781Sgibbs adv->initiate_sdtr &= ~target_id; 70918781Sgibbs adv->sdtr_done &= ~target_id; 71018781Sgibbs adv_set_chip_sdtr(adv, asyn_sdtr, tid_no); 71118781Sgibbs } else { 71218781Sgibbs if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 71318781Sgibbs q_cntl &= ~QC_MSG_OUT; 71418781Sgibbs adv->sdtr_done |= target_id; 71518781Sgibbs adv->initiate_sdtr |= target_id; 71618781Sgibbs adv->needs_async_bug_fix &= ~target_id; 71718781Sgibbs adv_set_chip_sdtr(adv, sdtr_data, tid_no); 71818781Sgibbs } else { 71918781Sgibbs 72018781Sgibbs q_cntl |= QC_MSG_OUT; 72118781Sgibbs 72218781Sgibbs adv_msgout_sdtr(adv, 72318781Sgibbs sdtr_xmsg.xfer_period, 72418781Sgibbs sdtr_xmsg.req_ack_offset); 72518781Sgibbs adv->needs_async_bug_fix &= ~target_id; 72618781Sgibbs adv_set_chip_sdtr(adv, sdtr_data, tid_no); 72718781Sgibbs adv->sdtr_done |= target_id; 72818781Sgibbs adv->initiate_sdtr |= target_id; 72918781Sgibbs } 73018781Sgibbs } 73118781Sgibbs 73218781Sgibbs adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl); 73318781Sgibbs } 73418781Sgibbs } 73518781Sgibbs /* 73618781Sgibbs * XXX Hey, shouldn't we be rejecting any messages we don't understand? 73718781Sgibbs * The old code also did not un-halt the processor if it recieved 73818781Sgibbs * an extended message that it didn't understand. That didn't 73918781Sgibbs * seem right, so I changed this routine to always un-halt the 74018781Sgibbs * processor at the end. 74118781Sgibbs */ 74218781Sgibbs } else if (int_halt_code == ADV_HALT_CHK_CONDITION) { 74318781Sgibbs u_int8_t tag_code; 74418781Sgibbs u_int8_t q_status; 74518781Sgibbs 74618781Sgibbs q_cntl |= QC_REQ_SENSE; 74718781Sgibbs if (((adv->initiate_sdtr & target_id) != 0) && 74818781Sgibbs ((adv->sdtr_done & target_id) != 0)) { 74918781Sgibbs 75018781Sgibbs sdtr_data = adv_read_lram_8(adv, ADVV_SDTR_DATA_BEG + tid_no); 75118781Sgibbs /* XXX Macrotize the extraction of the index from sdtr_data ??? */ 75218781Sgibbs adv_msgout_sdtr(adv, adv_sdtr_period_tbl[(sdtr_data >> 4) & 0x0F], 75318781Sgibbs sdtr_data & ADV_SYN_MAX_OFFSET); 75418781Sgibbs q_cntl |= QC_MSG_OUT; 75518781Sgibbs } 75618781Sgibbs adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl); 75718781Sgibbs 75818781Sgibbs /* Don't tag request sense commands */ 75918781Sgibbs tag_code = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TAG_CODE); 76018781Sgibbs tag_code &= ~(MSG_SIMPLE_Q_TAG|MSG_HEAD_OF_Q_TAG|MSG_ORDERED_Q_TAG); 76118781Sgibbs adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TAG_CODE, tag_code); 76218781Sgibbs 76318781Sgibbs q_status = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_STATUS); 76418781Sgibbs q_status |= (QS_READY | QS_BUSY); 76518781Sgibbs adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_STATUS, q_status); 76618781Sgibbs 76718781Sgibbs scsi_busy = adv_read_lram_8(adv, ADVV_SCSIBUSY_B); 76818781Sgibbs scsi_busy &= ~target_id; 76918781Sgibbs adv_write_lram_8(adv, ADVV_SCSIBUSY_B, scsi_busy); 77018781Sgibbs } else if (int_halt_code == ADV_HALT_SDTR_REJECTED) { 77118781Sgibbs struct sdtr_xmsg out_msg; 77218781Sgibbs 77318781Sgibbs adv_read_lram_16_multi(adv, ADVV_MSGOUT_BEG, 77418781Sgibbs (u_int16_t *) &out_msg, 77518781Sgibbs sizeof(out_msg)/2); 77618781Sgibbs 77718781Sgibbs if ((out_msg.msg_type == MSG_EXTENDED) && 77818781Sgibbs (out_msg.msg_len == MSG_EXT_SDTR_LEN) && 77918781Sgibbs (out_msg.msg_req == MSG_EXT_SDTR)) { 78018781Sgibbs 78118781Sgibbs adv->initiate_sdtr &= ~target_id; 78218781Sgibbs adv->sdtr_done &= ~target_id; 78318781Sgibbs adv_set_chip_sdtr(adv, asyn_sdtr, tid_no); 78418781Sgibbs } 78518781Sgibbs q_cntl &= ~QC_MSG_OUT; 78618781Sgibbs adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl); 78718781Sgibbs } else if (int_halt_code == ADV_HALT_SS_QUEUE_FULL) { 78818781Sgibbs u_int8_t cur_dvc_qng; 78918781Sgibbs u_int8_t scsi_status; 79018781Sgibbs 79118781Sgibbs /* 79218781Sgibbs * XXX It would be nice if we could push the responsibility for handling 79318781Sgibbs * this situation onto the generic SCSI layer as other drivers do. 79418781Sgibbs * This would be done by completing the command with the status byte 79518781Sgibbs * set to QUEUE_FULL, whereupon it will request that any transactions 79618781Sgibbs * pending on the target that where scheduled after this one be aborted 79718781Sgibbs * (so as to maintain queue ordering) and the number of requests the 79818781Sgibbs * upper level will attempt to send this target will be reduced. 79918781Sgibbs * 80018781Sgibbs * With this current strategy, am I guaranteed that once I unbusy the 80118781Sgibbs * target the queued up transactions will be sent in the order they 80218781Sgibbs * were queued? If the ASC chip does a round-robin on all queued 80318781Sgibbs * transactions looking for queues to run, the order is not guaranteed. 80418781Sgibbs */ 80518781Sgibbs scsi_status = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_SCSI_STATUS); 80618781Sgibbs cur_dvc_qng = adv_read_lram_8(adv, ADV_QADR_BEG + target_ix); 80718781Sgibbs printf("adv%d: Queue full - target %d, active transactions %d\n", adv->unit, 80818781Sgibbs tid_no, cur_dvc_qng); 80918781Sgibbs#if 0 81018781Sgibbs /* XXX FIX LATER */ 81118781Sgibbs if ((cur_dvc_qng > 0) && (adv->cur_dvc_qng[tid_no] > 0)) { 81218781Sgibbs scsi_busy = adv_read_lram_8(adv, ADVV_SCSIBUSY_B); 81318781Sgibbs scsi_busy |= target_id; 81418781Sgibbs adv_write_lram_8(adv, ADVV_SCSIBUSY_B, scsi_busy); 81518781Sgibbs asc_dvc->queue_full_or_busy |= target_id; 81618781Sgibbs 81718781Sgibbs if (scsi_status == SS_QUEUE_FULL) { 81818781Sgibbs if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 81918781Sgibbs cur_dvc_qng -= 1; 82018781Sgibbs asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng; 82118781Sgibbs 82218781Sgibbs adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + tid_no, 82318781Sgibbs cur_dvc_qng); 82418781Sgibbs } 82518781Sgibbs } 82618781Sgibbs } 82718781Sgibbs#endif 82818781Sgibbs } 82918781Sgibbs adv_write_lram_16(adv, ADVV_HALTCODE_W, 0); 83018781Sgibbs} 83118781Sgibbs 83218781Sgibbs/* Internal Routines */ 83318781Sgibbs 83418781Sgibbsstatic void 83518781Sgibbsadv_read_lram_16_multi(adv, s_addr, buffer, count) 83618781Sgibbs struct adv_softc *adv; 83718781Sgibbs u_int16_t s_addr; 83818781Sgibbs u_int16_t *buffer; 83918781Sgibbs int count; 84018781Sgibbs{ 84118781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 84218781Sgibbs ADV_INSW(adv, ADV_LRAM_DATA, buffer, count); 84318781Sgibbs} 84418781Sgibbs 84518781Sgibbsstatic void 84618781Sgibbsadv_write_lram_16_multi(adv, s_addr, buffer, count) 84718781Sgibbs struct adv_softc *adv; 84818781Sgibbs u_int16_t s_addr; 84918781Sgibbs u_int16_t *buffer; 85018781Sgibbs int count; 85118781Sgibbs{ 85218781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 85318781Sgibbs ADV_OUTSW(adv, ADV_LRAM_DATA, buffer, count); 85418781Sgibbs} 85518781Sgibbs 85618781Sgibbsstatic void 85718781Sgibbsadv_mset_lram_16(adv, s_addr, set_value, count) 85818781Sgibbs struct adv_softc *adv; 85918781Sgibbs u_int16_t s_addr; 86018781Sgibbs u_int16_t set_value; 86118781Sgibbs int count; 86218781Sgibbs{ 86318781Sgibbs int i; 86418781Sgibbs 86518781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 86618781Sgibbs for (i = 0; i < count; i++) 86718781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, set_value); 86818781Sgibbs} 86918781Sgibbs 87018781Sgibbsstatic u_int32_t 87118781Sgibbsadv_msum_lram_16(adv, s_addr, count) 87218781Sgibbs struct adv_softc *adv; 87318781Sgibbs u_int16_t s_addr; 87418781Sgibbs int count; 87518781Sgibbs{ 87618781Sgibbs u_int32_t sum; 87718781Sgibbs int i; 87818781Sgibbs 87918781Sgibbs sum = 0; 88018781Sgibbs for (i = 0; i < count; i++, s_addr += 2) 88118781Sgibbs sum += adv_read_lram_16(adv, s_addr); 88218781Sgibbs return (sum); 88318781Sgibbs} 88418781Sgibbs 88518781Sgibbsstatic int 88618781Sgibbsadv_write_and_verify_lram_16(adv, addr, value) 88718781Sgibbs struct adv_softc *adv; 88818781Sgibbs u_int16_t addr; 88918781Sgibbs u_int16_t value; 89018781Sgibbs{ 89118781Sgibbs int retval; 89218781Sgibbs 89318781Sgibbs retval = 0; 89418781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 89518781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, value); 89618781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 89718781Sgibbs if (value != ADV_INW(adv, ADV_LRAM_DATA)) 89818781Sgibbs retval = 1; 89918781Sgibbs return (retval); 90018781Sgibbs} 90118781Sgibbs 90218781Sgibbsstatic u_int32_t 90318781Sgibbsadv_read_lram_32(adv, addr) 90418781Sgibbs struct adv_softc *adv; 90518781Sgibbs u_int16_t addr; 90618781Sgibbs{ 90718781Sgibbs u_int16_t val_low, val_high; 90818781Sgibbs 90918781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 91018781Sgibbs 91118781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 91218781Sgibbs val_high = ADV_INW(adv, ADV_LRAM_DATA); 91318781Sgibbs val_low = ADV_INW(adv, ADV_LRAM_DATA); 91418781Sgibbs#else 91518781Sgibbs val_low = ADV_INW(adv, ADV_LRAM_DATA); 91618781Sgibbs val_high = ADV_INW(adv, ADV_LRAM_DATA); 91718781Sgibbs#endif 91818781Sgibbs 91918781Sgibbs return (((u_int32_t)val_high << 16) | (u_int32_t)val_low); 92018781Sgibbs} 92118781Sgibbs 92218781Sgibbsstatic void 92318781Sgibbsadv_write_lram_32(adv, addr, value) 92418781Sgibbs struct adv_softc *adv; 92518781Sgibbs u_int16_t addr; 92618781Sgibbs u_int32_t value; 92718781Sgibbs{ 92818781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, addr); 92918781Sgibbs 93018781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 93118781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)((value >> 16) & 0xFFFF)); 93218781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)(value & 0xFFFF)); 93318781Sgibbs#else 93418781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)(value & 0xFFFF)); 93518781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, (u_int16_t)((value >> 16) & 0xFFFF)); 93618781Sgibbs#endif 93718781Sgibbs} 93818781Sgibbs 93918781Sgibbsstatic void 94018781Sgibbsadv_write_lram_32_multi(adv, s_addr, buffer, count) 94118781Sgibbs struct adv_softc *adv; 94218781Sgibbs u_int16_t s_addr; 94318781Sgibbs u_int32_t *buffer; 94418781Sgibbs int count; 94518781Sgibbs{ 94618781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 94718781Sgibbs ADV_OUTSW(adv, ADV_LRAM_DATA, buffer, count * 2); 94818781Sgibbs} 94918781Sgibbs 95018781Sgibbsstatic u_int16_t 95118781Sgibbsadv_read_eeprom_16(adv, addr) 95218781Sgibbs struct adv_softc *adv; 95318781Sgibbs u_int8_t addr; 95418781Sgibbs{ 95518781Sgibbs u_int16_t read_wval; 95618781Sgibbs u_int8_t cmd_reg; 95718781Sgibbs 95818781Sgibbs adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_DISABLE); 95918781Sgibbs DELAY(1000); 96018781Sgibbs cmd_reg = addr | ADV_EEPROM_CMD_READ; 96118781Sgibbs adv_write_eeprom_cmd_reg(adv, cmd_reg); 96218781Sgibbs DELAY(1000); 96318781Sgibbs read_wval = ADV_INW(adv, ADV_EEPROM_DATA); 96418781Sgibbs DELAY(1000); 96518781Sgibbs return (read_wval); 96618781Sgibbs} 96718781Sgibbs 96818781Sgibbsstatic u_int16_t 96918781Sgibbsadv_write_eeprom_16(adv, addr, value) 97018781Sgibbs struct adv_softc *adv; 97118781Sgibbs u_int8_t addr; 97218781Sgibbs u_int16_t value; 97318781Sgibbs{ 97418781Sgibbs u_int16_t read_value; 97518781Sgibbs 97618781Sgibbs read_value = adv_read_eeprom_16(adv, addr); 97718781Sgibbs if (read_value != value) { 97818781Sgibbs adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_ENABLE); 97918781Sgibbs DELAY(1000); 98018781Sgibbs 98118781Sgibbs ADV_OUTW(adv, ADV_EEPROM_DATA, value); 98218781Sgibbs DELAY(1000); 98318781Sgibbs 98418781Sgibbs adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE | addr); 98518781Sgibbs DELAY(20 * 1000); 98618781Sgibbs 98718781Sgibbs adv_write_eeprom_cmd_reg(adv, ADV_EEPROM_CMD_WRITE_DISABLE); 98818781Sgibbs DELAY(1000); 98918781Sgibbs read_value = adv_read_eeprom_16(adv, addr); 99018781Sgibbs } 99118781Sgibbs return (read_value); 99218781Sgibbs} 99318781Sgibbs 99418781Sgibbsstatic int 99518781Sgibbsadv_write_eeprom_cmd_reg(adv, cmd_reg) 99618781Sgibbs struct adv_softc *adv; 99718781Sgibbs u_int8_t cmd_reg; 99818781Sgibbs{ 99918781Sgibbs u_int8_t read_back; 100018781Sgibbs int retry; 100118781Sgibbs 100218781Sgibbs retry = 0; 100318781Sgibbs while (1) { 100418781Sgibbs ADV_OUTB(adv, ADV_EEPROM_CMD, cmd_reg); 100518781Sgibbs DELAY(1000); 100618781Sgibbs read_back = ADV_INB(adv, ADV_EEPROM_CMD); 100718781Sgibbs if (read_back == cmd_reg) { 100818781Sgibbs return (1); 100918781Sgibbs } 101018781Sgibbs if (retry++ > ADV_EEPROM_MAX_RETRY) { 101118781Sgibbs return (0); 101218781Sgibbs } 101318781Sgibbs } 101418781Sgibbs} 101518781Sgibbs 101618781Sgibbsstatic int 101718781Sgibbsadv_set_eeprom_config_once(adv, eeprom_config) 101818781Sgibbs struct adv_softc *adv; 101918781Sgibbs struct adv_eeprom_config *eeprom_config; 102018781Sgibbs{ 102118781Sgibbs int n_error; 102218781Sgibbs u_int16_t *wbuf; 102318781Sgibbs u_int16_t sum; 102418781Sgibbs u_int8_t s_addr; 102518781Sgibbs u_int8_t cfg_beg; 102618781Sgibbs u_int8_t cfg_end; 102718781Sgibbs 102818781Sgibbs wbuf = (u_int16_t *)eeprom_config; 102918781Sgibbs n_error = 0; 103018781Sgibbs sum = 0; 103118781Sgibbs for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 103218781Sgibbs sum += *wbuf; 103318781Sgibbs if (*wbuf != adv_write_eeprom_16(adv, s_addr, *wbuf)) { 103418781Sgibbs n_error++; 103518781Sgibbs } 103618781Sgibbs } 103718781Sgibbs if (adv->type & ADV_VL) { 103818781Sgibbs cfg_beg = ADV_EEPROM_CFG_BEG_VL; 103918781Sgibbs cfg_end = ADV_EEPROM_MAX_ADDR_VL; 104018781Sgibbs } else { 104118781Sgibbs cfg_beg = ADV_EEPROM_CFG_BEG; 104218781Sgibbs cfg_end = ADV_EEPROM_MAX_ADDR; 104318781Sgibbs } 104418781Sgibbs 104518781Sgibbs for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 104618781Sgibbs sum += *wbuf; 104718781Sgibbs if (*wbuf != adv_write_eeprom_16(adv, s_addr, *wbuf)) { 104818781Sgibbs n_error++; 104918781Sgibbs } 105018781Sgibbs } 105118781Sgibbs *wbuf = sum; 105218781Sgibbs if (sum != adv_write_eeprom_16(adv, s_addr, sum)) { 105318781Sgibbs n_error++; 105418781Sgibbs } 105518781Sgibbs wbuf = (u_int16_t *)eeprom_config; 105618781Sgibbs for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 105718781Sgibbs if (*wbuf != adv_read_eeprom_16(adv, s_addr)) { 105818781Sgibbs n_error++; 105918781Sgibbs } 106018781Sgibbs } 106118781Sgibbs for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 106218781Sgibbs if (*wbuf != adv_read_eeprom_16(adv, s_addr)) { 106318781Sgibbs n_error++; 106418781Sgibbs } 106518781Sgibbs } 106618781Sgibbs return (n_error); 106718781Sgibbs} 106818781Sgibbs 106918781Sgibbsstatic u_int32_t 107018781Sgibbsadv_load_microcode(adv, s_addr, mcode_buf, mcode_size) 107118781Sgibbs struct adv_softc *adv; 107218781Sgibbs u_int16_t s_addr; 107318781Sgibbs u_int16_t *mcode_buf; 107418781Sgibbs u_int16_t mcode_size; 107518781Sgibbs{ 107618781Sgibbs u_int32_t chksum; 107718781Sgibbs u_int16_t mcode_lram_size; 107818781Sgibbs u_int16_t mcode_chksum; 107918781Sgibbs 108018781Sgibbs mcode_lram_size = mcode_size >> 1; 108118781Sgibbs /* XXX Why zero the memory just before you write the whole thing?? */ 108218781Sgibbs /* adv_mset_lram_16(adv, s_addr, 0, mcode_lram_size);*/ 108318781Sgibbs adv_write_lram_16_multi(adv, s_addr, mcode_buf, mcode_lram_size); 108418781Sgibbs 108518781Sgibbs chksum = adv_msum_lram_16(adv, s_addr, mcode_lram_size); 108618781Sgibbs mcode_chksum = (u_int16_t)adv_msum_lram_16(adv, ADV_CODE_SEC_BEG, 108718781Sgibbs ((mcode_size - s_addr - ADV_CODE_SEC_BEG) >> 1)); 108818781Sgibbs adv_write_lram_16(adv, ADVV_MCODE_CHKSUM_W, mcode_chksum); 108918781Sgibbs adv_write_lram_16(adv, ADVV_MCODE_SIZE_W, mcode_size); 109018781Sgibbs return (chksum); 109118781Sgibbs} 109218781Sgibbs 109318781Sgibbsstatic void 109418781Sgibbsadv_init_lram(adv) 109518781Sgibbs struct adv_softc *adv; 109618781Sgibbs{ 109718781Sgibbs u_int8_t i; 109818781Sgibbs u_int16_t s_addr; 109918781Sgibbs 110018781Sgibbs adv_mset_lram_16(adv, ADV_QADR_BEG, 0, 110118781Sgibbs (u_int16_t)((((int)adv->max_openings + 2 + 1) * 64) >> 1)); 110218781Sgibbs 110318781Sgibbs i = ADV_MIN_ACTIVE_QNO; 110418781Sgibbs s_addr = ADV_QADR_BEG + ADV_QBLK_SIZE; 110518781Sgibbs 110618781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i + 1); 110718781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, adv->max_openings); 110818781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i); 110918781Sgibbs i++; 111018781Sgibbs s_addr += ADV_QBLK_SIZE; 111118781Sgibbs for (; i < adv->max_openings; i++, s_addr += ADV_QBLK_SIZE) { 111218781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i + 1); 111318781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, i - 1); 111418781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i); 111518781Sgibbs } 111618781Sgibbs 111718781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, ADV_QLINK_END); 111818781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, adv->max_openings - 1); 111918781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, adv->max_openings); 112018781Sgibbs i++; 112118781Sgibbs s_addr += ADV_QBLK_SIZE; 112218781Sgibbs 112318781Sgibbs for (; i <= adv->max_openings + 3; i++, s_addr += ADV_QBLK_SIZE) { 112418781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_FWD, i); 112518781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_BWD, i); 112618781Sgibbs adv_write_lram_8(adv, s_addr + ADV_SCSIQ_B_QNO, i); 112718781Sgibbs } 112818781Sgibbs} 112918781Sgibbs 113018781Sgibbsstatic int 113118781Sgibbsadv_init_microcode_var(adv) 113218781Sgibbs struct adv_softc *adv; 113318781Sgibbs{ 113418781Sgibbs int i; 113518781Sgibbs 113618781Sgibbs for (i = 0; i <= ADV_MAX_TID; i++) { 113718781Sgibbs adv_write_lram_8(adv, ADVV_SDTR_DATA_BEG + i, 113818781Sgibbs adv->sdtr_data[i]); 113918781Sgibbs } 114018781Sgibbs 114118781Sgibbs adv_init_qlink_var(adv); 114218781Sgibbs 114318781Sgibbs /* XXX Again, what about wide busses??? */ 114418781Sgibbs adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable); 114518781Sgibbs adv_write_lram_8(adv, ADVV_HOSTSCSI_ID_B, 0x01 << adv->scsi_id); 114618781Sgibbs 114718781Sgibbs /* What are the extra 8 bytes for?? */ 114818781Sgibbs adv_write_lram_32(adv, ADVV_OVERRUN_PADDR_D, vtophys(&(adv->overrun_buf[0])) + 8); 114918781Sgibbs 115018781Sgibbs adv_write_lram_32(adv, ADVV_OVERRUN_BSIZE_D, ADV_OVERRUN_BSIZE - 8); 115118781Sgibbs 115218781Sgibbs#if 0 115318781Sgibbs /* If we're going to print anything, RCS ids are more meaningful */ 115418781Sgibbs mcode_date = adv_read_lram_16(adv, ADVV_MC_DATE_W); 115518781Sgibbs mcode_version = adv_read_lram_16(adv, ADVV_MC_VER_W); 115618781Sgibbs#endif 115718781Sgibbs ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR); 115818781Sgibbs if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) { 115918781Sgibbs printf("adv%d: Unable to set program counter. Aborting.\n", adv->unit); 116018781Sgibbs return (1); 116118781Sgibbs } 116218781Sgibbs if (adv_start_chip(adv) != 1) { 116318781Sgibbs printf("adv%d: Unable to start on board processor. Aborting.\n", 116418781Sgibbs adv->unit); 116518781Sgibbs return (1); 116618781Sgibbs } 116718781Sgibbs return (0); 116818781Sgibbs} 116918781Sgibbs 117018781Sgibbsstatic void 117118781Sgibbsadv_init_qlink_var(adv) 117218781Sgibbs struct adv_softc *adv; 117318781Sgibbs{ 117418781Sgibbs int i; 117518781Sgibbs u_int16_t lram_addr; 117618781Sgibbs 117718781Sgibbs adv_write_lram_8(adv, ADVV_NEXTRDY_B, 1); 117818781Sgibbs adv_write_lram_8(adv, ADVV_DONENEXT_B, adv->max_openings); 117918781Sgibbs 118018781Sgibbs adv_write_lram_16(adv, ADVV_FREE_Q_HEAD_W, 1); 118118781Sgibbs adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, adv->max_openings); 118218781Sgibbs 118318781Sgibbs adv_write_lram_8(adv, ADVV_BUSY_QHEAD_B, 118418781Sgibbs (u_int8_t)((int) adv->max_openings + 1)); 118518781Sgibbs adv_write_lram_8(adv, ADVV_DISC1_QHEAD_B, 118618781Sgibbs (u_int8_t)((int) adv->max_openings + 2)); 118718781Sgibbs 118818781Sgibbs adv_write_lram_8(adv, ADVV_TOTAL_READY_Q_B, adv->max_openings); 118918781Sgibbs 119018781Sgibbs adv_write_lram_16(adv, ADVV_ASCDVC_ERR_CODE_W, 0); 119118781Sgibbs adv_write_lram_16(adv, ADVV_HALTCODE_W, 0); 119218781Sgibbs adv_write_lram_8(adv, ADVV_STOP_CODE_B, 0); 119318781Sgibbs adv_write_lram_8(adv, ADVV_SCSIBUSY_B, 0); 119418781Sgibbs adv_write_lram_8(adv, ADVV_WTM_FLAG_B, 0); 119518781Sgibbs 119618781Sgibbs adv_write_lram_8(adv, ADVV_CDBCNT_B, 0); 119718781Sgibbs 119818781Sgibbs lram_addr = ADV_QADR_BEG; 119918781Sgibbs for (i = 0; i < 32; i++, lram_addr += 2) 120018781Sgibbs adv_write_lram_16(adv, lram_addr, 0); 120118781Sgibbs} 120218781Sgibbsstatic void 120318781Sgibbsadv_disable_interrupt(adv) 120418781Sgibbs struct adv_softc *adv; 120518781Sgibbs{ 120618781Sgibbs u_int16_t cfg; 120718781Sgibbs 120818781Sgibbs cfg = ADV_INW(adv, ADV_CONFIG_LSW); 120918781Sgibbs ADV_OUTW(adv, ADV_CONFIG_LSW, cfg & ~ADV_CFG_LSW_HOST_INT_ON); 121018781Sgibbs} 121118781Sgibbs 121218781Sgibbsstatic void 121318781Sgibbsadv_enable_interrupt(adv) 121418781Sgibbs struct adv_softc *adv; 121518781Sgibbs{ 121618781Sgibbs u_int16_t cfg; 121718781Sgibbs 121818781Sgibbs cfg = ADV_INW(adv, ADV_CONFIG_LSW); 121918781Sgibbs ADV_OUTW(adv, ADV_CONFIG_LSW, cfg | ADV_CFG_LSW_HOST_INT_ON); 122018781Sgibbs} 122118781Sgibbs 122218781Sgibbsstatic void 122318781Sgibbsadv_toggle_irq_act(adv) 122418781Sgibbs struct adv_softc *adv; 122518781Sgibbs{ 122618781Sgibbs ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_IRQ_ACT); 122718781Sgibbs ADV_OUTW(adv, ADV_CHIP_STATUS, 0); 122818781Sgibbs} 122918781Sgibbs 123018781Sgibbs#if UNUSED 123118781Sgibbsstatic void 123218781Sgibbsadv_start_execution(adv) 123318781Sgibbs struct adv_softc *adv; 123418781Sgibbs{ 123518781Sgibbs if (adv_read_lram_8(adv, ADV_STOP_CODE_B) != 0) { 123618781Sgibbs adv_write_lram_8(adv, ADV_STOP_CODE_B, 0); 123718781Sgibbs } 123818781Sgibbs} 123918781Sgibbs#endif 124018781Sgibbs 124118781Sgibbsstatic int 124218781Sgibbsadv_start_chip(adv) 124318781Sgibbs struct adv_softc *adv; 124418781Sgibbs{ 124518781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, 0); 124618781Sgibbs if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0) 124718781Sgibbs return (0); 124818781Sgibbs return (1); 124918781Sgibbs} 125018781Sgibbs 125118781Sgibbsstatic int 125218781Sgibbsadv_stop_chip(adv) 125318781Sgibbs struct adv_softc *adv; 125418781Sgibbs{ 125518781Sgibbs u_int8_t cc_val; 125618781Sgibbs 125718781Sgibbs cc_val = ADV_INB(adv, ADV_CHIP_CTRL) 125818781Sgibbs & (~(ADV_CC_SINGLE_STEP | ADV_CC_TEST | ADV_CC_DIAG)); 125918781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, cc_val | ADV_CC_HALT); 126018781Sgibbs adv_set_chip_ih(adv, ADV_INS_HALT); 126118781Sgibbs adv_set_chip_ih(adv, ADV_INS_RFLAG_WTM); 126218781Sgibbs if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) == 0) { 126318781Sgibbs return (0); 126418781Sgibbs } 126518781Sgibbs return (1); 126618781Sgibbs} 126718781Sgibbs 126818781Sgibbsstatic void 126918781Sgibbsadv_set_chip_ih(adv, ins_code) 127018781Sgibbs struct adv_softc *adv; 127118781Sgibbs u_int16_t ins_code; 127218781Sgibbs{ 127318781Sgibbs adv_set_bank(adv, 1); 127418781Sgibbs ADV_OUTW(adv, ADV_REG_IH, ins_code); 127518781Sgibbs adv_set_bank(adv, 0); 127618781Sgibbs} 127718781Sgibbs 127818781Sgibbsstatic void 127918781Sgibbsadv_set_bank(adv, bank) 128018781Sgibbs struct adv_softc *adv; 128118781Sgibbs u_int8_t bank; 128218781Sgibbs{ 128318781Sgibbs u_int8_t control; 128418781Sgibbs 128518781Sgibbs /* 128618781Sgibbs * Start out with the bank reset to 0 128718781Sgibbs */ 128818781Sgibbs control = ADV_INB(adv, ADV_CHIP_CTRL) 128918781Sgibbs & (~(ADV_CC_SINGLE_STEP | ADV_CC_TEST 129018781Sgibbs | ADV_CC_DIAG | ADV_CC_SCSI_RESET 129118781Sgibbs | ADV_CC_CHIP_RESET | ADV_CC_BANK_ONE)); 129218781Sgibbs if (bank == 1) { 129318781Sgibbs control |= ADV_CC_BANK_ONE; 129418781Sgibbs } else if (bank == 2) { 129518781Sgibbs control |= ADV_CC_DIAG | ADV_CC_BANK_ONE; 129618781Sgibbs } 129718781Sgibbs ADV_OUTB(adv, ADV_CHIP_CTRL, control); 129818781Sgibbs} 129918781Sgibbs 130018781Sgibbs#if UNUSED 130118781Sgibbsstatic u_int8_t 130218781Sgibbsadv_get_chip_scsi_ctrl(adv) 130318781Sgibbs struct adv_softc *adv; 130418781Sgibbs{ 130518781Sgibbs u_int8_t scsi_ctrl; 130618781Sgibbs 130718781Sgibbs adv_set_bank(adv, 1); 130818781Sgibbs scsi_ctrl = ADV_INB(adv, ADV_REG_SC); 130918781Sgibbs adv_set_bank(adv, 0); 131018781Sgibbs return (scsi_ctrl); 131118781Sgibbs} 131218781Sgibbs#endif 131318781Sgibbs 131418781Sgibbsstatic int 131518781Sgibbsadv_sgcount_to_qcount(sgcount) 131618781Sgibbs int sgcount; 131718781Sgibbs{ 131818781Sgibbs int n_sg_list_qs; 131918781Sgibbs 132018781Sgibbs n_sg_list_qs = ((sgcount - 1) / ADV_SG_LIST_PER_Q); 132118781Sgibbs if (((sgcount - 1) % ADV_SG_LIST_PER_Q) != 0) 132218781Sgibbs n_sg_list_qs++; 132318781Sgibbs return (n_sg_list_qs + 1); 132418781Sgibbs} 132518781Sgibbs 132618781Sgibbs/* 132718781Sgibbs * XXX Looks like more padding issues in this routine as well. 132818781Sgibbs * There has to be a way to turn this into an insw. 132918781Sgibbs */ 133018781Sgibbsstatic void 133118781Sgibbsadv_get_q_info(adv, s_addr, inbuf, words) 133218781Sgibbs struct adv_softc *adv; 133318781Sgibbs u_int16_t s_addr; 133418781Sgibbs u_int16_t *inbuf; 133518781Sgibbs int words; 133618781Sgibbs{ 133718781Sgibbs int i; 133818781Sgibbs 133918781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 134018781Sgibbs for (i = 0; i < words; i++, inbuf++) { 134118781Sgibbs if (i == 5) { 134218781Sgibbs continue; 134318781Sgibbs } 134418781Sgibbs *inbuf = ADV_INW(adv, ADV_LRAM_DATA); 134518781Sgibbs } 134618781Sgibbs} 134718781Sgibbs 134818781Sgibbsstatic u_int 134918781Sgibbsadv_get_num_free_queues(adv, n_qs) 135018781Sgibbs struct adv_softc *adv; 135118781Sgibbs u_int8_t n_qs; 135218781Sgibbs{ 135318781Sgibbs u_int cur_used_qs; 135418781Sgibbs u_int cur_free_qs; 135518781Sgibbs 135618781Sgibbs if (n_qs == 1) 135718781Sgibbs cur_used_qs = adv->cur_active + 135818781Sgibbs adv->openings_needed + 135918781Sgibbs ADV_MIN_FREE_Q; 136018781Sgibbs else 136118781Sgibbs cur_used_qs = adv->cur_active + 136218781Sgibbs ADV_MIN_FREE_Q; 136318781Sgibbs 136418781Sgibbs if ((cur_used_qs + n_qs) <= adv->max_openings) { 136518781Sgibbs cur_free_qs = adv->max_openings - cur_used_qs; 136618781Sgibbs return (cur_free_qs); 136718781Sgibbs } 136818781Sgibbs if (n_qs > 1) 136918781Sgibbs if (n_qs > adv->openings_needed) 137018781Sgibbs adv->openings_needed = n_qs; 137118781Sgibbs return (0); 137218781Sgibbs} 137318781Sgibbs 137418781Sgibbsstatic u_int8_t 137518781Sgibbsadv_alloc_free_queues(adv, free_q_head, n_free_q) 137618781Sgibbs struct adv_softc *adv; 137718781Sgibbs u_int8_t free_q_head; 137818781Sgibbs u_int8_t n_free_q; 137918781Sgibbs{ 138018781Sgibbs int i; 138118781Sgibbs 138218781Sgibbs for (i = 0; i < n_free_q; i++) { 138318781Sgibbs free_q_head = adv_alloc_free_queue(adv, free_q_head); 138418781Sgibbs if (free_q_head == ADV_QLINK_END) 138518781Sgibbs break; 138618781Sgibbs } 138718781Sgibbs return (free_q_head); 138818781Sgibbs} 138918781Sgibbs 139018781Sgibbsstatic u_int8_t 139118781Sgibbsadv_alloc_free_queue(adv, free_q_head) 139218781Sgibbs struct adv_softc *adv; 139318781Sgibbs u_int8_t free_q_head; 139418781Sgibbs{ 139518781Sgibbs u_int16_t q_addr; 139618781Sgibbs u_int8_t next_qp; 139718781Sgibbs u_int8_t q_status; 139818781Sgibbs 139918781Sgibbs next_qp = ADV_QLINK_END; 140018781Sgibbs q_addr = ADV_QNO_TO_QADDR(free_q_head); 140118781Sgibbs q_status = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_STATUS); 140218781Sgibbs 140318781Sgibbs if ((q_status & QS_READY) == 0) 140418781Sgibbs next_qp = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_FWD); 140518781Sgibbs 140618781Sgibbs return (next_qp); 140718781Sgibbs} 140818781Sgibbs 140918781Sgibbsstatic int 141018781Sgibbsadv_send_scsi_queue(adv, scsiq, n_q_required) 141118781Sgibbs struct adv_softc *adv; 141218781Sgibbs struct adv_scsi_q *scsiq; 141318781Sgibbs u_int8_t n_q_required; 141418781Sgibbs{ 141518781Sgibbs u_int8_t free_q_head; 141618781Sgibbs u_int8_t next_qp; 141718781Sgibbs u_int8_t tid_no; 141818781Sgibbs u_int8_t target_ix; 141918781Sgibbs int retval; 142018781Sgibbs 142118781Sgibbs retval = 1; 142218781Sgibbs target_ix = scsiq->q2.target_ix; 142318781Sgibbs tid_no = ADV_TIX_TO_TID(target_ix); 142418781Sgibbs free_q_head = adv_read_lram_16(adv, ADVV_FREE_Q_HEAD_W) & 0xFF; 142518781Sgibbs if ((next_qp = adv_alloc_free_queues(adv, free_q_head, n_q_required)) 142618781Sgibbs != ADV_QLINK_END) { 142718781Sgibbs if (n_q_required > 1) { 142818781Sgibbs /* 142918781Sgibbs * Only reset the shortage value when processing 143018781Sgibbs * a "normal" request and not error recovery or 143118781Sgibbs * other requests that dip into our reserved queues. 143218781Sgibbs * Generally speaking, a normal request will need more 143318781Sgibbs * than one queue. 143418781Sgibbs */ 143518781Sgibbs adv->openings_needed = 0; 143618781Sgibbs } 143718781Sgibbs scsiq->q1.q_no = free_q_head; 143818781Sgibbs 143918781Sgibbs /* 144018781Sgibbs * Now that we know our Q number, point our sense 144118781Sgibbs * buffer pointer to an area below 16M if we are 144218781Sgibbs * an ISA adapter. 144318781Sgibbs */ 144418781Sgibbs if (adv->sense_buffers != NULL) 144518781Sgibbs scsiq->q1.sense_addr = (u_int32_t)vtophys(&(adv->sense_buffers[free_q_head])); 144618781Sgibbs adv_put_ready_sg_list_queue(adv, scsiq, free_q_head); 144718781Sgibbs adv_write_lram_16(adv, ADVV_FREE_Q_HEAD_W, next_qp); 144818781Sgibbs adv->cur_active += n_q_required; 144918781Sgibbs retval = 0; 145018781Sgibbs } 145118781Sgibbs return (retval); 145218781Sgibbs} 145318781Sgibbs 145418781Sgibbs 145518781Sgibbsstatic void 145618781Sgibbsadv_put_ready_sg_list_queue(adv, scsiq, q_no) 145718781Sgibbs struct adv_softc *adv; 145818781Sgibbs struct adv_scsi_q *scsiq; 145918781Sgibbs u_int8_t q_no; 146018781Sgibbs{ 146118781Sgibbs u_int8_t sg_list_dwords; 146218781Sgibbs u_int8_t sg_index, i; 146318781Sgibbs u_int8_t sg_entry_cnt; 146418781Sgibbs u_int8_t next_qp; 146518781Sgibbs u_int16_t q_addr; 146618781Sgibbs struct adv_sg_head *sg_head; 146718781Sgibbs struct adv_sg_list_q scsi_sg_q; 146818781Sgibbs 146918781Sgibbs sg_head = scsiq->sg_head; 147018781Sgibbs 147118781Sgibbs if (sg_head) { 147218781Sgibbs sg_entry_cnt = sg_head->entry_cnt - 1; 147318781Sgibbs#ifdef DIAGNOSTIC 147418781Sgibbs if (sg_entry_cnt == 0) 147518781Sgibbs panic("adv_put_ready_sg_list_queue: ScsiQ with a SG list but only one element"); 147618781Sgibbs if ((scsiq->q1.cntl & QC_SG_HEAD) == 0) 147718781Sgibbs panic("adv_put_ready_sg_list_queue: ScsiQ with a SG list but QC_SG_HEAD not set"); 147818781Sgibbs#endif 147918781Sgibbs q_addr = ADV_QNO_TO_QADDR(q_no); 148018781Sgibbs sg_index = 1; 148118781Sgibbs scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 148218781Sgibbs scsi_sg_q.sg_head_qp = q_no; 148318781Sgibbs scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 148418781Sgibbs for (i = 0; i < sg_head->queue_cnt; i++) { 148518781Sgibbs u_int8_t segs_this_q; 148618781Sgibbs 148718781Sgibbs if (sg_entry_cnt > ADV_SG_LIST_PER_Q) 148818781Sgibbs segs_this_q = ADV_SG_LIST_PER_Q; 148918781Sgibbs else { 149018781Sgibbs /* This will be the last segment then */ 149118781Sgibbs segs_this_q = sg_entry_cnt; 149218781Sgibbs scsi_sg_q.cntl |= QCSG_SG_XFER_END; 149318781Sgibbs } 149418781Sgibbs scsi_sg_q.seq_no = i + 1; 149518781Sgibbs sg_list_dwords = segs_this_q * 2; 149618781Sgibbs if (i == 0) { 149718781Sgibbs scsi_sg_q.sg_list_cnt = segs_this_q; 149818781Sgibbs scsi_sg_q.sg_cur_list_cnt = segs_this_q; 149918781Sgibbs } else { 150018781Sgibbs scsi_sg_q.sg_list_cnt = segs_this_q - 1; 150118781Sgibbs scsi_sg_q.sg_cur_list_cnt = segs_this_q - 1; 150218781Sgibbs } 150318781Sgibbs next_qp = adv_read_lram_8(adv, q_addr + ADV_SCSIQ_B_FWD); 150418781Sgibbs scsi_sg_q.q_no = next_qp; 150518781Sgibbs q_addr = ADV_QNO_TO_QADDR(next_qp); 150618781Sgibbs 150718781Sgibbs adv_write_lram_16_multi(adv, q_addr + ADV_SCSIQ_SGHD_CPY_BEG, 150818781Sgibbs (u_int16_t *)&scsi_sg_q, 150918781Sgibbs sizeof(scsi_sg_q) >> 1); 151018781Sgibbs adv_write_lram_32_multi(adv, q_addr + ADV_SGQ_LIST_BEG, 151118781Sgibbs (u_int32_t *)&sg_head->sg_list[sg_index], 151218781Sgibbs sg_list_dwords); 151318781Sgibbs sg_entry_cnt -= segs_this_q; 151418781Sgibbs sg_index += ADV_SG_LIST_PER_Q; 151518781Sgibbs } 151618781Sgibbs } 151718781Sgibbs adv_put_ready_queue(adv, scsiq, q_no); 151818781Sgibbs} 151918781Sgibbs 152018781Sgibbsstatic void 152118781Sgibbsadv_put_ready_queue(adv, scsiq, q_no) 152218781Sgibbs struct adv_softc *adv; 152318781Sgibbs struct adv_scsi_q *scsiq; 152418781Sgibbs u_int8_t q_no; 152518781Sgibbs{ 152618781Sgibbs u_int16_t q_addr; 152718781Sgibbs u_int8_t tid_no; 152818781Sgibbs u_int8_t sdtr_data; 152918781Sgibbs u_int8_t syn_period_ix; 153018781Sgibbs u_int8_t syn_offset; 153118781Sgibbs 153218781Sgibbs if (((adv->initiate_sdtr & scsiq->q1.target_id) != 0) && 153318781Sgibbs ((adv->sdtr_done & scsiq->q1.target_id) == 0)) { 153418781Sgibbs 153518781Sgibbs tid_no = ADV_TIX_TO_TID(scsiq->q2.target_ix); 153618781Sgibbs 153718781Sgibbs sdtr_data = adv_read_lram_8(adv, ADVV_SDTR_DATA_BEG + tid_no); 153818781Sgibbs syn_period_ix = (sdtr_data >> 4) & (ADV_SYN_XFER_NO - 1); 153918781Sgibbs syn_offset = sdtr_data & ADV_SYN_MAX_OFFSET; 154018781Sgibbs adv_msgout_sdtr(adv, adv_sdtr_period_tbl[syn_period_ix], 154118781Sgibbs syn_offset); 154218781Sgibbs 154318781Sgibbs scsiq->q1.cntl |= QC_MSG_OUT; 154418781Sgibbs } 154518781Sgibbs q_addr = ADV_QNO_TO_QADDR(q_no); 154618781Sgibbs 154718781Sgibbs scsiq->q1.status = QS_FREE; 154818781Sgibbs 154918781Sgibbs adv_write_lram_16_multi(adv, q_addr + ADV_SCSIQ_CDB_BEG, 155018781Sgibbs (u_int16_t *)scsiq->cdbptr, 155118781Sgibbs scsiq->q2.cdb_len >> 1); 155218781Sgibbs 155318781Sgibbs#if BYTE_ORDER == BIG_ENDIAN 155418781Sgibbs adv_adj_scsiq_endian(scsiq); 155518781Sgibbs#endif 155618781Sgibbs 155718781Sgibbs adv_put_scsiq(adv, q_addr + ADV_SCSIQ_CPY_BEG, 155818781Sgibbs (u_int16_t *) &scsiq->q1.cntl, 155918781Sgibbs ((sizeof(scsiq->q1) + sizeof(scsiq->q2)) / 2) - 1); 156018781Sgibbs 156118781Sgibbs#if CC_WRITE_IO_COUNT 156218781Sgibbs adv_write_lram_16(adv, q_addr + ADV_SCSIQ_W_REQ_COUNT, 156318781Sgibbs adv->req_count); 156418781Sgibbs#endif 156518781Sgibbs 156618781Sgibbs#if CC_CLEAR_DMA_REMAIN 156718781Sgibbs 156818781Sgibbs adv_write_lram_32(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_ADDR, 0); 156918781Sgibbs adv_write_lram_32(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_CNT, 0); 157018781Sgibbs#endif 157118781Sgibbs 157218781Sgibbs adv_write_lram_16(adv, q_addr + ADV_SCSIQ_B_STATUS, 157318781Sgibbs (scsiq->q1.q_no << 8) | QS_READY); 157418781Sgibbs} 157518781Sgibbs 157618781Sgibbsstatic void 157718781Sgibbsadv_put_scsiq(adv, s_addr, buffer, words) 157818781Sgibbs struct adv_softc *adv; 157918781Sgibbs u_int16_t s_addr; 158018781Sgibbs u_int16_t *buffer; 158118781Sgibbs int words; 158218781Sgibbs{ 158318781Sgibbs int i; 158418781Sgibbs 158518781Sgibbs /* 158618781Sgibbs * XXX This routine makes *gross* assumptions 158718781Sgibbs * about padding in the data structures. 158818781Sgibbs * Either the data structures should have explicit 158918781Sgibbs * padding members added, or they should have padding 159018781Sgibbs * turned off via compiler attributes depending on 159118781Sgibbs * which yields better overall performance. My hunch 159218781Sgibbs * would be that turning off padding would be the 159318781Sgibbs * faster approach as an outsw is much faster than 159418781Sgibbs * this crude loop and accessing un-aligned data 159518781Sgibbs * members isn't *that* expensive. The other choice 159618781Sgibbs * would be to modify the ASC script so that the 159718781Sgibbs * the adv_scsiq_1 structure can be re-arranged so 159818781Sgibbs * padding isn't required. 159918781Sgibbs */ 160018781Sgibbs ADV_OUTW(adv, ADV_LRAM_ADDR, s_addr); 160118781Sgibbs for (i = 0; i < words; i++, buffer++) { 160218781Sgibbs if (i == 2 || i == 10) { 160318781Sgibbs continue; 160418781Sgibbs } 160518781Sgibbs ADV_OUTW(adv, ADV_LRAM_DATA, *buffer); 160618781Sgibbs } 160718781Sgibbs} 160818781Sgibbs 160918781Sgibbsstatic u_int8_t 161018781Sgibbsadv_msgout_sdtr(adv, sdtr_period, sdtr_offset) 161118781Sgibbs struct adv_softc *adv; 161218781Sgibbs u_int8_t sdtr_period; 161318781Sgibbs u_int8_t sdtr_offset; 161418781Sgibbs{ 161518781Sgibbs struct sdtr_xmsg sdtr_buf; 161618781Sgibbs 161718781Sgibbs sdtr_buf.msg_type = MSG_EXTENDED; 161818781Sgibbs sdtr_buf.msg_len = MSG_EXT_SDTR_LEN; 161918781Sgibbs sdtr_buf.msg_req = MSG_EXT_SDTR; 162018781Sgibbs sdtr_buf.xfer_period = sdtr_period; 162118781Sgibbs sdtr_offset &= ADV_SYN_MAX_OFFSET; 162218781Sgibbs sdtr_buf.req_ack_offset = sdtr_offset; 162318781Sgibbs adv_write_lram_16_multi(adv, ADVV_MSGOUT_BEG, 162418781Sgibbs (u_int16_t *) &sdtr_buf, 162518781Sgibbs sizeof(sdtr_buf) / 2); 162618781Sgibbs 162718781Sgibbs return (adv_get_card_sync_setting(sdtr_period, sdtr_offset)); 162818781Sgibbs} 162918781Sgibbs 163018781Sgibbsstatic u_int8_t 163118781Sgibbsadv_get_card_sync_setting(period, offset) 163218781Sgibbs u_int8_t period; 163318781Sgibbs u_int8_t offset; 163418781Sgibbs{ 163518781Sgibbs u_int i; 163618781Sgibbs 163718781Sgibbs if (period >= adv_sdtr_period_tbl[0]) { 163818781Sgibbs for (i = 0; i < sizeof(adv_sdtr_period_tbl); i++) { 163918781Sgibbs if (period <= adv_sdtr_period_tbl[i]) 164018781Sgibbs return ((adv_sdtr_period_tbl[i] << 4) | offset); 164118781Sgibbs } 164218781Sgibbs } 164318781Sgibbs return (0); 164418781Sgibbs} 164518781Sgibbs 164618781Sgibbsstatic void 164718781Sgibbsadv_set_chip_sdtr(adv, sdtr_data, tid_no) 164818781Sgibbs struct adv_softc *adv; 164918781Sgibbs u_int8_t sdtr_data; 165018781Sgibbs u_int8_t tid_no; 165118781Sgibbs{ 165218781Sgibbs ADV_OUTB(adv, ADV_SYN_OFFSET, sdtr_data); 165318781Sgibbs adv_write_lram_8(adv, ADVV_SDTR_DONE_BEG + tid_no, sdtr_data); 165418781Sgibbs} 1655