cvmx-pcsx-defs.h revision 225736
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pcsx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pcsx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCSX_TYPEDEFS_H__ 53#define __CVMX_PCSX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 61 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 62 cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 63 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 64} 65#else 66#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 73 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 75 cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 76 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 77} 78#else 79#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 86 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 87 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 88 cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 89 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 90} 91#else 92#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 99 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 100 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 101 cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 102 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 103} 104#else 105#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 112 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 114 cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 115 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 116} 117#else 118#define CVMX_PCSX_INTX_EN_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 125 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 126 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 127 cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 128 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 129} 130#else 131#define CVMX_PCSX_INTX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 139 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 140 cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 141 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 142} 143#else 144#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 151 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 152 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 153 cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 154 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 155} 156#else 157#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 166 cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 167 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 168} 169#else 170#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 177 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 178 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 179 cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 180 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 181} 182#else 183#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 192 cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 193 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 194} 195#else 196#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 204 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 205 cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 206 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 207} 208#else 209#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 217 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 218 cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 219 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 220} 221#else 222#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 230 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 231 cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 232 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 233} 234#else 235#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 242 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 244 cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 245 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 246} 247#else 248#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 255 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 257 cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 258 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 259} 260#else 261#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 262#endif 263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) 265{ 266 if (!( 267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) || 268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) || 269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0)))))) 270 cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id); 271 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 272} 273#else 274#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024) 275#endif 276 277/** 278 * cvmx_pcs#_an#_adv_reg 279 * 280 * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification, 281 * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating 282 * that the chip cannot operate in the corresponding modes. 283 * 284 * Bit [4] RM_FLT is a don't care when the selected mode is SGMII. 285 * 286 * 287 * 288 * PCS_AN_ADV_REG = AN Advertisement Register4 289 */ 290union cvmx_pcsx_anx_adv_reg 291{ 292 uint64_t u64; 293 struct cvmx_pcsx_anx_adv_reg_s 294 { 295#if __BYTE_ORDER == __BIG_ENDIAN 296 uint64_t reserved_16_63 : 48; 297 uint64_t np : 1; /**< Always 0, no next page capability supported */ 298 uint64_t reserved_14_14 : 1; 299 uint64_t rem_flt : 2; /**< [<13>,<12>] 300 0 0 Link OK XMIT=DATA 301 0 1 Link failure (loss of sync, XMIT!= DATA) 302 1 0 local device Offline 303 1 1 AN Error failure to complete AN 304 AN Error is set if resolution function 305 precludes operation with link partner */ 306 uint64_t reserved_9_11 : 3; 307 uint64_t pause : 2; /**< [<8>, <7>] Pause frame flow capability across link 308 Exchanged during Auto Negotiation 309 0 0 No Pause 310 0 1 Symmetric pause 311 1 0 Asymmetric Pause 312 1 1 Both symm and asymm pause to local device */ 313 uint64_t hfd : 1; /**< 1 means local device Half Duplex capable */ 314 uint64_t fd : 1; /**< 1 means local device Full Duplex capable */ 315 uint64_t reserved_0_4 : 5; 316#else 317 uint64_t reserved_0_4 : 5; 318 uint64_t fd : 1; 319 uint64_t hfd : 1; 320 uint64_t pause : 2; 321 uint64_t reserved_9_11 : 3; 322 uint64_t rem_flt : 2; 323 uint64_t reserved_14_14 : 1; 324 uint64_t np : 1; 325 uint64_t reserved_16_63 : 48; 326#endif 327 } s; 328 struct cvmx_pcsx_anx_adv_reg_s cn52xx; 329 struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; 330 struct cvmx_pcsx_anx_adv_reg_s cn56xx; 331 struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; 332 struct cvmx_pcsx_anx_adv_reg_s cn63xx; 333 struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; 334}; 335typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t; 336 337/** 338 * cvmx_pcs#_an#_ext_st_reg 339 * 340 * NOTE: 341 * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1 342 * the an_results_reg is valid. 343 * 344 * 345 * PCS_AN_EXT_ST_REG = AN Extended Status Register15 346 * as per IEEE802.3 Clause 22 347 */ 348union cvmx_pcsx_anx_ext_st_reg 349{ 350 uint64_t u64; 351 struct cvmx_pcsx_anx_ext_st_reg_s 352 { 353#if __BYTE_ORDER == __BIG_ENDIAN 354 uint64_t reserved_16_63 : 48; 355 uint64_t thou_xfd : 1; /**< 1 means PHY is 1000BASE-X Full Dup capable */ 356 uint64_t thou_xhd : 1; /**< 1 means PHY is 1000BASE-X Half Dup capable */ 357 uint64_t thou_tfd : 1; /**< 1 means PHY is 1000BASE-T Full Dup capable */ 358 uint64_t thou_thd : 1; /**< 1 means PHY is 1000BASE-T Half Dup capable */ 359 uint64_t reserved_0_11 : 12; 360#else 361 uint64_t reserved_0_11 : 12; 362 uint64_t thou_thd : 1; 363 uint64_t thou_tfd : 1; 364 uint64_t thou_xhd : 1; 365 uint64_t thou_xfd : 1; 366 uint64_t reserved_16_63 : 48; 367#endif 368 } s; 369 struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; 370 struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; 371 struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; 372 struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; 373 struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; 374 struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; 375}; 376typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t; 377 378/** 379 * cvmx_pcs#_an#_lp_abil_reg 380 * 381 * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5 382 * as per IEEE802.3 Clause 37 383 */ 384union cvmx_pcsx_anx_lp_abil_reg 385{ 386 uint64_t u64; 387 struct cvmx_pcsx_anx_lp_abil_reg_s 388 { 389#if __BYTE_ORDER == __BIG_ENDIAN 390 uint64_t reserved_16_63 : 48; 391 uint64_t np : 1; /**< 1=lp next page capable, 0=lp not next page capable */ 392 uint64_t ack : 1; /**< 1=Acknowledgement received */ 393 uint64_t rem_flt : 2; /**< [<13>,<12>] Link Partner's link status 394 0 0 Link OK 395 0 1 Offline 396 1 0 Link failure 397 1 1 AN Error */ 398 uint64_t reserved_9_11 : 3; 399 uint64_t pause : 2; /**< [<8>, <7>] Link Partner Pause setting 400 0 0 No Pause 401 0 1 Symmetric pause 402 1 0 Asymmetric Pause 403 1 1 Both symm and asymm pause to local device */ 404 uint64_t hfd : 1; /**< 1 means link partner Half Duplex capable */ 405 uint64_t fd : 1; /**< 1 means link partner Full Duplex capable */ 406 uint64_t reserved_0_4 : 5; 407#else 408 uint64_t reserved_0_4 : 5; 409 uint64_t fd : 1; 410 uint64_t hfd : 1; 411 uint64_t pause : 2; 412 uint64_t reserved_9_11 : 3; 413 uint64_t rem_flt : 2; 414 uint64_t ack : 1; 415 uint64_t np : 1; 416 uint64_t reserved_16_63 : 48; 417#endif 418 } s; 419 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; 420 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; 421 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; 422 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; 423 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; 424 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; 425}; 426typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t; 427 428/** 429 * cvmx_pcs#_an#_results_reg 430 * 431 * PCS_AN_RESULTS_REG = AN Results Register 432 * 433 */ 434union cvmx_pcsx_anx_results_reg 435{ 436 uint64_t u64; 437 struct cvmx_pcsx_anx_results_reg_s 438 { 439#if __BYTE_ORDER == __BIG_ENDIAN 440 uint64_t reserved_7_63 : 57; 441 uint64_t pause : 2; /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII) 442 0 0 Disable Pause, TX and RX 443 0 1 Enable pause frames RX only 444 1 0 Enable Pause frames TX only 445 1 1 Enable pause frames TX and RX */ 446 uint64_t spd : 2; /**< [<4>, <3>] Link Speed Selection 447 0 0 10Mb/s 448 0 1 100Mb/s 449 1 0 1000Mb/s 450 1 1 NS */ 451 uint64_t an_cpt : 1; /**< 1=AN Completed, 0=AN not completed or failed */ 452 uint64_t dup : 1; /**< 1=Full Duplex, 0=Half Duplex */ 453 uint64_t link_ok : 1; /**< 1=Link up(OK), 0=Link down */ 454#else 455 uint64_t link_ok : 1; 456 uint64_t dup : 1; 457 uint64_t an_cpt : 1; 458 uint64_t spd : 2; 459 uint64_t pause : 2; 460 uint64_t reserved_7_63 : 57; 461#endif 462 } s; 463 struct cvmx_pcsx_anx_results_reg_s cn52xx; 464 struct cvmx_pcsx_anx_results_reg_s cn52xxp1; 465 struct cvmx_pcsx_anx_results_reg_s cn56xx; 466 struct cvmx_pcsx_anx_results_reg_s cn56xxp1; 467 struct cvmx_pcsx_anx_results_reg_s cn63xx; 468 struct cvmx_pcsx_anx_results_reg_s cn63xxp1; 469}; 470typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t; 471 472/** 473 * cvmx_pcs#_int#_en_reg 474 * 475 * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising 476 * DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from 477 * SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an indication that a bad code group 478 * was received after code group synchronizaton was achieved. This interrupt should be disabled during normal link operation. 479 * Use it as a debug help feature only. 480 * 481 * 482 * PCS Interrupt Enable Register 483 */ 484union cvmx_pcsx_intx_en_reg 485{ 486 uint64_t u64; 487 struct cvmx_pcsx_intx_en_reg_s 488 { 489#if __BYTE_ORDER == __BIG_ENDIAN 490 uint64_t reserved_13_63 : 51; 491 uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */ 492 uint64_t dup : 1; /**< Enable duplex mode changed interrupt */ 493 uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */ 494 uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */ 495 uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */ 496 uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */ 497 uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */ 498 uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */ 499 uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */ 500 uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */ 501 uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */ 502 uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */ 503 uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */ 504#else 505 uint64_t lnkspd_en : 1; 506 uint64_t xmit_en : 1; 507 uint64_t an_err_en : 1; 508 uint64_t txfifu_en : 1; 509 uint64_t txfifo_en : 1; 510 uint64_t txbad_en : 1; 511 uint64_t rxerr_en : 1; 512 uint64_t rxbad_en : 1; 513 uint64_t rxlock_en : 1; 514 uint64_t an_bad_en : 1; 515 uint64_t sync_bad_en : 1; 516 uint64_t dup : 1; 517 uint64_t dbg_sync_en : 1; 518 uint64_t reserved_13_63 : 51; 519#endif 520 } s; 521 struct cvmx_pcsx_intx_en_reg_cn52xx 522 { 523#if __BYTE_ORDER == __BIG_ENDIAN 524 uint64_t reserved_12_63 : 52; 525 uint64_t dup : 1; /**< Enable duplex mode changed interrupt */ 526 uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */ 527 uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */ 528 uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */ 529 uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */ 530 uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */ 531 uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */ 532 uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */ 533 uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */ 534 uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */ 535 uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */ 536 uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */ 537#else 538 uint64_t lnkspd_en : 1; 539 uint64_t xmit_en : 1; 540 uint64_t an_err_en : 1; 541 uint64_t txfifu_en : 1; 542 uint64_t txfifo_en : 1; 543 uint64_t txbad_en : 1; 544 uint64_t rxerr_en : 1; 545 uint64_t rxbad_en : 1; 546 uint64_t rxlock_en : 1; 547 uint64_t an_bad_en : 1; 548 uint64_t sync_bad_en : 1; 549 uint64_t dup : 1; 550 uint64_t reserved_12_63 : 52; 551#endif 552 } cn52xx; 553 struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; 554 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; 555 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; 556 struct cvmx_pcsx_intx_en_reg_s cn63xx; 557 struct cvmx_pcsx_intx_en_reg_s cn63xxp1; 558}; 559typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t; 560 561/** 562 * cvmx_pcs#_int#_reg 563 * 564 * SGMII bit [12] is really a misnomer, it is a decode of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes. 565 * 566 * Note: MODE bit 567 * When MODE=1, 1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37. 568 * When MODE=0, SGMII mode is selected and the following note will apply. 569 * Repeat note from SGM_AN_ADV register 570 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg 571 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1. 572 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 573 * 574 * PCS Interrupt Register 575 */ 576union cvmx_pcsx_intx_reg 577{ 578 uint64_t u64; 579 struct cvmx_pcsx_intx_reg_s 580 { 581#if __BYTE_ORDER == __BIG_ENDIAN 582 uint64_t reserved_13_63 : 51; 583 uint64_t dbg_sync : 1; /**< Code Group sync failure debug help */ 584 uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */ 585 uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad 586 state. Should never be set during normal operation */ 587 uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad 588 state. Should never be set during normal operation */ 589 uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock 590 failure occurs 591 Cannot fire in loopback1 mode */ 592 uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad 593 state. Should never be set during normal operation */ 594 uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in 595 10 bit to 8 bit decode logic 596 Cannot fire in loopback1 mode */ 597 uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad 598 state. Should never be set during normal operation */ 599 uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow 600 condition */ 601 uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow 602 condition */ 603 uint64_t an_err : 1; /**< AN Error, AN resolution function failed */ 604 uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT 605 variable. XMIT variable states are IDLE, CONFIG and 606 DATA */ 607 uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */ 608#else 609 uint64_t lnkspd : 1; 610 uint64_t xmit : 1; 611 uint64_t an_err : 1; 612 uint64_t txfifu : 1; 613 uint64_t txfifo : 1; 614 uint64_t txbad : 1; 615 uint64_t rxerr : 1; 616 uint64_t rxbad : 1; 617 uint64_t rxlock : 1; 618 uint64_t an_bad : 1; 619 uint64_t sync_bad : 1; 620 uint64_t dup : 1; 621 uint64_t dbg_sync : 1; 622 uint64_t reserved_13_63 : 51; 623#endif 624 } s; 625 struct cvmx_pcsx_intx_reg_cn52xx 626 { 627#if __BYTE_ORDER == __BIG_ENDIAN 628 uint64_t reserved_12_63 : 52; 629 uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */ 630 uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad 631 state. Should never be set during normal operation */ 632 uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad 633 state. Should never be set during normal operation */ 634 uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock 635 failure occurs 636 Cannot fire in loopback1 mode */ 637 uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad 638 state. Should never be set during normal operation */ 639 uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in 640 10 bit to 8 bit decode logic 641 Cannot fire in loopback1 mode */ 642 uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad 643 state. Should never be set during normal operation */ 644 uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow 645 condition */ 646 uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow 647 condition */ 648 uint64_t an_err : 1; /**< AN Error, AN resolution function failed */ 649 uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT 650 variable. XMIT variable states are IDLE, CONFIG and 651 DATA */ 652 uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */ 653#else 654 uint64_t lnkspd : 1; 655 uint64_t xmit : 1; 656 uint64_t an_err : 1; 657 uint64_t txfifu : 1; 658 uint64_t txfifo : 1; 659 uint64_t txbad : 1; 660 uint64_t rxerr : 1; 661 uint64_t rxbad : 1; 662 uint64_t rxlock : 1; 663 uint64_t an_bad : 1; 664 uint64_t sync_bad : 1; 665 uint64_t dup : 1; 666 uint64_t reserved_12_63 : 52; 667#endif 668 } cn52xx; 669 struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; 670 struct cvmx_pcsx_intx_reg_cn52xx cn56xx; 671 struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; 672 struct cvmx_pcsx_intx_reg_s cn63xx; 673 struct cvmx_pcsx_intx_reg_s cn63xxp1; 674}; 675typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t; 676 677/** 678 * cvmx_pcs#_link#_timer_count_reg 679 * 680 * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register 681 * 682 */ 683union cvmx_pcsx_linkx_timer_count_reg 684{ 685 uint64_t u64; 686 struct cvmx_pcsx_linkx_timer_count_reg_s 687 { 688#if __BYTE_ORDER == __BIG_ENDIAN 689 uint64_t reserved_16_63 : 48; 690 uint64_t count : 16; /**< (core clock period times 1024) times "COUNT" should 691 be 1.6ms(SGMII)/10ms(otherwise) which is the link 692 timer used in auto negotiation. 693 Reset assums a 700MHz eclk for 1.6ms link timer */ 694#else 695 uint64_t count : 16; 696 uint64_t reserved_16_63 : 48; 697#endif 698 } s; 699 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; 700 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; 701 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; 702 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; 703 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; 704 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; 705}; 706typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t; 707 708/** 709 * cvmx_pcs#_log_anl#_reg 710 * 711 * PCS Logic Analyzer Register 712 * 713 */ 714union cvmx_pcsx_log_anlx_reg 715{ 716 uint64_t u64; 717 struct cvmx_pcsx_log_anlx_reg_s 718 { 719#if __BYTE_ORDER == __BIG_ENDIAN 720 uint64_t reserved_4_63 : 60; 721 uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed during packetization 722 Write 1 to clear this bit */ 723 uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */ 724 uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size 725 0 0 Packet size 1k bytes 726 0 1 Packet size 4k bytes 727 1 0 Packet size 8k bytes 728 1 1 Packet size 16k bytes */ 729#else 730 uint64_t pkt_sz : 2; 731 uint64_t la_en : 1; 732 uint64_t lafifovfl : 1; 733 uint64_t reserved_4_63 : 60; 734#endif 735 } s; 736 struct cvmx_pcsx_log_anlx_reg_s cn52xx; 737 struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; 738 struct cvmx_pcsx_log_anlx_reg_s cn56xx; 739 struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; 740 struct cvmx_pcsx_log_anlx_reg_s cn63xx; 741 struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; 742}; 743typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t; 744 745/** 746 * cvmx_pcs#_misc#_ctl_reg 747 * 748 * SGMII Misc Control Register 749 * 750 */ 751union cvmx_pcsx_miscx_ctl_reg 752{ 753 uint64_t u64; 754 struct cvmx_pcsx_miscx_ctl_reg_s 755 { 756#if __BYTE_ORDER == __BIG_ENDIAN 757 uint64_t reserved_13_63 : 51; 758 uint64_t sgmii : 1; /**< 1=SGMII or 1000Base-X mode selected, 759 0=XAUI or PCIE mode selected 760 This bit represents pi_qlm1/3_cfg[1:0] pin status */ 761 uint64_t gmxeno : 1; /**< GMX Enable override. When set to 1, forces GMX to 762 appear disabled. The enable/disable status of GMX 763 is checked only at SOP of every packet. */ 764 uint64_t loopbck2 : 1; /**< Sets external loopback mode to return rx data back 765 out via tx data path. 0=no loopback, 1=loopback */ 766 uint64_t mac_phy : 1; /**< 0=MAC, 1=PHY decides the tx_config_reg value to be 767 sent during auto negotiation. 768 See SGMII spec ENG-46158 from CISCO */ 769 uint64_t mode : 1; /**< 0=SGMII or 1= 1000 Base X */ 770 uint64_t an_ovrd : 1; /**< 0=disable, 1= enable over ride AN results 771 Auto negotiation is allowed to happen but the 772 results are ignored when set. Duplex and Link speed 773 values are set from the pcs_mr_ctrl reg */ 774 uint64_t samp_pt : 7; /**< Byte# in elongated frames for 10/100Mb/s operation 775 for data sampling on RX side in PCS. 776 Recommended values are 0x5 for 100Mb/s operation 777 and 0x32 for 10Mb/s operation. 778 For 10Mb/s operaton this field should be set to a 779 value less than 99 and greater than 0. If set out 780 of this range a value of 50 will be used for actual 781 sampling internally without affecting the CSR field 782 For 100Mb/s operation this field should be set to a 783 value less than 9 and greater than 0. If set out of 784 this range a value of 5 will be used for actual 785 sampling internally without affecting the CSR field */ 786#else 787 uint64_t samp_pt : 7; 788 uint64_t an_ovrd : 1; 789 uint64_t mode : 1; 790 uint64_t mac_phy : 1; 791 uint64_t loopbck2 : 1; 792 uint64_t gmxeno : 1; 793 uint64_t sgmii : 1; 794 uint64_t reserved_13_63 : 51; 795#endif 796 } s; 797 struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; 798 struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; 799 struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; 800 struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; 801 struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; 802 struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; 803}; 804typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t; 805 806/** 807 * cvmx_pcs#_mr#_control_reg 808 * 809 * PCS_MR_CONTROL_REG = Control Register0 810 * 811 */ 812union cvmx_pcsx_mrx_control_reg 813{ 814 uint64_t u64; 815 struct cvmx_pcsx_mrx_control_reg_s 816 { 817#if __BYTE_ORDER == __BIG_ENDIAN 818 uint64_t reserved_16_63 : 48; 819 uint64_t reset : 1; /**< 1=SW Reset, the bit will return to 0 after pcs has 820 been reset. Takes 32 eclk cycles to reset pcs */ 821 uint64_t loopbck1 : 1; /**< 0=normal operation, 1=loopback. The loopback mode 822 will return(loopback) tx data from GMII tx back to 823 GMII rx interface. The loopback happens in the pcs 824 module. Auto Negotiation will be disabled even if 825 the AN_EN bit is set, during loopback */ 826 uint64_t spdlsb : 1; /**< See bit 6 description */ 827 uint64_t an_en : 1; /**< 1=AN Enable, 0=AN Disable */ 828 uint64_t pwr_dn : 1; /**< 1=Power Down(HW reset), 0=Normal operation */ 829 uint64_t reserved_10_10 : 1; 830 uint64_t rst_an : 1; /**< If bit 12 is set and bit 3 of status reg is 1 831 Auto Negotiation begins. Else,SW writes are ignored 832 and this bit remians at 0. This bit clears itself 833 to 0, when AN starts. */ 834 uint64_t dup : 1; /**< 1=full duplex, 0=half duplex; effective only if AN 835 disabled. If status register bits [15:9] and and 836 extended status reg bits [15:12] allow only one 837 duplex mode|, this bit will correspond to that 838 value and any attempt to write will be ignored. */ 839 uint64_t coltst : 1; /**< 1=enable COL signal test, 0=disable test 840 During COL test, the COL signal will reflect the 841 GMII TX_EN signal with less than 16BT delay */ 842 uint64_t spdmsb : 1; /**< [<6>, <13>]Link Speed effective only if AN disabled 843 0 0 10Mb/s 844 0 1 100Mb/s 845 1 0 1000Mb/s 846 1 1 NS */ 847 uint64_t uni : 1; /**< Unidirectional (Std 802.3-2005, Clause 66.2) 848 This bit will override the AN_EN bit and disable 849 auto-negotiation variable mr_an_enable, when set 850 Used in both 1000Base-X and SGMII modes */ 851 uint64_t reserved_0_4 : 5; 852#else 853 uint64_t reserved_0_4 : 5; 854 uint64_t uni : 1; 855 uint64_t spdmsb : 1; 856 uint64_t coltst : 1; 857 uint64_t dup : 1; 858 uint64_t rst_an : 1; 859 uint64_t reserved_10_10 : 1; 860 uint64_t pwr_dn : 1; 861 uint64_t an_en : 1; 862 uint64_t spdlsb : 1; 863 uint64_t loopbck1 : 1; 864 uint64_t reset : 1; 865 uint64_t reserved_16_63 : 48; 866#endif 867 } s; 868 struct cvmx_pcsx_mrx_control_reg_s cn52xx; 869 struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; 870 struct cvmx_pcsx_mrx_control_reg_s cn56xx; 871 struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; 872 struct cvmx_pcsx_mrx_control_reg_s cn63xx; 873 struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; 874}; 875typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t; 876 877/** 878 * cvmx_pcs#_mr#_status_reg 879 * 880 * NOTE: 881 * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results 882 * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set, 883 * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values 884 * from the pcs_mr_ctrl reg. 885 * 886 * PCS_MR_STATUS_REG = Status Register1 887 */ 888union cvmx_pcsx_mrx_status_reg 889{ 890 uint64_t u64; 891 struct cvmx_pcsx_mrx_status_reg_s 892 { 893#if __BYTE_ORDER == __BIG_ENDIAN 894 uint64_t reserved_16_63 : 48; 895 uint64_t hun_t4 : 1; /**< 1 means 100Base-T4 capable */ 896 uint64_t hun_xfd : 1; /**< 1 means 100Base-X Full Duplex */ 897 uint64_t hun_xhd : 1; /**< 1 means 100Base-X Half Duplex */ 898 uint64_t ten_fd : 1; /**< 1 means 10Mb/s Full Duplex */ 899 uint64_t ten_hd : 1; /**< 1 means 10Mb/s Half Duplex */ 900 uint64_t hun_t2fd : 1; /**< 1 means 100Base-T2 Full Duplex */ 901 uint64_t hun_t2hd : 1; /**< 1 means 100Base-T2 Half Duplex */ 902 uint64_t ext_st : 1; /**< 1 means extended status info in reg15 */ 903 uint64_t reserved_7_7 : 1; 904 uint64_t prb_sup : 1; /**< 1 means able to work without preamble bytes at the 905 beginning of frames. 0 means not able to accept 906 frames without preamble bytes preceding them. */ 907 uint64_t an_cpt : 1; /**< 1 means Auto Negotiation is complete and the 908 contents of the an_results_reg are valid. */ 909 uint64_t rm_flt : 1; /**< Set to 1 when remote flt condition occurs. This bit 910 implements a latching Hi behavior. It is cleared by 911 SW read of this reg or when reset bit [15] in 912 Control Reg is asserted. 913 See an adv reg[13:12] for flt conditions */ 914 uint64_t an_abil : 1; /**< 1 means Auto Negotiation capable */ 915 uint64_t lnk_st : 1; /**< 1=link up, 0=link down. Set during AN process 916 Set whenever XMIT=DATA. Latching Lo behavior when 917 link goes down. Link down value of the bit stays 918 low until SW reads the reg. */ 919 uint64_t reserved_1_1 : 1; 920 uint64_t extnd : 1; /**< Always 0, no extended capability regs present */ 921#else 922 uint64_t extnd : 1; 923 uint64_t reserved_1_1 : 1; 924 uint64_t lnk_st : 1; 925 uint64_t an_abil : 1; 926 uint64_t rm_flt : 1; 927 uint64_t an_cpt : 1; 928 uint64_t prb_sup : 1; 929 uint64_t reserved_7_7 : 1; 930 uint64_t ext_st : 1; 931 uint64_t hun_t2hd : 1; 932 uint64_t hun_t2fd : 1; 933 uint64_t ten_hd : 1; 934 uint64_t ten_fd : 1; 935 uint64_t hun_xhd : 1; 936 uint64_t hun_xfd : 1; 937 uint64_t hun_t4 : 1; 938 uint64_t reserved_16_63 : 48; 939#endif 940 } s; 941 struct cvmx_pcsx_mrx_status_reg_s cn52xx; 942 struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; 943 struct cvmx_pcsx_mrx_status_reg_s cn56xx; 944 struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; 945 struct cvmx_pcsx_mrx_status_reg_s cn63xx; 946 struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; 947}; 948typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t; 949 950/** 951 * cvmx_pcs#_rx#_states_reg 952 * 953 * PCS_RX_STATES_REG = RX State Machines states register 954 * 955 */ 956union cvmx_pcsx_rxx_states_reg 957{ 958 uint64_t u64; 959 struct cvmx_pcsx_rxx_states_reg_s 960 { 961#if __BYTE_ORDER == __BIG_ENDIAN 962 uint64_t reserved_16_63 : 48; 963 uint64_t rx_bad : 1; /**< Receive state machine in an illegal state */ 964 uint64_t rx_st : 5; /**< Receive state machine state */ 965 uint64_t sync_bad : 1; /**< Receive synchronization SM in an illegal state */ 966 uint64_t sync : 4; /**< Receive synchronization SM state */ 967 uint64_t an_bad : 1; /**< Auto Negotiation state machine in an illegal state */ 968 uint64_t an_st : 4; /**< Auto Negotiation state machine state */ 969#else 970 uint64_t an_st : 4; 971 uint64_t an_bad : 1; 972 uint64_t sync : 4; 973 uint64_t sync_bad : 1; 974 uint64_t rx_st : 5; 975 uint64_t rx_bad : 1; 976 uint64_t reserved_16_63 : 48; 977#endif 978 } s; 979 struct cvmx_pcsx_rxx_states_reg_s cn52xx; 980 struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; 981 struct cvmx_pcsx_rxx_states_reg_s cn56xx; 982 struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; 983 struct cvmx_pcsx_rxx_states_reg_s cn63xx; 984 struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; 985}; 986typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t; 987 988/** 989 * cvmx_pcs#_rx#_sync_reg 990 * 991 * Note: 992 * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved. 993 * 994 * 995 * PCS_RX_SYNC_REG = Code Group synchronization reg 996 */ 997union cvmx_pcsx_rxx_sync_reg 998{ 999 uint64_t u64; 1000 struct cvmx_pcsx_rxx_sync_reg_s 1001 { 1002#if __BYTE_ORDER == __BIG_ENDIAN 1003 uint64_t reserved_2_63 : 62; 1004 uint64_t sync : 1; /**< 1 means code group synchronization achieved */ 1005 uint64_t bit_lock : 1; /**< 1 means bit lock achieved */ 1006#else 1007 uint64_t bit_lock : 1; 1008 uint64_t sync : 1; 1009 uint64_t reserved_2_63 : 62; 1010#endif 1011 } s; 1012 struct cvmx_pcsx_rxx_sync_reg_s cn52xx; 1013 struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; 1014 struct cvmx_pcsx_rxx_sync_reg_s cn56xx; 1015 struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; 1016 struct cvmx_pcsx_rxx_sync_reg_s cn63xx; 1017 struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; 1018}; 1019typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t; 1020 1021/** 1022 * cvmx_pcs#_sgm#_an_adv_reg 1023 * 1024 * SGMII AN Advertisement Register (sent out as tx_config_reg) 1025 * 1026 */ 1027union cvmx_pcsx_sgmx_an_adv_reg 1028{ 1029 uint64_t u64; 1030 struct cvmx_pcsx_sgmx_an_adv_reg_s 1031 { 1032#if __BYTE_ORDER == __BIG_ENDIAN 1033 uint64_t reserved_16_63 : 48; 1034 uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */ 1035 uint64_t ack : 1; /**< Auto negotiation ack */ 1036 uint64_t reserved_13_13 : 1; 1037 uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */ 1038 uint64_t speed : 2; /**< Link Speed 1039 0 0 10Mb/s 1040 0 1 100Mb/s 1041 1 0 1000Mb/s 1042 1 1 NS */ 1043 uint64_t reserved_1_9 : 9; 1044 uint64_t one : 1; /**< Always set to match tx_config_reg<0> */ 1045#else 1046 uint64_t one : 1; 1047 uint64_t reserved_1_9 : 9; 1048 uint64_t speed : 2; 1049 uint64_t dup : 1; 1050 uint64_t reserved_13_13 : 1; 1051 uint64_t ack : 1; 1052 uint64_t link : 1; 1053 uint64_t reserved_16_63 : 48; 1054#endif 1055 } s; 1056 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; 1057 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; 1058 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; 1059 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; 1060 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; 1061 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; 1062}; 1063typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t; 1064 1065/** 1066 * cvmx_pcs#_sgm#_lp_adv_reg 1067 * 1068 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg 1069 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1. 1070 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 1071 * 1072 * SGMII LP Advertisement Register (received as rx_config_reg) 1073 */ 1074union cvmx_pcsx_sgmx_lp_adv_reg 1075{ 1076 uint64_t u64; 1077 struct cvmx_pcsx_sgmx_lp_adv_reg_s 1078 { 1079#if __BYTE_ORDER == __BIG_ENDIAN 1080 uint64_t reserved_16_63 : 48; 1081 uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */ 1082 uint64_t reserved_13_14 : 2; 1083 uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */ 1084 uint64_t speed : 2; /**< Link Speed 1085 0 0 10Mb/s 1086 0 1 100Mb/s 1087 1 0 1000Mb/s 1088 1 1 NS */ 1089 uint64_t reserved_1_9 : 9; 1090 uint64_t one : 1; /**< Always set to match tx_config_reg<0> */ 1091#else 1092 uint64_t one : 1; 1093 uint64_t reserved_1_9 : 9; 1094 uint64_t speed : 2; 1095 uint64_t dup : 1; 1096 uint64_t reserved_13_14 : 2; 1097 uint64_t link : 1; 1098 uint64_t reserved_16_63 : 48; 1099#endif 1100 } s; 1101 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; 1102 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; 1103 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; 1104 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; 1105 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; 1106 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; 1107}; 1108typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t; 1109 1110/** 1111 * cvmx_pcs#_tx#_states_reg 1112 * 1113 * PCS_TX_STATES_REG = TX State Machines states register 1114 * 1115 */ 1116union cvmx_pcsx_txx_states_reg 1117{ 1118 uint64_t u64; 1119 struct cvmx_pcsx_txx_states_reg_s 1120 { 1121#if __BYTE_ORDER == __BIG_ENDIAN 1122 uint64_t reserved_7_63 : 57; 1123 uint64_t xmit : 2; /**< 0=undefined, 1=config, 2=idle, 3=data */ 1124 uint64_t tx_bad : 1; /**< Xmit state machine in a bad state */ 1125 uint64_t ord_st : 4; /**< Xmit ordered set state machine state */ 1126#else 1127 uint64_t ord_st : 4; 1128 uint64_t tx_bad : 1; 1129 uint64_t xmit : 2; 1130 uint64_t reserved_7_63 : 57; 1131#endif 1132 } s; 1133 struct cvmx_pcsx_txx_states_reg_s cn52xx; 1134 struct cvmx_pcsx_txx_states_reg_s cn52xxp1; 1135 struct cvmx_pcsx_txx_states_reg_s cn56xx; 1136 struct cvmx_pcsx_txx_states_reg_s cn56xxp1; 1137 struct cvmx_pcsx_txx_states_reg_s cn63xx; 1138 struct cvmx_pcsx_txx_states_reg_s cn63xxp1; 1139}; 1140typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t; 1141 1142/** 1143 * cvmx_pcs#_tx_rx#_polarity_reg 1144 * 1145 * PCS_POLARITY_REG = TX_RX polarity reg 1146 * 1147 */ 1148union cvmx_pcsx_tx_rxx_polarity_reg 1149{ 1150 uint64_t u64; 1151 struct cvmx_pcsx_tx_rxx_polarity_reg_s 1152 { 1153#if __BYTE_ORDER == __BIG_ENDIAN 1154 uint64_t reserved_4_63 : 60; 1155 uint64_t rxovrd : 1; /**< When 0, <2> determines polarity 1156 when 1, <1> determines polarity */ 1157 uint64_t autorxpl : 1; /**< Auto RX polarity detected. 1=inverted, 0=normal 1158 This bit always represents the correct rx polarity 1159 setting needed for successful rx path operartion, 1160 once a successful code group sync is obtained */ 1161 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1162 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1163#else 1164 uint64_t txplrt : 1; 1165 uint64_t rxplrt : 1; 1166 uint64_t autorxpl : 1; 1167 uint64_t rxovrd : 1; 1168 uint64_t reserved_4_63 : 60; 1169#endif 1170 } s; 1171 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; 1172 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; 1173 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; 1174 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; 1175 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; 1176 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; 1177}; 1178typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t; 1179 1180#endif 1181