cvmx-ndf-defs.h revision 215976
125184Sjkh/***********************license start*************** 225184Sjkh * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 350472Speter * reserved. 425184Sjkh * 525184Sjkh * 651231Ssheldonh * Redistribution and use in source and binary forms, with or without 751231Ssheldonh * modification, are permitted provided that the following conditions are 825184Sjkh * met: 925184Sjkh * 1025184Sjkh * * Redistributions of source code must retain the above copyright 1125184Sjkh * notice, this list of conditions and the following disclaimer. 1251231Ssheldonh * 1325184Sjkh * * Redistributions in binary form must reproduce the above 1451231Ssheldonh * copyright notice, this list of conditions and the following 1525184Sjkh * disclaimer in the documentation and/or other materials provided 1651231Ssheldonh * with the distribution. 1751231Ssheldonh 1851231Ssheldonh * * Neither the name of Cavium Networks nor the names of 1951231Ssheldonh * its contributors may be used to endorse or promote products 2051231Ssheldonh * derived from this software without specific prior written 2151231Ssheldonh * permission. 2225184Sjkh 2351231Ssheldonh * This Software, including technical data, may be subject to U.S. export control 2451231Ssheldonh * laws, including the U.S. Export Administration Act and its associated 2551231Ssheldonh * regulations, and may be subject to export or import regulations in other 2651231Ssheldonh * countries. 2751231Ssheldonh 2851231Ssheldonh * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2951231Ssheldonh * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 3051231Ssheldonh * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3151231Ssheldonh * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3251231Ssheldonh * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3340006Sphk * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3451231Ssheldonh * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3542621Shm * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3651231Ssheldonh * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3751231Ssheldonh * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3851231Ssheldonh ***********************license end**************************************/ 3951231Ssheldonh 4051231Ssheldonh 4151231Ssheldonh/** 4251231Ssheldonh * cvmx-ndf-defs.h 4351231Ssheldonh * 4451231Ssheldonh * Configuration and status register (CSR) type definitions for 4551231Ssheldonh * Octeon ndf. 4642627Sjoerg * 4751231Ssheldonh * This file is auto generated. Do not edit. 4851231Ssheldonh * 4951231Ssheldonh * <hr>$Revision$<hr> 5051231Ssheldonh * 5151231Ssheldonh */ 5251231Ssheldonh#ifndef __CVMX_NDF_TYPEDEFS_H__ 5351231Ssheldonh#define __CVMX_NDF_TYPEDEFS_H__ 5451231Ssheldonh 5551231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5651231Ssheldonh#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 5751231Ssheldonhstatic inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 5851231Ssheldonh{ 5951231Ssheldonh if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 6051231Ssheldonh cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 6149122Sbrian return CVMX_ADD_IO_SEG(0x0001070001000018ull); 6251231Ssheldonh} 6351231Ssheldonh#else 6451231Ssheldonh#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 6551231Ssheldonh#endif 6651231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6751231Ssheldonh#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 6851231Ssheldonhstatic inline uint64_t CVMX_NDF_CMD_FUNC(void) 6949122Sbrian{ 7054458Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 7151231Ssheldonh cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 7251231Ssheldonh return CVMX_ADD_IO_SEG(0x0001070001000000ull); 7351231Ssheldonh} 7454458Sobrien#else 7551231Ssheldonh#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 7649122Sbrian#endif 7751231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 7851231Ssheldonh#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 7951231Ssheldonhstatic inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 8029300Sdanny{ 8151231Ssheldonh if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 8251231Ssheldonh cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 8351231Ssheldonh return CVMX_ADD_IO_SEG(0x0001070001000030ull); 8451231Ssheldonh} 8554458Sobrien#else 8654458Sobrien#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 8754458Sobrien#endif 8851231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8951231Ssheldonh#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 9051231Ssheldonhstatic inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 9154458Sobrien{ 9251231Ssheldonh if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 9351231Ssheldonh cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 9454458Sobrien return CVMX_ADD_IO_SEG(0x0001070001000010ull); 9551231Ssheldonh} 9654458Sobrien#else 9754458Sobrien#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 9854458Sobrien#endif 9954458Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 10054458Sobrien#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 10151231Ssheldonhstatic inline uint64_t CVMX_NDF_INT_FUNC(void) 10251231Ssheldonh{ 10351231Ssheldonh if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 10451231Ssheldonh cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 10551231Ssheldonh return CVMX_ADD_IO_SEG(0x0001070001000020ull); 10651231Ssheldonh} 10751231Ssheldonh#else 10854458Sobrien#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 10951231Ssheldonh#endif 11051231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 11151231Ssheldonh#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 11251231Ssheldonhstatic inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 11351231Ssheldonh{ 11451231Ssheldonh if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 11551231Ssheldonh cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 11651231Ssheldonh return CVMX_ADD_IO_SEG(0x0001070001000028ull); 11751231Ssheldonh} 11851231Ssheldonh#else 11951231Ssheldonh#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 12054458Sobrien#endif 12151231Ssheldonh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 12254458Sobrien#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 12351231Ssheldonhstatic inline uint64_t CVMX_NDF_MISC_FUNC(void) 12454458Sobrien{ 12554458Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 12654458Sobrien cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 12751231Ssheldonh return CVMX_ADD_IO_SEG(0x0001070001000008ull); 12854458Sobrien} 12951231Ssheldonh#else 13051231Ssheldonh#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 13157012Shm#endif 13257012Shm#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 13357012Shm#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 13457012Shmstatic inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 13557012Shm{ 13657012Shm if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 13757012Shm cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 13857012Shm return CVMX_ADD_IO_SEG(0x0001070001000038ull); 13957012Shm} 14057012Shm#else 14164471Sbrian#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 14251231Ssheldonh#endif 14351231Ssheldonh 14451231Ssheldonh/** 14551231Ssheldonh * cvmx_ndf_bt_pg_info 14651231Ssheldonh * 14751231Ssheldonh * Notes: 14851231Ssheldonh * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 14951231Ssheldonh * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 15064471Sbrian * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 15151231Ssheldonh * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 15251231Ssheldonh * 15364471Sbrian * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 15451231Ssheldonh * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 15564471Sbrian * 15651231Ssheldonh * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 15751231Ssheldonh * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 15851231Ssheldonh * 15964471Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 16051231Ssheldonh */ 16151231Ssheldonhunion cvmx_ndf_bt_pg_info 16251231Ssheldonh{ 16364471Sbrian uint64_t u64; 16464471Sbrian struct cvmx_ndf_bt_pg_info_s 16564471Sbrian { 16664471Sbrian#if __BYTE_ORDER == __BIG_ENDIAN 16751231Ssheldonh uint64_t reserved_11_63 : 53; 16851231Ssheldonh uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 16951231Ssheldonh command */ 17051231Ssheldonh uint64_t adr_cyc : 4; /**< # of column address cycles */ 17151231Ssheldonh uint64_t size : 3; /**< bytes per page in the nand device */ 17251231Ssheldonh#else 17351231Ssheldonh uint64_t size : 3; 17429300Sdanny uint64_t adr_cyc : 4; 17551231Ssheldonh uint64_t t_mult : 4; 17629300Sdanny uint64_t reserved_11_63 : 53; 17729300Sdanny#endif 17851231Ssheldonh } s; 17951231Ssheldonh struct cvmx_ndf_bt_pg_info_s cn52xx; 18051231Ssheldonh struct cvmx_ndf_bt_pg_info_s cn63xx; 18151231Ssheldonh struct cvmx_ndf_bt_pg_info_s cn63xxp1; 18251231Ssheldonh}; 18351231Ssheldonhtypedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 18451231Ssheldonh 18551231Ssheldonh/** 18651231Ssheldonh * cvmx_ndf_cmd 18751231Ssheldonh * 18844992Sbrian * Notes: 18951231Ssheldonh * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 19051231Ssheldonh * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 19151231Ssheldonh * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 19251231Ssheldonh * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 19351231Ssheldonh * 19451231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 19544992Sbrian */ 19651231Ssheldonhunion cvmx_ndf_cmd 19751231Ssheldonh{ 19851231Ssheldonh uint64_t u64; 19951426Sgreen struct cvmx_ndf_cmd_s 20051426Sgreen { 20151231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 20251231Ssheldonh uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 20351231Ssheldonh#else 20451231Ssheldonh uint64_t nf_cmd : 64; 20551231Ssheldonh#endif 20651231Ssheldonh } s; 20751231Ssheldonh struct cvmx_ndf_cmd_s cn52xx; 20851231Ssheldonh struct cvmx_ndf_cmd_s cn63xx; 20951231Ssheldonh struct cvmx_ndf_cmd_s cn63xxp1; 21051231Ssheldonh}; 21151231Ssheldonhtypedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 21251231Ssheldonh 21351231Ssheldonh/** 21451231Ssheldonh * cvmx_ndf_drbell 21551231Ssheldonh * 21651231Ssheldonh * Notes: 21751231Ssheldonh * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 21851231Ssheldonh * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 21951231Ssheldonh * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 22051231Ssheldonh * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 22151231Ssheldonh * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 22251231Ssheldonh * 22351231Ssheldonh * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 22451231Ssheldonh * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 22551231Ssheldonh * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 22651231Ssheldonh * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 22760103Sache * the last command in the sequence will be a bus release command. The execution unit will start execution of 22860103Sache * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 22960103Sache * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 23060103Sache * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 23160103Sache * CNT field by the number of the command sequences, loaded to the command fifo. 23260103Sache * 23360103Sache * Like all NDF_... registers, 64-bit operations must be used to access this register 23460103Sache */ 23560103Sacheunion cvmx_ndf_drbell 23660103Sache{ 23751231Ssheldonh uint64_t u64; 23851231Ssheldonh struct cvmx_ndf_drbell_s 23951231Ssheldonh { 24051231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 24151231Ssheldonh uint64_t reserved_8_63 : 56; 24251231Ssheldonh uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 24351231Ssheldonh#else 24451231Ssheldonh uint64_t cnt : 8; 24551231Ssheldonh uint64_t reserved_8_63 : 56; 24629300Sdanny#endif 24725184Sjkh } s; 24851231Ssheldonh struct cvmx_ndf_drbell_s cn52xx; 24951231Ssheldonh struct cvmx_ndf_drbell_s cn63xx; 25051231Ssheldonh struct cvmx_ndf_drbell_s cn63xxp1; 25151231Ssheldonh}; 25251231Ssheldonhtypedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 25351231Ssheldonh 25451231Ssheldonh/** 25551231Ssheldonh * cvmx_ndf_ecc_cnt 25651231Ssheldonh * 25751231Ssheldonh * Notes: 25840006Sphk * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 25951231Ssheldonh * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 26051231Ssheldonh * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 26151231Ssheldonh * 26251231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 26351231Ssheldonh */ 26451231Ssheldonhunion cvmx_ndf_ecc_cnt 26551231Ssheldonh{ 26651231Ssheldonh uint64_t u64; 26729300Sdanny struct cvmx_ndf_ecc_cnt_s 26851231Ssheldonh { 26951231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 27051231Ssheldonh uint64_t reserved_32_63 : 32; 27151231Ssheldonh uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 27251231Ssheldonh bytes. The value pertains to the last 1 bit ecc err */ 27351231Ssheldonh uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 27451231Ssheldonh This count saturates instead of wrapping around. */ 27551231Ssheldonh#else 27651231Ssheldonh uint64_t ecc_err : 8; 27725184Sjkh uint64_t xor_ecc : 24; 27851231Ssheldonh uint64_t reserved_32_63 : 32; 27951231Ssheldonh#endif 28051231Ssheldonh } s; 28151231Ssheldonh struct cvmx_ndf_ecc_cnt_s cn52xx; 28251231Ssheldonh struct cvmx_ndf_ecc_cnt_s cn63xx; 28351231Ssheldonh struct cvmx_ndf_ecc_cnt_s cn63xxp1; 28445096Simp}; 28551231Ssheldonhtypedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 28651231Ssheldonh 28751231Ssheldonh/** 28851231Ssheldonh * cvmx_ndf_int 28951231Ssheldonh * 29051231Ssheldonh * Notes: 29139267Sjkoshy * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 29251231Ssheldonh * 29351231Ssheldonh * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 29451231Ssheldonh * last instruction out of the command fifo. 29551231Ssheldonh * 29651231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 29751231Ssheldonh */ 29833439Sguidounion cvmx_ndf_int 29951231Ssheldonh{ 30051231Ssheldonh uint64_t u64; 30151231Ssheldonh struct cvmx_ndf_int_s 30251231Ssheldonh { 30351231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 30451231Ssheldonh uint64_t reserved_7_63 : 57; 30533439Sguido uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 30651231Ssheldonh fatal error. */ 30751231Ssheldonh uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 30851231Ssheldonh uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 30951231Ssheldonh uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 31051231Ssheldonh uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 31151231Ssheldonh uint64_t full : 1; /**< Command fifo is full */ 31247752Sphk uint64_t empty : 1; /**< Command fifo is empty */ 31351231Ssheldonh#else 31451231Ssheldonh uint64_t empty : 1; 31551231Ssheldonh uint64_t full : 1; 31651231Ssheldonh uint64_t wdog : 1; 31751231Ssheldonh uint64_t sm_bad : 1; 31851231Ssheldonh uint64_t ecc_1bit : 1; 31951209Sdes uint64_t ecc_mult : 1; 32051231Ssheldonh uint64_t ovrf : 1; 32151231Ssheldonh uint64_t reserved_7_63 : 57; 32251231Ssheldonh#endif 32351231Ssheldonh } s; 32451231Ssheldonh struct cvmx_ndf_int_s cn52xx; 32551231Ssheldonh struct cvmx_ndf_int_s cn63xx; 32651209Sdes struct cvmx_ndf_int_s cn63xxp1; 32751231Ssheldonh}; 32851231Ssheldonhtypedef union cvmx_ndf_int cvmx_ndf_int_t; 32951231Ssheldonh 33051231Ssheldonh/** 33151231Ssheldonh * cvmx_ndf_int_en 33251231Ssheldonh * 33336174Sjkh * Notes: 33451231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 33551231Ssheldonh * 33651231Ssheldonh */ 33751231Ssheldonhunion cvmx_ndf_int_en 33851231Ssheldonh{ 33951231Ssheldonh uint64_t u64; 34036174Sjkh struct cvmx_ndf_int_en_s 34151231Ssheldonh { 34251231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 34351231Ssheldonh uint64_t reserved_7_63 : 57; 34451231Ssheldonh uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 34551231Ssheldonh uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 34651231Ssheldonh uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 34751231Ssheldonh uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 34851231Ssheldonh uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 34951231Ssheldonh uint64_t full : 1; /**< Command fifo is full */ 35051231Ssheldonh uint64_t empty : 1; /**< Command fifo is empty */ 35151231Ssheldonh#else 35251231Ssheldonh uint64_t empty : 1; 35351231Ssheldonh uint64_t full : 1; 35461961Sdillon uint64_t wdog : 1; 35561961Sdillon uint64_t sm_bad : 1; 35661961Sdillon uint64_t ecc_1bit : 1; 35761961Sdillon uint64_t ecc_mult : 1; 35861961Sdillon uint64_t ovrf : 1; 35961961Sdillon uint64_t reserved_7_63 : 57; 36061961Sdillon#endif 36161961Sdillon } s; 36261961Sdillon struct cvmx_ndf_int_en_s cn52xx; 36361961Sdillon struct cvmx_ndf_int_en_s cn63xx; 36461961Sdillon struct cvmx_ndf_int_en_s cn63xxp1; 36561961Sdillon}; 36664731Sjhbtypedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 36761961Sdillon 36861961Sdillon/** 36961961Sdillon * cvmx_ndf_misc 37061961Sdillon * 37161961Sdillon * Notes: 37261961Sdillon * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 37351231Ssheldonh * the fifo size is 16 entries. 37451231Ssheldonh * 37560628Sdillon * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 37660628Sdillon * represents number of eclk cycles. 37760628Sdillon * 37860628Sdillon * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 37960628Sdillon * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 38060628Sdillon * 38160628Sdillon * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 38260628Sdillon * in response to RD_CMD bit being set to 1 by SW. 38360628Sdillon * 38460628Sdillon * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 38560628Sdillon * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 38651231Ssheldonh * 38751231Ssheldonh * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 38851231Ssheldonh * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 38951231Ssheldonh * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 39051231Ssheldonh * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 39151231Ssheldonh * bit will be cleared on any NDF_CMD csr write by SW. 39251231Ssheldonh * 39351231Ssheldonh * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 39451231Ssheldonh * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 39551231Ssheldonh * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 39651231Ssheldonh * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 39751231Ssheldonh * 39851231Ssheldonh * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 39951231Ssheldonh * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 40051231Ssheldonh * never be set when booting from nand flash and region zero is enabled. 40151231Ssheldonh * 40251231Ssheldonh * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 40351231Ssheldonh * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 40451231Ssheldonh * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 40551231Ssheldonh * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 40651231Ssheldonh * 40751231Ssheldonh * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 40851231Ssheldonh * the fifo. The fifo comes up empty at the end of power on reset. 40951231Ssheldonh * 41051231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 41151231Ssheldonh */ 41251231Ssheldonhunion cvmx_ndf_misc 41351231Ssheldonh{ 41451231Ssheldonh uint64_t u64; 41551231Ssheldonh struct cvmx_ndf_misc_s 41625184Sjkh { 41725184Sjkh#if __BYTE_ORDER == __BIG_ENDIAN 41825184Sjkh uint64_t reserved_28_63 : 36; 41951231Ssheldonh uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 42051231Ssheldonh or boot dma's proceed as if no multi bit errors 42151231Ssheldonh occured. HW will fix single bit errors as usual */ 42251231Ssheldonh uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 42351231Ssheldonh uint64_t wait_cnt : 6; /**< WAIT input filter count */ 42451231Ssheldonh uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 42525184Sjkh uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 42651231Ssheldonh command fifo read out, in response to RD_CMD */ 42751231Ssheldonh uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 42851231Ssheldonh bytes from Command fifo into the NDF_CMD csr 42951231Ssheldonh SW reads NDF_CMD csr, HW clears this bit to 0 */ 43051231Ssheldonh uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 43151231Ssheldonh bytes at a time into the NDF_CMD csr */ 43225184Sjkh uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 43351231Ssheldonh uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 43451231Ssheldonh causes boot state mchines to sleep */ 43554739Sroberto uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 43651231Ssheldonh next command in the fifo. */ 43751231Ssheldonh uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 43825184Sjkh 0=normal operation */ 43951231Ssheldonh#else 44051231Ssheldonh uint64_t rst_ff : 1; 44151231Ssheldonh uint64_t ex_dis : 1; 44251231Ssheldonh uint64_t bt_dis : 1; 44351231Ssheldonh uint64_t bt_dma : 1; 44425184Sjkh uint64_t rd_cmd : 1; 44551231Ssheldonh uint64_t rd_val : 1; 44651231Ssheldonh uint64_t rd_done : 1; 44751231Ssheldonh uint64_t fr_byt : 11; 44851231Ssheldonh uint64_t wait_cnt : 6; 44951231Ssheldonh uint64_t nbr_hwm : 3; 45025184Sjkh uint64_t mb_dis : 1; 45151231Ssheldonh uint64_t reserved_28_63 : 36; 45251231Ssheldonh#endif 45351231Ssheldonh } s; 45451231Ssheldonh struct cvmx_ndf_misc_cn52xx 45551231Ssheldonh { 45651231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 45725184Sjkh uint64_t reserved_27_63 : 37; 45851231Ssheldonh uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 45951231Ssheldonh uint64_t wait_cnt : 6; /**< WAIT input filter count */ 46051231Ssheldonh uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 46151231Ssheldonh uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 46251231Ssheldonh command fifo read out, in response to RD_CMD */ 46351231Ssheldonh uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 46425184Sjkh bytes from Command fifo into the NDF_CMD csr 46551231Ssheldonh SW reads NDF_CMD csr, HW clears this bit to 0 */ 46651231Ssheldonh uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 46751231Ssheldonh bytes at a time into the NDF_CMD csr */ 46851231Ssheldonh uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 46951231Ssheldonh uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 47051231Ssheldonh causes boot state mchines to sleep */ 47151231Ssheldonh uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 47251231Ssheldonh next command in the fifo. */ 47335149Smarkm uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 47451231Ssheldonh 0=normal operation */ 47551231Ssheldonh#else 47651231Ssheldonh uint64_t rst_ff : 1; 47751231Ssheldonh uint64_t ex_dis : 1; 47851231Ssheldonh uint64_t bt_dis : 1; 47951231Ssheldonh uint64_t bt_dma : 1; 48051231Ssheldonh uint64_t rd_cmd : 1; 48151231Ssheldonh uint64_t rd_val : 1; 48251231Ssheldonh uint64_t rd_done : 1; 48351231Ssheldonh uint64_t fr_byt : 11; 48451231Ssheldonh uint64_t wait_cnt : 6; 48551231Ssheldonh uint64_t nbr_hwm : 3; 48640006Sphk uint64_t reserved_27_63 : 37; 48751231Ssheldonh#endif 48851231Ssheldonh } cn52xx; 48951231Ssheldonh struct cvmx_ndf_misc_s cn63xx; 49051231Ssheldonh struct cvmx_ndf_misc_s cn63xxp1; 49151231Ssheldonh}; 49251231Ssheldonhtypedef union cvmx_ndf_misc cvmx_ndf_misc_t; 49351231Ssheldonh 49451231Ssheldonh/** 49551231Ssheldonh * cvmx_ndf_st_reg 49651231Ssheldonh * 49751231Ssheldonh * Notes: 49851231Ssheldonh * This CSR aggregates all state machines used in nand flash controller for debug. 49951231Ssheldonh * Like all NDF_... registers, 64-bit operations must be used to access this register 50051231Ssheldonh */ 50151231Ssheldonhunion cvmx_ndf_st_reg 50251231Ssheldonh{ 50351231Ssheldonh uint64_t u64; 50451231Ssheldonh struct cvmx_ndf_st_reg_s 50551231Ssheldonh { 50651231Ssheldonh#if __BYTE_ORDER == __BIG_ENDIAN 50751231Ssheldonh uint64_t reserved_16_63 : 48; 50851231Ssheldonh uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 50951231Ssheldonh 1 means execution of command sequence is complete 51025184Sjkh and command fifo is empty */ 51125184Sjkh uint64_t exe_sm : 4; /**< Command Execution State machine states */ 51225184Sjkh uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 51351231Ssheldonh uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 51425184Sjkh uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 51551231Ssheldonh uint64_t main_bad : 1; /**< Main State machine in bad state */ 51651231Ssheldonh uint64_t main_sm : 3; /**< Main State machine states */ 51751231Ssheldonh#else 51851231Ssheldonh uint64_t main_sm : 3; 51951231Ssheldonh uint64_t main_bad : 1; 52051231Ssheldonh uint64_t rd_ff : 2; 52151231Ssheldonh uint64_t rd_ff_bad : 1; 52263147Snbm uint64_t bt_sm : 4; 52351231Ssheldonh uint64_t exe_sm : 4; 52451231Ssheldonh uint64_t exe_idle : 1; 52551231Ssheldonh uint64_t reserved_16_63 : 48; 52651231Ssheldonh#endif 52751231Ssheldonh } s; 52851231Ssheldonh struct cvmx_ndf_st_reg_s cn52xx; 52951231Ssheldonh struct cvmx_ndf_st_reg_s cn63xx; 53051231Ssheldonh struct cvmx_ndf_st_reg_s cn63xxp1; 53151231Ssheldonh}; 53251231Ssheldonhtypedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 53351231Ssheldonh 53451231Ssheldonh#endif 53551231Ssheldonh