1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-mixx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon mixx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_MIXX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_MIXX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_MIXX_BIST(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 62215976Sjmallett cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset); 63215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048; 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048) 67215976Sjmallett#endif 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallettstatic inline uint64_t CVMX_MIXX_CTL(unsigned long offset) 70215976Sjmallett{ 71215976Sjmallett if (!( 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 73215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 75215976Sjmallett cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset); 76215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048; 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallettstatic inline uint64_t CVMX_MIXX_INTENA(unsigned long offset) 83215976Sjmallett{ 84215976Sjmallett if (!( 85215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 86215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 87215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 88215976Sjmallett cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset); 89215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048; 90215976Sjmallett} 91215976Sjmallett#else 92215976Sjmallett#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048) 93215976Sjmallett#endif 94215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset) 96215976Sjmallett{ 97215976Sjmallett if (!( 98215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 99215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 100215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 101215976Sjmallett cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset); 102215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048; 103215976Sjmallett} 104215976Sjmallett#else 105215976Sjmallett#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048) 106215976Sjmallett#endif 107215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset) 109215976Sjmallett{ 110215976Sjmallett if (!( 111215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 112215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 114215976Sjmallett cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset); 115215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048; 116215976Sjmallett} 117215976Sjmallett#else 118215976Sjmallett#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048) 119215976Sjmallett#endif 120215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRING1(unsigned long offset) 122215976Sjmallett{ 123215976Sjmallett if (!( 124215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 126215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 127215976Sjmallett cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset); 128215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048; 129215976Sjmallett} 130215976Sjmallett#else 131215976Sjmallett#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048) 132215976Sjmallett#endif 133215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRING2(unsigned long offset) 135215976Sjmallett{ 136215976Sjmallett if (!( 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 139215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 140215976Sjmallett cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset); 141215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048; 142215976Sjmallett} 143215976Sjmallett#else 144215976Sjmallett#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048) 145215976Sjmallett#endif 146215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147215976Sjmallettstatic inline uint64_t CVMX_MIXX_ISR(unsigned long offset) 148215976Sjmallett{ 149215976Sjmallett if (!( 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 153215976Sjmallett cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset); 154215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048; 155215976Sjmallett} 156215976Sjmallett#else 157215976Sjmallett#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048) 158215976Sjmallett#endif 159215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset) 161215976Sjmallett{ 162215976Sjmallett if (!( 163215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 166215976Sjmallett cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset); 167215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048; 168215976Sjmallett} 169215976Sjmallett#else 170215976Sjmallett#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048) 171215976Sjmallett#endif 172215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset) 174215976Sjmallett{ 175215976Sjmallett if (!( 176215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 177215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 179215976Sjmallett cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset); 180215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048; 181215976Sjmallett} 182215976Sjmallett#else 183215976Sjmallett#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048) 184215976Sjmallett#endif 185215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORING1(unsigned long offset) 187215976Sjmallett{ 188215976Sjmallett if (!( 189215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 192215976Sjmallett cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORING2(unsigned long offset) 200215976Sjmallett{ 201215976Sjmallett if (!( 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 205215976Sjmallett cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 218215976Sjmallett cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset); 219215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallettstatic inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset) 226215976Sjmallett{ 227215976Sjmallett if (!( 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 229215976Sjmallett cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 240215976Sjmallett cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset); 241215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048; 242215976Sjmallett} 243215976Sjmallett#else 244215976Sjmallett#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048) 245215976Sjmallett#endif 246215976Sjmallett 247215976Sjmallett/** 248215976Sjmallett * cvmx_mix#_bist 249215976Sjmallett * 250215976Sjmallett * MIX_BIST = MIX BIST Register 251215976Sjmallett * 252215976Sjmallett * Description: 253215976Sjmallett * NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO. 254215976Sjmallett */ 255215976Sjmallettunion cvmx_mixx_bist 256215976Sjmallett{ 257215976Sjmallett uint64_t u64; 258215976Sjmallett struct cvmx_mixx_bist_s 259215976Sjmallett { 260215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 261215976Sjmallett uint64_t reserved_6_63 : 58; 262215976Sjmallett uint64_t opfdat : 1; /**< Bist Results for AGO OPF Buffer RAM 263215976Sjmallett - 0: GOOD (or bist in progress/never run) 264215976Sjmallett - 1: BAD */ 265215976Sjmallett uint64_t mrgdat : 1; /**< Bist Results for AGI MRG Buffer RAM 266215976Sjmallett - 0: GOOD (or bist in progress/never run) 267215976Sjmallett - 1: BAD */ 268215976Sjmallett uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM 269215976Sjmallett - 0: GOOD (or bist in progress/never run) 270215976Sjmallett - 1: BAD */ 271215976Sjmallett uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM 272215976Sjmallett - 0: GOOD (or bist in progress/never run) 273215976Sjmallett - 1: BAD */ 274215976Sjmallett uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM 275215976Sjmallett - 0: GOOD (or bist in progress/never run) 276215976Sjmallett - 1: BAD */ 277215976Sjmallett uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM 278215976Sjmallett - 0: GOOD (or bist in progress/never run) 279215976Sjmallett - 1: BAD */ 280215976Sjmallett#else 281215976Sjmallett uint64_t orfdat : 1; 282215976Sjmallett uint64_t irfdat : 1; 283215976Sjmallett uint64_t ipfdat : 1; 284215976Sjmallett uint64_t mrqdat : 1; 285215976Sjmallett uint64_t mrgdat : 1; 286215976Sjmallett uint64_t opfdat : 1; 287215976Sjmallett uint64_t reserved_6_63 : 58; 288215976Sjmallett#endif 289215976Sjmallett } s; 290215976Sjmallett struct cvmx_mixx_bist_cn52xx 291215976Sjmallett { 292215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 293215976Sjmallett uint64_t reserved_4_63 : 60; 294215976Sjmallett uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM 295215976Sjmallett - 0: GOOD (or bist in progress/never run) 296215976Sjmallett - 1: BAD */ 297215976Sjmallett uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM 298215976Sjmallett - 0: GOOD (or bist in progress/never run) 299215976Sjmallett - 1: BAD */ 300215976Sjmallett uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM 301215976Sjmallett - 0: GOOD (or bist in progress/never run) 302215976Sjmallett - 1: BAD */ 303215976Sjmallett uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM 304215976Sjmallett - 0: GOOD (or bist in progress/never run) 305215976Sjmallett - 1: BAD */ 306215976Sjmallett#else 307215976Sjmallett uint64_t orfdat : 1; 308215976Sjmallett uint64_t irfdat : 1; 309215976Sjmallett uint64_t ipfdat : 1; 310215976Sjmallett uint64_t mrqdat : 1; 311215976Sjmallett uint64_t reserved_4_63 : 60; 312215976Sjmallett#endif 313215976Sjmallett } cn52xx; 314215976Sjmallett struct cvmx_mixx_bist_cn52xx cn52xxp1; 315215976Sjmallett struct cvmx_mixx_bist_cn52xx cn56xx; 316215976Sjmallett struct cvmx_mixx_bist_cn52xx cn56xxp1; 317215976Sjmallett struct cvmx_mixx_bist_s cn63xx; 318215976Sjmallett struct cvmx_mixx_bist_s cn63xxp1; 319215976Sjmallett}; 320215976Sjmalletttypedef union cvmx_mixx_bist cvmx_mixx_bist_t; 321215976Sjmallett 322215976Sjmallett/** 323215976Sjmallett * cvmx_mix#_ctl 324215976Sjmallett * 325215976Sjmallett * MIX_CTL = MIX Control Register 326215976Sjmallett * 327215976Sjmallett * Description: 328215976Sjmallett * NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO. 329215976Sjmallett * To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO. 330215976Sjmallett */ 331215976Sjmallettunion cvmx_mixx_ctl 332215976Sjmallett{ 333215976Sjmallett uint64_t u64; 334215976Sjmallett struct cvmx_mixx_ctl_s 335215976Sjmallett { 336215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 337215976Sjmallett uint64_t reserved_12_63 : 52; 338215976Sjmallett uint64_t ts_thresh : 4; /**< TimeStamp Interrupt Threshold 339215976Sjmallett When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT] 340215976Sjmallett is greater than MIX_CTL[TS_THRESH], then a programmable 341215976Sjmallett TimeStamp Interrupt is issued (see MIX_INTR[TS] 342215976Sjmallett MIX_INTENA[TSENA]). 343215976Sjmallett SWNOTE: For o63, since the implementation only supports 344215976Sjmallett 4 oustanding timestamp interrupts, this field should 345215976Sjmallett only be programmed from [0..3]. */ 346215976Sjmallett uint64_t crc_strip : 1; /**< HW CRC Strip Enable 347215976Sjmallett When enabled, the last 4 bytes(CRC) of the ingress packet 348215976Sjmallett are not included in cumulative packet byte length. 349215976Sjmallett In other words, the cumulative LEN field for all 350215976Sjmallett I-Ring Buffer Entries associated with a given ingress 351215976Sjmallett packet will be 4 bytes less (so that the final 4B HW CRC 352215976Sjmallett packet data is not processed by software). */ 353215976Sjmallett uint64_t busy : 1; /**< MIX Busy Status bit 354215976Sjmallett MIX will assert busy status any time there are: 355215976Sjmallett 1) L2/DRAM reads in-flight (NCB-arb to read 356215976Sjmallett response) 357215976Sjmallett 2) L2/DRAM writes in-flight (NCB-arb to write 358215976Sjmallett data is sent. 359215976Sjmallett 3) L2/DRAM write commits in-flight (NCB-arb to write 360215976Sjmallett commit response). 361215976Sjmallett NOTE: After MIX_CTL[EN]=0, the MIX will eventually 362215976Sjmallett complete any "inflight" transactions, at which point the 363215976Sjmallett BUSY will de-assert. */ 364215976Sjmallett uint64_t en : 1; /**< MIX Enable bit 365215976Sjmallett When EN=0, MIX will no longer arbitrate for 366215976Sjmallett any new L2/DRAM read/write requests on the NCB Bus. 367215976Sjmallett MIX will complete any requests that are currently 368215976Sjmallett pended for the NCB Bus. */ 369215976Sjmallett uint64_t reset : 1; /**< MIX Soft Reset 370215976Sjmallett When SW writes a '1' to MIX_CTL[RESET], the 371215976Sjmallett MII-MIX/AGL logic will execute a soft reset. 372215976Sjmallett NOTE: During a soft reset, CSR accesses are not effected. 373215976Sjmallett However, the values of the CSR fields will be effected by 374215976Sjmallett soft reset (except MIX_CTL[RESET] itself). 375215976Sjmallett NOTE: After power-on, the MII-AGL/MIX are held in reset 376215976Sjmallett until the MIX_CTL[RESET] is written to zero. 377215976Sjmallett The intended "soft reset" sequence is: (please also 378215976Sjmallett refer to HRM Section 12.6.2 on MIX/AGL Block Reset). 379215976Sjmallett 1) Write MIX_CTL[EN]=0 380215976Sjmallett [To prevent any NEW transactions from being started] 381215976Sjmallett 2) Wait for MIX_CTL[BUSY]=0 382215976Sjmallett [To indicate that all inflight transactions have 383215976Sjmallett completed] 384215976Sjmallett 3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read 385215976Sjmallett and wait for the result. 386215976Sjmallett 4) Re-Initialize the MIX/AGL just as would be done 387215976Sjmallett for a hard reset. 388215976Sjmallett NOTE: Once the MII has been soft-reset, please refer to HRM Section 389215976Sjmallett 12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL 390215976Sjmallett re-initialization sequence. */ 391215976Sjmallett uint64_t lendian : 1; /**< Packet Little Endian Mode 392215976Sjmallett (0: Big Endian Mode/1: Little Endian Mode) 393215976Sjmallett When the mode is set, MIX will byte-swap packet data 394215976Sjmallett loads/stores at the MIX/NCB boundary. */ 395215976Sjmallett uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode. 396215976Sjmallett When set to zero, the arbiter is fixed priority with 397215976Sjmallett the following priority scheme: 398215976Sjmallett Highest Priority: I-Ring Packet Write Request 399215976Sjmallett O-Ring Packet Read Request 400215976Sjmallett I-Ring Entry Write Request 401215976Sjmallett I-Ring Entry Read Request 402215976Sjmallett O-Ring Entry Read Request 403215976Sjmallett When set to one, the arbiter is round robin. */ 404215976Sjmallett uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark. 405215976Sjmallett The MRQ contains 16 CB-Requests which are CSR Rd/Wr 406215976Sjmallett Requests. If the MRQ backs up with "HWM" entries, 407215976Sjmallett then new CB-Requests are 'stalled'. 408215976Sjmallett [0]: HWM = 11 409215976Sjmallett [1]: HWM = 10 410215976Sjmallett [2]: HWM = 9 411215976Sjmallett [3]: HWM = 8 412215976Sjmallett NOTE: This must only be written at power-on/boot time. */ 413215976Sjmallett#else 414215976Sjmallett uint64_t mrq_hwm : 2; 415215976Sjmallett uint64_t nbtarb : 1; 416215976Sjmallett uint64_t lendian : 1; 417215976Sjmallett uint64_t reset : 1; 418215976Sjmallett uint64_t en : 1; 419215976Sjmallett uint64_t busy : 1; 420215976Sjmallett uint64_t crc_strip : 1; 421215976Sjmallett uint64_t ts_thresh : 4; 422215976Sjmallett uint64_t reserved_12_63 : 52; 423215976Sjmallett#endif 424215976Sjmallett } s; 425215976Sjmallett struct cvmx_mixx_ctl_cn52xx 426215976Sjmallett { 427215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 428215976Sjmallett uint64_t reserved_8_63 : 56; 429215976Sjmallett uint64_t crc_strip : 1; /**< HW CRC Strip Enable 430215976Sjmallett When enabled, the last 4 bytes(CRC) of the ingress packet 431215976Sjmallett are not included in cumulative packet byte length. 432215976Sjmallett In other words, the cumulative LEN field for all 433215976Sjmallett I-Ring Buffer Entries associated with a given ingress 434215976Sjmallett packet will be 4 bytes less (so that the final 4B HW CRC 435215976Sjmallett packet data is not processed by software). */ 436215976Sjmallett uint64_t busy : 1; /**< MIX Busy Status bit 437215976Sjmallett MIX will assert busy status any time there are: 438215976Sjmallett 1) L2/DRAM reads in-flight (NCB-arb to read 439215976Sjmallett response) 440215976Sjmallett 2) L2/DRAM writes in-flight (NCB-arb to write 441215976Sjmallett data is sent. 442215976Sjmallett 3) L2/DRAM write commits in-flight (NCB-arb to write 443215976Sjmallett commit response). 444215976Sjmallett NOTE: After MIX_CTL[EN]=0, the MIX will eventually 445215976Sjmallett complete any "inflight" transactions, at which point the 446215976Sjmallett BUSY will de-assert. */ 447215976Sjmallett uint64_t en : 1; /**< MIX Enable bit 448215976Sjmallett When EN=0, MIX will no longer arbitrate for 449215976Sjmallett any new L2/DRAM read/write requests on the NCB Bus. 450215976Sjmallett MIX will complete any requests that are currently 451215976Sjmallett pended for the NCB Bus. */ 452215976Sjmallett uint64_t reset : 1; /**< MIX Soft Reset 453215976Sjmallett When SW writes a '1' to MIX_CTL[RESET], the 454215976Sjmallett MII-MIX/AGL logic will execute a soft reset. 455215976Sjmallett NOTE: During a soft reset, CSR accesses are not effected. 456215976Sjmallett However, the values of the CSR fields will be effected by 457215976Sjmallett soft reset (except MIX_CTL[RESET] itself). 458215976Sjmallett NOTE: After power-on, the MII-AGL/MIX are held in reset 459215976Sjmallett until the MIX_CTL[RESET] is written to zero. 460215976Sjmallett The intended "soft reset" sequence is: (please also 461215976Sjmallett refer to HRM Section 12.6.2 on MIX/AGL Block Reset). 462215976Sjmallett 1) Write MIX_CTL[EN]=0 463215976Sjmallett [To prevent any NEW transactions from being started] 464215976Sjmallett 2) Wait for MIX_CTL[BUSY]=0 465215976Sjmallett [To indicate that all inflight transactions have 466215976Sjmallett completed] 467215976Sjmallett 3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read 468215976Sjmallett and wait for the result. 469215976Sjmallett 4) Re-Initialize the MIX/AGL just as would be done 470215976Sjmallett for a hard reset. 471215976Sjmallett NOTE: Once the MII has been soft-reset, please refer to HRM Section 472215976Sjmallett 12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL 473215976Sjmallett re-initialization sequence. */ 474215976Sjmallett uint64_t lendian : 1; /**< Packet Little Endian Mode 475215976Sjmallett (0: Big Endian Mode/1: Little Endian Mode) 476215976Sjmallett When the mode is set, MIX will byte-swap packet data 477215976Sjmallett loads/stores at the MIX/NCB boundary. */ 478215976Sjmallett uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode. 479215976Sjmallett When set to zero, the arbiter is fixed priority with 480215976Sjmallett the following priority scheme: 481215976Sjmallett Highest Priority: I-Ring Packet Write Request 482215976Sjmallett O-Ring Packet Read Request 483215976Sjmallett I-Ring Entry Write Request 484215976Sjmallett I-Ring Entry Read Request 485215976Sjmallett O-Ring Entry Read Request 486215976Sjmallett When set to one, the arbiter is round robin. */ 487215976Sjmallett uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark. 488215976Sjmallett The MRQ contains 16 CB-Requests which are CSR Rd/Wr 489215976Sjmallett Requests. If the MRQ backs up with "HWM" entries, 490215976Sjmallett then new CB-Requests are 'stalled'. 491215976Sjmallett [0]: HWM = 11 492215976Sjmallett [1]: HWM = 10 493215976Sjmallett [2]: HWM = 9 494215976Sjmallett [3]: HWM = 8 495215976Sjmallett NOTE: This must only be written at power-on/boot time. */ 496215976Sjmallett#else 497215976Sjmallett uint64_t mrq_hwm : 2; 498215976Sjmallett uint64_t nbtarb : 1; 499215976Sjmallett uint64_t lendian : 1; 500215976Sjmallett uint64_t reset : 1; 501215976Sjmallett uint64_t en : 1; 502215976Sjmallett uint64_t busy : 1; 503215976Sjmallett uint64_t crc_strip : 1; 504215976Sjmallett uint64_t reserved_8_63 : 56; 505215976Sjmallett#endif 506215976Sjmallett } cn52xx; 507215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn52xxp1; 508215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn56xx; 509215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn56xxp1; 510215976Sjmallett struct cvmx_mixx_ctl_s cn63xx; 511215976Sjmallett struct cvmx_mixx_ctl_s cn63xxp1; 512215976Sjmallett}; 513215976Sjmalletttypedef union cvmx_mixx_ctl cvmx_mixx_ctl_t; 514215976Sjmallett 515215976Sjmallett/** 516215976Sjmallett * cvmx_mix#_intena 517215976Sjmallett * 518215976Sjmallett * MIX_INTENA = MIX Local Interrupt Enable Mask Register 519215976Sjmallett * 520215976Sjmallett * Description: 521215976Sjmallett * NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO. 522215976Sjmallett * To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO. 523215976Sjmallett */ 524215976Sjmallettunion cvmx_mixx_intena 525215976Sjmallett{ 526215976Sjmallett uint64_t u64; 527215976Sjmallett struct cvmx_mixx_intena_s 528215976Sjmallett { 529215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 530215976Sjmallett uint64_t reserved_8_63 : 56; 531215976Sjmallett uint64_t tsena : 1; /**< TimeStamp Interrupt Enable 532215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 533215976Sjmallett and this local interrupt mask bit is set, than an 534215976Sjmallett interrupt is reported for an Outbound Ring with Timestamp 535215976Sjmallett event (see: MIX_ISR[TS]). */ 536215976Sjmallett uint64_t orunena : 1; /**< ORCNT UnderFlow Detected Enable 537215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 538215976Sjmallett and this local interrupt mask bit is set, than an 539215976Sjmallett interrupt is reported for an ORCNT underflow condition 540215976Sjmallett MIX_ISR[ORUN]. */ 541215976Sjmallett uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable 542215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 543215976Sjmallett and this local interrupt mask bit is set, than an 544215976Sjmallett interrupt is reported for an IRCNT underflow condition 545215976Sjmallett MIX_ISR[IRUN]. */ 546215976Sjmallett uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt 547215976Sjmallett enable. If both the global interrupt mask bits 548215976Sjmallett (CIU_INTx_EN*[MII]) and the local interrupt mask 549215976Sjmallett bit(DATA_DRPENA) is set, than an interrupt is 550215976Sjmallett reported for this event. */ 551215976Sjmallett uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable 552215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 553215976Sjmallett and this local interrupt mask bit is set, than an 554215976Sjmallett interrupt is reported for an Inbound Ring Threshold 555215976Sjmallett Exceeded event(IRTHRESH). */ 556215976Sjmallett uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable 557215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 558215976Sjmallett and this local interrupt mask bit is set, than an 559215976Sjmallett interrupt is reported for an Outbound Ring Threshold 560215976Sjmallett Exceeded event(ORTHRESH). */ 561215976Sjmallett uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 562215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 563215976Sjmallett and this local interrupt mask bit is set, than an 564215976Sjmallett interrupt is reported for an Inbound Doorbell Overflow 565215976Sjmallett event(IDBOVF). */ 566215976Sjmallett uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable 567215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 568215976Sjmallett and this local interrupt mask bit is set, than an 569215976Sjmallett interrupt is reported for an Outbound Doorbell Overflow 570215976Sjmallett event(ODBOVF). */ 571215976Sjmallett#else 572215976Sjmallett uint64_t ovfena : 1; 573215976Sjmallett uint64_t ivfena : 1; 574215976Sjmallett uint64_t othena : 1; 575215976Sjmallett uint64_t ithena : 1; 576215976Sjmallett uint64_t data_drpena : 1; 577215976Sjmallett uint64_t irunena : 1; 578215976Sjmallett uint64_t orunena : 1; 579215976Sjmallett uint64_t tsena : 1; 580215976Sjmallett uint64_t reserved_8_63 : 56; 581215976Sjmallett#endif 582215976Sjmallett } s; 583215976Sjmallett struct cvmx_mixx_intena_cn52xx 584215976Sjmallett { 585215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 586215976Sjmallett uint64_t reserved_7_63 : 57; 587215976Sjmallett uint64_t orunena : 1; /**< ORCNT UnderFlow Detected 588215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 589215976Sjmallett and this local interrupt mask bit is set, than an 590215976Sjmallett interrupt is reported for an ORCNT underflow condition 591215976Sjmallett MIX_ISR[ORUN]. */ 592215976Sjmallett uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable 593215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 594215976Sjmallett and this local interrupt mask bit is set, than an 595215976Sjmallett interrupt is reported for an IRCNT underflow condition 596215976Sjmallett MIX_ISR[IRUN]. */ 597215976Sjmallett uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt 598215976Sjmallett enable. If both the global interrupt mask bits 599215976Sjmallett (CIU_INTx_EN*[MII]) and the local interrupt mask 600215976Sjmallett bit(DATA_DRPENA) is set, than an interrupt is 601215976Sjmallett reported for this event. */ 602215976Sjmallett uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable 603215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 604215976Sjmallett and this local interrupt mask bit is set, than an 605215976Sjmallett interrupt is reported for an Inbound Ring Threshold 606215976Sjmallett Exceeded event(IRTHRESH). */ 607215976Sjmallett uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable 608215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 609215976Sjmallett and this local interrupt mask bit is set, than an 610215976Sjmallett interrupt is reported for an Outbound Ring Threshold 611215976Sjmallett Exceeded event(ORTHRESH). */ 612215976Sjmallett uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 613215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 614215976Sjmallett and this local interrupt mask bit is set, than an 615215976Sjmallett interrupt is reported for an Inbound Doorbell Overflow 616215976Sjmallett event(IDBOVF). */ 617215976Sjmallett uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable 618215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 619215976Sjmallett and this local interrupt mask bit is set, than an 620215976Sjmallett interrupt is reported for an Outbound Doorbell Overflow 621215976Sjmallett event(ODBOVF). */ 622215976Sjmallett#else 623215976Sjmallett uint64_t ovfena : 1; 624215976Sjmallett uint64_t ivfena : 1; 625215976Sjmallett uint64_t othena : 1; 626215976Sjmallett uint64_t ithena : 1; 627215976Sjmallett uint64_t data_drpena : 1; 628215976Sjmallett uint64_t irunena : 1; 629215976Sjmallett uint64_t orunena : 1; 630215976Sjmallett uint64_t reserved_7_63 : 57; 631215976Sjmallett#endif 632215976Sjmallett } cn52xx; 633215976Sjmallett struct cvmx_mixx_intena_cn52xx cn52xxp1; 634215976Sjmallett struct cvmx_mixx_intena_cn52xx cn56xx; 635215976Sjmallett struct cvmx_mixx_intena_cn52xx cn56xxp1; 636215976Sjmallett struct cvmx_mixx_intena_s cn63xx; 637215976Sjmallett struct cvmx_mixx_intena_s cn63xxp1; 638215976Sjmallett}; 639215976Sjmalletttypedef union cvmx_mixx_intena cvmx_mixx_intena_t; 640215976Sjmallett 641215976Sjmallett/** 642215976Sjmallett * cvmx_mix#_ircnt 643215976Sjmallett * 644215976Sjmallett * MIX_IRCNT = MIX I-Ring Pending Packet Counter 645215976Sjmallett * 646215976Sjmallett * Description: 647215976Sjmallett * NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO. 648215976Sjmallett * To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO. 649215976Sjmallett */ 650215976Sjmallettunion cvmx_mixx_ircnt 651215976Sjmallett{ 652215976Sjmallett uint64_t u64; 653215976Sjmallett struct cvmx_mixx_ircnt_s 654215976Sjmallett { 655215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 656215976Sjmallett uint64_t reserved_20_63 : 44; 657215976Sjmallett uint64_t ircnt : 20; /**< Pending \# of I-Ring Packets. 658215976Sjmallett Whenever HW writes a completion code of Done, Trunc, 659215976Sjmallett CRCErr or Err, it increments the IRCNT (to indicate 660215976Sjmallett to SW the \# of pending Input packets in system memory). 661215976Sjmallett NOTE: The HW guarantees that the completion code write 662215976Sjmallett is always visible in system memory BEFORE it increments 663215976Sjmallett the IRCNT. 664215976Sjmallett Reads of IRCNT return the current inbound packet count. 665215976Sjmallett Writes of IRCNT decrement the count by the value 666215976Sjmallett written. 667215976Sjmallett This register is used to generate interrupts to alert 668215976Sjmallett SW of pending inbound MIX packets in system memory. 669215976Sjmallett NOTE: In the case of inbound packets that span multiple 670215976Sjmallett I-Ring entries, SW must keep track of the \# of I-Ring Entries 671215976Sjmallett associated with a given inbound packet to reclaim the 672215976Sjmallett proper \# of I-Ring Entries for re-use. */ 673215976Sjmallett#else 674215976Sjmallett uint64_t ircnt : 20; 675215976Sjmallett uint64_t reserved_20_63 : 44; 676215976Sjmallett#endif 677215976Sjmallett } s; 678215976Sjmallett struct cvmx_mixx_ircnt_s cn52xx; 679215976Sjmallett struct cvmx_mixx_ircnt_s cn52xxp1; 680215976Sjmallett struct cvmx_mixx_ircnt_s cn56xx; 681215976Sjmallett struct cvmx_mixx_ircnt_s cn56xxp1; 682215976Sjmallett struct cvmx_mixx_ircnt_s cn63xx; 683215976Sjmallett struct cvmx_mixx_ircnt_s cn63xxp1; 684215976Sjmallett}; 685215976Sjmalletttypedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t; 686215976Sjmallett 687215976Sjmallett/** 688215976Sjmallett * cvmx_mix#_irhwm 689215976Sjmallett * 690215976Sjmallett * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register 691215976Sjmallett * 692215976Sjmallett * Description: 693215976Sjmallett * NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO. 694215976Sjmallett * To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO. 695215976Sjmallett */ 696215976Sjmallettunion cvmx_mixx_irhwm 697215976Sjmallett{ 698215976Sjmallett uint64_t u64; 699215976Sjmallett struct cvmx_mixx_irhwm_s 700215976Sjmallett { 701215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 702215976Sjmallett uint64_t reserved_40_63 : 24; 703215976Sjmallett uint64_t ibplwm : 20; /**< I-Ring BackPressure Low Water Mark Threshold. 704215976Sjmallett When the \#of available I-Ring Entries (IDBELL) 705215976Sjmallett is less than IBPLWM, the AGL-MAC will: 706215976Sjmallett a) In full-duplex mode: send periodic PAUSE packets. 707215976Sjmallett b) In half-duplex mode: Force collisions. 708215976Sjmallett This programmable mechanism is provided as a means 709215976Sjmallett to backpressure input traffic 'early' enough (so 710215976Sjmallett that packets are not 'dropped' by OCTEON). */ 711215976Sjmallett uint64_t irhwm : 20; /**< I-Ring Entry High Water Mark Threshold. 712215976Sjmallett Used to determine when the \# of Inbound packets 713215976Sjmallett in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM 714215976Sjmallett threshold. 715215976Sjmallett NOTE: The power-on value of the CIU_INTx_EN*[MII] 716215976Sjmallett interrupt enable bits is zero and must be enabled 717215976Sjmallett to allow interrupts to be reported. */ 718215976Sjmallett#else 719215976Sjmallett uint64_t irhwm : 20; 720215976Sjmallett uint64_t ibplwm : 20; 721215976Sjmallett uint64_t reserved_40_63 : 24; 722215976Sjmallett#endif 723215976Sjmallett } s; 724215976Sjmallett struct cvmx_mixx_irhwm_s cn52xx; 725215976Sjmallett struct cvmx_mixx_irhwm_s cn52xxp1; 726215976Sjmallett struct cvmx_mixx_irhwm_s cn56xx; 727215976Sjmallett struct cvmx_mixx_irhwm_s cn56xxp1; 728215976Sjmallett struct cvmx_mixx_irhwm_s cn63xx; 729215976Sjmallett struct cvmx_mixx_irhwm_s cn63xxp1; 730215976Sjmallett}; 731215976Sjmalletttypedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t; 732215976Sjmallett 733215976Sjmallett/** 734215976Sjmallett * cvmx_mix#_iring1 735215976Sjmallett * 736215976Sjmallett * MIX_IRING1 = MIX Inbound Ring Register \#1 737215976Sjmallett * 738215976Sjmallett * Description: 739215976Sjmallett * NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO. 740215976Sjmallett * To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO. 741215976Sjmallett */ 742215976Sjmallettunion cvmx_mixx_iring1 743215976Sjmallett{ 744215976Sjmallett uint64_t u64; 745215976Sjmallett struct cvmx_mixx_iring1_s 746215976Sjmallett { 747215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 748215976Sjmallett uint64_t reserved_60_63 : 4; 749215976Sjmallett uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B 750215976Sjmallett words). The ring can be as large as 1M entries. 751215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 752215976Sjmallett (when IDBELL/IRCNT=0). */ 753215976Sjmallett uint64_t ibase : 37; /**< Represents the 8B-aligned base address of the first 754215976Sjmallett Inbound Ring entry in system memory. 755215976Sjmallett NOTE: SW MUST ONLY write to this register during 756215976Sjmallett power-on/boot code. */ 757215976Sjmallett uint64_t reserved_0_2 : 3; 758215976Sjmallett#else 759215976Sjmallett uint64_t reserved_0_2 : 3; 760215976Sjmallett uint64_t ibase : 37; 761215976Sjmallett uint64_t isize : 20; 762215976Sjmallett uint64_t reserved_60_63 : 4; 763215976Sjmallett#endif 764215976Sjmallett } s; 765215976Sjmallett struct cvmx_mixx_iring1_cn52xx 766215976Sjmallett { 767215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 768215976Sjmallett uint64_t reserved_60_63 : 4; 769215976Sjmallett uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B 770215976Sjmallett words). The ring can be as large as 1M entries. 771215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 772215976Sjmallett (when IDBELL/IRCNT=0). */ 773215976Sjmallett uint64_t reserved_36_39 : 4; 774215976Sjmallett uint64_t ibase : 33; /**< Represents the 8B-aligned base address of the first 775215976Sjmallett Inbound Ring entry in system memory. 776215976Sjmallett NOTE: SW MUST ONLY write to this register during 777215976Sjmallett power-on/boot code. */ 778215976Sjmallett uint64_t reserved_0_2 : 3; 779215976Sjmallett#else 780215976Sjmallett uint64_t reserved_0_2 : 3; 781215976Sjmallett uint64_t ibase : 33; 782215976Sjmallett uint64_t reserved_36_39 : 4; 783215976Sjmallett uint64_t isize : 20; 784215976Sjmallett uint64_t reserved_60_63 : 4; 785215976Sjmallett#endif 786215976Sjmallett } cn52xx; 787215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn52xxp1; 788215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn56xx; 789215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn56xxp1; 790215976Sjmallett struct cvmx_mixx_iring1_s cn63xx; 791215976Sjmallett struct cvmx_mixx_iring1_s cn63xxp1; 792215976Sjmallett}; 793215976Sjmalletttypedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t; 794215976Sjmallett 795215976Sjmallett/** 796215976Sjmallett * cvmx_mix#_iring2 797215976Sjmallett * 798215976Sjmallett * MIX_IRING2 = MIX Inbound Ring Register \#2 799215976Sjmallett * 800215976Sjmallett * Description: 801215976Sjmallett * NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO. 802215976Sjmallett * To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO. 803215976Sjmallett */ 804215976Sjmallettunion cvmx_mixx_iring2 805215976Sjmallett{ 806215976Sjmallett uint64_t u64; 807215976Sjmallett struct cvmx_mixx_iring2_s 808215976Sjmallett { 809215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 810215976Sjmallett uint64_t reserved_52_63 : 12; 811215976Sjmallett uint64_t itlptr : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring 812215976Sjmallett Entry that the HW will process next. After the HW 813215976Sjmallett completes receiving an inbound packet, it increments 814215976Sjmallett the I-Ring Tail Pointer. [NOTE: The I-Ring Tail 815215976Sjmallett Pointer HW increment is always modulo ISIZE. 816215976Sjmallett NOTE: This field is 'read-only' to SW. */ 817215976Sjmallett uint64_t reserved_20_31 : 12; 818215976Sjmallett uint64_t idbell : 20; /**< Represents the cumulative total of pending 819215976Sjmallett Inbound Ring Buffer Entries. Each I-Ring 820215976Sjmallett Buffer Entry contains 1) an L2/DRAM byte pointer 821215976Sjmallett along with a 2) a Byte Length. 822215976Sjmallett After SW inserts a new entry into the I-Ring Buffer, 823215976Sjmallett it "rings the doorbell for the inbound ring". When 824215976Sjmallett the MIX HW receives the doorbell ring, it advances 825215976Sjmallett the doorbell count for the I-Ring. 826215976Sjmallett SW must never cause the doorbell count for the 827215976Sjmallett I-Ring to exceed the size of the I-ring(ISIZE). 828215976Sjmallett A read of the CSR indicates the current doorbell 829215976Sjmallett count. */ 830215976Sjmallett#else 831215976Sjmallett uint64_t idbell : 20; 832215976Sjmallett uint64_t reserved_20_31 : 12; 833215976Sjmallett uint64_t itlptr : 20; 834215976Sjmallett uint64_t reserved_52_63 : 12; 835215976Sjmallett#endif 836215976Sjmallett } s; 837215976Sjmallett struct cvmx_mixx_iring2_s cn52xx; 838215976Sjmallett struct cvmx_mixx_iring2_s cn52xxp1; 839215976Sjmallett struct cvmx_mixx_iring2_s cn56xx; 840215976Sjmallett struct cvmx_mixx_iring2_s cn56xxp1; 841215976Sjmallett struct cvmx_mixx_iring2_s cn63xx; 842215976Sjmallett struct cvmx_mixx_iring2_s cn63xxp1; 843215976Sjmallett}; 844215976Sjmalletttypedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t; 845215976Sjmallett 846215976Sjmallett/** 847215976Sjmallett * cvmx_mix#_isr 848215976Sjmallett * 849215976Sjmallett * MIX_ISR = MIX Interrupt/Status Register 850215976Sjmallett * 851215976Sjmallett * Description: 852215976Sjmallett * NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO. 853215976Sjmallett * To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO. 854215976Sjmallett */ 855215976Sjmallettunion cvmx_mixx_isr 856215976Sjmallett{ 857215976Sjmallett uint64_t u64; 858215976Sjmallett struct cvmx_mixx_isr_s 859215976Sjmallett { 860215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 861215976Sjmallett uint64_t reserved_8_63 : 56; 862215976Sjmallett uint64_t ts : 1; /**< TimeStamp Interrupt 863215976Sjmallett When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT]) 864215976Sjmallett is greater than the TimeStamp Interrupt Threshold 865215976Sjmallett (MIX_CTL[TS_THRESH]) value this interrupt bit is set. 866215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 867215976Sjmallett and this local interrupt mask bit is set, than an 868215976Sjmallett interrupt is reported for an Outbound Ring with Timestamp 869215976Sjmallett event (see: MIX_INTENA[TSENA]). */ 870215976Sjmallett uint64_t orun : 1; /**< ORCNT UnderFlow Detected 871215976Sjmallett If SW writes a larger value than what is currently 872215976Sjmallett in the MIX_ORCNT[ORCNT], then HW will report the 873215976Sjmallett underflow condition. 874215976Sjmallett NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero. 875215976Sjmallett NOTE: If an ORUN underflow condition is detected, 876215976Sjmallett the integrity of the MIX/AGL HW state has 877215976Sjmallett been compromised. To recover, SW must issue a 878215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 879215976Sjmallett uint64_t irun : 1; /**< IRCNT UnderFlow Detected 880215976Sjmallett If SW writes a larger value than what is currently 881215976Sjmallett in the MIX_IRCNT[IRCNT], then HW will report the 882215976Sjmallett underflow condition. 883215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero. 884215976Sjmallett NOTE: If an IRUN underflow condition is detected, 885215976Sjmallett the integrity of the MIX/AGL HW state has 886215976Sjmallett been compromised. To recover, SW must issue a 887215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 888215976Sjmallett uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full 889215976Sjmallett If this does occur, the DATA_DRP is set and the 890215976Sjmallett CIU_INTx_SUM0,4[MII] bits are set. 891215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 892215976Sjmallett and the local interrupt mask bit(DATA_DRPENA) is set, than an 893215976Sjmallett interrupt is reported for this event. */ 894215976Sjmallett uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded 895215976Sjmallett When the pending \#inbound packets in system 896215976Sjmallett memory(IRCNT) has exceeded a programmable threshold 897215976Sjmallett (IRHWM), then this bit is set. If this does occur, 898215976Sjmallett the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 899215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 900215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 901215976Sjmallett and the local interrupt mask bit(ITHENA) is set, than an 902215976Sjmallett interrupt is reported for this event. */ 903215976Sjmallett uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded 904215976Sjmallett When the pending \#outbound packets in system 905215976Sjmallett memory(ORCNT) has exceeded a programmable threshold 906215976Sjmallett (ORHWM), then this bit is set. If this does occur, 907215976Sjmallett the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 908215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 909215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 910215976Sjmallett and the local interrupt mask bit(OTHENA) is set, than an 911215976Sjmallett interrupt is reported for this event. */ 912215976Sjmallett uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 913215976Sjmallett If SW attempts to write to the MIX_IRING2[IDBELL] 914215976Sjmallett with a value greater than the remaining \#of 915215976Sjmallett I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then 916215976Sjmallett the following occurs: 917215976Sjmallett 1) The MIX_IRING2[IDBELL] write is IGNORED 918215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 919215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 920215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 921215976Sjmallett and the local interrupt mask bit(IVFENA) is set, than an 922215976Sjmallett interrupt is reported for this event. 923215976Sjmallett SW should keep track of the \#I-Ring Entries in use 924215976Sjmallett (ie: cumulative \# of IDBELL writes), and ensure that 925215976Sjmallett future IDBELL writes don't exceed the size of the 926215976Sjmallett I-Ring Buffer (MIX_IRING2[ISIZE]). 927215976Sjmallett SW must reclaim I-Ring Entries by keeping track of the 928215976Sjmallett \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT]. 929215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] register represents the 930215976Sjmallett total \#packets(not IRing Entries) and SW must further 931215976Sjmallett keep track of the \# of I-Ring Entries associated with 932215976Sjmallett each packet as they are processed. 933215976Sjmallett NOTE: There is no recovery from an IDBLOVF Interrupt. 934215976Sjmallett If it occurs, it's an indication that SW has 935215976Sjmallett overwritten the I-Ring buffer, and the only recourse 936215976Sjmallett is a HW reset. */ 937215976Sjmallett uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected 938215976Sjmallett If SW attempts to write to the MIX_ORING2[ODBELL] 939215976Sjmallett with a value greater than the remaining \#of 940215976Sjmallett O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then 941215976Sjmallett the following occurs: 942215976Sjmallett 1) The MIX_ORING2[ODBELL] write is IGNORED 943215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 944215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 945215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 946215976Sjmallett and the local interrupt mask bit(OVFENA) is set, than an 947215976Sjmallett interrupt is reported for this event. 948215976Sjmallett SW should keep track of the \#I-Ring Entries in use 949215976Sjmallett (ie: cumulative \# of ODBELL writes), and ensure that 950215976Sjmallett future ODBELL writes don't exceed the size of the 951215976Sjmallett O-Ring Buffer (MIX_ORING2[OSIZE]). 952215976Sjmallett SW must reclaim O-Ring Entries by writing to the 953215976Sjmallett MIX_ORCNT[ORCNT]. . 954215976Sjmallett NOTE: There is no recovery from an ODBLOVF Interrupt. 955215976Sjmallett If it occurs, it's an indication that SW has 956215976Sjmallett overwritten the O-Ring buffer, and the only recourse 957215976Sjmallett is a HW reset. */ 958215976Sjmallett#else 959215976Sjmallett uint64_t odblovf : 1; 960215976Sjmallett uint64_t idblovf : 1; 961215976Sjmallett uint64_t orthresh : 1; 962215976Sjmallett uint64_t irthresh : 1; 963215976Sjmallett uint64_t data_drp : 1; 964215976Sjmallett uint64_t irun : 1; 965215976Sjmallett uint64_t orun : 1; 966215976Sjmallett uint64_t ts : 1; 967215976Sjmallett uint64_t reserved_8_63 : 56; 968215976Sjmallett#endif 969215976Sjmallett } s; 970215976Sjmallett struct cvmx_mixx_isr_cn52xx 971215976Sjmallett { 972215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 973215976Sjmallett uint64_t reserved_7_63 : 57; 974215976Sjmallett uint64_t orun : 1; /**< ORCNT UnderFlow Detected 975215976Sjmallett If SW writes a larger value than what is currently 976215976Sjmallett in the MIX_ORCNT[ORCNT], then HW will report the 977215976Sjmallett underflow condition. 978215976Sjmallett NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero. 979215976Sjmallett NOTE: If an ORUN underflow condition is detected, 980215976Sjmallett the integrity of the MIX/AGL HW state has 981215976Sjmallett been compromised. To recover, SW must issue a 982215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 983215976Sjmallett uint64_t irun : 1; /**< IRCNT UnderFlow Detected 984215976Sjmallett If SW writes a larger value than what is currently 985215976Sjmallett in the MIX_IRCNT[IRCNT], then HW will report the 986215976Sjmallett underflow condition. 987215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero. 988215976Sjmallett NOTE: If an IRUN underflow condition is detected, 989215976Sjmallett the integrity of the MIX/AGL HW state has 990215976Sjmallett been compromised. To recover, SW must issue a 991215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 992215976Sjmallett uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full 993215976Sjmallett If this does occur, the DATA_DRP is set and the 994215976Sjmallett CIU_INTx_SUM0,4[MII] bits are set. 995215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 996215976Sjmallett and the local interrupt mask bit(DATA_DRPENA) is set, than an 997215976Sjmallett interrupt is reported for this event. */ 998215976Sjmallett uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded 999215976Sjmallett When the pending \#inbound packets in system 1000215976Sjmallett memory(IRCNT) has exceeded a programmable threshold 1001215976Sjmallett (IRHWM), then this bit is set. If this does occur, 1002215976Sjmallett the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 1003215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 1004215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1005215976Sjmallett and the local interrupt mask bit(ITHENA) is set, than an 1006215976Sjmallett interrupt is reported for this event. */ 1007215976Sjmallett uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded 1008215976Sjmallett When the pending \#outbound packets in system 1009215976Sjmallett memory(ORCNT) has exceeded a programmable threshold 1010215976Sjmallett (ORHWM), then this bit is set. If this does occur, 1011215976Sjmallett the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 1012215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 1013215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1014215976Sjmallett and the local interrupt mask bit(OTHENA) is set, than an 1015215976Sjmallett interrupt is reported for this event. */ 1016215976Sjmallett uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 1017215976Sjmallett If SW attempts to write to the MIX_IRING2[IDBELL] 1018215976Sjmallett with a value greater than the remaining \#of 1019215976Sjmallett I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then 1020215976Sjmallett the following occurs: 1021215976Sjmallett 1) The MIX_IRING2[IDBELL] write is IGNORED 1022215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 1023215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 1024215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1025215976Sjmallett and the local interrupt mask bit(IVFENA) is set, than an 1026215976Sjmallett interrupt is reported for this event. 1027215976Sjmallett SW should keep track of the \#I-Ring Entries in use 1028215976Sjmallett (ie: cumulative \# of IDBELL writes), and ensure that 1029215976Sjmallett future IDBELL writes don't exceed the size of the 1030215976Sjmallett I-Ring Buffer (MIX_IRING2[ISIZE]). 1031215976Sjmallett SW must reclaim I-Ring Entries by keeping track of the 1032215976Sjmallett \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT]. 1033215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] register represents the 1034215976Sjmallett total \#packets(not IRing Entries) and SW must further 1035215976Sjmallett keep track of the \# of I-Ring Entries associated with 1036215976Sjmallett each packet as they are processed. 1037215976Sjmallett NOTE: There is no recovery from an IDBLOVF Interrupt. 1038215976Sjmallett If it occurs, it's an indication that SW has 1039215976Sjmallett overwritten the I-Ring buffer, and the only recourse 1040215976Sjmallett is a HW reset. */ 1041215976Sjmallett uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected 1042215976Sjmallett If SW attempts to write to the MIX_ORING2[ODBELL] 1043215976Sjmallett with a value greater than the remaining \#of 1044215976Sjmallett O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then 1045215976Sjmallett the following occurs: 1046215976Sjmallett 1) The MIX_ORING2[ODBELL] write is IGNORED 1047215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 1048215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 1049215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1050215976Sjmallett and the local interrupt mask bit(OVFENA) is set, than an 1051215976Sjmallett interrupt is reported for this event. 1052215976Sjmallett SW should keep track of the \#I-Ring Entries in use 1053215976Sjmallett (ie: cumulative \# of ODBELL writes), and ensure that 1054215976Sjmallett future ODBELL writes don't exceed the size of the 1055215976Sjmallett O-Ring Buffer (MIX_ORING2[OSIZE]). 1056215976Sjmallett SW must reclaim O-Ring Entries by writing to the 1057215976Sjmallett MIX_ORCNT[ORCNT]. . 1058215976Sjmallett NOTE: There is no recovery from an ODBLOVF Interrupt. 1059215976Sjmallett If it occurs, it's an indication that SW has 1060215976Sjmallett overwritten the O-Ring buffer, and the only recourse 1061215976Sjmallett is a HW reset. */ 1062215976Sjmallett#else 1063215976Sjmallett uint64_t odblovf : 1; 1064215976Sjmallett uint64_t idblovf : 1; 1065215976Sjmallett uint64_t orthresh : 1; 1066215976Sjmallett uint64_t irthresh : 1; 1067215976Sjmallett uint64_t data_drp : 1; 1068215976Sjmallett uint64_t irun : 1; 1069215976Sjmallett uint64_t orun : 1; 1070215976Sjmallett uint64_t reserved_7_63 : 57; 1071215976Sjmallett#endif 1072215976Sjmallett } cn52xx; 1073215976Sjmallett struct cvmx_mixx_isr_cn52xx cn52xxp1; 1074215976Sjmallett struct cvmx_mixx_isr_cn52xx cn56xx; 1075215976Sjmallett struct cvmx_mixx_isr_cn52xx cn56xxp1; 1076215976Sjmallett struct cvmx_mixx_isr_s cn63xx; 1077215976Sjmallett struct cvmx_mixx_isr_s cn63xxp1; 1078215976Sjmallett}; 1079215976Sjmalletttypedef union cvmx_mixx_isr cvmx_mixx_isr_t; 1080215976Sjmallett 1081215976Sjmallett/** 1082215976Sjmallett * cvmx_mix#_orcnt 1083215976Sjmallett * 1084215976Sjmallett * MIX_ORCNT = MIX O-Ring Packets Sent Counter 1085215976Sjmallett * 1086215976Sjmallett * Description: 1087215976Sjmallett * NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO. 1088215976Sjmallett * To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO. 1089215976Sjmallett */ 1090215976Sjmallettunion cvmx_mixx_orcnt 1091215976Sjmallett{ 1092215976Sjmallett uint64_t u64; 1093215976Sjmallett struct cvmx_mixx_orcnt_s 1094215976Sjmallett { 1095215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1096215976Sjmallett uint64_t reserved_20_63 : 44; 1097215976Sjmallett uint64_t orcnt : 20; /**< Pending \# of O-Ring Packets. 1098215976Sjmallett Whenever HW removes a packet from the O-Ring, it 1099215976Sjmallett increments the ORCNT (to indicate to SW the \# of 1100215976Sjmallett Output packets in system memory that can be reclaimed). 1101215976Sjmallett Reads of ORCNT return the current count. 1102215976Sjmallett Writes of ORCNT decrement the count by the value 1103215976Sjmallett written. 1104215976Sjmallett This register is used to generate interrupts to alert 1105215976Sjmallett SW of pending outbound MIX packets that have been 1106215976Sjmallett removed from system memory. (see MIX_ISR[ORTHRESH] 1107215976Sjmallett description for more details). 1108215976Sjmallett NOTE: For outbound packets, the \# of O-Ring Packets 1109215976Sjmallett is equal to the \# of O-Ring Entries. */ 1110215976Sjmallett#else 1111215976Sjmallett uint64_t orcnt : 20; 1112215976Sjmallett uint64_t reserved_20_63 : 44; 1113215976Sjmallett#endif 1114215976Sjmallett } s; 1115215976Sjmallett struct cvmx_mixx_orcnt_s cn52xx; 1116215976Sjmallett struct cvmx_mixx_orcnt_s cn52xxp1; 1117215976Sjmallett struct cvmx_mixx_orcnt_s cn56xx; 1118215976Sjmallett struct cvmx_mixx_orcnt_s cn56xxp1; 1119215976Sjmallett struct cvmx_mixx_orcnt_s cn63xx; 1120215976Sjmallett struct cvmx_mixx_orcnt_s cn63xxp1; 1121215976Sjmallett}; 1122215976Sjmalletttypedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t; 1123215976Sjmallett 1124215976Sjmallett/** 1125215976Sjmallett * cvmx_mix#_orhwm 1126215976Sjmallett * 1127215976Sjmallett * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register 1128215976Sjmallett * 1129215976Sjmallett * Description: 1130215976Sjmallett * NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO. 1131215976Sjmallett * To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO. 1132215976Sjmallett */ 1133215976Sjmallettunion cvmx_mixx_orhwm 1134215976Sjmallett{ 1135215976Sjmallett uint64_t u64; 1136215976Sjmallett struct cvmx_mixx_orhwm_s 1137215976Sjmallett { 1138215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1139215976Sjmallett uint64_t reserved_20_63 : 44; 1140215976Sjmallett uint64_t orhwm : 20; /**< O-Ring Entry High Water Mark Threshold. 1141215976Sjmallett Used to determine when the \# of Outbound packets 1142215976Sjmallett in system memory that can be reclaimed 1143215976Sjmallett (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold. 1144215976Sjmallett NOTE: The power-on value of the CIU_INTx_EN*[MII] 1145215976Sjmallett interrupt enable bits is zero and must be enabled 1146215976Sjmallett to allow interrupts to be reported. */ 1147215976Sjmallett#else 1148215976Sjmallett uint64_t orhwm : 20; 1149215976Sjmallett uint64_t reserved_20_63 : 44; 1150215976Sjmallett#endif 1151215976Sjmallett } s; 1152215976Sjmallett struct cvmx_mixx_orhwm_s cn52xx; 1153215976Sjmallett struct cvmx_mixx_orhwm_s cn52xxp1; 1154215976Sjmallett struct cvmx_mixx_orhwm_s cn56xx; 1155215976Sjmallett struct cvmx_mixx_orhwm_s cn56xxp1; 1156215976Sjmallett struct cvmx_mixx_orhwm_s cn63xx; 1157215976Sjmallett struct cvmx_mixx_orhwm_s cn63xxp1; 1158215976Sjmallett}; 1159215976Sjmalletttypedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t; 1160215976Sjmallett 1161215976Sjmallett/** 1162215976Sjmallett * cvmx_mix#_oring1 1163215976Sjmallett * 1164215976Sjmallett * MIX_ORING1 = MIX Outbound Ring Register \#1 1165215976Sjmallett * 1166215976Sjmallett * Description: 1167215976Sjmallett * NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO. 1168215976Sjmallett * To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO. 1169215976Sjmallett */ 1170215976Sjmallettunion cvmx_mixx_oring1 1171215976Sjmallett{ 1172215976Sjmallett uint64_t u64; 1173215976Sjmallett struct cvmx_mixx_oring1_s 1174215976Sjmallett { 1175215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1176215976Sjmallett uint64_t reserved_60_63 : 4; 1177215976Sjmallett uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B 1178215976Sjmallett words). The ring can be as large as 1M entries. 1179215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 1180215976Sjmallett (when ODBELL/ORCNT=0). */ 1181215976Sjmallett uint64_t obase : 37; /**< Represents the 8B-aligned base address of the first 1182215976Sjmallett Outbound Ring(O-Ring) Entry in system memory. 1183215976Sjmallett NOTE: SW MUST ONLY write to this register during 1184215976Sjmallett power-on/boot code. */ 1185215976Sjmallett uint64_t reserved_0_2 : 3; 1186215976Sjmallett#else 1187215976Sjmallett uint64_t reserved_0_2 : 3; 1188215976Sjmallett uint64_t obase : 37; 1189215976Sjmallett uint64_t osize : 20; 1190215976Sjmallett uint64_t reserved_60_63 : 4; 1191215976Sjmallett#endif 1192215976Sjmallett } s; 1193215976Sjmallett struct cvmx_mixx_oring1_cn52xx 1194215976Sjmallett { 1195215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1196215976Sjmallett uint64_t reserved_60_63 : 4; 1197215976Sjmallett uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B 1198215976Sjmallett words). The ring can be as large as 1M entries. 1199215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 1200215976Sjmallett (when ODBELL/ORCNT=0). */ 1201215976Sjmallett uint64_t reserved_36_39 : 4; 1202215976Sjmallett uint64_t obase : 33; /**< Represents the 8B-aligned base address of the first 1203215976Sjmallett Outbound Ring(O-Ring) Entry in system memory. 1204215976Sjmallett NOTE: SW MUST ONLY write to this register during 1205215976Sjmallett power-on/boot code. */ 1206215976Sjmallett uint64_t reserved_0_2 : 3; 1207215976Sjmallett#else 1208215976Sjmallett uint64_t reserved_0_2 : 3; 1209215976Sjmallett uint64_t obase : 33; 1210215976Sjmallett uint64_t reserved_36_39 : 4; 1211215976Sjmallett uint64_t osize : 20; 1212215976Sjmallett uint64_t reserved_60_63 : 4; 1213215976Sjmallett#endif 1214215976Sjmallett } cn52xx; 1215215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn52xxp1; 1216215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn56xx; 1217215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn56xxp1; 1218215976Sjmallett struct cvmx_mixx_oring1_s cn63xx; 1219215976Sjmallett struct cvmx_mixx_oring1_s cn63xxp1; 1220215976Sjmallett}; 1221215976Sjmalletttypedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t; 1222215976Sjmallett 1223215976Sjmallett/** 1224215976Sjmallett * cvmx_mix#_oring2 1225215976Sjmallett * 1226215976Sjmallett * MIX_ORING2 = MIX Outbound Ring Register \#2 1227215976Sjmallett * 1228215976Sjmallett * Description: 1229215976Sjmallett * NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO. 1230215976Sjmallett * To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO. 1231215976Sjmallett */ 1232215976Sjmallettunion cvmx_mixx_oring2 1233215976Sjmallett{ 1234215976Sjmallett uint64_t u64; 1235215976Sjmallett struct cvmx_mixx_oring2_s 1236215976Sjmallett { 1237215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1238215976Sjmallett uint64_t reserved_52_63 : 12; 1239215976Sjmallett uint64_t otlptr : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring 1240215976Sjmallett Entry that the HW will process next. After the HW 1241215976Sjmallett completes sending an outbound packet, it increments 1242215976Sjmallett the O-Ring Tail Pointer. [NOTE: The O-Ring Tail 1243215976Sjmallett Pointer HW increment is always modulo 1244215976Sjmallett MIX_ORING2[OSIZE]. 1245215976Sjmallett NOTE: This field is 'read-only' to SW. */ 1246215976Sjmallett uint64_t reserved_20_31 : 12; 1247215976Sjmallett uint64_t odbell : 20; /**< Represents the cumulative total of pending 1248215976Sjmallett Outbound Ring(O-Ring) Buffer Entries. Each O-Ring 1249215976Sjmallett Buffer Entry contains 1) an L2/DRAM byte pointer 1250215976Sjmallett along with a 2) a Byte Length. 1251215976Sjmallett After SW inserts new entries into the O-Ring Buffer, 1252215976Sjmallett it "rings the doorbell with the count of the newly 1253215976Sjmallett inserted entries". When the MIX HW receives the 1254215976Sjmallett doorbell ring, it increments the current doorbell 1255215976Sjmallett count by the CSR write value. 1256215976Sjmallett SW must never cause the doorbell count for the 1257215976Sjmallett O-Ring to exceed the size of the ring(OSIZE). 1258215976Sjmallett A read of the CSR indicates the current doorbell 1259215976Sjmallett count. */ 1260215976Sjmallett#else 1261215976Sjmallett uint64_t odbell : 20; 1262215976Sjmallett uint64_t reserved_20_31 : 12; 1263215976Sjmallett uint64_t otlptr : 20; 1264215976Sjmallett uint64_t reserved_52_63 : 12; 1265215976Sjmallett#endif 1266215976Sjmallett } s; 1267215976Sjmallett struct cvmx_mixx_oring2_s cn52xx; 1268215976Sjmallett struct cvmx_mixx_oring2_s cn52xxp1; 1269215976Sjmallett struct cvmx_mixx_oring2_s cn56xx; 1270215976Sjmallett struct cvmx_mixx_oring2_s cn56xxp1; 1271215976Sjmallett struct cvmx_mixx_oring2_s cn63xx; 1272215976Sjmallett struct cvmx_mixx_oring2_s cn63xxp1; 1273215976Sjmallett}; 1274215976Sjmalletttypedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t; 1275215976Sjmallett 1276215976Sjmallett/** 1277215976Sjmallett * cvmx_mix#_remcnt 1278215976Sjmallett * 1279215976Sjmallett * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only) 1280215976Sjmallett * 1281215976Sjmallett * Description: 1282215976Sjmallett * NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO. 1283215976Sjmallett */ 1284215976Sjmallettunion cvmx_mixx_remcnt 1285215976Sjmallett{ 1286215976Sjmallett uint64_t u64; 1287215976Sjmallett struct cvmx_mixx_remcnt_s 1288215976Sjmallett { 1289215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1290215976Sjmallett uint64_t reserved_52_63 : 12; 1291215976Sjmallett uint64_t iremcnt : 20; /**< Remaining I-Ring Buffer Count 1292215976Sjmallett Reflects the \# of unused/remaining I-Ring Entries 1293215976Sjmallett that HW currently detects in the I-Ring Buffer. 1294215976Sjmallett HW uses this value to detect I-Ring Doorbell overflows. 1295215976Sjmallett (see: MIX_ISR[IDBLOVF]) 1296215976Sjmallett When SW writes the MIX_IRING1[ISIZE], the IREMCNT 1297215976Sjmallett is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only 1298215976Sjmallett be written at power-on, when it's known that there are 1299215976Sjmallett no I-Ring Entries currently in use by HW). 1300215976Sjmallett When SW writes to the IDBELL register, the IREMCNT 1301215976Sjmallett is decremented by the CSR write value. 1302215976Sjmallett When HW issues an IRing Write Request(onto NCB Bus), 1303215976Sjmallett the IREMCNT is incremented by 1. */ 1304215976Sjmallett uint64_t reserved_20_31 : 12; 1305215976Sjmallett uint64_t oremcnt : 20; /**< Remaining O-Ring Buffer Count 1306215976Sjmallett Reflects the \# of unused/remaining O-Ring Entries 1307215976Sjmallett that HW currently detects in the O-Ring Buffer. 1308215976Sjmallett HW uses this value to detect O-Ring Doorbell overflows. 1309215976Sjmallett (see: MIX_ISR[ODBLOVF]) 1310215976Sjmallett When SW writes the MIX_IRING1[OSIZE], the OREMCNT 1311215976Sjmallett is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only 1312215976Sjmallett be written at power-on, when it's known that there are 1313215976Sjmallett no O-Ring Entries currently in use by HW). 1314215976Sjmallett When SW writes to the ODBELL register, the OREMCNT 1315215976Sjmallett is decremented by the CSR write value. 1316215976Sjmallett When SW writes to MIX_[OREMCNT], the OREMCNT is decremented 1317215976Sjmallett by the CSR write value. */ 1318215976Sjmallett#else 1319215976Sjmallett uint64_t oremcnt : 20; 1320215976Sjmallett uint64_t reserved_20_31 : 12; 1321215976Sjmallett uint64_t iremcnt : 20; 1322215976Sjmallett uint64_t reserved_52_63 : 12; 1323215976Sjmallett#endif 1324215976Sjmallett } s; 1325215976Sjmallett struct cvmx_mixx_remcnt_s cn52xx; 1326215976Sjmallett struct cvmx_mixx_remcnt_s cn52xxp1; 1327215976Sjmallett struct cvmx_mixx_remcnt_s cn56xx; 1328215976Sjmallett struct cvmx_mixx_remcnt_s cn56xxp1; 1329215976Sjmallett struct cvmx_mixx_remcnt_s cn63xx; 1330215976Sjmallett struct cvmx_mixx_remcnt_s cn63xxp1; 1331215976Sjmallett}; 1332215976Sjmalletttypedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t; 1333215976Sjmallett 1334215976Sjmallett/** 1335215976Sjmallett * cvmx_mix#_tsctl 1336215976Sjmallett * 1337215976Sjmallett * MIX_TSCTL = MIX TimeStamp Control Register 1338215976Sjmallett * 1339215976Sjmallett * Description: 1340215976Sjmallett * NOTE: To read the MIX_TSCTL register, a device would issue an IOBLD64 directed at the MIO. 1341215976Sjmallett * 1342215976Sjmallett * Notes: 1343215976Sjmallett * SW can read the MIX_TSCTL register to determine the \#pending timestamp interrupts(TSCNT) 1344215976Sjmallett * as well as the \#outstanding timestamp requests in flight(TSTOT), as well as the \#of available 1345215976Sjmallett * timestamp entries (TSAVL) in the timestamp fifo. 1346215976Sjmallett * A write to the MIX_TSCTL register will advance the MIX*_TSTAMP fifo head ptr by 1, and 1347215976Sjmallett * also decrements the MIX*_TSCTL[TSCNT] and MIX*_TSCTL[TSTOT] pending count(s) by 1. 1348215976Sjmallett * For example, if SW reads MIX*_TSCTL[TSCNT]=2 (2 pending timestamp interrupts), it would immediately 1349215976Sjmallett * issue this sequence: 1350215976Sjmallett * 1) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write 1351215976Sjmallett * [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1] 1352215976Sjmallett * 2) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write 1353215976Sjmallett * [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1] 1354215976Sjmallett * 1355215976Sjmallett * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored. 1356215976Sjmallett */ 1357215976Sjmallettunion cvmx_mixx_tsctl 1358215976Sjmallett{ 1359215976Sjmallett uint64_t u64; 1360215976Sjmallett struct cvmx_mixx_tsctl_s 1361215976Sjmallett { 1362215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1363215976Sjmallett uint64_t reserved_21_63 : 43; 1364215976Sjmallett uint64_t tsavl : 5; /**< # of MIX TimeStamp Entries Available for use 1365215976Sjmallett For o63: TSAVL MAX=4 (implementation 1366215976Sjmallett depth of timestamp fifo) 1367215976Sjmallett TSAVL = [IMPLEMENTATION_DEPTH=4(MAX) - TSCNT] */ 1368215976Sjmallett uint64_t reserved_13_15 : 3; 1369215976Sjmallett uint64_t tstot : 5; /**< # of pending MIX TimeStamp Requests in-flight 1370215976Sjmallett For o63: TSTOT must never exceed MAX=4 (implementation 1371215976Sjmallett depth of timestamp fifo) */ 1372215976Sjmallett uint64_t reserved_5_7 : 3; 1373215976Sjmallett uint64_t tscnt : 5; /**< # of pending MIX TimeStamp Interrupts 1374215976Sjmallett For o63: TSCNT must never exceed MAX=4 (implementation 1375215976Sjmallett depth of timestamp fifo) */ 1376215976Sjmallett#else 1377215976Sjmallett uint64_t tscnt : 5; 1378215976Sjmallett uint64_t reserved_5_7 : 3; 1379215976Sjmallett uint64_t tstot : 5; 1380215976Sjmallett uint64_t reserved_13_15 : 3; 1381215976Sjmallett uint64_t tsavl : 5; 1382215976Sjmallett uint64_t reserved_21_63 : 43; 1383215976Sjmallett#endif 1384215976Sjmallett } s; 1385215976Sjmallett struct cvmx_mixx_tsctl_s cn63xx; 1386215976Sjmallett struct cvmx_mixx_tsctl_s cn63xxp1; 1387215976Sjmallett}; 1388215976Sjmalletttypedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t; 1389215976Sjmallett 1390215976Sjmallett/** 1391215976Sjmallett * cvmx_mix#_tstamp 1392215976Sjmallett * 1393215976Sjmallett * MIX_TSTAMP = MIX TimeStamp Register 1394215976Sjmallett * 1395215976Sjmallett * Description: 1396215976Sjmallett * NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO. 1397215976Sjmallett */ 1398215976Sjmallettunion cvmx_mixx_tstamp 1399215976Sjmallett{ 1400215976Sjmallett uint64_t u64; 1401215976Sjmallett struct cvmx_mixx_tstamp_s 1402215976Sjmallett { 1403215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1404215976Sjmallett uint64_t tstamp : 64; /**< MIX TimeStamp Value 1405215976Sjmallett When SW sets up an ORING Entry with [47]=1(TSTAMP), 1406215976Sjmallett The packet is tagged with a specal SOP w/TSTAMP flag 1407215976Sjmallett as it is sent to the AGL. 1408215976Sjmallett Later the AGL will send "sample" strobe(s) to capture 1409215976Sjmallett a global 64bit timestamp value followed by a "commit" 1410215976Sjmallett strobe which writes the last sampled value into the 1411215976Sjmallett outbound Timestamp fifo (max depth=4) and increments 1412215976Sjmallett the MIX_TSCTL[TSCNT] register to indicate the total 1413215976Sjmallett \#of pending Timestamp interrupts. 1414215976Sjmallett If the \#pending Timestamp interrupts (MIX_TSCTL[TSCNT]) 1415215976Sjmallett is greater than the MIX_CTL[TS_THRESH] value, then 1416215976Sjmallett a programmable interrupt is also triggered (see: 1417215976Sjmallett MIX_ISR[TS] MIX_INTENA[TSENA]). 1418215976Sjmallett SW will then read the MIX*_TSTAMP[TSTAMP] 1419215976Sjmallett register value, and MUST THEN write the MIX_TSCTL 1420215976Sjmallett register, which will decrement MIX_TSCTL[TSCNT] register, 1421215976Sjmallett to indicate that a single timestamp interrupt has 1422215976Sjmallett been serviced. 1423215976Sjmallett NOTE: The MIO-MIX HW tracks upto MAX=4 outstanding 1424215976Sjmallett timestamped outbound packets at a time. All subsequent 1425215976Sjmallett ORING Entries w/SOP-TSTAMP will be stalled until 1426215976Sjmallett SW can service the 4 outstanding interrupts. 1427215976Sjmallett SW can read the MIX_TSCTL register to determine the 1428215976Sjmallett \#pending timestamp interrupts(TSCNT) as well as the 1429215976Sjmallett \#outstanding timestamp requests in flight(TSTOT), as 1430215976Sjmallett well as the \#of available timestamp entries (TSAVL). 1431215976Sjmallett SW NOTE: A MIX_TSTAMP read when MIX_TSCTL[TSCNT]=0, will 1432215976Sjmallett result in a return value of all zeroes. SW should only 1433215976Sjmallett read this register when MIX_ISR[TS]=1 (or when 1434215976Sjmallett MIX_TSCTL[TSCNT] != 0) to retrieve the timestamp value 1435215976Sjmallett recorded by HW. If SW reads the TSTAMP when HW has not 1436215976Sjmallett recorded a valid timestamp, then an all zeroes value is 1437215976Sjmallett returned. */ 1438215976Sjmallett#else 1439215976Sjmallett uint64_t tstamp : 64; 1440215976Sjmallett#endif 1441215976Sjmallett } s; 1442215976Sjmallett struct cvmx_mixx_tstamp_s cn63xx; 1443215976Sjmallett struct cvmx_mixx_tstamp_s cn63xxp1; 1444215976Sjmallett}; 1445215976Sjmalletttypedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t; 1446215976Sjmallett 1447215976Sjmallett#endif 1448