1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-l2d-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon l2d. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_L2D_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_L2D_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_L2D_BST0_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 60215976Sjmallett cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000780ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_L2D_BST1_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 71215976Sjmallett cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000788ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_L2D_BST2_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 82215976Sjmallett cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000790ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_L2D_BST3_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 93215976Sjmallett cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000798ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_L2D_ERR_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 104215976Sjmallett cvmx_warn("CVMX_L2D_ERR not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000010ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_L2D_FADR_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 115215976Sjmallett cvmx_warn("CVMX_L2D_FADR not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000018ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_L2D_FSYN0_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 126215976Sjmallett cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000020ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_L2D_FSYN1_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 137215976Sjmallett cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000028ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS0_FUNC(void) 146215976Sjmallett{ 147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 148215976Sjmallett cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007A0ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS1_FUNC(void) 157215976Sjmallett{ 158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 159215976Sjmallett cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007A8ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS2_FUNC(void) 168215976Sjmallett{ 169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 170215976Sjmallett cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007B0ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_L2D_FUS3_FUNC(void) 179215976Sjmallett{ 180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 181215976Sjmallett cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007B8ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 186215976Sjmallett#endif 187215976Sjmallett 188215976Sjmallett/** 189215976Sjmallett * cvmx_l2d_bst0 190215976Sjmallett * 191215976Sjmallett * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register 192215976Sjmallett * 193215976Sjmallett */ 194215976Sjmallettunion cvmx_l2d_bst0 195215976Sjmallett{ 196215976Sjmallett uint64_t u64; 197215976Sjmallett struct cvmx_l2d_bst0_s 198215976Sjmallett { 199215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 200215976Sjmallett uint64_t reserved_35_63 : 29; 201215976Sjmallett uint64_t ftl : 1; /**< L2C Data Store Fatal Defect(across all QUADs) 202215976Sjmallett 2 or more columns were detected bad across all 203215976Sjmallett QUADs[0-3]. Please refer to individual quad failures 204215976Sjmallett for bad column = 0x7e to determine which QUAD was in 205215976Sjmallett error. */ 206215976Sjmallett uint64_t q0stat : 34; /**< Bist Results for QUAD0 207215976Sjmallett Failure \#1 Status 208215976Sjmallett [16:14] bad bank 209215976Sjmallett [13:7] bad high column 210215976Sjmallett [6:0] bad low column 211215976Sjmallett Failure \#2 Status 212215976Sjmallett [33:31] bad bank 213215976Sjmallett [30:24] bad high column 214215976Sjmallett [23:17] bad low column 215215976Sjmallett NOTES: For bad high/low column reporting: 216215976Sjmallett 0x7f: No failure 217215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 218215976Sjmallett 0-0x45: Bad column 219215976Sjmallett NOTE: If there are less than 2 failures then the 220215976Sjmallett bad bank will be 0x7. */ 221215976Sjmallett#else 222215976Sjmallett uint64_t q0stat : 34; 223215976Sjmallett uint64_t ftl : 1; 224215976Sjmallett uint64_t reserved_35_63 : 29; 225215976Sjmallett#endif 226215976Sjmallett } s; 227215976Sjmallett struct cvmx_l2d_bst0_s cn30xx; 228215976Sjmallett struct cvmx_l2d_bst0_s cn31xx; 229215976Sjmallett struct cvmx_l2d_bst0_s cn38xx; 230215976Sjmallett struct cvmx_l2d_bst0_s cn38xxp2; 231215976Sjmallett struct cvmx_l2d_bst0_s cn50xx; 232215976Sjmallett struct cvmx_l2d_bst0_s cn52xx; 233215976Sjmallett struct cvmx_l2d_bst0_s cn52xxp1; 234215976Sjmallett struct cvmx_l2d_bst0_s cn56xx; 235215976Sjmallett struct cvmx_l2d_bst0_s cn56xxp1; 236215976Sjmallett struct cvmx_l2d_bst0_s cn58xx; 237215976Sjmallett struct cvmx_l2d_bst0_s cn58xxp1; 238215976Sjmallett}; 239215976Sjmalletttypedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t; 240215976Sjmallett 241215976Sjmallett/** 242215976Sjmallett * cvmx_l2d_bst1 243215976Sjmallett * 244215976Sjmallett * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register 245215976Sjmallett * 246215976Sjmallett */ 247215976Sjmallettunion cvmx_l2d_bst1 248215976Sjmallett{ 249215976Sjmallett uint64_t u64; 250215976Sjmallett struct cvmx_l2d_bst1_s 251215976Sjmallett { 252215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 253215976Sjmallett uint64_t reserved_34_63 : 30; 254215976Sjmallett uint64_t q1stat : 34; /**< Bist Results for QUAD1 255215976Sjmallett Failure \#1 Status 256215976Sjmallett [16:14] bad bank 257215976Sjmallett [13:7] bad high column 258215976Sjmallett [6:0] bad low column 259215976Sjmallett Failure \#2 Status 260215976Sjmallett [33:31] bad bank 261215976Sjmallett [30:24] bad high column 262215976Sjmallett [23:17] bad low column 263215976Sjmallett NOTES: For bad high/low column reporting: 264215976Sjmallett 0x7f: No failure 265215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 266215976Sjmallett 0-0x45: Bad column 267215976Sjmallett NOTE: If there are less than 2 failures then the 268215976Sjmallett bad bank will be 0x7. */ 269215976Sjmallett#else 270215976Sjmallett uint64_t q1stat : 34; 271215976Sjmallett uint64_t reserved_34_63 : 30; 272215976Sjmallett#endif 273215976Sjmallett } s; 274215976Sjmallett struct cvmx_l2d_bst1_s cn30xx; 275215976Sjmallett struct cvmx_l2d_bst1_s cn31xx; 276215976Sjmallett struct cvmx_l2d_bst1_s cn38xx; 277215976Sjmallett struct cvmx_l2d_bst1_s cn38xxp2; 278215976Sjmallett struct cvmx_l2d_bst1_s cn50xx; 279215976Sjmallett struct cvmx_l2d_bst1_s cn52xx; 280215976Sjmallett struct cvmx_l2d_bst1_s cn52xxp1; 281215976Sjmallett struct cvmx_l2d_bst1_s cn56xx; 282215976Sjmallett struct cvmx_l2d_bst1_s cn56xxp1; 283215976Sjmallett struct cvmx_l2d_bst1_s cn58xx; 284215976Sjmallett struct cvmx_l2d_bst1_s cn58xxp1; 285215976Sjmallett}; 286215976Sjmalletttypedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t; 287215976Sjmallett 288215976Sjmallett/** 289215976Sjmallett * cvmx_l2d_bst2 290215976Sjmallett * 291215976Sjmallett * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register 292215976Sjmallett * 293215976Sjmallett */ 294215976Sjmallettunion cvmx_l2d_bst2 295215976Sjmallett{ 296215976Sjmallett uint64_t u64; 297215976Sjmallett struct cvmx_l2d_bst2_s 298215976Sjmallett { 299215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 300215976Sjmallett uint64_t reserved_34_63 : 30; 301215976Sjmallett uint64_t q2stat : 34; /**< Bist Results for QUAD2 302215976Sjmallett Failure \#1 Status 303215976Sjmallett [16:14] bad bank 304215976Sjmallett [13:7] bad high column 305215976Sjmallett [6:0] bad low column 306215976Sjmallett Failure \#2 Status 307215976Sjmallett [33:31] bad bank 308215976Sjmallett [30:24] bad high column 309215976Sjmallett [23:17] bad low column 310215976Sjmallett NOTES: For bad high/low column reporting: 311215976Sjmallett 0x7f: No failure 312215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 313215976Sjmallett 0-0x45: Bad column 314215976Sjmallett NOTE: If there are less than 2 failures then the 315215976Sjmallett bad bank will be 0x7. */ 316215976Sjmallett#else 317215976Sjmallett uint64_t q2stat : 34; 318215976Sjmallett uint64_t reserved_34_63 : 30; 319215976Sjmallett#endif 320215976Sjmallett } s; 321215976Sjmallett struct cvmx_l2d_bst2_s cn30xx; 322215976Sjmallett struct cvmx_l2d_bst2_s cn31xx; 323215976Sjmallett struct cvmx_l2d_bst2_s cn38xx; 324215976Sjmallett struct cvmx_l2d_bst2_s cn38xxp2; 325215976Sjmallett struct cvmx_l2d_bst2_s cn50xx; 326215976Sjmallett struct cvmx_l2d_bst2_s cn52xx; 327215976Sjmallett struct cvmx_l2d_bst2_s cn52xxp1; 328215976Sjmallett struct cvmx_l2d_bst2_s cn56xx; 329215976Sjmallett struct cvmx_l2d_bst2_s cn56xxp1; 330215976Sjmallett struct cvmx_l2d_bst2_s cn58xx; 331215976Sjmallett struct cvmx_l2d_bst2_s cn58xxp1; 332215976Sjmallett}; 333215976Sjmalletttypedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t; 334215976Sjmallett 335215976Sjmallett/** 336215976Sjmallett * cvmx_l2d_bst3 337215976Sjmallett * 338215976Sjmallett * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register 339215976Sjmallett * 340215976Sjmallett */ 341215976Sjmallettunion cvmx_l2d_bst3 342215976Sjmallett{ 343215976Sjmallett uint64_t u64; 344215976Sjmallett struct cvmx_l2d_bst3_s 345215976Sjmallett { 346215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 347215976Sjmallett uint64_t reserved_34_63 : 30; 348215976Sjmallett uint64_t q3stat : 34; /**< Bist Results for QUAD3 349215976Sjmallett Failure \#1 Status 350215976Sjmallett [16:14] bad bank 351215976Sjmallett [13:7] bad high column 352215976Sjmallett [6:0] bad low column 353215976Sjmallett Failure \#2 Status 354215976Sjmallett [33:31] bad bank 355215976Sjmallett [30:24] bad high column 356215976Sjmallett [23:17] bad low column 357215976Sjmallett NOTES: For bad high/low column reporting: 358215976Sjmallett 0x7f: No failure 359215976Sjmallett 0x7e: Fatal Defect: 2 or more bad columns 360215976Sjmallett 0-0x45: Bad column 361215976Sjmallett NOTE: If there are less than 2 failures then the 362215976Sjmallett bad bank will be 0x7. */ 363215976Sjmallett#else 364215976Sjmallett uint64_t q3stat : 34; 365215976Sjmallett uint64_t reserved_34_63 : 30; 366215976Sjmallett#endif 367215976Sjmallett } s; 368215976Sjmallett struct cvmx_l2d_bst3_s cn30xx; 369215976Sjmallett struct cvmx_l2d_bst3_s cn31xx; 370215976Sjmallett struct cvmx_l2d_bst3_s cn38xx; 371215976Sjmallett struct cvmx_l2d_bst3_s cn38xxp2; 372215976Sjmallett struct cvmx_l2d_bst3_s cn50xx; 373215976Sjmallett struct cvmx_l2d_bst3_s cn52xx; 374215976Sjmallett struct cvmx_l2d_bst3_s cn52xxp1; 375215976Sjmallett struct cvmx_l2d_bst3_s cn56xx; 376215976Sjmallett struct cvmx_l2d_bst3_s cn56xxp1; 377215976Sjmallett struct cvmx_l2d_bst3_s cn58xx; 378215976Sjmallett struct cvmx_l2d_bst3_s cn58xxp1; 379215976Sjmallett}; 380215976Sjmalletttypedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t; 381215976Sjmallett 382215976Sjmallett/** 383215976Sjmallett * cvmx_l2d_err 384215976Sjmallett * 385215976Sjmallett * L2D_ERR = L2 Data Errors 386215976Sjmallett * 387215976Sjmallett * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable 388215976Sjmallett */ 389215976Sjmallettunion cvmx_l2d_err 390215976Sjmallett{ 391215976Sjmallett uint64_t u64; 392215976Sjmallett struct cvmx_l2d_err_s 393215976Sjmallett { 394215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 395215976Sjmallett uint64_t reserved_6_63 : 58; 396215976Sjmallett uint64_t bmhclsel : 1; /**< L2 Bit Map Half CacheLine ECC Selector 397215976Sjmallett 398215976Sjmallett When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects 399215976Sjmallett which half cacheline to conditionally latch into 400215976Sjmallett the L2D_FSYN0/L2D_FSYN1 registers when an LDD command 401215976Sjmallett is detected from the diagnostic PP (see L2C_DBG[PPNUM]). 402215976Sjmallett - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to 403215976Sjmallett be conditionally latched into the L2D_FSYN0/1 CSRs. 404215976Sjmallett - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to 405215976Sjmallett be conditionally latched into 406215976Sjmallett the L2D_FSYN0/1 CSRs. */ 407215976Sjmallett uint64_t ded_err : 1; /**< L2D Double Error detected (DED) */ 408215976Sjmallett uint64_t sec_err : 1; /**< L2D Single Error corrected (SEC) */ 409215976Sjmallett uint64_t ded_intena : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit 410215976Sjmallett When set, allows interrupts to be reported on double bit 411215976Sjmallett (uncorrectable) errors from the L2 Data Arrays. */ 412215976Sjmallett uint64_t sec_intena : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit 413215976Sjmallett When set, allows interrupts to be reported on single bit 414215976Sjmallett (correctable) errors from the L2 Data Arrays. */ 415215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Data ECC Enable 416215976Sjmallett When set, enables 10-bit SEC/DED codeword for 128bit L2 417215976Sjmallett Data Arrays. */ 418215976Sjmallett#else 419215976Sjmallett uint64_t ecc_ena : 1; 420215976Sjmallett uint64_t sec_intena : 1; 421215976Sjmallett uint64_t ded_intena : 1; 422215976Sjmallett uint64_t sec_err : 1; 423215976Sjmallett uint64_t ded_err : 1; 424215976Sjmallett uint64_t bmhclsel : 1; 425215976Sjmallett uint64_t reserved_6_63 : 58; 426215976Sjmallett#endif 427215976Sjmallett } s; 428215976Sjmallett struct cvmx_l2d_err_s cn30xx; 429215976Sjmallett struct cvmx_l2d_err_s cn31xx; 430215976Sjmallett struct cvmx_l2d_err_s cn38xx; 431215976Sjmallett struct cvmx_l2d_err_s cn38xxp2; 432215976Sjmallett struct cvmx_l2d_err_s cn50xx; 433215976Sjmallett struct cvmx_l2d_err_s cn52xx; 434215976Sjmallett struct cvmx_l2d_err_s cn52xxp1; 435215976Sjmallett struct cvmx_l2d_err_s cn56xx; 436215976Sjmallett struct cvmx_l2d_err_s cn56xxp1; 437215976Sjmallett struct cvmx_l2d_err_s cn58xx; 438215976Sjmallett struct cvmx_l2d_err_s cn58xxp1; 439215976Sjmallett}; 440215976Sjmalletttypedef union cvmx_l2d_err cvmx_l2d_err_t; 441215976Sjmallett 442215976Sjmallett/** 443215976Sjmallett * cvmx_l2d_fadr 444215976Sjmallett * 445215976Sjmallett * L2D_FADR = L2 Failing Address 446215976Sjmallett * 447215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Address 448215976Sjmallett * 449215976Sjmallett * Notes: 450215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index. 451215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 452215976Sjmallett */ 453215976Sjmallettunion cvmx_l2d_fadr 454215976Sjmallett{ 455215976Sjmallett uint64_t u64; 456215976Sjmallett struct cvmx_l2d_fadr_s 457215976Sjmallett { 458215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 459215976Sjmallett uint64_t reserved_19_63 : 45; 460215976Sjmallett uint64_t fadru : 1; /**< Failing L2 Data Store Upper Index bit(MSB) */ 461215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 462215976Sjmallett error) */ 463215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 464215976Sjmallett uint64_t fadr : 11; /**< Failing L2 Data Store Lower Index bits 465215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 466215976Sjmallett [FADRU, FADR[10:1]]: cacheline index[17:7] 467215976Sjmallett FADR[0]: 1/2 cacheline index 468215976Sjmallett NOTE: FADR[1] is used to select between upper/lower 1MB 469215976Sjmallett physical L2 Data Store banks. */ 470215976Sjmallett#else 471215976Sjmallett uint64_t fadr : 11; 472215976Sjmallett uint64_t fset : 3; 473215976Sjmallett uint64_t fowmsk : 4; 474215976Sjmallett uint64_t fadru : 1; 475215976Sjmallett uint64_t reserved_19_63 : 45; 476215976Sjmallett#endif 477215976Sjmallett } s; 478215976Sjmallett struct cvmx_l2d_fadr_cn30xx 479215976Sjmallett { 480215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 481215976Sjmallett uint64_t reserved_18_63 : 46; 482215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 483215976Sjmallett error) */ 484215976Sjmallett uint64_t reserved_13_13 : 1; 485215976Sjmallett uint64_t fset : 2; /**< Failing SET# */ 486215976Sjmallett uint64_t reserved_9_10 : 2; 487215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */ 488215976Sjmallett#else 489215976Sjmallett uint64_t fadr : 9; 490215976Sjmallett uint64_t reserved_9_10 : 2; 491215976Sjmallett uint64_t fset : 2; 492215976Sjmallett uint64_t reserved_13_13 : 1; 493215976Sjmallett uint64_t fowmsk : 4; 494215976Sjmallett uint64_t reserved_18_63 : 46; 495215976Sjmallett#endif 496215976Sjmallett } cn30xx; 497215976Sjmallett struct cvmx_l2d_fadr_cn31xx 498215976Sjmallett { 499215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 500215976Sjmallett uint64_t reserved_18_63 : 46; 501215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 502215976Sjmallett error) */ 503215976Sjmallett uint64_t reserved_13_13 : 1; 504215976Sjmallett uint64_t fset : 2; /**< Failing SET# */ 505215976Sjmallett uint64_t reserved_10_10 : 1; 506215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Data Store Index 507215976Sjmallett (1 of 1024 = half cacheline indices) */ 508215976Sjmallett#else 509215976Sjmallett uint64_t fadr : 10; 510215976Sjmallett uint64_t reserved_10_10 : 1; 511215976Sjmallett uint64_t fset : 2; 512215976Sjmallett uint64_t reserved_13_13 : 1; 513215976Sjmallett uint64_t fowmsk : 4; 514215976Sjmallett uint64_t reserved_18_63 : 46; 515215976Sjmallett#endif 516215976Sjmallett } cn31xx; 517215976Sjmallett struct cvmx_l2d_fadr_cn38xx 518215976Sjmallett { 519215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 520215976Sjmallett uint64_t reserved_18_63 : 46; 521215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 522215976Sjmallett error) */ 523215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 524215976Sjmallett uint64_t fadr : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */ 525215976Sjmallett#else 526215976Sjmallett uint64_t fadr : 11; 527215976Sjmallett uint64_t fset : 3; 528215976Sjmallett uint64_t fowmsk : 4; 529215976Sjmallett uint64_t reserved_18_63 : 46; 530215976Sjmallett#endif 531215976Sjmallett } cn38xx; 532215976Sjmallett struct cvmx_l2d_fadr_cn38xx cn38xxp2; 533215976Sjmallett struct cvmx_l2d_fadr_cn50xx 534215976Sjmallett { 535215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 536215976Sjmallett uint64_t reserved_18_63 : 46; 537215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 538215976Sjmallett error) */ 539215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 540215976Sjmallett uint64_t reserved_8_10 : 3; 541215976Sjmallett uint64_t fadr : 8; /**< Failing L2 Data Store Lower Index bits 542215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 543215976Sjmallett FADR[7:1]: cacheline index[13:7] 544215976Sjmallett FADR[0]: 1/2 cacheline index */ 545215976Sjmallett#else 546215976Sjmallett uint64_t fadr : 8; 547215976Sjmallett uint64_t reserved_8_10 : 3; 548215976Sjmallett uint64_t fset : 3; 549215976Sjmallett uint64_t fowmsk : 4; 550215976Sjmallett uint64_t reserved_18_63 : 46; 551215976Sjmallett#endif 552215976Sjmallett } cn50xx; 553215976Sjmallett struct cvmx_l2d_fadr_cn52xx 554215976Sjmallett { 555215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 556215976Sjmallett uint64_t reserved_18_63 : 46; 557215976Sjmallett uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED 558215976Sjmallett error) */ 559215976Sjmallett uint64_t fset : 3; /**< Failing SET# */ 560215976Sjmallett uint64_t reserved_10_10 : 1; 561215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Data Store Lower Index bits 562215976Sjmallett (NOTE: L2 Data Store Index is for each 1/2 cacheline) 563215976Sjmallett FADR[9:1]: cacheline index[15:7] 564215976Sjmallett FADR[0]: 1/2 cacheline index */ 565215976Sjmallett#else 566215976Sjmallett uint64_t fadr : 10; 567215976Sjmallett uint64_t reserved_10_10 : 1; 568215976Sjmallett uint64_t fset : 3; 569215976Sjmallett uint64_t fowmsk : 4; 570215976Sjmallett uint64_t reserved_18_63 : 46; 571215976Sjmallett#endif 572215976Sjmallett } cn52xx; 573215976Sjmallett struct cvmx_l2d_fadr_cn52xx cn52xxp1; 574215976Sjmallett struct cvmx_l2d_fadr_s cn56xx; 575215976Sjmallett struct cvmx_l2d_fadr_s cn56xxp1; 576215976Sjmallett struct cvmx_l2d_fadr_s cn58xx; 577215976Sjmallett struct cvmx_l2d_fadr_s cn58xxp1; 578215976Sjmallett}; 579215976Sjmalletttypedef union cvmx_l2d_fadr cvmx_l2d_fadr_t; 580215976Sjmallett 581215976Sjmallett/** 582215976Sjmallett * cvmx_l2d_fsyn0 583215976Sjmallett * 584215976Sjmallett * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5] 585215976Sjmallett * 586215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line 587215976Sjmallett * 588215976Sjmallett * Notes: 589215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome. 590215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 591215976Sjmallett */ 592215976Sjmallettunion cvmx_l2d_fsyn0 593215976Sjmallett{ 594215976Sjmallett uint64_t u64; 595215976Sjmallett struct cvmx_l2d_fsyn0_s 596215976Sjmallett { 597215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 598215976Sjmallett uint64_t reserved_20_63 : 44; 599215976Sjmallett uint64_t fsyn_ow1 : 10; /**< Failing L2 Data Store SYNDROME OW[1,5] 600215976Sjmallett When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR] 601215976Sjmallett or L2D_ERR[DED_ERR] are set, this field represents 602215976Sjmallett the failing OWECC syndrome for the half cacheline 603215976Sjmallett indexed by L2D_FADR[FADR]. 604215976Sjmallett NOTE: The L2D_FADR[FOWMSK] further qualifies which 605215976Sjmallett OW lane(1of4) detected the error. 606215976Sjmallett When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD 607215976Sjmallett command from the diagnostic PP will conditionally latch 608215976Sjmallett the raw OWECC for the selected half cacheline. 609215976Sjmallett (see: L2D_ERR[BMHCLSEL] */ 610215976Sjmallett uint64_t fsyn_ow0 : 10; /**< Failing L2 Data Store SYNDROME OW[0,4] 611215976Sjmallett When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR] 612215976Sjmallett or L2D_ERR[DED_ERR] are set, this field represents 613215976Sjmallett the failing OWECC syndrome for the half cacheline 614215976Sjmallett indexed by L2D_FADR[FADR]. 615215976Sjmallett NOTE: The L2D_FADR[FOWMSK] further qualifies which 616215976Sjmallett OW lane(1of4) detected the error. 617215976Sjmallett When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD 618215976Sjmallett (L1 load-miss) from the diagnostic PP will conditionally 619215976Sjmallett latch the raw OWECC for the selected half cacheline. 620215976Sjmallett (see: L2D_ERR[BMHCLSEL] */ 621215976Sjmallett#else 622215976Sjmallett uint64_t fsyn_ow0 : 10; 623215976Sjmallett uint64_t fsyn_ow1 : 10; 624215976Sjmallett uint64_t reserved_20_63 : 44; 625215976Sjmallett#endif 626215976Sjmallett } s; 627215976Sjmallett struct cvmx_l2d_fsyn0_s cn30xx; 628215976Sjmallett struct cvmx_l2d_fsyn0_s cn31xx; 629215976Sjmallett struct cvmx_l2d_fsyn0_s cn38xx; 630215976Sjmallett struct cvmx_l2d_fsyn0_s cn38xxp2; 631215976Sjmallett struct cvmx_l2d_fsyn0_s cn50xx; 632215976Sjmallett struct cvmx_l2d_fsyn0_s cn52xx; 633215976Sjmallett struct cvmx_l2d_fsyn0_s cn52xxp1; 634215976Sjmallett struct cvmx_l2d_fsyn0_s cn56xx; 635215976Sjmallett struct cvmx_l2d_fsyn0_s cn56xxp1; 636215976Sjmallett struct cvmx_l2d_fsyn0_s cn58xx; 637215976Sjmallett struct cvmx_l2d_fsyn0_s cn58xxp1; 638215976Sjmallett}; 639215976Sjmalletttypedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t; 640215976Sjmallett 641215976Sjmallett/** 642215976Sjmallett * cvmx_l2d_fsyn1 643215976Sjmallett * 644215976Sjmallett * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7] 645215976Sjmallett * 646215976Sjmallett * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line 647215976Sjmallett * 648215976Sjmallett * Notes: 649215976Sjmallett * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome. 650215976Sjmallett * (A DED Error will always overwrite a SEC Error SYNDROME and FADR). 651215976Sjmallett */ 652215976Sjmallettunion cvmx_l2d_fsyn1 653215976Sjmallett{ 654215976Sjmallett uint64_t u64; 655215976Sjmallett struct cvmx_l2d_fsyn1_s 656215976Sjmallett { 657215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 658215976Sjmallett uint64_t reserved_20_63 : 44; 659215976Sjmallett uint64_t fsyn_ow3 : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */ 660215976Sjmallett uint64_t fsyn_ow2 : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */ 661215976Sjmallett#else 662215976Sjmallett uint64_t fsyn_ow2 : 10; 663215976Sjmallett uint64_t fsyn_ow3 : 10; 664215976Sjmallett uint64_t reserved_20_63 : 44; 665215976Sjmallett#endif 666215976Sjmallett } s; 667215976Sjmallett struct cvmx_l2d_fsyn1_s cn30xx; 668215976Sjmallett struct cvmx_l2d_fsyn1_s cn31xx; 669215976Sjmallett struct cvmx_l2d_fsyn1_s cn38xx; 670215976Sjmallett struct cvmx_l2d_fsyn1_s cn38xxp2; 671215976Sjmallett struct cvmx_l2d_fsyn1_s cn50xx; 672215976Sjmallett struct cvmx_l2d_fsyn1_s cn52xx; 673215976Sjmallett struct cvmx_l2d_fsyn1_s cn52xxp1; 674215976Sjmallett struct cvmx_l2d_fsyn1_s cn56xx; 675215976Sjmallett struct cvmx_l2d_fsyn1_s cn56xxp1; 676215976Sjmallett struct cvmx_l2d_fsyn1_s cn58xx; 677215976Sjmallett struct cvmx_l2d_fsyn1_s cn58xxp1; 678215976Sjmallett}; 679215976Sjmalletttypedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t; 680215976Sjmallett 681215976Sjmallett/** 682215976Sjmallett * cvmx_l2d_fus0 683215976Sjmallett * 684215976Sjmallett * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register 685215976Sjmallett * 686215976Sjmallett */ 687215976Sjmallettunion cvmx_l2d_fus0 688215976Sjmallett{ 689215976Sjmallett uint64_t u64; 690215976Sjmallett struct cvmx_l2d_fus0_s 691215976Sjmallett { 692215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 693215976Sjmallett uint64_t reserved_34_63 : 30; 694215976Sjmallett uint64_t q0fus : 34; /**< Fuse Register for QUAD0 695215976Sjmallett This is purely for debug and not needed in the general 696215976Sjmallett manufacturing flow. 697215976Sjmallett Note that the fuse are complementary (Assigning a 698215976Sjmallett fuse to 1 will read as a zero). This means the case 699215976Sjmallett where no fuses are blown result in these csr's showing 700215976Sjmallett all ones. 701215976Sjmallett Failure \#1 Fuse Mapping 702215976Sjmallett [16:14] bad bank 703215976Sjmallett [13:7] bad high column 704215976Sjmallett [6:0] bad low column 705215976Sjmallett Failure \#2 Fuse Mapping 706215976Sjmallett [33:31] bad bank 707215976Sjmallett [30:24] bad high column 708215976Sjmallett [23:17] bad low column */ 709215976Sjmallett#else 710215976Sjmallett uint64_t q0fus : 34; 711215976Sjmallett uint64_t reserved_34_63 : 30; 712215976Sjmallett#endif 713215976Sjmallett } s; 714215976Sjmallett struct cvmx_l2d_fus0_s cn30xx; 715215976Sjmallett struct cvmx_l2d_fus0_s cn31xx; 716215976Sjmallett struct cvmx_l2d_fus0_s cn38xx; 717215976Sjmallett struct cvmx_l2d_fus0_s cn38xxp2; 718215976Sjmallett struct cvmx_l2d_fus0_s cn50xx; 719215976Sjmallett struct cvmx_l2d_fus0_s cn52xx; 720215976Sjmallett struct cvmx_l2d_fus0_s cn52xxp1; 721215976Sjmallett struct cvmx_l2d_fus0_s cn56xx; 722215976Sjmallett struct cvmx_l2d_fus0_s cn56xxp1; 723215976Sjmallett struct cvmx_l2d_fus0_s cn58xx; 724215976Sjmallett struct cvmx_l2d_fus0_s cn58xxp1; 725215976Sjmallett}; 726215976Sjmalletttypedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t; 727215976Sjmallett 728215976Sjmallett/** 729215976Sjmallett * cvmx_l2d_fus1 730215976Sjmallett * 731215976Sjmallett * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register 732215976Sjmallett * 733215976Sjmallett */ 734215976Sjmallettunion cvmx_l2d_fus1 735215976Sjmallett{ 736215976Sjmallett uint64_t u64; 737215976Sjmallett struct cvmx_l2d_fus1_s 738215976Sjmallett { 739215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 740215976Sjmallett uint64_t reserved_34_63 : 30; 741215976Sjmallett uint64_t q1fus : 34; /**< Fuse Register for QUAD1 742215976Sjmallett This is purely for debug and not needed in the general 743215976Sjmallett manufacturing flow. 744215976Sjmallett Note that the fuse are complementary (Assigning a 745215976Sjmallett fuse to 1 will read as a zero). This means the case 746215976Sjmallett where no fuses are blown result in these csr's showing 747215976Sjmallett all ones. 748215976Sjmallett Failure \#1 Fuse Mapping 749215976Sjmallett [16:14] bad bank 750215976Sjmallett [13:7] bad high column 751215976Sjmallett [6:0] bad low column 752215976Sjmallett Failure \#2 Fuse Mapping 753215976Sjmallett [33:31] bad bank 754215976Sjmallett [30:24] bad high column 755215976Sjmallett [23:17] bad low column */ 756215976Sjmallett#else 757215976Sjmallett uint64_t q1fus : 34; 758215976Sjmallett uint64_t reserved_34_63 : 30; 759215976Sjmallett#endif 760215976Sjmallett } s; 761215976Sjmallett struct cvmx_l2d_fus1_s cn30xx; 762215976Sjmallett struct cvmx_l2d_fus1_s cn31xx; 763215976Sjmallett struct cvmx_l2d_fus1_s cn38xx; 764215976Sjmallett struct cvmx_l2d_fus1_s cn38xxp2; 765215976Sjmallett struct cvmx_l2d_fus1_s cn50xx; 766215976Sjmallett struct cvmx_l2d_fus1_s cn52xx; 767215976Sjmallett struct cvmx_l2d_fus1_s cn52xxp1; 768215976Sjmallett struct cvmx_l2d_fus1_s cn56xx; 769215976Sjmallett struct cvmx_l2d_fus1_s cn56xxp1; 770215976Sjmallett struct cvmx_l2d_fus1_s cn58xx; 771215976Sjmallett struct cvmx_l2d_fus1_s cn58xxp1; 772215976Sjmallett}; 773215976Sjmalletttypedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t; 774215976Sjmallett 775215976Sjmallett/** 776215976Sjmallett * cvmx_l2d_fus2 777215976Sjmallett * 778215976Sjmallett * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register 779215976Sjmallett * 780215976Sjmallett */ 781215976Sjmallettunion cvmx_l2d_fus2 782215976Sjmallett{ 783215976Sjmallett uint64_t u64; 784215976Sjmallett struct cvmx_l2d_fus2_s 785215976Sjmallett { 786215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 787215976Sjmallett uint64_t reserved_34_63 : 30; 788215976Sjmallett uint64_t q2fus : 34; /**< Fuse Register for QUAD2 789215976Sjmallett This is purely for debug and not needed in the general 790215976Sjmallett manufacturing flow. 791215976Sjmallett Note that the fuse are complementary (Assigning a 792215976Sjmallett fuse to 1 will read as a zero). This means the case 793215976Sjmallett where no fuses are blown result in these csr's showing 794215976Sjmallett all ones. 795215976Sjmallett Failure \#1 Fuse Mapping 796215976Sjmallett [16:14] bad bank 797215976Sjmallett [13:7] bad high column 798215976Sjmallett [6:0] bad low column 799215976Sjmallett Failure \#2 Fuse Mapping 800215976Sjmallett [33:31] bad bank 801215976Sjmallett [30:24] bad high column 802215976Sjmallett [23:17] bad low column */ 803215976Sjmallett#else 804215976Sjmallett uint64_t q2fus : 34; 805215976Sjmallett uint64_t reserved_34_63 : 30; 806215976Sjmallett#endif 807215976Sjmallett } s; 808215976Sjmallett struct cvmx_l2d_fus2_s cn30xx; 809215976Sjmallett struct cvmx_l2d_fus2_s cn31xx; 810215976Sjmallett struct cvmx_l2d_fus2_s cn38xx; 811215976Sjmallett struct cvmx_l2d_fus2_s cn38xxp2; 812215976Sjmallett struct cvmx_l2d_fus2_s cn50xx; 813215976Sjmallett struct cvmx_l2d_fus2_s cn52xx; 814215976Sjmallett struct cvmx_l2d_fus2_s cn52xxp1; 815215976Sjmallett struct cvmx_l2d_fus2_s cn56xx; 816215976Sjmallett struct cvmx_l2d_fus2_s cn56xxp1; 817215976Sjmallett struct cvmx_l2d_fus2_s cn58xx; 818215976Sjmallett struct cvmx_l2d_fus2_s cn58xxp1; 819215976Sjmallett}; 820215976Sjmalletttypedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t; 821215976Sjmallett 822215976Sjmallett/** 823215976Sjmallett * cvmx_l2d_fus3 824215976Sjmallett * 825215976Sjmallett * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register 826215976Sjmallett * 827215976Sjmallett */ 828215976Sjmallettunion cvmx_l2d_fus3 829215976Sjmallett{ 830215976Sjmallett uint64_t u64; 831215976Sjmallett struct cvmx_l2d_fus3_s 832215976Sjmallett { 833215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 834215976Sjmallett uint64_t reserved_40_63 : 24; 835215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 836215976Sjmallett These bits are used to 'observe' the EMA[1:0] inputs 837215976Sjmallett for the L2 Data Store RAMs which are controlled by 838215976Sjmallett either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR. 839215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 840215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 841215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 842215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 843215976Sjmallett (until dc_ok). */ 844215976Sjmallett uint64_t reserved_34_36 : 3; 845215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 846215976Sjmallett This is purely for debug and not needed in the general 847215976Sjmallett manufacturing flow. 848215976Sjmallett Note that the fuses are complementary (Assigning a 849215976Sjmallett fuse to 1 will read as a zero). This means the case 850215976Sjmallett where no fuses are blown result in these csr's showing 851215976Sjmallett all ones. 852215976Sjmallett Failure \#1 Fuse Mapping 853215976Sjmallett [16:14] bad bank 854215976Sjmallett [13:7] bad high column 855215976Sjmallett [6:0] bad low column 856215976Sjmallett Failure \#2 Fuse Mapping 857215976Sjmallett [33:31] bad bank 858215976Sjmallett [30:24] bad high column 859215976Sjmallett [23:17] bad low column */ 860215976Sjmallett#else 861215976Sjmallett uint64_t q3fus : 34; 862215976Sjmallett uint64_t reserved_34_36 : 3; 863215976Sjmallett uint64_t ema_ctl : 3; 864215976Sjmallett uint64_t reserved_40_63 : 24; 865215976Sjmallett#endif 866215976Sjmallett } s; 867215976Sjmallett struct cvmx_l2d_fus3_cn30xx 868215976Sjmallett { 869215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 870215976Sjmallett uint64_t reserved_35_63 : 29; 871215976Sjmallett uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general 872215976Sjmallett manufacturing flow. 873215976Sjmallett If the FUSE is not-blown, then this bit should read 874215976Sjmallett as 0. If the FUSE is blown, then this bit should read 875215976Sjmallett as 1. */ 876215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 877215976Sjmallett This is purely for debug and not needed in the general 878215976Sjmallett manufacturing flow. 879215976Sjmallett Note that the fuses are complementary (Assigning a 880215976Sjmallett fuse to 1 will read as a zero). This means the case 881215976Sjmallett where no fuses are blown result in these csr's showing 882215976Sjmallett all ones. 883215976Sjmallett Failure \#1 Fuse Mapping 884215976Sjmallett [16:15] UNUSED 885215976Sjmallett [14] bad bank 886215976Sjmallett [13:7] bad high column 887215976Sjmallett [6:0] bad low column 888215976Sjmallett Failure \#2 Fuse Mapping 889215976Sjmallett [33:32] UNUSED 890215976Sjmallett [31] bad bank 891215976Sjmallett [30:24] bad high column 892215976Sjmallett [23:17] bad low column */ 893215976Sjmallett#else 894215976Sjmallett uint64_t q3fus : 34; 895215976Sjmallett uint64_t crip_64k : 1; 896215976Sjmallett uint64_t reserved_35_63 : 29; 897215976Sjmallett#endif 898215976Sjmallett } cn30xx; 899215976Sjmallett struct cvmx_l2d_fus3_cn31xx 900215976Sjmallett { 901215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 902215976Sjmallett uint64_t reserved_35_63 : 29; 903215976Sjmallett uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general 904215976Sjmallett manufacturing flow. 905215976Sjmallett If the FUSE is not-blown, then this bit should read 906215976Sjmallett as 0. If the FUSE is blown, then this bit should read 907215976Sjmallett as 1. */ 908215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 909215976Sjmallett This is purely for debug and not needed in the general 910215976Sjmallett manufacturing flow. 911215976Sjmallett Note that the fuses are complementary (Assigning a 912215976Sjmallett fuse to 1 will read as a zero). This means the case 913215976Sjmallett where no fuses are blown result in these csr's showing 914215976Sjmallett all ones. 915215976Sjmallett Failure \#1 Fuse Mapping 916215976Sjmallett [16:15] UNUSED 917215976Sjmallett [14] bad bank 918215976Sjmallett [13:7] bad high column 919215976Sjmallett [6:0] bad low column 920215976Sjmallett Failure \#2 Fuse Mapping 921215976Sjmallett [33:32] UNUSED 922215976Sjmallett [31] bad bank 923215976Sjmallett [30:24] bad high column 924215976Sjmallett [23:17] bad low column */ 925215976Sjmallett#else 926215976Sjmallett uint64_t q3fus : 34; 927215976Sjmallett uint64_t crip_128k : 1; 928215976Sjmallett uint64_t reserved_35_63 : 29; 929215976Sjmallett#endif 930215976Sjmallett } cn31xx; 931215976Sjmallett struct cvmx_l2d_fus3_cn38xx 932215976Sjmallett { 933215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 934215976Sjmallett uint64_t reserved_36_63 : 28; 935215976Sjmallett uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general 936215976Sjmallett manufacturing flow. 937215976Sjmallett If the FUSE is not-blown, then this bit should read 938215976Sjmallett as 0. If the FUSE is blown, then this bit should read 939215976Sjmallett as 1. 940215976Sjmallett *** NOTE: Pass2 Addition */ 941215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 942215976Sjmallett manufacturing flow. 943215976Sjmallett If the FUSE is not-blown, then this bit should read 944215976Sjmallett as 0. If the FUSE is blown, then this bit should read 945215976Sjmallett as 1. 946215976Sjmallett *** NOTE: Pass2 Addition */ 947215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 948215976Sjmallett This is purely for debug and not needed in the general 949215976Sjmallett manufacturing flow. 950215976Sjmallett Note that the fuses are complementary (Assigning a 951215976Sjmallett fuse to 1 will read as a zero). This means the case 952215976Sjmallett where no fuses are blown result in these csr's showing 953215976Sjmallett all ones. 954215976Sjmallett Failure \#1 Fuse Mapping 955215976Sjmallett [16:14] bad bank 956215976Sjmallett [13:7] bad high column 957215976Sjmallett [6:0] bad low column 958215976Sjmallett Failure \#2 Fuse Mapping 959215976Sjmallett [33:31] bad bank 960215976Sjmallett [30:24] bad high column 961215976Sjmallett [23:17] bad low column */ 962215976Sjmallett#else 963215976Sjmallett uint64_t q3fus : 34; 964215976Sjmallett uint64_t crip_512k : 1; 965215976Sjmallett uint64_t crip_256k : 1; 966215976Sjmallett uint64_t reserved_36_63 : 28; 967215976Sjmallett#endif 968215976Sjmallett } cn38xx; 969215976Sjmallett struct cvmx_l2d_fus3_cn38xx cn38xxp2; 970215976Sjmallett struct cvmx_l2d_fus3_cn50xx 971215976Sjmallett { 972215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 973215976Sjmallett uint64_t reserved_40_63 : 24; 974215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 975215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 976215976Sjmallett for the L2 Data Store RAMs which are controlled by 977215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 978215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 979215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 980215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 981215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 982215976Sjmallett (until dc_ok). */ 983215976Sjmallett uint64_t reserved_36_36 : 1; 984215976Sjmallett uint64_t crip_32k : 1; /**< This is purely for debug and not needed in the general 985215976Sjmallett manufacturing flow. 986215976Sjmallett If the FUSE is not-blown, then this bit should read 987215976Sjmallett as 0. If the FUSE is blown, then this bit should read 988215976Sjmallett as 1. */ 989215976Sjmallett uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general 990215976Sjmallett manufacturing flow. 991215976Sjmallett If the FUSE is not-blown, then this bit should read 992215976Sjmallett as 0. If the FUSE is blown, then this bit should read 993215976Sjmallett as 1. */ 994215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 995215976Sjmallett This is purely for debug and not needed in the general 996215976Sjmallett manufacturing flow. 997215976Sjmallett Note that the fuses are complementary (Assigning a 998215976Sjmallett fuse to 1 will read as a zero). This means the case 999215976Sjmallett where no fuses are blown result in these csr's showing 1000215976Sjmallett all ones. 1001215976Sjmallett Failure \#1 Fuse Mapping 1002215976Sjmallett [16:14] UNUSED (5020 uses single physical bank per quad) 1003215976Sjmallett [13:7] bad high column 1004215976Sjmallett [6:0] bad low column 1005215976Sjmallett Failure \#2 Fuse Mapping 1006215976Sjmallett [33:31] UNUSED (5020 uses single physical bank per quad) 1007215976Sjmallett [30:24] bad high column 1008215976Sjmallett [23:17] bad low column */ 1009215976Sjmallett#else 1010215976Sjmallett uint64_t q3fus : 34; 1011215976Sjmallett uint64_t crip_64k : 1; 1012215976Sjmallett uint64_t crip_32k : 1; 1013215976Sjmallett uint64_t reserved_36_36 : 1; 1014215976Sjmallett uint64_t ema_ctl : 3; 1015215976Sjmallett uint64_t reserved_40_63 : 24; 1016215976Sjmallett#endif 1017215976Sjmallett } cn50xx; 1018215976Sjmallett struct cvmx_l2d_fus3_cn52xx 1019215976Sjmallett { 1020215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1021215976Sjmallett uint64_t reserved_40_63 : 24; 1022215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 1023215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 1024215976Sjmallett for the L2 Data Store RAMs which are controlled by 1025215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 1026215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 1027215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 1028215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 1029215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 1030215976Sjmallett (until dc_ok). */ 1031215976Sjmallett uint64_t reserved_36_36 : 1; 1032215976Sjmallett uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general 1033215976Sjmallett manufacturing flow. 1034215976Sjmallett If the FUSE is not-blown, then this bit should read 1035215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1036215976Sjmallett as 1. */ 1037215976Sjmallett uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general 1038215976Sjmallett manufacturing flow. 1039215976Sjmallett If the FUSE is not-blown, then this bit should read 1040215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1041215976Sjmallett as 1. */ 1042215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1043215976Sjmallett This is purely for debug and not needed in the general 1044215976Sjmallett manufacturing flow. 1045215976Sjmallett Note that the fuses are complementary (Assigning a 1046215976Sjmallett fuse to 1 will read as a zero). This means the case 1047215976Sjmallett where no fuses are blown result in these csr's showing 1048215976Sjmallett all ones. 1049215976Sjmallett Failure \#1 Fuse Mapping 1050215976Sjmallett [16:14] UNUSED (5020 uses single physical bank per quad) 1051215976Sjmallett [13:7] bad high column 1052215976Sjmallett [6:0] bad low column 1053215976Sjmallett Failure \#2 Fuse Mapping 1054215976Sjmallett [33:31] UNUSED (5020 uses single physical bank per quad) 1055215976Sjmallett [30:24] bad high column 1056215976Sjmallett [23:17] bad low column */ 1057215976Sjmallett#else 1058215976Sjmallett uint64_t q3fus : 34; 1059215976Sjmallett uint64_t crip_256k : 1; 1060215976Sjmallett uint64_t crip_128k : 1; 1061215976Sjmallett uint64_t reserved_36_36 : 1; 1062215976Sjmallett uint64_t ema_ctl : 3; 1063215976Sjmallett uint64_t reserved_40_63 : 24; 1064215976Sjmallett#endif 1065215976Sjmallett } cn52xx; 1066215976Sjmallett struct cvmx_l2d_fus3_cn52xx cn52xxp1; 1067215976Sjmallett struct cvmx_l2d_fus3_cn56xx 1068215976Sjmallett { 1069215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1070215976Sjmallett uint64_t reserved_40_63 : 24; 1071215976Sjmallett uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control 1072215976Sjmallett These bits are used to 'observe' the EMA[2:0] inputs 1073215976Sjmallett for the L2 Data Store RAMs which are controlled by 1074215976Sjmallett either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR. 1075215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 1076215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 1077215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 1078215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 1079215976Sjmallett (until dc_ok). */ 1080215976Sjmallett uint64_t reserved_36_36 : 1; 1081215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 1082215976Sjmallett manufacturing flow. 1083215976Sjmallett If the FUSE is not-blown, then this bit should read 1084215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1085215976Sjmallett as 1. 1086215976Sjmallett *** NOTE: Pass2 Addition */ 1087215976Sjmallett uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general 1088215976Sjmallett manufacturing flow. 1089215976Sjmallett If the FUSE is not-blown, then this bit should read 1090215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1091215976Sjmallett as 1. 1092215976Sjmallett *** NOTE: Pass2 Addition */ 1093215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1094215976Sjmallett This is purely for debug and not needed in the general 1095215976Sjmallett manufacturing flow. 1096215976Sjmallett Note that the fuses are complementary (Assigning a 1097215976Sjmallett fuse to 1 will read as a zero). This means the case 1098215976Sjmallett where no fuses are blown result in these csr's showing 1099215976Sjmallett all ones. 1100215976Sjmallett Failure \#1 Fuse Mapping 1101215976Sjmallett [16:14] bad bank 1102215976Sjmallett [13:7] bad high column 1103215976Sjmallett [6:0] bad low column 1104215976Sjmallett Failure \#2 Fuse Mapping 1105215976Sjmallett [33:31] bad bank 1106215976Sjmallett [30:24] bad high column 1107215976Sjmallett [23:17] bad low column */ 1108215976Sjmallett#else 1109215976Sjmallett uint64_t q3fus : 34; 1110215976Sjmallett uint64_t crip_1024k : 1; 1111215976Sjmallett uint64_t crip_512k : 1; 1112215976Sjmallett uint64_t reserved_36_36 : 1; 1113215976Sjmallett uint64_t ema_ctl : 3; 1114215976Sjmallett uint64_t reserved_40_63 : 24; 1115215976Sjmallett#endif 1116215976Sjmallett } cn56xx; 1117215976Sjmallett struct cvmx_l2d_fus3_cn56xx cn56xxp1; 1118215976Sjmallett struct cvmx_l2d_fus3_cn58xx 1119215976Sjmallett { 1120215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1121215976Sjmallett uint64_t reserved_39_63 : 25; 1122215976Sjmallett uint64_t ema_ctl : 2; /**< L2 Data Store EMA Control 1123215976Sjmallett These bits are used to 'observe' the EMA[1:0] inputs 1124215976Sjmallett for the L2 Data Store RAMs which are controlled by 1125215976Sjmallett either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR. 1126215976Sjmallett From poweron (dc_ok), the EMA_CTL are driven from 1127215976Sjmallett FUSE[141:140]. However after the 1st CSR write to the 1128215976Sjmallett MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source 1129215976Sjmallett from the MIO_FUSE_EMA[EMA] register permanently 1130215976Sjmallett (until dc_ok). */ 1131215976Sjmallett uint64_t reserved_36_36 : 1; 1132215976Sjmallett uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general 1133215976Sjmallett manufacturing flow. 1134215976Sjmallett If the FUSE is not-blown, then this bit should read 1135215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1136215976Sjmallett as 1. 1137215976Sjmallett *** NOTE: Pass2 Addition */ 1138215976Sjmallett uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general 1139215976Sjmallett manufacturing flow. 1140215976Sjmallett If the FUSE is not-blown, then this bit should read 1141215976Sjmallett as 0. If the FUSE is blown, then this bit should read 1142215976Sjmallett as 1. 1143215976Sjmallett *** NOTE: Pass2 Addition */ 1144215976Sjmallett uint64_t q3fus : 34; /**< Fuse Register for QUAD3 1145215976Sjmallett This is purely for debug and not needed in the general 1146215976Sjmallett manufacturing flow. 1147215976Sjmallett Note that the fuses are complementary (Assigning a 1148215976Sjmallett fuse to 1 will read as a zero). This means the case 1149215976Sjmallett where no fuses are blown result in these csr's showing 1150215976Sjmallett all ones. 1151215976Sjmallett Failure \#1 Fuse Mapping 1152215976Sjmallett [16:14] bad bank 1153215976Sjmallett [13:7] bad high column 1154215976Sjmallett [6:0] bad low column 1155215976Sjmallett Failure \#2 Fuse Mapping 1156215976Sjmallett [33:31] bad bank 1157215976Sjmallett [30:24] bad high column 1158215976Sjmallett [23:17] bad low column */ 1159215976Sjmallett#else 1160215976Sjmallett uint64_t q3fus : 34; 1161215976Sjmallett uint64_t crip_1024k : 1; 1162215976Sjmallett uint64_t crip_512k : 1; 1163215976Sjmallett uint64_t reserved_36_36 : 1; 1164215976Sjmallett uint64_t ema_ctl : 2; 1165215976Sjmallett uint64_t reserved_39_63 : 25; 1166215976Sjmallett#endif 1167215976Sjmallett } cn58xx; 1168215976Sjmallett struct cvmx_l2d_fus3_cn58xx cn58xxp1; 1169215976Sjmallett}; 1170215976Sjmalletttypedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t; 1171215976Sjmallett 1172215976Sjmallett#endif 1173