i80321reg.h revision 161592
138032Speter/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ 290792Sgshapiro 364562Sgshapiro/*- 438032Speter * Copyright (c) 2002 Wasabi Systems, Inc. 538032Speter * All rights reserved. 638032Speter * 738032Speter * Written by Jason R. Thorpe for Wasabi Systems, Inc. 838032Speter * 938032Speter * Redistribution and use in source and binary forms, with or without 1038032Speter * modification, are permitted provided that the following conditions 1138032Speter * are met: 1238032Speter * 1. Redistributions of source code must retain the above copyright 1338032Speter * notice, this list of conditions and the following disclaimer. 1464562Sgshapiro * 2. Redistributions in binary form must reproduce the above copyright 1538032Speter * notice, this list of conditions and the following disclaimer in the 1690792Sgshapiro * documentation and/or other materials provided with the distribution. 1764562Sgshapiro * 3. All advertising materials mentioning features or use of this software 1890792Sgshapiro * must display the following acknowledgement: 1990792Sgshapiro * This product includes software developed for the NetBSD Project by 2090792Sgshapiro * Wasabi Systems, Inc. 2190792Sgshapiro * 4. The name of Wasabi Systems, Inc. may not be used to endorse 2290792Sgshapiro * or promote products derived from this software without specific prior 2338032Speter * written permission. 2438032Speter * 2538032Speter * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 2638032Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2738032Speter * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2838032Speter * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 2964562Sgshapiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 3064562Sgshapiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3190792Sgshapiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3238032Speter * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3338032Speter * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3438032Speter * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3564562Sgshapiro * POSSIBILITY OF SUCH DAMAGE. 3664562Sgshapiro * 3790792Sgshapiro * $FreeBSD: head/sys/arm/xscale/i80321/i80321reg.h 161592 2006-08-24 23:51:28Z cognet $ 3838032Speter * 3938032Speter */ 4090792Sgshapiro 4138032Speter#ifndef _ARM_XSCALE_I80321REG_H_ 4264562Sgshapiro#define _ARM_XSCALE_I80321REG_H_ 4364562Sgshapiro 4438032Speter/* 4590792Sgshapiro * Register definitions for the Intel 80321 (``Verde'') I/O processor, 4664562Sgshapiro * based on the XScale core. 4764562Sgshapiro */ 4864562Sgshapiro 4964562Sgshapiro/* 5064562Sgshapiro * Base i80321 memory map: 5164562Sgshapiro * 5264562Sgshapiro * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window 5364562Sgshapiro * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows 5464562Sgshapiro * 0x9002.0000 - 0xffff.dfff External Memory 5564562Sgshapiro * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers 5673188Sgshapiro * 0xffff.e900 - 0xffff.ffff Reserved 5790792Sgshapiro */ 5890792Sgshapiro 5964562Sgshapiro#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 6090792Sgshapiro#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 6164562Sgshapiro 6290792Sgshapiro#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 6364562Sgshapiro#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 6464562Sgshapiro 6590792Sgshapiro#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 6664562Sgshapiro#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 6764562Sgshapiro 6864562Sgshapiro#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 6964562Sgshapiro 7064562Sgshapiro#define VERDE_EXTMEM_BASE 0x90020000UL 7164562Sgshapiro 7264562Sgshapiro#define VERDE_PMMR_BASE 0xffffe000UL 7390792Sgshapiro#define VERDE_PMMR_SIZE 0x00001700UL 7490792Sgshapiro 7590792Sgshapiro/* 7690792Sgshapiro * Peripheral Memory Mapped Registers. Defined as offsets 7790792Sgshapiro * from the VERDE_PMMR_BASE. 7890792Sgshapiro */ 7990792Sgshapiro#define VERDE_ATU_BASE 0x0100 8090792Sgshapiro#define VERDE_ATU_SIZE 0x0100 8190792Sgshapiro 8290792Sgshapiro#define VERDE_MU_BASE 0x0300 8390792Sgshapiro#define VERDE_MU_SIZE 0x0100 8438032Speter 8538032Speter#define VERDE_DMA_BASE 0x0400 8638032Speter#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) 8738032Speter#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) 8838032Speter#define VERDE_DMA_SIZE 0x0100 8938032Speter#define VERDE_DMA_CHSIZE 0x0040 9090792Sgshapiro 9190792Sgshapiro#define VERDE_MCU_BASE 0x0500 9238032Speter#define VERDE_MCU_SIZE 0x0100 9338032Speter 9438032Speter#if defined(CPU_XSCALE_80321) 9538032Speter#define VERDE_SSP_BASE 0x0600 9638032Speter#define VERDE_SSP_SIZE 0x0080 9738032Speter#endif 9838032Speter 9938032Speter#define VERDE_PBIU_BASE 0x0680 10038032Speter#define VERDE_PBIU_SIZE 0x0080 10138032Speter 10238032Speter#if defined(CPU_XSCALE_80321) 10338032Speter#define VERDE_AAU_BASE 0x0800 10438032Speter#define VERDE_AAU_SIZE 0x0100 10538032Speter#endif 10638032Speter 10738032Speter#define VERDE_I2C_BASE 0x1680 10838032Speter#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) 10990792Sgshapiro#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) 11090792Sgshapiro#define VERDE_I2C_SIZE 0x0080 11190792Sgshapiro#define VERDE_I2C_CHSIZE 0x0020 11238032Speter 11338032Speter/* 11438032Speter * Address Translation Unit 11538032Speter */ 11638032Speter /* 0x00 - 0x38 -- PCI configuration space header */ 11738032Speter#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ 11838032Speter#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ 11938032Speter#define ATU_ERLR 0x48 /* Expansion ROM Limit */ 12038032Speter#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ 12138032Speter#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ 12238032Speter#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ 12338032Speter#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ 12438032Speter#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ 12538032Speter#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ 12638032Speter#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ 12738032Speter#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ 12864562Sgshapiro#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ 12938032Speter#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ 13064562Sgshapiro#define ATU_ATUCR 0x80 /* ATU Configuration */ 13138032Speter#define ATU_PCSR 0x84 /* PCI Configuration and Status */ 13290792Sgshapiro#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ 13338032Speter#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ 13438032Speter#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ 13538032Speter#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ 13638032Speter#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ 13738032Speter#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ 13838032Speter#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ 13938032Speter#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ 14038032Speter#define ATU_MSI_PORT 0xb4 /* MSI port */ 14138032Speter#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ 14290792Sgshapiro#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ 14390792Sgshapiro#define ATU_PCI_X_NEXT 0xe1 /* (1) */ 14438032Speter#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ 14538032Speter#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ 14638032Speter 14738032Speter#define ATUCR_DRC_ALIAS (1U << 19) 14838032Speter#define ATUCR_DAU2GXEN (1U << 18) 14938032Speter#define ATUCR_P_SERR_MA (1U << 16) 15038032Speter#define ATUCR_DTS (1U << 15) 15138032Speter#define ATUCR_P_SERR_DIE (1U << 9) 15238032Speter#define ATUCR_DAE (1U << 8) 15338032Speter#define ATUCR_BIST_IE (1U << 3) 15438032Speter#define ATUCR_OUT_EN (1U << 1) 15538032Speter 15664562Sgshapiro#define PCSR_DAAAPE (1U << 18) 15790792Sgshapiro#define PCSR_PCI_X_CAP (3U << 16) 15890792Sgshapiro#define PCSR_PCI_X_CAP_BORING (0 << 16) 15964562Sgshapiro#define PCSR_PCI_X_CAP_66 (1U << 16) 16090792Sgshapiro#define PCSR_PCI_X_CAP_100 (2U << 16) 16190792Sgshapiro#define PCSR_PCI_X_CAP_133 (3U << 16) 16264562Sgshapiro#define PCSR_OTQB (1U << 15) 16338032Speter#define PCSR_IRTQB (1U << 14) 16438032Speter#define PCSR_DTV (1U << 12) 16538032Speter#define PCSR_BUS66 (1U << 10) 16638032Speter#define PCSR_BUS64 (1U << 8) 16738032Speter#define PCSR_RIB (1U << 5) 16838032Speter#define PCSR_RPB (1U << 4) 16938032Speter#define PCSR_CCR (1U << 2) 17038032Speter#define PCSR_CPR (1U << 1) 17138032Speter 17238032Speter#define ATUISR_IMW1BU (1U << 14) 17338032Speter#define ATUISR_ISCEM (1U << 13) 17438032Speter#define ATUISR_RSCEM (1U << 12) 17538032Speter#define ATUISR_PST (1U << 11) 17638032Speter#define ATUISR_P_SERR_ASRT (1U << 10) 17738032Speter#define ATUISR_DPE (1U << 9) 17838032Speter#define ATUISR_BIST (1U << 8) 17938032Speter#define ATUISR_IBMA (1U << 7) 18038032Speter#define ATUISR_P_SERR_DET (1U << 4) 18138032Speter#define ATUISR_PMA (1U << 3) 18238032Speter#define ATUISR_PTAM (1U << 2) 18338032Speter#define ATUISR_PTAT (1U << 1) 18438032Speter#define ATUISR_PMPE (1U << 0) 18538032Speter 18638032Speter#define ATUIMR_IMW1BU (1U << 11) 18738032Speter#define ATUIMR_ISCEM (1U << 10) 18838032Speter#define ATUIMR_RSCEM (1U << 9) 18938032Speter#define ATUIMR_PST (1U << 8) 19038032Speter#define ATUIMR_DPE (1U << 7) 19138032Speter#define ATUIMR_P_SERR_ASRT (1U << 6) 19238032Speter#define ATUIMR_PMA (1U << 5) 19338032Speter#define ATUIMR_PTAM (1U << 4) 19438032Speter#define ATUIMR_PTAT (1U << 3) 19538032Speter#define ATUIMR_PMPE (1U << 2) 19638032Speter#define ATUIMR_IE_SERR_EN (1U << 1) 19738032Speter#define ATUIMR_ECC_TAE (1U << 0) 19838032Speter 19938032Speter#define PCIXCMD_MOST_1 (0 << 4) 20038032Speter#define PCIXCMD_MOST_2 (1 << 4) 20138032Speter#define PCIXCMD_MOST_3 (2 << 4) 20238032Speter#define PCIXCMD_MOST_4 (3 << 4) 20338032Speter#define PCIXCMD_MOST_8 (4 << 4) 20438032Speter#define PCIXCMD_MOST_12 (5 << 4) 20538032Speter#define PCIXCMD_MOST_16 (6 << 4) 20638032Speter#define PCIXCMD_MOST_32 (7 << 4) 20738032Speter#define PCIXCMD_MOST_MASK (7 << 4) 20838032Speter#define PCIXCMD_MMRBC_512 (0 << 2) 20938032Speter#define PCIXCMD_MMRBC_1024 (1 << 2) 21038032Speter#define PCIXCMD_MMRBC_2048 (2 << 2) 21138032Speter#define PCIXCMD_MMRBC_4096 (3 << 2) 21238032Speter#define PCIXCMD_MMRBC_MASK (3 << 2) 21338032Speter#define PCIXCMD_ERO (1U << 1) 21438032Speter#define PCIXCMD_DPERE (1U << 0) 21538032Speter 21638032Speter#define PCIXSR_RSCEM (1U << 29) 21738032Speter#define PCIXSR_DMCRS_MASK (7 << 26) 21838032Speter#define PCIXSR_DMOST_MASK (7 << 23) 21938032Speter#define PCIXSR_COMPLEX (1U << 20) 22038032Speter#define PCIXSR_USC (1U << 19) 22138032Speter#define PCIXSR_SCD (1U << 18) 22238032Speter#define PCIXSR_133_CAP (1U << 17) 22338032Speter#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ 22438032Speter#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 22538032Speter#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) 22638032Speter#define PCIXSR_FUNCNO(x) ((x) & 0x7) 22738032Speter 22838032Speter/* 22938032Speter * Memory Controller Unit 23038032Speter */ 23138032Speter#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ 23238032Speter#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ 23338032Speter#define MCU_SDBR 0x08 /* SDRAM Base Register */ 23438032Speter#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ 23538032Speter#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ 23638032Speter#define MCU_ECCR 0x34 /* ECC Control Register */ 23738032Speter#define MCU_ELOG0 0x38 /* ECC Log 0 */ 23838032Speter#define MCU_ELOG1 0x3c /* ECC Log 1 */ 23938032Speter#define MCU_ECAR0 0x40 /* ECC address 0 */ 24038032Speter#define MCU_ECAR1 0x44 /* ECC address 1 */ 24138032Speter#define MCU_ECTST 0x48 /* ECC test register */ 24238032Speter#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ 24338032Speter#define MCU_RFR 0x50 /* Refresh Frequency Register */ 24438032Speter#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ 24564562Sgshapiro#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ 24664562Sgshapiro#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ 24764562Sgshapiro#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ 24838032Speter#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ 24938032Speter#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ 25064562Sgshapiro#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ 25164562Sgshapiro#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ 25238032Speter#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ 25364562Sgshapiro#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ 25464562Sgshapiro#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ 25564562Sgshapiro#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ 25664562Sgshapiro#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ 25738032Speter#define MCU_REDR 0x88 /* Rx Enable Delay Register */ 25838032Speter 25938032Speter#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ 26038032Speter#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ 26138032Speter 26238032Speter#define SBRx_TECH (1U << 31) 26338032Speter#define SBRx_BOUND 0x0000003f 26438032Speter 26538032Speter#define ECCR_SBERE (1U << 0) 26638032Speter#define ECCR_MBERE (1U << 1) 26738032Speter#define ECCR_SBECE (1U << 2) 26838032Speter#define ECCR_ECCEN (1U << 3) 26938032Speter 27038032Speter#define ELOGx_SYNDROME 0x000000ff 27138032Speter#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ 27238032Speter#define ELOGx_RW (1U << 12) /* 1 = write error */ 27338032Speter /* 27438032Speter * Dev ID Func Requester 27538032Speter * 2 0 XScale core 27638032Speter * 2 1 ATU 27738032Speter * 13 0 DMA channel 0 27838032Speter * 13 1 DMA channel 1 27938032Speter * 26 0 ATU 28038032Speter */ 28138032Speter#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 28238032Speter#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 28338032Speter 28438032Speter#define MCISR_ECC_ERR0 (1U << 0) 28538032Speter#define MCISR_ECC_ERR1 (1U << 1) 28638032Speter#define MCISR_ECC_ERRN (1U << 2) 28738032Speter 28838032Speter/* 28938032Speter * Timers 29038032Speter * 29138032Speter * The i80321 timer registers are available in both memory-mapped 29290792Sgshapiro * and coprocessor spaces. Most of the registers are read-only 29338032Speter * if memory-mapped, so we access them via coprocessor space. 29490792Sgshapiro * 29538032Speter * TMR0 cp6 c0,1 0xffffe7e0 29690792Sgshapiro * TMR1 cp6 c1,1 0xffffe7e4 29738032Speter * TCR0 cp6 c2,1 0xffffe7e8 29838032Speter * TCR1 cp6 c3,1 0xffffe7ec 29938032Speter * TRR0 cp6 c4,1 0xffffe7f0 30038032Speter * TRR1 cp6 c5,1 0xffffe7f4 30138032Speter * TISR cp6 c6,1 0xffffe7f8 30238032Speter * WDTCR cp6 c7,1 0xffffe7fc 30338032Speter */ 30438032Speter 30538032Speter#define TMRx_TC (1U << 0) 30638032Speter#define TMRx_ENABLE (1U << 1) 30738032Speter#define TMRx_RELOAD (1U << 2) 30838032Speter#define TMRx_CSEL_CORE (0 << 4) 30938032Speter#define TMRx_CSEL_CORE_div4 (1 << 4) 31038032Speter#define TMRx_CSEL_CORE_div8 (2 << 4) 31138032Speter#define TMRx_CSEL_CORE_div16 (3 << 4) 31238032Speter 31338032Speter#define TISR_TMR0 (1U << 0) 31438032Speter#define TISR_TMR1 (1U << 1) 31538032Speter 31638032Speter#define WDTCR_ENABLE1 0x1e1e1e1e 31738032Speter#define WDTCR_ENABLE2 0xe1e1e1e1 31838032Speter 31938032Speter/* 32038032Speter * Interrupt Controller Unit. 32138032Speter * 32238032Speter * INTCTL cp6 c0,0 0xffffe7d0 32338032Speter * INTSTR cp6 c4,0 0xffffe7d4 32438032Speter * IINTSRC cp6 c8,0 0xffffe7d8 32538032Speter * FINTSRC cp6 c9,0 0xffffe7dc 32638032Speter * PIRSR 0xffffe1ec 32738032Speter */ 32838032Speter 32938032Speter#define ICU_PIRSR 0x01ec 33038032Speter#define ICU_GPOE 0x07c4 33190792Sgshapiro#define ICU_GPID 0x07c8 33238032Speter#define ICU_GPOD 0x07cc 33390792Sgshapiro 33438032Speter/* 33538032Speter * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE 33638032Speter * INTERRUPTS. See i80321_icu.c 33790792Sgshapiro */ 33838032Speter#define ICU_INT_HPI 31 /* high priority interrupt */ 33990792Sgshapiro#define ICU_INT_XINT0 27 /* external interrupts */ 34038032Speter#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) 34138032Speter#define ICU_INT_bit26 26 34238032Speter 34338032Speter#if defined (CPU_XSCALE_80219) 34438032Speter#define ICU_INT_bit25 25 /* reserved */ 34538032Speter#else 34638032Speter/* CPU_XSCALE_80321 */ 34738032Speter#define ICU_INT_SSP 25 /* SSP serial port */ 34838032Speter#endif 34938032Speter 35038032Speter#define ICU_INT_MUE 24 /* msg unit error */ 35138032Speter 35238032Speter#if defined (CPU_XSCALE_80219) 35338032Speter#define ICU_INT_bit23 23 /* reserved */ 35438032Speter#else 35538032Speter/* CPU_XSCALE_80321 */ 35638032Speter#define ICU_INT_AAUE 23 /* AAU error */ 35738032Speter#endif 35838032Speter 35938032Speter#define ICU_INT_bit22 22 36038032Speter#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ 36138032Speter#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ 36238032Speter#define ICU_INT_MCUE 19 /* memory controller error */ 36338032Speter#define ICU_INT_ATUE 18 /* ATU error */ 36438032Speter#define ICU_INT_BIUE 17 /* bus interface unit error */ 36538032Speter#define ICU_INT_PMU 16 /* XScale PMU */ 36638032Speter#define ICU_INT_PPM 15 /* peripheral PMU */ 36738032Speter#define ICU_INT_BIST 14 /* ATU Start BIST */ 36838032Speter#define ICU_INT_MU 13 /* messaging unit */ 36938032Speter#define ICU_INT_I2C1 12 /* i2c unit 1 */ 37038032Speter#define ICU_INT_I2C0 11 /* i2c unit 0 */ 37177349Sgshapiro#define ICU_INT_TMR1 10 /* timer 1 */ 37290792Sgshapiro#define ICU_INT_TMR0 9 /* timer 0 */ 37338032Speter#define ICU_INT_CPPM 8 /* core processor PMU */ 37438032Speter 37538032Speter#if defined(CPU_XSCALE_80219) 37638032Speter#define ICU_INT_bit7 7 /* reserved */ 37738032Speter#define ICU_INT_bit6 6 /* reserved */ 37864562Sgshapiro#else 37938032Speter/* CPU_XSCALE_80321 */ 38064562Sgshapiro#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ 38164562Sgshapiro#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ 38264562Sgshapiro#endif 38338032Speter 38438032Speter#define ICU_INT_bit5 5 38538032Speter#define ICU_INT_bit4 4 38638032Speter#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ 38738032Speter#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ 38838032Speter#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ 38938032Speter#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ 39038032Speter 39164562Sgshapiro#if defined (CPU_XSCALE_80219) 39290792Sgshapiro#define ICU_INT_HWMASK (0xffffffff & \ 39338032Speter ~((1 << ICU_INT_bit26) | \ 39438032Speter (1 << ICU_INT_bit25) | \ 39538032Speter (1 << ICU_INT_bit23) | \ 39638032Speter (1 << ICU_INT_bit22) | \ 39738032Speter (1 << ICU_INT_bit7) | \ 39838032Speter (1 << ICU_INT_bit6) | \ 39938032Speter (1 << ICU_INT_bit5) | \ 40038032Speter (1 << ICU_INT_bit4))) 40138032Speter 40238032Speter#else 40364562Sgshapiro/* CPU_XSCALE_80321 */ 40438032Speter#define ICU_INT_HWMASK (0xffffffff & \ 40538032Speter ~((1 << ICU_INT_bit26) | \ 40638032Speter (1 << ICU_INT_bit22) | \ 40738032Speter (1 << ICU_INT_bit5) | \ 40838032Speter (1 << ICU_INT_bit4))) 40938032Speter#endif 41038032Speter 41138032Speter/* 41264562Sgshapiro * SSP Serial Port 41338032Speter */ 41438032Speter#if defined (CPU_XSCALE_80321) 41538032Speter 41664562Sgshapiro#define SSP_SSCR0 0x00 /* SSC control 0 */ 41790792Sgshapiro#define SSP_SSCR1 0x04 /* SSC control 1 */ 41838032Speter#define SSP_SSSR 0x08 /* SSP status */ 41938032Speter#define SSP_SSITR 0x0c /* SSP interrupt test */ 42038032Speter#define SSP_SSDR 0x10 /* SSP data */ 42190792Sgshapiro 42238032Speter#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */ 42338032Speter#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ 42490792Sgshapiro#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ 42564562Sgshapiro#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ 42638032Speter#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ 42738032Speter#define SSP_SSCR0_ECS (1U << 6)/* external clock select */ 42864562Sgshapiro#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ 42938032Speter#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */ 43038032Speter /* bit rate = 3.6864 * 10e6 / 43138032Speter (2 * (SCR + 1)) */ 43238032Speter 43338032Speter#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */ 43438032Speter#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */ 43564562Sgshapiro#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ 43638032Speter#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ 43738032Speter#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase: 43838032Speter 0 = inactive full at start, 43964562Sgshapiro 1/2 at end of frame 44038032Speter 1 = inactive 1/2 at start, 44138032Speter full at end of frame */ 44238032Speter#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size: 44364562Sgshapiro 0 = 8 bit 44438032Speter 1 = 16 bit */ 44590792Sgshapiro#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ 44664562Sgshapiro#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ 44764562Sgshapiro#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ 44864562Sgshapiro#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO select: 44964562Sgshapiro 0 = Tx FIFO 45064562Sgshapiro 1 = Rx FIFO */ 45164562Sgshapiro 45264562Sgshapiro#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ 45364562Sgshapiro#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ 45464562Sgshapiro#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */ 45564562Sgshapiro#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ 45664562Sgshapiro#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ 45764562Sgshapiro#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ 45838032Speter#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */ 45964562Sgshapiro#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */ 46064562Sgshapiro 46164562Sgshapiro#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ 46238032Speter#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ 46364562Sgshapiro#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ 46438032Speter 46538032Speter#endif /* CPU_XSCALE_80321 */ 46638032Speter 46738032Speter/* 46890792Sgshapiro * Peripheral Bus Interface Unit 46938032Speter */ 47038032Speter 47138032Speter#define PBIU_PBCR 0x00 /* PBIU Control Register */ 47238032Speter#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ 47338032Speter#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ 47438032Speter#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ 47538032Speter#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ 47690792Sgshapiro#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ 47738032Speter#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ 47838032Speter#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ 47938032Speter#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ 48064562Sgshapiro#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ 48138032Speter#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ 48264562Sgshapiro#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ 48364562Sgshapiro#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ 48438032Speter#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ 48538032Speter#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ 48690792Sgshapiro#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ 48738032Speter#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ 48838032Speter 48938032Speter#define PBIU_PBCR_PBIEN (1 << 0) 49038032Speter#define PBIU_PBCR_PBI100 (1 << 1) 49138032Speter#define PBIU_PBCR_PBI66 (2 << 1) 49238032Speter#define PBIU_PBCR_PBI33 (3 << 1) 49377349Sgshapiro#define PBIU_PBCR_PBBEN (1 << 3) 49438032Speter 49577349Sgshapiro#define PBIU_PBARx_WIDTH8 (0 << 0) 49638032Speter#define PBIU_PBARx_WIDTH16 (1 << 0) 49738032Speter#define PBIU_PBARx_WIDTH32 (2 << 0) 49890792Sgshapiro#define PBIU_PBARx_ADWAIT4 (0 << 2) 49964562Sgshapiro#define PBIU_PBARx_ADWAIT8 (1 << 2) 50064562Sgshapiro#define PBIU_PBARx_ADWAIT12 (2 << 2) 50190792Sgshapiro#define PBIU_PBARx_ADWAIT16 (3 << 2) 50264562Sgshapiro#define PBIU_PBARx_ADWAIT20 (4 << 2) 50364562Sgshapiro#define PBIU_PBARx_RCWAIT1 (0 << 6) 50464562Sgshapiro#define PBIU_PBARx_RCWAIT4 (1 << 6) 50564562Sgshapiro#define PBIU_PBARx_RCWAIT8 (2 << 6) 50664562Sgshapiro#define PBIU_PBARx_RCWAIT12 (3 << 6) 50764562Sgshapiro#define PBIU_PBARx_RCWAIT16 (4 << 6) 50864562Sgshapiro#define PBIU_PBARx_RCWAIT20 (5 << 6) 50964562Sgshapiro#define PBIU_PBARx_FWE (1 << 9) 51064562Sgshapiro#define PBIU_BASE_MASK 0xfffff000U 51164562Sgshapiro 51264562Sgshapiro#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) 51364562Sgshapiro 51464562Sgshapiro/* 51590792Sgshapiro * Messaging Unit 51664562Sgshapiro */ 51764562Sgshapiro#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ 51864562Sgshapiro#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ 51964562Sgshapiro#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ 52064562Sgshapiro#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ 52190792Sgshapiro#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ 52264562Sgshapiro#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ 52364562Sgshapiro#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ 52464562Sgshapiro#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ 52590792Sgshapiro#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ 52664562Sgshapiro#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ 52764562Sgshapiro#define MU_MUCR 0x0050 /* MU Configuration Register */ 52864562Sgshapiro#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ 52964562Sgshapiro#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ 53038032Speter#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ 53190792Sgshapiro#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ 53290792Sgshapiro#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ 53390792Sgshapiro#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ 53438032Speter#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ 53538032Speter#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ 53664562Sgshapiro#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ 53738032Speter#define MU_IAR 0x0080 /* MU Index Address Register */ 53838032Speter 53938032Speter#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ 54090792Sgshapiro#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ 54138032Speter#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ 54238032Speter#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ 54338032Speter#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ 54438032Speter#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ 54538032Speter#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ 54638032Speter 54738032Speter#endif /* _ARM_XSCALE_I80321REG_H_ */ 54890792Sgshapiro