1139735Simp/*- 2129212Scognet * Copyright (c) 2003 Marcel Moolenaar 3129212Scognet * All rights reserved. 4129212Scognet * 5129212Scognet * Redistribution and use in source and binary forms, with or without 6129212Scognet * modification, are permitted provided that the following conditions 7129212Scognet * are met: 8129212Scognet * 9129212Scognet * 1. Redistributions of source code must retain the above copyright 10129212Scognet * notice, this list of conditions and the following disclaimer. 11129212Scognet * 2. Redistributions in binary form must reproduce the above copyright 12129212Scognet * notice, this list of conditions and the following disclaimer in the 13129212Scognet * documentation and/or other materials provided with the distribution. 14129212Scognet * 15129212Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16129212Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17129212Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18129212Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19129212Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20129212Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21129212Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22129212Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23129212Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24129212Scognet * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25129212Scognet * 26129212Scognet * $FreeBSD$ 27129212Scognet */ 28129212Scognet 29129212Scognet#ifndef _DEV_UART_DEV_SA1110_H_ 30129212Scognet#define _DEV_UART_DEV_SA1110_H_ 31129212Scognet 32129212Scognet#define SACOM_FREQ (3686400 / 16) 33129212Scognet#define SACOMSPEED(b) (SACOM_FREQ / (b) - 1) 34129212Scognet 35129212Scognet/* UART control register 0 */ 36129212Scognet#define SACOM_CR0 0x00 37129212Scognet#define CR0_PE 0x01 /* Parity enable */ 38129212Scognet#define CR0_OES 0x02 /* Odd/even parity select */ 39129212Scognet#define CR0_SBS 0x04 /* Stop bit select */ 40129212Scognet#define CR0_DSS 0x08 /* Data size select */ 41129212Scognet#define CR0_SCE 0x10 /* Sample clock enable */ 42129212Scognet#define CR0_RCE 0x20 /* Receive clock edge enable */ 43129212Scognet#define CR0_TCE 0x40 /* Transmit clock edge enable */ 44129212Scognet 45129212Scognet/* UART control register 1 and 2 - baud rate divisor */ 46129212Scognet#define SACOM_CR1 0x04 47129212Scognet#define SACOM_CR2 0x08 48129212Scognet 49129212Scognet/* UART control register 3 */ 50129212Scognet#define SACOM_CR3 0x0C 51129212Scognet#define CR3_RXE 0x01 /* Receiver enable */ 52129212Scognet#define CR3_TXE 0x02 /* Transmitter enable */ 53129212Scognet#define CR3_BRK 0x04 /* Break */ 54129212Scognet#define CR3_RIE 0x08 /* Receive FIFO interrupt enable */ 55129212Scognet#define CR3_TIE 0x10 /* Transmit FIFO interrupt enable */ 56129212Scognet#define CR3_LBM 0x20 /* Loopback mode */ 57129212Scognet 58129212Scognet/* UART data register */ 59129212Scognet#define SACOM_DR 0x14 60129212Scognet#define DR_PRE 0x100 /* Parity error */ 61129212Scognet#define DR_FRE 0x200 /* Framing error */ 62129212Scognet#define DR_ROR 0x400 /* Receiver overrun */ 63129212Scognet 64129212Scognet/* UART status register 0 */ 65129212Scognet#define SACOM_SR0 0x1C 66129212Scognet#define SR0_TFS 0x01 /* Transmit FIFO service request */ 67129212Scognet#define SR0_RFS 0x02 /* Receive FIFO service request */ 68129212Scognet#define SR0_RID 0x04 /* Receiver idle */ 69129212Scognet#define SR0_RBB 0x08 /* Receiver begin of break */ 70129212Scognet#define SR0_REB 0x10 /* Receiver end of break */ 71129212Scognet#define SR0_EIF 0x20 /* Error in FIFO */ 72129212Scognet 73129212Scognet/* UART status register 1 */ 74129212Scognet#define SACOM_SR1 0x20 75129212Scognet#define SR1_TBY 0x01 /* Transmitter busy */ 76129212Scognet#define SR1_RNE 0x02 /* Receive FIFO not empty */ 77129212Scognet#define SR1_TNF 0x04 /* Transmit FIFO not full */ 78129212Scognet#define SR1_PRE 0x08 /* Parity error */ 79129212Scognet#define SR1_FRE 0x10 /* Framing error */ 80129212Scognet#define SR1_ROR 0x20 /* Receive FIFO overrun */ 81129212Scognet 82129212Scognet#define ISSET(a, b) ((a) & (b)) 83129212Scognet#endif 84