sa11x0_reg.h revision 129198
1193323Sed/*	$NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $	*/
2193323Sed
3193323Sed/*-
4193323Sed * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
5193323Sed *
6193323Sed * This code is derived from software contributed to The NetBSD Foundation
7193323Sed * by IWAMOTO Toshihiro.
8193323Sed *
9193323Sed * Redistribution and use in source and binary forms, with or without
10193323Sed * modification, are permitted provided that the following conditions
11193323Sed * are met:
12193323Sed * 1. Redistributions of source code must retain the above copyright
13193323Sed *    notice, this list of conditions and the following disclaimer.
14193323Sed * 2. Redistributions in binary form must reproduce the above copyright
15193323Sed *    notice, this list of conditions and the following disclaimer in the
16193323Sed *    documentation and/or other materials provided with the distribution.
17193323Sed * 3. All advertising materials mentioning features or use of this software
18218893Sdim *    must display the following acknowledgement:
19193323Sed *	This product includes software developed by the NetBSD
20193323Sed *	Foundation, Inc. and its contributors.
21193323Sed * 4. Neither the name of The NetBSD Foundation nor the names of its
22193323Sed *    contributors may be used to endorse or promote products derived
23193323Sed *    from this software without specific prior written permission.
24193323Sed *
25193323Sed * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
26193323Sed * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27193323Sed * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28193323Sed * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
29193323Sed * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30193323Sed * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31193323Sed * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32193323Sed * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33193323Sed * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34193323Sed * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35193323Sed * POSSIBILITY OF SUCH DAMAGE.
36193323Sed *
37193323Sed * $FreeBSD: head/sys/arm/sa11x0/sa11x0_reg.h 129198 2004-05-14 11:46:45Z cognet $
38193323Sed *
39193323Sed */
40193323Sed
41198892Srdivacky#ifndef _ARM_SA11X0_REG_H_
42193323Sed#define _ARM_SA11X0_REG_H_
43193323Sed
44193323Sed/* Physical register base addresses */
45193323Sed#define SAOST_BASE		0x90000000	/* OS Timer */
46193323Sed#define SARTC_BASE		0x90010000	/* Real-Time Clock */
47193323Sed#define SAPMR_BASE		0x90020000	/* Power Manager */
48193323Sed#define SARCR_BASE		0x90030000	/* Reset Controller */
49193323Sed#define SAGPIO_BASE		0x90040000	/* GPIO */
50193323Sed#define SAIPIC_BASE		0x90050000	/* Interrupt Controller */
51193323Sed#define SAPPC_BASE		0x90060000	/* Peripheral Pin Controller */
52193323Sed#define SAUDC_BASE		0x80000000	/* USB Device Controller*/
53198090Srdivacky#define	SACOM1_BASE		0x80010000	/* GPCLK/UART 1 */
54198090Srdivacky#define SACOM3_HW_BASE		0x80050000	/* UART 3  */
55193323Sed#define SAMCP_BASE		0x80060000	/* MCP Controller */
56198090Srdivacky#define SASSP_BASE		0x80070000	/* Synchronous serial port */
57198090Srdivacky
58198090Srdivacky#define SADMAC_BASE		0xB0000000	/* DMA Controller */
59193323Sed#define SALCD_BASE		0xB0100000	/* LCD */
60198090Srdivacky
61193323Sed/* Register base virtual addresses mapped by initarm() */
62198090Srdivacky#define SACOM3_BASE             0xd000d000
63193323Sed
64193323Sed/* Interrupt controller registers */
65193323Sed#define SAIPIC_NPORTS		9
66193323Sed#define SAIPIC_IP		0x00		/* IRQ pending register */
67193323Sed#define SAIPIC_MR		0x04		/* Mask register */
68193323Sed#define SAIPIC_LR		0x08		/* Level register */
69193323Sed#define SAIPIC_FP		0x10		/* FIQ pending register */
70193323Sed#define SAIPIC_PR		0x20		/* Pending register */
71193323Sed#define SAIPIC_CR		0x0C		/* Control register */
72193323Sed
73193323Sed/* width of interrupt controller */
74193323Sed#define ICU_LEN			32
75193323Sed
76193323Sed/* Reset controller registers */
77193323Sed#define SARCR_RSRR		0x0		/* Software reset register */
78193323Sed#define SARCR_RCSR		0x4		/* Reset status register */
79193323Sed#define SARCR_TUCR		0x8		/* Test Unit control reg */
80193323Sed
81193323Sed#endif /* _ARM_SA11X0_REG_H_ */
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