1129198Scognet/* $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $ */ 2129198Scognet 3129198Scognet/*- 4129198Scognet * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5129198Scognet * 6129198Scognet * This code is derived from software contributed to The NetBSD Foundation 7129198Scognet * by IWAMOTO Toshihiro. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 18129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28129198Scognet * POSSIBILITY OF SUCH DAMAGE. 29129198Scognet * 30129198Scognet * $FreeBSD$ 31129198Scognet * 32129198Scognet */ 33129198Scognet 34129198Scognet#ifndef _ARM_SA11X0_REG_H_ 35129198Scognet#define _ARM_SA11X0_REG_H_ 36129198Scognet 37129198Scognet/* Physical register base addresses */ 38129198Scognet#define SAOST_BASE 0x90000000 /* OS Timer */ 39129198Scognet#define SARTC_BASE 0x90010000 /* Real-Time Clock */ 40129198Scognet#define SAPMR_BASE 0x90020000 /* Power Manager */ 41129198Scognet#define SARCR_BASE 0x90030000 /* Reset Controller */ 42129198Scognet#define SAGPIO_BASE 0x90040000 /* GPIO */ 43129198Scognet#define SAIPIC_BASE 0x90050000 /* Interrupt Controller */ 44158854Scognet#define SAIPIC_SIZE 0x24 45129198Scognet#define SAPPC_BASE 0x90060000 /* Peripheral Pin Controller */ 46129198Scognet#define SAUDC_BASE 0x80000000 /* USB Device Controller*/ 47129198Scognet#define SACOM1_BASE 0x80010000 /* GPCLK/UART 1 */ 48158854Scognet#define SACOM1_SIZE 0x24 49129198Scognet#define SACOM3_HW_BASE 0x80050000 /* UART 3 */ 50129198Scognet#define SAMCP_BASE 0x80060000 /* MCP Controller */ 51129198Scognet#define SASSP_BASE 0x80070000 /* Synchronous serial port */ 52129198Scognet 53129198Scognet#define SADMAC_BASE 0xB0000000 /* DMA Controller */ 54129198Scognet#define SALCD_BASE 0xB0100000 /* LCD */ 55129198Scognet 56129198Scognet/* Register base virtual addresses mapped by initarm() */ 57158839Scognet#define SACOM1_VBASE 0xd000d000 58129198Scognet 59129198Scognet/* Interrupt controller registers */ 60129198Scognet#define SAIPIC_NPORTS 9 61129198Scognet#define SAIPIC_IP 0x00 /* IRQ pending register */ 62129198Scognet#define SAIPIC_MR 0x04 /* Mask register */ 63129198Scognet#define SAIPIC_LR 0x08 /* Level register */ 64129198Scognet#define SAIPIC_FP 0x10 /* FIQ pending register */ 65129198Scognet#define SAIPIC_PR 0x20 /* Pending register */ 66129198Scognet#define SAIPIC_CR 0x0C /* Control register */ 67129198Scognet 68129198Scognet/* width of interrupt controller */ 69129198Scognet#define ICU_LEN 32 70129198Scognet 71129198Scognet/* Reset controller registers */ 72129198Scognet#define SARCR_RSRR 0x0 /* Software reset register */ 73129198Scognet#define SARCR_RCSR 0x4 /* Reset status register */ 74129198Scognet#define SARCR_TUCR 0x8 /* Test Unit control reg */ 75129198Scognet 76129198Scognet#endif /* _ARM_SA11X0_REG_H_ */ 77