1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#define BRIDGE_IRQ_CAUSE 0x10 38#define BRIGDE_IRQ_MASK 0x14 39 40#if defined(SOC_MV_DISCOVERY) 41#define IRQ_CAUSE_ERROR 0x0 42#define IRQ_CAUSE 0x4 43#define IRQ_CAUSE_HI 0x8 44#define IRQ_MASK_ERROR 0xC 45#define IRQ_MASK 0x10 46#define IRQ_MASK_HI 0x14 47#define IRQ_CAUSE_SELECT 0x18 48#define FIQ_MASK_ERROR 0x1C 49#define FIQ_MASK 0x20 50#define FIQ_MASK_HI 0x24 51#define FIQ_CAUSE_SELECT 0x28 52#define ENDPOINT_IRQ_MASK_ERROR 0x2C 53#define ENDPOINT_IRQ_MASK 0x30 54#define ENDPOINT_IRQ_MASK_HI 0x34 55#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 56#else /* !SOC_MV_DISCOVERY */ 57#define IRQ_CAUSE 0x0 58#define IRQ_MASK 0x4 59#define FIQ_MASK 0x8 60#define ENDPOINT_IRQ_MASK 0xC 61#define IRQ_CAUSE_HI 0x10 62#define IRQ_MASK_HI 0x14 63#define FIQ_MASK_HI 0x18 64#define ENDPOINT_IRQ_MASK_HI 0x1C 65#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 66#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 67#endif 68 69#define BRIDGE_IRQ_CAUSE 0x10 70#define IRQ_CPU_SELF 0x00000001 71#define IRQ_TIMER0 0x00000002 72#define IRQ_TIMER1 0x00000004 73#define IRQ_TIMER_WD 0x00000008 74 75#define BRIDGE_IRQ_MASK 0x14 76#define IRQ_CPU_MASK 0x00000001 77#define IRQ_TIMER0_MASK 0x00000002 78#define IRQ_TIMER1_MASK 0x00000004 79#define IRQ_TIMER_WD_MASK 0x00000008 80 81/* 82 * System reset 83 */ 84#define RSTOUTn_MASK 0x8 85#define WD_RST_OUT_EN 0x00000002 86#define SOFT_RST_OUT_EN 0x00000004 87#define SYSTEM_SOFT_RESET 0xc 88#define SYS_SOFT_RST 0x00000001 89 90/* 91 * Power Control 92 */ 93#define CPU_PM_CTRL 0x1C 94#define CPU_PM_CTRL_NONE 0 95#define CPU_PM_CTRL_ALL ~0x0 96 97#if defined(SOC_MV_KIRKWOOD) 98#define CPU_PM_CTRL_GE0 (1 << 0) 99#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 100#define CPU_PM_CTRL_PEX0 (1 << 2) 101#define CPU_PM_CTRL_USB0 (1 << 3) 102#define CPU_PM_CTRL_SDIO (1 << 4) 103#define CPU_PM_CTRL_TSU (1 << 5) 104#define CPU_PM_CTRL_DUNIT (1 << 6) 105#define CPU_PM_CTRL_RUNIT (1 << 7) 106#define CPU_PM_CTRL_XOR0 (1 << 8) 107#define CPU_PM_CTRL_AUDIO (1 << 9) 108#define CPU_PM_CTRL_SATA0 (1 << 14) 109#define CPU_PM_CTRL_SATA1 (1 << 15) 110#define CPU_PM_CTRL_XOR1 (1 << 16) 111#define CPU_PM_CTRL_CRYPTO (1 << 17) 112#define CPU_PM_CTRL_GE1 (1 << 19) 113#define CPU_PM_CTRL_TDM (1 << 20) 114#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 115#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 116#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 117#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 118 (1 - (u))) 119#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 120#elif defined(SOC_MV_DISCOVERY) 121#define CPU_PM_CTRL_GE0 (1 << 1) 122#define CPU_PM_CTRL_GE1 (1 << 2) 123#define CPU_PM_CTRL_PEX00 (1 << 5) 124#define CPU_PM_CTRL_PEX01 (1 << 6) 125#define CPU_PM_CTRL_PEX02 (1 << 7) 126#define CPU_PM_CTRL_PEX03 (1 << 8) 127#define CPU_PM_CTRL_PEX10 (1 << 9) 128#define CPU_PM_CTRL_PEX11 (1 << 10) 129#define CPU_PM_CTRL_PEX12 (1 << 11) 130#define CPU_PM_CTRL_PEX13 (1 << 12) 131#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 132#define CPU_PM_CTRL_SATA0 (1 << 14) 133#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 134#define CPU_PM_CTRL_SATA1 (1 << 16) 135#define CPU_PM_CTRL_USB0 (1 << 17) 136#define CPU_PM_CTRL_USB1 (1 << 18) 137#define CPU_PM_CTRL_USB2 (1 << 19) 138#define CPU_PM_CTRL_IDMA (1 << 20) 139#define CPU_PM_CTRL_XOR (1 << 21) 140#define CPU_PM_CTRL_CRYPTO (1 << 22) 141#define CPU_PM_CTRL_DEVICE (1 << 23) 142#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 143#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 144#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 145 (1 - (u))) 146#else 147#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 148#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 149#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 150#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 151#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 152#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 153#endif 154 155/* 156 * Timers 157 */ 158#define CPU_TIMER_CONTROL 0x0 159#define CPU_TIMER0_EN 0x00000001 160#define CPU_TIMER0_AUTO 0x00000002 161#define CPU_TIMER1_EN 0x00000004 162#define CPU_TIMER1_AUTO 0x00000008 163#define CPU_TIMER_WD_EN 0x00000010 164#define CPU_TIMER_WD_AUTO 0x00000020 165#define CPU_TIMER0_REL 0x10 166#define CPU_TIMER0 0x14 167 168/* 169 * SATA 170 */ 171#define SATA_CHAN_NUM 2 172 173#define EDMA_REGISTERS_OFFSET 0x2000 174#define EDMA_REGISTERS_SIZE 0x2000 175#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 176 ((ch) * EDMA_REGISTERS_SIZE)) 177 178/* SATAHC registers */ 179#define SATA_CR 0x000 /* Configuration Reg. */ 180#define SATA_CR_NODMABS (1 << 8) 181#define SATA_CR_NOEDMABS (1 << 9) 182#define SATA_CR_NOPRDPBS (1 << 10) 183#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 184 185#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 186#define SATA_ICR_DMADONE(ch) (1 << (ch)) 187#define SATA_ICR_COAL (1 << 4) 188#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 189 190#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 191#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 192#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 193#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 194#define SATA_MICR_COAL (1 << 8) 195 196#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 197 198/* Shadow registers */ 199#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 200#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 201 202/* SATA registers */ 203#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 204#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 205#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 206#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 207 208/* EDMA registers */ 209#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 210#define SATA_EDMA_CFG_QL128 (1 << 19) 211#define SATA_EDMA_CFG_HQCACHE (1 << 22) 212 213#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 214 215#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 216#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 217#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 218#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 219#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 220#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 221#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 222 223#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 224#define SATA_EDMA_CMD_ENABLE (1 << 0) 225#define SATA_EDMA_CMD_DISABLE (1 << 1) 226#define SATA_EDMA_CMD_RESET (1 << 2) 227 228#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 229#define SATA_EDMA_STATUS_IDLE (1 << 7) 230 231/* Offset to extract input slot from REQIPR register */ 232#define SATA_EDMA_REQIS_OFS 5 233 234/* Offset to extract input slot from RESOPR register */ 235#define SATA_EDMA_RESOS_OFS 3 236 237/* 238 * GPIO 239 */ 240#define GPIO_DATA_OUT 0x00 241#define GPIO_DATA_OUT_EN_CTRL 0x04 242#define GPIO_BLINK_EN 0x08 243#define GPIO_DATA_IN_POLAR 0x0c 244#define GPIO_DATA_IN 0x10 245#define GPIO_INT_CAUSE 0x14 246#define GPIO_INT_EDGE_MASK 0x18 247#define GPIO_INT_LEV_MASK 0x1c 248 249#define GPIO_HI_DATA_OUT 0x40 250#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 251#define GPIO_HI_BLINK_EN 0x48 252#define GPIO_HI_DATA_IN_POLAR 0x4c 253#define GPIO_HI_DATA_IN 0x50 254#define GPIO_HI_INT_CAUSE 0x54 255#define GPIO_HI_INT_EDGE_MASK 0x58 256#define GPIO_HI_INT_LEV_MASK 0x5c 257 258#define GPIO(n) (1 << (n)) 259#define MV_GPIO_MAX_NPINS 64 260 261#define MV_GPIO_IN_NONE 0x0 262#define MV_GPIO_IN_POL_LOW (1 << 16) 263#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 264#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 265#define MV_GPIO_OUT_NONE 0x0 266#define MV_GPIO_OUT_BLINK 0x1 267#define MV_GPIO_OUT_OPEN_DRAIN 0x2 268#define MV_GPIO_OUT_OPEN_SRC 0x4 269 270#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 271#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 272#define IRQ2GPIO(irq) ((irq) - NIRQ) 273 274/* 275 * MPP 276 */ 277#if defined(SOC_MV_ORION) 278#define MPP_CONTROL0 0x00 279#define MPP_CONTROL1 0x04 280#define MPP_CONTROL2 0x50 281#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 282#define MPP_CONTROL0 0x00 283#define MPP_CONTROL1 0x04 284#define MPP_CONTROL2 0x08 285#define MPP_CONTROL3 0x0C 286#define MPP_CONTROL4 0x10 287#define MPP_CONTROL5 0x14 288#define MPP_CONTROL6 0x18 289#else 290#error SOC_MV_XX not defined 291#endif 292 293#if defined(SOC_MV_ORION) 294#define SAMPLE_AT_RESET 0x10 295#elif defined(SOC_MV_KIRKWOOD) 296#define SAMPLE_AT_RESET 0x30 297#elif defined(SOC_MV_DISCOVERY) 298#define SAMPLE_AT_RESET_LO 0x30 299#define SAMPLE_AT_RESET_HI 0x34 300#else 301#error SOC_MV_XX not defined 302#endif 303 304/* 305 * Clocks 306 */ 307#if defined(SOC_MV_ORION) 308#define TCLK_MASK 0x00000300 309#define TCLK_SHIFT 0x08 310#elif defined(SOC_MV_DISCOVERY) 311#define TCLK_MASK 0x00000180 312#define TCLK_SHIFT 0x07 313#endif 314 315#define TCLK_100MHZ 100000000 316#define TCLK_125MHZ 125000000 317#define TCLK_133MHZ 133333333 318#define TCLK_150MHZ 150000000 319#define TCLK_166MHZ 166666667 320#define TCLK_200MHZ 200000000 321 322/* 323 * Chip ID 324 */ 325#define MV_DEV_88F5181 0x5181 326#define MV_DEV_88F5182 0x5182 327#define MV_DEV_88F5281 0x5281 328#define MV_DEV_88F6281 0x6281 329#define MV_DEV_MV78100_Z0 0x6381 330#define MV_DEV_MV78100 0x7810 331 332#endif /* _MVREG_H_ */ 333