1155324Simp/*- 2155324Simp * Copyright (c) 1994-1998 Mark Brinicombe. 3155324Simp * Copyright (c) 1994 Brini. 4155324Simp * All rights reserved. 5155324Simp * 6155324Simp * This code is derived from software written for Brini by Mark Brinicombe 7155324Simp * 8155324Simp * Redistribution and use in source and binary forms, with or without 9155324Simp * modification, are permitted provided that the following conditions 10155324Simp * are met: 11155324Simp * 1. Redistributions of source code must retain the above copyright 12155324Simp * notice, this list of conditions and the following disclaimer. 13155324Simp * 2. Redistributions in binary form must reproduce the above copyright 14155324Simp * notice, this list of conditions and the following disclaimer in the 15155324Simp * documentation and/or other materials provided with the distribution. 16155324Simp * 3. All advertising materials mentioning features or use of this software 17155324Simp * must display the following acknowledgement: 18155324Simp * This product includes software developed by Brini. 19155324Simp * 4. The name of the company nor the name of the author may be used to 20155324Simp * endorse or promote products derived from this software without specific 21155324Simp * prior written permission. 22155324Simp * 23155324Simp * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24155324Simp * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25155324Simp * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26155324Simp * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27155324Simp * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28155324Simp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29155324Simp * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30155324Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31155324Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32155324Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33155324Simp * SUCH DAMAGE. 34155324Simp * 35155324Simp * RiscBSD kernel project 36155324Simp * 37155324Simp * machdep.c 38155324Simp * 39155324Simp * Machine dependant functions for kernel setup 40155324Simp * 41185270Simp * This file needs a lot of work. 42155324Simp * 43155324Simp * Created : 17/09/94 44155324Simp */ 45155324Simp 46155324Simp#include <sys/cdefs.h> 47155324Simp__FBSDID("$FreeBSD$"); 48155324Simp 49155324Simp#define _ARM32_BUS_DMA_PRIVATE 50155324Simp#include <sys/param.h> 51155324Simp#include <sys/systm.h> 52155324Simp#include <sys/sysproto.h> 53155324Simp#include <sys/signalvar.h> 54155324Simp#include <sys/imgact.h> 55155324Simp#include <sys/kernel.h> 56155324Simp#include <sys/ktr.h> 57155324Simp#include <sys/linker.h> 58155324Simp#include <sys/lock.h> 59155324Simp#include <sys/malloc.h> 60155324Simp#include <sys/mutex.h> 61155324Simp#include <sys/pcpu.h> 62155324Simp#include <sys/proc.h> 63155324Simp#include <sys/ptrace.h> 64155324Simp#include <sys/cons.h> 65155324Simp#include <sys/bio.h> 66155324Simp#include <sys/bus.h> 67155324Simp#include <sys/buf.h> 68155324Simp#include <sys/exec.h> 69155324Simp#include <sys/kdb.h> 70155324Simp#include <sys/msgbuf.h> 71155324Simp#include <machine/reg.h> 72155324Simp#include <machine/cpu.h> 73155324Simp 74155324Simp#include <vm/vm.h> 75155324Simp#include <vm/pmap.h> 76155324Simp#include <vm/vm_object.h> 77155324Simp#include <vm/vm_page.h> 78155324Simp#include <vm/vm_pager.h> 79155324Simp#include <vm/vm_map.h> 80155324Simp#include <machine/pmap.h> 81155324Simp#include <machine/vmparam.h> 82155324Simp#include <machine/pcb.h> 83155324Simp#include <machine/undefined.h> 84155324Simp#include <machine/machdep.h> 85155324Simp#include <machine/metadata.h> 86155324Simp#include <machine/armreg.h> 87155324Simp#include <machine/bus.h> 88155324Simp#include <sys/reboot.h> 89155324Simp 90185305Simp#include <arm/at91/at91board.h> 91213496Scognet#include <arm/at91/at91var.h> 92155324Simp#include <arm/at91/at91rm92reg.h> 93213496Scognet#include <arm/at91/at91sam9g20reg.h> 94155324Simp 95155324Simp#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 96185270Simp#define KERNEL_PT_KERN 1 97159556Scognet#define KERNEL_PT_KERN_NUM 22 98155324Simp#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */ 99155324Simp#define KERNEL_PT_AFKERNEL_NUM 5 100155324Simp 101155324Simp/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 102155324Simp#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 103155324Simp 104155324Simp/* Define various stack sizes in pages */ 105155324Simp#define IRQ_STACK_SIZE 1 106155324Simp#define ABT_STACK_SIZE 1 107155324Simp#define UND_STACK_SIZE 1 108155324Simp 109155324Simpextern u_int data_abort_handler_address; 110155324Simpextern u_int prefetch_abort_handler_address; 111155324Simpextern u_int undefined_handler_address; 112155324Simp 113155324Simpstruct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 114155324Simp 115155324Simpextern void *_end; 116155324Simp 117155324Simpextern int *end; 118155324Simp 119155324Simpstruct pcpu __pcpu; 120155324Simpstruct pcpu *pcpup = &__pcpu; 121155324Simp 122155324Simp/* Physical and virtual addresses for some global pages */ 123155324Simp 124155324Simpvm_paddr_t phys_avail[10]; 125155324Simpvm_paddr_t dump_avail[4]; 126155324Simpvm_offset_t physical_pages; 127155324Simp 128155324Simpstruct pv_addr systempage; 129155324Simpstruct pv_addr msgbufpv; 130155324Simpstruct pv_addr irqstack; 131155324Simpstruct pv_addr undstack; 132155324Simpstruct pv_addr abtstack; 133155324Simpstruct pv_addr kernelstack; 134155324Simp 135185288Simpstatic void *boot_arg1; 136185288Simpstatic void *boot_arg2; 137185288Simp 138155324Simpstatic struct trapframe proc0_tf; 139155324Simp 140155324Simp/* Static device mappings. */ 141213496Scognetconst struct pmap_devmap at91_devmap[] = { 142185270Simp /* 143155324Simp * Map the on-board devices VA == PA so that we can access them 144155324Simp * with the MMU on or off. 145155324Simp */ 146156832Simp { 147156832Simp /* 148156832Simp * This at least maps the interrupt controller, the UART 149156832Simp * and the timer. Other devices should use newbus to 150156832Simp * map their memory anyway. 151156832Simp */ 152161704Scognet 0xdff00000, 153156832Simp 0xfff00000, 154213496Scognet 0x00100000, 155185270Simp VM_PROT_READ|VM_PROT_WRITE, 156156832Simp PTE_NOCACHE, 157156832Simp }, 158213496Scognet /* We can't just map the OHCI registers VA == PA, because 159213496Scognet * AT91xx_xxx_BASE belongs to the userland address space. 160160374Scognet * We could just choose a different virtual address, but a better 161160374Scognet * solution would probably be to just use pmap_mapdev() to allocate 162160374Scognet * KVA, as we don't need the OHCI controller before the vm 163160374Scognet * initialization is done. However, the AT91 resource allocation 164160374Scognet * system doesn't know how to use pmap_mapdev() yet. 165213496Scognet * Care must be taken to ensure PA and VM address do not overlap 166213496Scognet * between entries. 167160374Scognet */ 168156832Simp { 169156832Simp /* 170156832Simp * Add the ohci controller, and anything else that might be 171156832Simp * on this chip select for a VA/PA mapping. 172156832Simp */ 173213496Scognet /* Internal Memory 1MB */ 174156832Simp AT91RM92_OHCI_BASE, 175171673Simp AT91RM92_OHCI_PA_BASE, 176213496Scognet 0x00100000, 177185270Simp VM_PROT_READ|VM_PROT_WRITE, 178156832Simp PTE_NOCACHE, 179156832Simp }, 180156832Simp { 181213496Scognet /* CompactFlash controller. Portion of EBI CS4 1MB */ 182191408Sstas AT91RM92_CF_BASE, 183191408Sstas AT91RM92_CF_PA_BASE, 184213496Scognet 0x00100000, 185191408Sstas VM_PROT_READ|VM_PROT_WRITE, 186191408Sstas PTE_NOCACHE, 187191408Sstas }, 188213496Scognet /* The next two should be good for the 9260, 9261 and 9G20 since 189213496Scognet * addresses mapping is the same. */ 190191408Sstas { 191213496Scognet /* Internal Memory 1MB */ 192213496Scognet AT91SAM9G20_OHCI_BASE, 193213496Scognet AT91SAM9G20_OHCI_PA_BASE, 194213496Scognet 0x00100000, 195213496Scognet VM_PROT_READ|VM_PROT_WRITE, 196213496Scognet PTE_NOCACHE, 197213496Scognet }, 198213496Scognet { 199213496Scognet /* EBI CS3 256MB */ 200213496Scognet AT91SAM9G20_NAND_BASE, 201213496Scognet AT91SAM9G20_NAND_PA_BASE, 202213496Scognet AT91SAM9G20_NAND_SIZE, 203213496Scognet VM_PROT_READ|VM_PROT_WRITE, 204213496Scognet PTE_NOCACHE, 205213496Scognet }, 206213496Scognet { 0, 0, 0, 0, 0, } 207155324Simp}; 208155324Simp 209185305Simplong 210185305Simpat91_ramsize(void) 211159795Simp{ 212213496Scognet uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE); 213159795Simp uint32_t cr, mr; 214160363Simp int banks, rows, cols, bw; 215185270Simp 216213496Scognet if (at91_is_rm92()) { 217213496Scognet SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE); 218213496Scognet cr = SDRAMC[AT91RM92_SDRAMC_CR / 4]; 219213496Scognet mr = SDRAMC[AT91RM92_SDRAMC_MR / 4]; 220213496Scognet banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1; 221213496Scognet rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11; 222213496Scognet cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8; 223213496Scognet bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2; 224213496Scognet } else { 225213496Scognet /* This should be good for the 9260, 9261 and 9G20 as addresses 226213496Scognet * and registers are the same */ 227213496Scognet SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE); 228213496Scognet cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4]; 229213496Scognet mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4]; 230213496Scognet banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1; 231213496Scognet rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11; 232213496Scognet cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8; 233213496Scognet bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2; 234213496Scognet } 235213496Scognet 236218667Scognet return (1 << (cols + rows + banks + bw)); 237159795Simp} 238159795Simp 239155324Simpvoid * 240155324Simpinitarm(void *arg, void *arg2) 241155324Simp{ 242155324Simp struct pv_addr kernel_l1pt; 243194784Sjeff struct pv_addr dpcpu; 244177883Simp int loop, i; 245155324Simp u_int l1pagetable; 246155324Simp vm_offset_t freemempos; 247155324Simp vm_offset_t afterkern; 248159795Simp uint32_t memsize; 249157024Scognet vm_offset_t lastaddr; 250155324Simp 251185288Simp boot_arg1 = arg; 252185288Simp boot_arg2 = arg2; 253155324Simp set_cpufuncs(); 254177883Simp lastaddr = fake_preload_metadata(); 255155324Simp pcpu_init(pcpup, 0, sizeof(struct pcpu)); 256155324Simp PCPU_SET(curthread, &thread0); 257155324Simp 258218913Scognet /* Do basic tuning, hz etc */ 259218913Scognet init_param1(); 260218913Scognet 261157024Scognet freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 262155324Simp /* Define a macro to simplify memory allocation */ 263155324Simp#define valloc_pages(var, np) \ 264155324Simp alloc_pages((var).pv_va, (np)); \ 265155324Simp (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); 266155324Simp 267155324Simp#define alloc_pages(var, np) \ 268155324Simp (var) = freemempos; \ 269155324Simp freemempos += (np * PAGE_SIZE); \ 270155324Simp memset((char *)(var), 0, ((np) * PAGE_SIZE)); 271155324Simp 272155324Simp while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 273155324Simp freemempos += PAGE_SIZE; 274155324Simp valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 275155324Simp for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 276155324Simp if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 277155324Simp valloc_pages(kernel_pt_table[loop], 278155324Simp L2_TABLE_SIZE / PAGE_SIZE); 279155324Simp } else { 280155324Simp kernel_pt_table[loop].pv_va = freemempos - 281155324Simp (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 282155324Simp L2_TABLE_SIZE_REAL; 283185270Simp kernel_pt_table[loop].pv_pa = 284155324Simp kernel_pt_table[loop].pv_va - KERNVIRTADDR + 285155324Simp KERNPHYSADDR; 286155324Simp } 287155324Simp i++; 288155324Simp } 289155324Simp /* 290155324Simp * Allocate a page for the system page mapped to V0x00000000 291155324Simp * This page will just contain the system vectors and can be 292155324Simp * shared by all processes. 293155324Simp */ 294155324Simp valloc_pages(systempage, 1); 295155324Simp 296194784Sjeff /* Allocate dynamic per-cpu area. */ 297194784Sjeff valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 298194784Sjeff dpcpu_init((void *)dpcpu.pv_va, 0); 299194784Sjeff 300155324Simp /* Allocate stacks for all modes */ 301155324Simp valloc_pages(irqstack, IRQ_STACK_SIZE); 302155324Simp valloc_pages(abtstack, ABT_STACK_SIZE); 303155324Simp valloc_pages(undstack, UND_STACK_SIZE); 304155324Simp valloc_pages(kernelstack, KSTACK_PAGES); 305217688Spluknet valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 306185287Simp 307155324Simp /* 308155324Simp * Now we start construction of the L1 page table 309155324Simp * We start by mapping the L2 page tables into the L1. 310155324Simp * This means that we can replace L1 mappings later on if necessary 311155324Simp */ 312155324Simp l1pagetable = kernel_l1pt.pv_va; 313155324Simp 314155324Simp /* Map the L2 pages tables in the L1 page table */ 315161704Scognet pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 316155324Simp &kernel_pt_table[KERNEL_PT_SYS]); 317155324Simp for (i = 0; i < KERNEL_PT_KERN_NUM; i++) 318185266Simp pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE, 319155324Simp &kernel_pt_table[KERNEL_PT_KERN + i]); 320172943Scognet pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 321177883Simp (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1), 322155324Simp VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 323185270Simp afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1)); 324155324Simp for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 325185266Simp pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE, 326155324Simp &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 327155324Simp } 328155324Simp 329155324Simp /* Map the vector page. */ 330161704Scognet pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 331155324Simp VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 332195256Sraj 333195256Sraj /* Map the DPCPU pages */ 334195256Sraj pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE, 335195256Sraj VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 336195256Sraj 337155324Simp /* Map the stack pages */ 338155324Simp pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 339155324Simp IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 340155324Simp pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 341155324Simp ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 342155324Simp pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 343155324Simp UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 344155324Simp pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 345155324Simp KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 346155324Simp 347155324Simp pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 348155324Simp L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 349155324Simp pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa, 350217688Spluknet msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 351155324Simp 352155324Simp for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 353155324Simp pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, 354155324Simp kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, 355155324Simp VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 356155324Simp } 357155324Simp 358213496Scognet pmap_devmap_bootstrap(l1pagetable, at91_devmap); 359155324Simp cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 360155324Simp setttb(kernel_l1pt.pv_pa); 361155324Simp cpu_tlb_flushID(); 362155324Simp cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 363213496Scognet 364157029Scognet cninit(); 365213496Scognet 366213496Scognet /* Get chip id so device drivers know about differences */ 367213496Scognet at91_chip_id = *(volatile uint32_t *) 368213496Scognet (AT91_BASE + AT91_DBGU_BASE + DBGU_C1R); 369213496Scognet 370159795Simp memsize = board_init(); 371159814Simp physmem = memsize / PAGE_SIZE; 372159814Simp 373155324Simp /* 374155324Simp * Pages were allocated during the secondary bootstrap for the 375155324Simp * stacks for different CPU modes. 376155324Simp * We must now set the r13 registers in the different CPU modes to 377155324Simp * point to these stacks. 378155324Simp * Since the ARM stacks use STMFD etc. we must set r13 to the top end 379155324Simp * of the stack memory. 380155324Simp */ 381155324Simp cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 382155324Simp set_stackptr(PSR_IRQ32_MODE, 383155324Simp irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 384155324Simp set_stackptr(PSR_ABT32_MODE, 385155324Simp abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 386155324Simp set_stackptr(PSR_UND32_MODE, 387155324Simp undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 388155324Simp 389155324Simp /* 390155324Simp * We must now clean the cache again.... 391155324Simp * Cleaning may be done by reading new data to displace any 392155324Simp * dirty data in the cache. This will have happened in setttb() 393155324Simp * but since we are boot strapping the addresses used for the read 394155324Simp * may have just been remapped and thus the cache could be out 395155324Simp * of sync. A re-clean after the switch will cure this. 396185513Sstas * After booting there are no gross relocations of the kernel thus 397155324Simp * this problem will not occur after initarm(). 398155324Simp */ 399155324Simp cpu_idcache_wbinv_all(); 400155324Simp 401155324Simp /* Set stack for exception handlers */ 402185270Simp 403155324Simp data_abort_handler_address = (u_int)data_abort_handler; 404155324Simp prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 405155324Simp undefined_handler_address = (u_int)undefinedinstruction_bounce; 406155324Simp undefined_init(); 407185270Simp 408173361Skib proc_linkup0(&proc0, &thread0); 409155324Simp thread0.td_kstack = kernelstack.pv_va; 410155324Simp thread0.td_pcb = (struct pcb *) 411155324Simp (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 412155324Simp thread0.td_pcb->pcb_flags = 0; 413155324Simp thread0.td_frame = &proc0_tf; 414155324Simp pcpup->pc_curpcb = thread0.td_pcb; 415185270Simp 416161704Scognet arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 417155324Simp 418185266Simp pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1); 419185287Simp 420161105Scognet /* 421161105Scognet * ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before 422161105Scognet * calling pmap_bootstrap. 423161105Scognet */ 424172943Scognet dump_avail[0] = PHYSADDR; 425172943Scognet dump_avail[1] = PHYSADDR + memsize; 426161105Scognet dump_avail[2] = 0; 427161105Scognet dump_avail[3] = 0; 428185270Simp 429259038Simp /* Use the full 256MB of KVA we have available, regardless of memory size */ 430259038Simp pmap_bootstrap(freemempos, KERNVIRTADDR + (256 << 20), &kernel_l1pt); 431155324Simp msgbufp = (void*)msgbufpv.pv_va; 432217688Spluknet msgbufinit(msgbufp, msgbufsize); 433155324Simp mutex_init(); 434185270Simp 435155324Simp i = 0; 436172943Scognet#if PHYSADDR != KERNPHYSADDR 437172943Scognet phys_avail[i++] = PHYSADDR; 438172943Scognet phys_avail[i++] = KERNPHYSADDR; 439172943Scognet#endif 440172943Scognet phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR; 441172989Scognet phys_avail[i++] = PHYSADDR + memsize; 442172943Scognet phys_avail[i++] = 0; 443172943Scognet phys_avail[i++] = 0; 444159814Simp init_param2(physmem); 445155324Simp kdb_init(); 446155324Simp return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 447155324Simp sizeof(struct pcb))); 448155324Simp} 449