xen-os.h revision 184235 
1/******************************************************************************
2 * os.h
3 *
4 * random collection of macros and definition
5 */
6
7#ifndef _XEN_OS_H_
8#define _XEN_OS_H_
9#include <machine/param.h>
10#ifdef PAE
11#define CONFIG_X86_PAE
12#endif
13
14#if defined(XEN) && !defined(__XEN_INTERFACE_VERSION__)
15/*
16 * Can update to a more recent version when we implement
17 * the hypercall page
18 */
19#define  __XEN_INTERFACE_VERSION__ 0x00030204
20#endif
21
22#include <xen/interface/xen.h>
23
24/* Force a proper event-channel callback from Xen. */
25void force_evtchn_callback(void);
26
27#ifndef vtophys
28#include <vm/vm.h>
29#include <vm/vm_param.h>
30#include <vm/pmap.h>
31#endif
32
33extern int gdtset;
34#ifdef SMP
35#include <sys/time.h> /* XXX for pcpu.h */
36#include <sys/pcpu.h> /* XXX for PCPU_GET */
37static inline int
38smp_processor_id(void)
39{
40    if (__predict_true(gdtset))
41	return PCPU_GET(cpuid);
42    return 0;
43}
44
45#else
46#define smp_processor_id() 0
47#endif
48
49#ifndef NULL
50#define NULL (void *)0
51#endif
52
53#ifndef PANIC_IF
54#define PANIC_IF(exp) if (unlikely(exp)) {printk("panic - %s: %s:%d\n",#exp, __FILE__, __LINE__); panic("%s: %s:%d", #exp, __FILE__, __LINE__);}
55#endif
56
57extern shared_info_t *HYPERVISOR_shared_info;
58
59/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented
60   a mechanism by which the user can annotate likely branch directions and
61   expect the blocks to be reordered appropriately.  Define __builtin_expect
62   to nothing for earlier compilers.  */
63
64/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
65static inline void rep_nop(void)
66{
67    __asm__ __volatile__ ( "rep;nop" : : : "memory" );
68}
69#define cpu_relax() rep_nop()
70
71
72#if __GNUC__ == 2 && __GNUC_MINOR__ < 96
73#define __builtin_expect(x, expected_value) (x)
74#endif
75
76#define per_cpu(var, cpu)           (pcpu_find((cpu))->pc_ ## var)
77
78/* crude memory allocator for memory allocation early in
79 *  boot
80 */
81void *bootmem_alloc(unsigned int size);
82void bootmem_free(void *ptr, unsigned int size);
83
84
85/* Everything below this point is not included by assembler (.S) files. */
86#ifndef __ASSEMBLY__
87#include <sys/types.h>
88
89void printk(const char *fmt, ...);
90
91/* some function prototypes */
92void trap_init(void);
93
94/*
95 * STI/CLI equivalents. These basically set and clear the virtual
96 * event_enable flag in teh shared_info structure. Note that when
97 * the enable bit is set, there may be pending events to be handled.
98 * We may therefore call into do_hypervisor_callback() directly.
99 */
100#define likely(x)  __builtin_expect((x),1)
101#define unlikely(x)  __builtin_expect((x),0)
102
103
104
105#define __cli()                                                         \
106do {                                                                    \
107        vcpu_info_t *_vcpu;                                             \
108        _vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
109        _vcpu->evtchn_upcall_mask = 1;                                  \
110        barrier();                                                      \
111} while (0)
112
113#define __sti()                                                         \
114do {                                                                    \
115        vcpu_info_t *_vcpu;                                             \
116        barrier();                                                      \
117        _vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
118        _vcpu->evtchn_upcall_mask = 0;                                  \
119        barrier(); /* unmask then check (avoid races) */                \
120        if ( unlikely(_vcpu->evtchn_upcall_pending) )                   \
121                force_evtchn_callback();                                \
122} while (0)
123
124#define __restore_flags(x)                                              \
125do {                                                                    \
126        vcpu_info_t *_vcpu;                                             \
127        barrier();                                                      \
128        _vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
129        if ((_vcpu->evtchn_upcall_mask = (x)) == 0) {                   \
130                barrier(); /* unmask then check (avoid races) */        \
131                if ( unlikely(_vcpu->evtchn_upcall_pending) )           \
132                        force_evtchn_callback();                        \
133        } 								\
134} while (0)
135
136/*
137 * Add critical_{enter, exit}?
138 *
139 */
140#define __save_and_cli(x)                                               \
141do {                                                                    \
142        vcpu_info_t *_vcpu;                                             \
143        _vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
144        (x) = _vcpu->evtchn_upcall_mask;                                \
145        _vcpu->evtchn_upcall_mask = 1;                                  \
146        barrier();                                                      \
147} while (0)
148
149
150#define cli() __cli()
151#define sti() __sti()
152#define save_flags(x) __save_flags(x)
153#define restore_flags(x) __restore_flags(x)
154#define save_and_cli(x) __save_and_cli(x)
155
156#define local_irq_save(x)       __save_and_cli(x)
157#define local_irq_restore(x)    __restore_flags(x)
158#define local_irq_disable()     __cli()
159#define local_irq_enable()      __sti()
160
161#define mtx_lock_irqsave(lock, x) {local_irq_save((x)); mtx_lock_spin((lock));}
162#define mtx_unlock_irqrestore(lock, x) {mtx_unlock_spin((lock)); local_irq_restore((x)); }
163#define spin_lock_irqsave mtx_lock_irqsave
164#define spin_unlock_irqrestore mtx_unlock_irqrestore
165
166
167#ifndef mb
168#define mb() __asm__ __volatile__("lock; addl $0, 0(%%esp)": : :"memory")
169#endif
170#ifndef rmb
171#define rmb() mb()
172#endif
173#ifndef wmb
174#define wmb() barrier()
175#endif
176#ifdef SMP
177#define smp_mb() mb()
178#define smp_rmb() rmb()
179#define smp_wmb() wmb()
180#define smp_read_barrier_depends()      read_barrier_depends()
181#define set_mb(var, value) do { xchg(&var, value); } while (0)
182#else
183#define smp_mb()        barrier()
184#define smp_rmb()       barrier()
185#define smp_wmb()       barrier()
186#define smp_read_barrier_depends()      do { } while(0)
187#define set_mb(var, value) do { var = value; barrier(); } while (0)
188#endif
189
190
191/* This is a barrier for the compiler only, NOT the processor! */
192#define barrier() __asm__ __volatile__("": : :"memory")
193
194#define LOCK_PREFIX ""
195#define LOCK ""
196#define ADDR (*(volatile long *) addr)
197/*
198 * Make sure gcc doesn't try to be clever and move things around
199 * on us. We need to use _exactly_ the address the user gave us,
200 * not some alias that contains the same information.
201 */
202typedef struct { volatile int counter; } atomic_t;
203
204
205
206#define xen_xchg(ptr,v) \
207        ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
208struct __xchg_dummy { unsigned long a[100]; };
209#define __xg(x) ((volatile struct __xchg_dummy *)(x))
210static __inline unsigned long __xchg(unsigned long x, volatile void * ptr,
211                                   int size)
212{
213    switch (size) {
214    case 1:
215        __asm__ __volatile__("xchgb %b0,%1"
216                             :"=q" (x)
217                             :"m" (*__xg(ptr)), "0" (x)
218                             :"memory");
219        break;
220    case 2:
221        __asm__ __volatile__("xchgw %w0,%1"
222                             :"=r" (x)
223                             :"m" (*__xg(ptr)), "0" (x)
224                             :"memory");
225        break;
226    case 4:
227        __asm__ __volatile__("xchgl %0,%1"
228                             :"=r" (x)
229                             :"m" (*__xg(ptr)), "0" (x)
230                             :"memory");
231        break;
232    }
233    return x;
234}
235
236/**
237 * test_and_clear_bit - Clear a bit and return its old value
238 * @nr: Bit to set
239 * @addr: Address to count from
240 *
241 * This operation is atomic and cannot be reordered.
242 * It also implies a memory barrier.
243 */
244static __inline int test_and_clear_bit(int nr, volatile void * addr)
245{
246        int oldbit;
247
248        __asm__ __volatile__( LOCK_PREFIX
249                "btrl %2,%1\n\tsbbl %0,%0"
250                :"=r" (oldbit),"=m" (ADDR)
251                :"Ir" (nr) : "memory");
252        return oldbit;
253}
254
255static __inline int constant_test_bit(int nr, const volatile void * addr)
256{
257    return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
258}
259
260static __inline int variable_test_bit(int nr, volatile void * addr)
261{
262    int oldbit;
263
264    __asm__ __volatile__(
265        "btl %2,%1\n\tsbbl %0,%0"
266        :"=r" (oldbit)
267        :"m" (ADDR),"Ir" (nr));
268    return oldbit;
269}
270
271#define test_bit(nr,addr) \
272(__builtin_constant_p(nr) ? \
273 constant_test_bit((nr),(addr)) : \
274 variable_test_bit((nr),(addr)))
275
276
277/**
278 * set_bit - Atomically set a bit in memory
279 * @nr: the bit to set
280 * @addr: the address to start counting from
281 *
282 * This function is atomic and may not be reordered.  See __set_bit()
283 * if you do not require the atomic guarantees.
284 * Note that @nr may be almost arbitrarily large; this function is not
285 * restricted to acting on a single-word quantity.
286 */
287static __inline__ void set_bit(int nr, volatile void * addr)
288{
289        __asm__ __volatile__( LOCK_PREFIX
290                "btsl %1,%0"
291                :"=m" (ADDR)
292                :"Ir" (nr));
293}
294
295/**
296 * clear_bit - Clears a bit in memory
297 * @nr: Bit to clear
298 * @addr: Address to start counting from
299 *
300 * clear_bit() is atomic and may not be reordered.  However, it does
301 * not contain a memory barrier, so if it is used for locking purposes,
302 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
303 * in order to ensure changes are visible on other processors.
304 */
305static __inline__ void clear_bit(int nr, volatile void * addr)
306{
307        __asm__ __volatile__( LOCK_PREFIX
308                "btrl %1,%0"
309                :"=m" (ADDR)
310                :"Ir" (nr));
311}
312
313/**
314 * atomic_inc - increment atomic variable
315 * @v: pointer of type atomic_t
316 *
317 * Atomically increments @v by 1.  Note that the guaranteed
318 * useful range of an atomic_t is only 24 bits.
319 */
320static __inline__ void atomic_inc(atomic_t *v)
321{
322        __asm__ __volatile__(
323                LOCK "incl %0"
324                :"=m" (v->counter)
325                :"m" (v->counter));
326}
327
328
329#define rdtscll(val) \
330     __asm__ __volatile__("rdtsc" : "=A" (val))
331
332
333
334/*
335 * Kernel pointers have redundant information, so we can use a
336 * scheme where we can return either an error code or a dentry
337 * pointer with the same return value.
338 *
339 * This should be a per-architecture thing, to allow different
340 * error and pointer decisions.
341 */
342#define IS_ERR_VALUE(x) unlikely((x) > (unsigned long)-1000L)
343
344static inline void *ERR_PTR(long error)
345{
346	return (void *) error;
347}
348
349static inline long PTR_ERR(const void *ptr)
350{
351	return (long) ptr;
352}
353
354static inline long IS_ERR(const void *ptr)
355{
356	return IS_ERR_VALUE((unsigned long)ptr);
357}
358
359#endif /* !__ASSEMBLY__ */
360
361#endif /* _OS_H_ */
362