machdep.c revision 287147
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: releng/9.3/sys/amd64/amd64/machdep.c 287147 2015-08-25 20:49:05Z delphij $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57#include "opt_kdtrace.h" 58 59#include <sys/param.h> 60#include <sys/proc.h> 61#include <sys/systm.h> 62#include <sys/bio.h> 63#include <sys/buf.h> 64#include <sys/bus.h> 65#include <sys/callout.h> 66#include <sys/cons.h> 67#include <sys/cpu.h> 68#include <sys/eventhandler.h> 69#include <sys/exec.h> 70#include <sys/imgact.h> 71#include <sys/kdb.h> 72#include <sys/kernel.h> 73#include <sys/ktr.h> 74#include <sys/linker.h> 75#include <sys/lock.h> 76#include <sys/malloc.h> 77#include <sys/memrange.h> 78#include <sys/msgbuf.h> 79#include <sys/mutex.h> 80#include <sys/pcpu.h> 81#include <sys/ptrace.h> 82#include <sys/reboot.h> 83#include <sys/sched.h> 84#include <sys/signalvar.h> 85#ifdef SMP 86#include <sys/smp.h> 87#endif 88#include <sys/syscallsubr.h> 89#include <sys/sysctl.h> 90#include <sys/sysent.h> 91#include <sys/sysproto.h> 92#include <sys/ucontext.h> 93#include <sys/vmmeter.h> 94 95#include <vm/vm.h> 96#include <vm/vm_extern.h> 97#include <vm/vm_kern.h> 98#include <vm/vm_page.h> 99#include <vm/vm_map.h> 100#include <vm/vm_object.h> 101#include <vm/vm_pager.h> 102#include <vm/vm_param.h> 103 104#ifdef DDB 105#ifndef KDB 106#error KDB must be enabled in order for DDB to work! 107#endif 108#include <ddb/ddb.h> 109#include <ddb/db_sym.h> 110#endif 111 112#include <net/netisr.h> 113 114#include <machine/clock.h> 115#include <machine/cpu.h> 116#include <machine/cputypes.h> 117#include <machine/intr_machdep.h> 118#include <x86/mca.h> 119#include <machine/md_var.h> 120#include <machine/metadata.h> 121#include <machine/mp_watchdog.h> 122#include <machine/pc/bios.h> 123#include <machine/pcb.h> 124#include <machine/proc.h> 125#include <machine/reg.h> 126#include <machine/sigframe.h> 127#include <machine/specialreg.h> 128#ifdef PERFMON 129#include <machine/perfmon.h> 130#endif 131#include <machine/tss.h> 132#ifdef SMP 133#include <machine/smp.h> 134#endif 135 136#ifdef DEV_ATPIC 137#include <x86/isa/icu.h> 138#else 139#include <machine/apicvar.h> 140#endif 141 142#include <isa/isareg.h> 143#include <isa/rtc.h> 144 145/* Sanity check for __curthread() */ 146CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 147 148extern u_int64_t hammer_time(u_int64_t, u_int64_t); 149 150extern void printcpuinfo(void); /* XXX header file */ 151extern void identify_cpu(void); 152extern void panicifcpuunsupported(void); 153 154#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 155#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 156 157static void cpu_startup(void *); 158static void get_fpcontext(struct thread *td, mcontext_t *mcp, 159 char *xfpusave, size_t xfpusave_len); 160static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 161 char *xfpustate, size_t xfpustate_len); 162SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 163 164/* 165 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 166 * the physical address at which the kernel is loaded. 167 */ 168extern char kernphys[]; 169#ifdef DDB 170extern vm_offset_t ksym_start, ksym_end; 171#endif 172 173struct msgbuf *msgbufp; 174 175/* Intel ICH registers */ 176#define ICH_PMBASE 0x400 177#define ICH_SMI_EN ICH_PMBASE + 0x30 178 179int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 180 181int cold = 1; 182 183long Maxmem = 0; 184long realmem = 0; 185 186/* 187 * The number of PHYSMAP entries must be one less than the number of 188 * PHYSSEG entries because the PHYSMAP entry that spans the largest 189 * physical address that is accessible by ISA DMA is split into two 190 * PHYSSEG entries. 191 */ 192#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 193 194vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 195vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 196 197/* must be 2 less so 0 0 can signal end of chunks */ 198#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 199#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 200 201struct kva_md_info kmi; 202 203static struct trapframe proc0_tf; 204struct region_descriptor r_gdt, r_idt; 205 206struct pcpu __pcpu[MAXCPU]; 207 208struct mtx icu_lock; 209 210struct mem_range_softc mem_range_softc; 211 212struct mtx dt_lock; /* lock for GDT and LDT */ 213 214static void 215cpu_startup(dummy) 216 void *dummy; 217{ 218 uintmax_t memsize; 219 char *sysenv; 220 221 /* 222 * On MacBooks, we need to disallow the legacy USB circuit to 223 * generate an SMI# because this can cause several problems, 224 * namely: incorrect CPU frequency detection and failure to 225 * start the APs. 226 * We do this by disabling a bit in the SMI_EN (SMI Control and 227 * Enable register) of the Intel ICH LPC Interface Bridge. 228 */ 229 sysenv = getenv("smbios.system.product"); 230 if (sysenv != NULL) { 231 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 232 strncmp(sysenv, "MacBook3,1", 10) == 0 || 233 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 234 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 235 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 236 strncmp(sysenv, "Macmini1,1", 10) == 0) { 237 if (bootverbose) 238 printf("Disabling LEGACY_USB_EN bit on " 239 "Intel ICH.\n"); 240 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 241 } 242 freeenv(sysenv); 243 } 244 245 /* 246 * Good {morning,afternoon,evening,night}. 247 */ 248 startrtclock(); 249 printcpuinfo(); 250 panicifcpuunsupported(); 251#ifdef PERFMON 252 perfmon_init(); 253#endif 254 realmem = Maxmem; 255 256 /* 257 * Display physical memory if SMBIOS reports reasonable amount. 258 */ 259 memsize = 0; 260 sysenv = getenv("smbios.memory.enabled"); 261 if (sysenv != NULL) { 262 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 263 freeenv(sysenv); 264 } 265 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 266 memsize = ptoa((uintmax_t)Maxmem); 267 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 268 269 /* 270 * Display any holes after the first chunk of extended memory. 271 */ 272 if (bootverbose) { 273 int indx; 274 275 printf("Physical memory chunk(s):\n"); 276 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 277 vm_paddr_t size; 278 279 size = phys_avail[indx + 1] - phys_avail[indx]; 280 printf( 281 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 282 (uintmax_t)phys_avail[indx], 283 (uintmax_t)phys_avail[indx + 1] - 1, 284 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 285 } 286 } 287 288 vm_ksubmap_init(&kmi); 289 290 printf("avail memory = %ju (%ju MB)\n", 291 ptoa((uintmax_t)cnt.v_free_count), 292 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 293 294 /* 295 * Set up buffers, so they can be used to read disk labels. 296 */ 297 bufinit(); 298 vm_pager_bufferinit(); 299 300 cpu_setregs(); 301 302 /* 303 * Add BSP as an interrupt target. 304 */ 305 intr_add_cpu(0); 306} 307 308/* 309 * Send an interrupt to process. 310 * 311 * Stack is set up to allow sigcode stored 312 * at top to call routine, followed by call 313 * to sigreturn routine below. After sigreturn 314 * resets the signal mask, the stack, and the 315 * frame pointer, it returns to the user 316 * specified pc, psl. 317 */ 318void 319sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 320{ 321 struct sigframe sf, *sfp; 322 struct pcb *pcb; 323 struct proc *p; 324 struct thread *td; 325 struct sigacts *psp; 326 char *sp; 327 struct trapframe *regs; 328 char *xfpusave; 329 size_t xfpusave_len; 330 int sig; 331 int oonstack; 332 333 td = curthread; 334 pcb = td->td_pcb; 335 p = td->td_proc; 336 PROC_LOCK_ASSERT(p, MA_OWNED); 337 sig = ksi->ksi_signo; 338 psp = p->p_sigacts; 339 mtx_assert(&psp->ps_mtx, MA_OWNED); 340 regs = td->td_frame; 341 oonstack = sigonstack(regs->tf_rsp); 342 343 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 344 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 345 xfpusave = __builtin_alloca(xfpusave_len); 346 } else { 347 xfpusave_len = 0; 348 xfpusave = NULL; 349 } 350 351 /* Save user context. */ 352 bzero(&sf, sizeof(sf)); 353 sf.sf_uc.uc_sigmask = *mask; 354 sf.sf_uc.uc_stack = td->td_sigstk; 355 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 356 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 357 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 358 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 359 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 360 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 361 fpstate_drop(td); 362 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 363 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 364 bzero(sf.sf_uc.uc_mcontext.mc_spare, 365 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 366 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 367 368 /* Allocate space for the signal handler context. */ 369 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 370 SIGISMEMBER(psp->ps_sigonstack, sig)) { 371 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 372#if defined(COMPAT_43) 373 td->td_sigstk.ss_flags |= SS_ONSTACK; 374#endif 375 } else 376 sp = (char *)regs->tf_rsp - 128; 377 if (xfpusave != NULL) { 378 sp -= xfpusave_len; 379 sp = (char *)((unsigned long)sp & ~0x3Ful); 380 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 381 } 382 sp -= sizeof(struct sigframe); 383 /* Align to 16 bytes. */ 384 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 385 386 /* Translate the signal if appropriate. */ 387 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 388 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 389 390 /* Build the argument list for the signal handler. */ 391 regs->tf_rdi = sig; /* arg 1 in %rdi */ 392 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 393 bzero(&sf.sf_si, sizeof(sf.sf_si)); 394 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 395 /* Signal handler installed with SA_SIGINFO. */ 396 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 397 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 398 399 /* Fill in POSIX parts */ 400 sf.sf_si = ksi->ksi_info; 401 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 402 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 403 } else { 404 /* Old FreeBSD-style arguments. */ 405 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 406 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 407 sf.sf_ahu.sf_handler = catcher; 408 } 409 mtx_unlock(&psp->ps_mtx); 410 PROC_UNLOCK(p); 411 412 /* 413 * Copy the sigframe out to the user's stack. 414 */ 415 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 416 (xfpusave != NULL && copyout(xfpusave, 417 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 418 != 0)) { 419#ifdef DEBUG 420 printf("process %ld has trashed its stack\n", (long)p->p_pid); 421#endif 422 PROC_LOCK(p); 423 sigexit(td, SIGILL); 424 } 425 426 regs->tf_rsp = (long)sfp; 427 regs->tf_rip = p->p_sysent->sv_sigcode_base; 428 regs->tf_rflags &= ~(PSL_T | PSL_D); 429 regs->tf_cs = _ucodesel; 430 regs->tf_ds = _udatasel; 431 regs->tf_ss = _udatasel; 432 regs->tf_es = _udatasel; 433 regs->tf_fs = _ufssel; 434 regs->tf_gs = _ugssel; 435 regs->tf_flags = TF_HASSEGS; 436 set_pcb_flags(pcb, PCB_FULL_IRET); 437 PROC_LOCK(p); 438 mtx_lock(&psp->ps_mtx); 439} 440 441/* 442 * System call to cleanup state after a signal 443 * has been taken. Reset signal mask and 444 * stack state from context left by sendsig (above). 445 * Return to previous pc and psl as specified by 446 * context left by sendsig. Check carefully to 447 * make sure that the user has not modified the 448 * state to gain improper privileges. 449 * 450 * MPSAFE 451 */ 452int 453sys_sigreturn(td, uap) 454 struct thread *td; 455 struct sigreturn_args /* { 456 const struct __ucontext *sigcntxp; 457 } */ *uap; 458{ 459 ucontext_t uc; 460 struct pcb *pcb; 461 struct proc *p; 462 struct trapframe *regs; 463 ucontext_t *ucp; 464 char *xfpustate; 465 size_t xfpustate_len; 466 long rflags; 467 int cs, error, ret; 468 ksiginfo_t ksi; 469 470 pcb = td->td_pcb; 471 p = td->td_proc; 472 473 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 474 if (error != 0) { 475 uprintf("pid %d (%s): sigreturn copyin failed\n", 476 p->p_pid, td->td_name); 477 return (error); 478 } 479 ucp = &uc; 480 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 481 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 482 td->td_name, ucp->uc_mcontext.mc_flags); 483 return (EINVAL); 484 } 485 regs = td->td_frame; 486 rflags = ucp->uc_mcontext.mc_rflags; 487 /* 488 * Don't allow users to change privileged or reserved flags. 489 */ 490 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 491 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 492 td->td_name, rflags); 493 return (EINVAL); 494 } 495 496 /* 497 * Don't allow users to load a valid privileged %cs. Let the 498 * hardware check for invalid selectors, excess privilege in 499 * other selectors, invalid %eip's and invalid %esp's. 500 */ 501 cs = ucp->uc_mcontext.mc_cs; 502 if (!CS_SECURE(cs)) { 503 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 504 td->td_name, cs); 505 ksiginfo_init_trap(&ksi); 506 ksi.ksi_signo = SIGBUS; 507 ksi.ksi_code = BUS_OBJERR; 508 ksi.ksi_trapno = T_PROTFLT; 509 ksi.ksi_addr = (void *)regs->tf_rip; 510 trapsignal(td, &ksi); 511 return (EINVAL); 512 } 513 514 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 515 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 516 if (xfpustate_len > cpu_max_ext_state_size - 517 sizeof(struct savefpu)) { 518 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 519 p->p_pid, td->td_name, xfpustate_len); 520 return (EINVAL); 521 } 522 xfpustate = __builtin_alloca(xfpustate_len); 523 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 524 xfpustate, xfpustate_len); 525 if (error != 0) { 526 uprintf( 527 "pid %d (%s): sigreturn copying xfpustate failed\n", 528 p->p_pid, td->td_name); 529 return (error); 530 } 531 } else { 532 xfpustate = NULL; 533 xfpustate_len = 0; 534 } 535 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 536 if (ret != 0) { 537 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 538 p->p_pid, td->td_name, ret); 539 return (ret); 540 } 541 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 542 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 543 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 544 545#if defined(COMPAT_43) 546 if (ucp->uc_mcontext.mc_onstack & 1) 547 td->td_sigstk.ss_flags |= SS_ONSTACK; 548 else 549 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 550#endif 551 552 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 553 set_pcb_flags(pcb, PCB_FULL_IRET); 554 return (EJUSTRETURN); 555} 556 557#ifdef COMPAT_FREEBSD4 558int 559freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 560{ 561 562 return sys_sigreturn(td, (struct sigreturn_args *)uap); 563} 564#endif 565 566 567/* 568 * Machine dependent boot() routine 569 * 570 * I haven't seen anything to put here yet 571 * Possibly some stuff might be grafted back here from boot() 572 */ 573void 574cpu_boot(int howto) 575{ 576} 577 578/* 579 * Flush the D-cache for non-DMA I/O so that the I-cache can 580 * be made coherent later. 581 */ 582void 583cpu_flush_dcache(void *ptr, size_t len) 584{ 585 /* Not applicable */ 586} 587 588/* Get current clock frequency for the given cpu id. */ 589int 590cpu_est_clockrate(int cpu_id, uint64_t *rate) 591{ 592 uint64_t tsc1, tsc2; 593 uint64_t acnt, mcnt, perf; 594 register_t reg; 595 596 if (pcpu_find(cpu_id) == NULL || rate == NULL) 597 return (EINVAL); 598 599 /* 600 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 601 * DELAY(9) based logic fails. 602 */ 603 if (tsc_is_invariant && !tsc_perf_stat) 604 return (EOPNOTSUPP); 605 606#ifdef SMP 607 if (smp_cpus > 1) { 608 /* Schedule ourselves on the indicated cpu. */ 609 thread_lock(curthread); 610 sched_bind(curthread, cpu_id); 611 thread_unlock(curthread); 612 } 613#endif 614 615 /* Calibrate by measuring a short delay. */ 616 reg = intr_disable(); 617 if (tsc_is_invariant) { 618 wrmsr(MSR_MPERF, 0); 619 wrmsr(MSR_APERF, 0); 620 tsc1 = rdtsc(); 621 DELAY(1000); 622 mcnt = rdmsr(MSR_MPERF); 623 acnt = rdmsr(MSR_APERF); 624 tsc2 = rdtsc(); 625 intr_restore(reg); 626 perf = 1000 * acnt / mcnt; 627 *rate = (tsc2 - tsc1) * perf; 628 } else { 629 tsc1 = rdtsc(); 630 DELAY(1000); 631 tsc2 = rdtsc(); 632 intr_restore(reg); 633 *rate = (tsc2 - tsc1) * 1000; 634 } 635 636#ifdef SMP 637 if (smp_cpus > 1) { 638 thread_lock(curthread); 639 sched_unbind(curthread); 640 thread_unlock(curthread); 641 } 642#endif 643 644 return (0); 645} 646 647/* 648 * Shutdown the CPU as much as possible 649 */ 650void 651cpu_halt(void) 652{ 653 for (;;) 654 __asm__ ("hlt"); 655} 656 657void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 658static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 659static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 660TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 661SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 662 0, "Use MONITOR/MWAIT for short idle"); 663 664#define STATE_RUNNING 0x0 665#define STATE_MWAIT 0x1 666#define STATE_SLEEPING 0x2 667 668static void 669cpu_idle_acpi(int busy) 670{ 671 int *state; 672 673 state = (int *)PCPU_PTR(monitorbuf); 674 *state = STATE_SLEEPING; 675 disable_intr(); 676 if (sched_runnable()) 677 enable_intr(); 678 else if (cpu_idle_hook) 679 cpu_idle_hook(); 680 else 681 __asm __volatile("sti; hlt"); 682 *state = STATE_RUNNING; 683} 684 685static void 686cpu_idle_hlt(int busy) 687{ 688 int *state; 689 690 state = (int *)PCPU_PTR(monitorbuf); 691 *state = STATE_SLEEPING; 692 /* 693 * We must absolutely guarentee that hlt is the next instruction 694 * after sti or we introduce a timing window. 695 */ 696 disable_intr(); 697 if (sched_runnable()) 698 enable_intr(); 699 else 700 __asm __volatile("sti; hlt"); 701 *state = STATE_RUNNING; 702} 703 704/* 705 * MWAIT cpu power states. Lower 4 bits are sub-states. 706 */ 707#define MWAIT_C0 0xf0 708#define MWAIT_C1 0x00 709#define MWAIT_C2 0x10 710#define MWAIT_C3 0x20 711#define MWAIT_C4 0x30 712 713static void 714cpu_idle_mwait(int busy) 715{ 716 int *state; 717 718 state = (int *)PCPU_PTR(monitorbuf); 719 *state = STATE_MWAIT; 720 if (!sched_runnable()) { 721 cpu_monitor(state, 0, 0); 722 if (*state == STATE_MWAIT) 723 cpu_mwait(0, MWAIT_C1); 724 } 725 *state = STATE_RUNNING; 726} 727 728static void 729cpu_idle_spin(int busy) 730{ 731 int *state; 732 int i; 733 734 state = (int *)PCPU_PTR(monitorbuf); 735 *state = STATE_RUNNING; 736 for (i = 0; i < 1000; i++) { 737 if (sched_runnable()) 738 return; 739 cpu_spinwait(); 740 } 741} 742 743/* 744 * C1E renders the local APIC timer dead, so we disable it by 745 * reading the Interrupt Pending Message register and clearing 746 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 747 * 748 * Reference: 749 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 750 * #32559 revision 3.00+ 751 */ 752#define MSR_AMDK8_IPM 0xc0010055 753#define AMDK8_SMIONCMPHALT (1ULL << 27) 754#define AMDK8_C1EONCMPHALT (1ULL << 28) 755#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 756 757static void 758cpu_probe_amdc1e(void) 759{ 760 761 /* 762 * Detect the presence of C1E capability mostly on latest 763 * dual-cores (or future) k8 family. 764 */ 765 if (cpu_vendor_id == CPU_VENDOR_AMD && 766 (cpu_id & 0x00000f00) == 0x00000f00 && 767 (cpu_id & 0x0fff0000) >= 0x00040000) { 768 cpu_ident_amdc1e = 1; 769 } 770} 771 772void (*cpu_idle_fn)(int) = cpu_idle_acpi; 773 774void 775cpu_idle(int busy) 776{ 777 uint64_t msr; 778 779 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 780 busy, curcpu); 781#ifdef MP_WATCHDOG 782 ap_watchdog(PCPU_GET(cpuid)); 783#endif 784 /* If we are busy - try to use fast methods. */ 785 if (busy) { 786 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 787 cpu_idle_mwait(busy); 788 goto out; 789 } 790 } 791 792 /* If we have time - switch timers into idle mode. */ 793 if (!busy) { 794 critical_enter(); 795 cpu_idleclock(); 796 } 797 798 /* Apply AMD APIC timer C1E workaround. */ 799 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 800 msr = rdmsr(MSR_AMDK8_IPM); 801 if (msr & AMDK8_CMPHALT) 802 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 803 } 804 805 /* Call main idle method. */ 806 cpu_idle_fn(busy); 807 808 /* Switch timers mack into active mode. */ 809 if (!busy) { 810 cpu_activeclock(); 811 critical_exit(); 812 } 813out: 814 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 815 busy, curcpu); 816} 817 818int 819cpu_idle_wakeup(int cpu) 820{ 821 struct pcpu *pcpu; 822 int *state; 823 824 pcpu = pcpu_find(cpu); 825 state = (int *)pcpu->pc_monitorbuf; 826 /* 827 * This doesn't need to be atomic since missing the race will 828 * simply result in unnecessary IPIs. 829 */ 830 if (*state == STATE_SLEEPING) 831 return (0); 832 if (*state == STATE_MWAIT) 833 *state = STATE_RUNNING; 834 return (1); 835} 836 837/* 838 * Ordered by speed/power consumption. 839 */ 840struct { 841 void *id_fn; 842 char *id_name; 843} idle_tbl[] = { 844 { cpu_idle_spin, "spin" }, 845 { cpu_idle_mwait, "mwait" }, 846 { cpu_idle_hlt, "hlt" }, 847 { cpu_idle_acpi, "acpi" }, 848 { NULL, NULL } 849}; 850 851static int 852idle_sysctl_available(SYSCTL_HANDLER_ARGS) 853{ 854 char *avail, *p; 855 int error; 856 int i; 857 858 avail = malloc(256, M_TEMP, M_WAITOK); 859 p = avail; 860 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 861 if (strstr(idle_tbl[i].id_name, "mwait") && 862 (cpu_feature2 & CPUID2_MON) == 0) 863 continue; 864 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 865 cpu_idle_hook == NULL) 866 continue; 867 p += sprintf(p, "%s%s", p != avail ? ", " : "", 868 idle_tbl[i].id_name); 869 } 870 error = sysctl_handle_string(oidp, avail, 0, req); 871 free(avail, M_TEMP); 872 return (error); 873} 874 875SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 876 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 877 878static int 879idle_sysctl(SYSCTL_HANDLER_ARGS) 880{ 881 char buf[16]; 882 int error; 883 char *p; 884 int i; 885 886 p = "unknown"; 887 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 888 if (idle_tbl[i].id_fn == cpu_idle_fn) { 889 p = idle_tbl[i].id_name; 890 break; 891 } 892 } 893 strncpy(buf, p, sizeof(buf)); 894 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 895 if (error != 0 || req->newptr == NULL) 896 return (error); 897 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 898 if (strstr(idle_tbl[i].id_name, "mwait") && 899 (cpu_feature2 & CPUID2_MON) == 0) 900 continue; 901 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 902 cpu_idle_hook == NULL) 903 continue; 904 if (strcmp(idle_tbl[i].id_name, buf)) 905 continue; 906 cpu_idle_fn = idle_tbl[i].id_fn; 907 return (0); 908 } 909 return (EINVAL); 910} 911 912SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 913 idle_sysctl, "A", "currently selected idle function"); 914 915/* 916 * Reset registers to default values on exec. 917 */ 918void 919exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 920{ 921 struct trapframe *regs = td->td_frame; 922 struct pcb *pcb = td->td_pcb; 923 924 mtx_lock(&dt_lock); 925 if (td->td_proc->p_md.md_ldt != NULL) 926 user_ldt_free(td); 927 else 928 mtx_unlock(&dt_lock); 929 930 pcb->pcb_fsbase = 0; 931 pcb->pcb_gsbase = 0; 932 clear_pcb_flags(pcb, PCB_32BIT); 933 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 934 set_pcb_flags(pcb, PCB_FULL_IRET); 935 936 bzero((char *)regs, sizeof(struct trapframe)); 937 regs->tf_rip = imgp->entry_addr; 938 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 939 regs->tf_rdi = stack; /* argv */ 940 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 941 regs->tf_ss = _udatasel; 942 regs->tf_cs = _ucodesel; 943 regs->tf_ds = _udatasel; 944 regs->tf_es = _udatasel; 945 regs->tf_fs = _ufssel; 946 regs->tf_gs = _ugssel; 947 regs->tf_flags = TF_HASSEGS; 948 td->td_retval[1] = 0; 949 950 /* 951 * Reset the hardware debug registers if they were in use. 952 * They won't have any meaning for the newly exec'd process. 953 */ 954 if (pcb->pcb_flags & PCB_DBREGS) { 955 pcb->pcb_dr0 = 0; 956 pcb->pcb_dr1 = 0; 957 pcb->pcb_dr2 = 0; 958 pcb->pcb_dr3 = 0; 959 pcb->pcb_dr6 = 0; 960 pcb->pcb_dr7 = 0; 961 if (pcb == curpcb) { 962 /* 963 * Clear the debug registers on the running 964 * CPU, otherwise they will end up affecting 965 * the next process we switch to. 966 */ 967 reset_dbregs(); 968 } 969 clear_pcb_flags(pcb, PCB_DBREGS); 970 } 971 972 /* 973 * Drop the FP state if we hold it, so that the process gets a 974 * clean FP state if it uses the FPU again. 975 */ 976 fpstate_drop(td); 977} 978 979void 980cpu_setregs(void) 981{ 982 register_t cr0; 983 984 cr0 = rcr0(); 985 /* 986 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 987 * BSP. See the comments there about why we set them. 988 */ 989 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 990 load_cr0(cr0); 991} 992 993/* 994 * Initialize amd64 and configure to run kernel 995 */ 996 997/* 998 * Initialize segments & interrupt table 999 */ 1000 1001struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1002static struct gate_descriptor idt0[NIDT]; 1003struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1004 1005static char dblfault_stack[PAGE_SIZE] __aligned(16); 1006 1007static char nmi0_stack[PAGE_SIZE] __aligned(16); 1008CTASSERT(sizeof(struct nmi_pcpu) == 16); 1009 1010struct amd64tss common_tss[MAXCPU]; 1011 1012/* 1013 * Software prototypes -- in more palatable form. 1014 * 1015 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1016 * slots as corresponding segments for i386 kernel. 1017 */ 1018struct soft_segment_descriptor gdt_segs[] = { 1019/* GNULL_SEL 0 Null Descriptor */ 1020{ .ssd_base = 0x0, 1021 .ssd_limit = 0x0, 1022 .ssd_type = 0, 1023 .ssd_dpl = 0, 1024 .ssd_p = 0, 1025 .ssd_long = 0, 1026 .ssd_def32 = 0, 1027 .ssd_gran = 0 }, 1028/* GNULL2_SEL 1 Null Descriptor */ 1029{ .ssd_base = 0x0, 1030 .ssd_limit = 0x0, 1031 .ssd_type = 0, 1032 .ssd_dpl = 0, 1033 .ssd_p = 0, 1034 .ssd_long = 0, 1035 .ssd_def32 = 0, 1036 .ssd_gran = 0 }, 1037/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1038{ .ssd_base = 0x0, 1039 .ssd_limit = 0xfffff, 1040 .ssd_type = SDT_MEMRWA, 1041 .ssd_dpl = SEL_UPL, 1042 .ssd_p = 1, 1043 .ssd_long = 0, 1044 .ssd_def32 = 1, 1045 .ssd_gran = 1 }, 1046/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1047{ .ssd_base = 0x0, 1048 .ssd_limit = 0xfffff, 1049 .ssd_type = SDT_MEMRWA, 1050 .ssd_dpl = SEL_UPL, 1051 .ssd_p = 1, 1052 .ssd_long = 0, 1053 .ssd_def32 = 1, 1054 .ssd_gran = 1 }, 1055/* GCODE_SEL 4 Code Descriptor for kernel */ 1056{ .ssd_base = 0x0, 1057 .ssd_limit = 0xfffff, 1058 .ssd_type = SDT_MEMERA, 1059 .ssd_dpl = SEL_KPL, 1060 .ssd_p = 1, 1061 .ssd_long = 1, 1062 .ssd_def32 = 0, 1063 .ssd_gran = 1 }, 1064/* GDATA_SEL 5 Data Descriptor for kernel */ 1065{ .ssd_base = 0x0, 1066 .ssd_limit = 0xfffff, 1067 .ssd_type = SDT_MEMRWA, 1068 .ssd_dpl = SEL_KPL, 1069 .ssd_p = 1, 1070 .ssd_long = 1, 1071 .ssd_def32 = 0, 1072 .ssd_gran = 1 }, 1073/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1074{ .ssd_base = 0x0, 1075 .ssd_limit = 0xfffff, 1076 .ssd_type = SDT_MEMERA, 1077 .ssd_dpl = SEL_UPL, 1078 .ssd_p = 1, 1079 .ssd_long = 0, 1080 .ssd_def32 = 1, 1081 .ssd_gran = 1 }, 1082/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1083{ .ssd_base = 0x0, 1084 .ssd_limit = 0xfffff, 1085 .ssd_type = SDT_MEMRWA, 1086 .ssd_dpl = SEL_UPL, 1087 .ssd_p = 1, 1088 .ssd_long = 0, 1089 .ssd_def32 = 1, 1090 .ssd_gran = 1 }, 1091/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1092{ .ssd_base = 0x0, 1093 .ssd_limit = 0xfffff, 1094 .ssd_type = SDT_MEMERA, 1095 .ssd_dpl = SEL_UPL, 1096 .ssd_p = 1, 1097 .ssd_long = 1, 1098 .ssd_def32 = 0, 1099 .ssd_gran = 1 }, 1100/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1101{ .ssd_base = 0x0, 1102 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1103 .ssd_type = SDT_SYSTSS, 1104 .ssd_dpl = SEL_KPL, 1105 .ssd_p = 1, 1106 .ssd_long = 0, 1107 .ssd_def32 = 0, 1108 .ssd_gran = 0 }, 1109/* Actually, the TSS is a system descriptor which is double size */ 1110{ .ssd_base = 0x0, 1111 .ssd_limit = 0x0, 1112 .ssd_type = 0, 1113 .ssd_dpl = 0, 1114 .ssd_p = 0, 1115 .ssd_long = 0, 1116 .ssd_def32 = 0, 1117 .ssd_gran = 0 }, 1118/* GUSERLDT_SEL 11 LDT Descriptor */ 1119{ .ssd_base = 0x0, 1120 .ssd_limit = 0x0, 1121 .ssd_type = 0, 1122 .ssd_dpl = 0, 1123 .ssd_p = 0, 1124 .ssd_long = 0, 1125 .ssd_def32 = 0, 1126 .ssd_gran = 0 }, 1127/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1128{ .ssd_base = 0x0, 1129 .ssd_limit = 0x0, 1130 .ssd_type = 0, 1131 .ssd_dpl = 0, 1132 .ssd_p = 0, 1133 .ssd_long = 0, 1134 .ssd_def32 = 0, 1135 .ssd_gran = 0 }, 1136}; 1137 1138void 1139setidt(idx, func, typ, dpl, ist) 1140 int idx; 1141 inthand_t *func; 1142 int typ; 1143 int dpl; 1144 int ist; 1145{ 1146 struct gate_descriptor *ip; 1147 1148 ip = idt + idx; 1149 ip->gd_looffset = (uintptr_t)func; 1150 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1151 ip->gd_ist = ist; 1152 ip->gd_xx = 0; 1153 ip->gd_type = typ; 1154 ip->gd_dpl = dpl; 1155 ip->gd_p = 1; 1156 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1157} 1158 1159extern inthand_t 1160 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1161 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1162 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1163 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1164 IDTVEC(xmm), IDTVEC(dblfault), 1165#ifdef KDTRACE_HOOKS 1166 IDTVEC(dtrace_ret), 1167#endif 1168 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1169 1170#ifdef DDB 1171/* 1172 * Display the index and function name of any IDT entries that don't use 1173 * the default 'rsvd' entry point. 1174 */ 1175DB_SHOW_COMMAND(idt, db_show_idt) 1176{ 1177 struct gate_descriptor *ip; 1178 int idx; 1179 uintptr_t func; 1180 1181 ip = idt; 1182 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1183 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1184 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1185 db_printf("%3d\t", idx); 1186 db_printsym(func, DB_STGY_PROC); 1187 db_printf("\n"); 1188 } 1189 ip++; 1190 } 1191} 1192 1193/* Show privileged registers. */ 1194DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1195{ 1196 struct { 1197 uint16_t limit; 1198 uint64_t base; 1199 } __packed idtr, gdtr; 1200 uint16_t ldt, tr; 1201 1202 __asm __volatile("sidt %0" : "=m" (idtr)); 1203 db_printf("idtr\t0x%016lx/%04x\n", 1204 (u_long)idtr.base, (u_int)idtr.limit); 1205 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1206 db_printf("gdtr\t0x%016lx/%04x\n", 1207 (u_long)gdtr.base, (u_int)gdtr.limit); 1208 __asm __volatile("sldt %0" : "=r" (ldt)); 1209 db_printf("ldtr\t0x%04x\n", ldt); 1210 __asm __volatile("str %0" : "=r" (tr)); 1211 db_printf("tr\t0x%04x\n", tr); 1212 db_printf("cr0\t0x%016lx\n", rcr0()); 1213 db_printf("cr2\t0x%016lx\n", rcr2()); 1214 db_printf("cr3\t0x%016lx\n", rcr3()); 1215 db_printf("cr4\t0x%016lx\n", rcr4()); 1216 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1217 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1218 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1219 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1220 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1221} 1222#endif 1223 1224void 1225sdtossd(sd, ssd) 1226 struct user_segment_descriptor *sd; 1227 struct soft_segment_descriptor *ssd; 1228{ 1229 1230 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1231 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1232 ssd->ssd_type = sd->sd_type; 1233 ssd->ssd_dpl = sd->sd_dpl; 1234 ssd->ssd_p = sd->sd_p; 1235 ssd->ssd_long = sd->sd_long; 1236 ssd->ssd_def32 = sd->sd_def32; 1237 ssd->ssd_gran = sd->sd_gran; 1238} 1239 1240void 1241ssdtosd(ssd, sd) 1242 struct soft_segment_descriptor *ssd; 1243 struct user_segment_descriptor *sd; 1244{ 1245 1246 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1247 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1248 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1249 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1250 sd->sd_type = ssd->ssd_type; 1251 sd->sd_dpl = ssd->ssd_dpl; 1252 sd->sd_p = ssd->ssd_p; 1253 sd->sd_long = ssd->ssd_long; 1254 sd->sd_def32 = ssd->ssd_def32; 1255 sd->sd_gran = ssd->ssd_gran; 1256} 1257 1258void 1259ssdtosyssd(ssd, sd) 1260 struct soft_segment_descriptor *ssd; 1261 struct system_segment_descriptor *sd; 1262{ 1263 1264 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1265 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1266 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1267 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1268 sd->sd_type = ssd->ssd_type; 1269 sd->sd_dpl = ssd->ssd_dpl; 1270 sd->sd_p = ssd->ssd_p; 1271 sd->sd_gran = ssd->ssd_gran; 1272} 1273 1274#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1275#include <isa/isavar.h> 1276#include <isa/isareg.h> 1277/* 1278 * Return a bitmap of the current interrupt requests. This is 8259-specific 1279 * and is only suitable for use at probe time. 1280 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1281 * It shouldn't be here. There should probably be an APIC centric 1282 * implementation in the apic driver code, if at all. 1283 */ 1284intrmask_t 1285isa_irq_pending(void) 1286{ 1287 u_char irr1; 1288 u_char irr2; 1289 1290 irr1 = inb(IO_ICU1); 1291 irr2 = inb(IO_ICU2); 1292 return ((irr2 << 8) | irr1); 1293} 1294#endif 1295 1296u_int basemem; 1297 1298static int 1299add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1300{ 1301 int i, insert_idx, physmap_idx; 1302 1303 physmap_idx = *physmap_idxp; 1304 1305 if (boothowto & RB_VERBOSE) 1306 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1307 smap->type, smap->base, smap->length); 1308 1309 if (smap->type != SMAP_TYPE_MEMORY) 1310 return (1); 1311 1312 if (smap->length == 0) 1313 return (0); 1314 1315 /* 1316 * Find insertion point while checking for overlap. Start off by 1317 * assuming the new entry will be added to the end. 1318 */ 1319 insert_idx = physmap_idx + 2; 1320 for (i = 0; i <= physmap_idx; i += 2) { 1321 if (smap->base < physmap[i + 1]) { 1322 if (smap->base + smap->length <= physmap[i]) { 1323 insert_idx = i; 1324 break; 1325 } 1326 if (boothowto & RB_VERBOSE) 1327 printf( 1328 "Overlapping memory regions, ignoring second region\n"); 1329 return (1); 1330 } 1331 } 1332 1333 /* See if we can prepend to the next entry. */ 1334 if (insert_idx <= physmap_idx && 1335 smap->base + smap->length == physmap[insert_idx]) { 1336 physmap[insert_idx] = smap->base; 1337 return (1); 1338 } 1339 1340 /* See if we can append to the previous entry. */ 1341 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1342 physmap[insert_idx - 1] += smap->length; 1343 return (1); 1344 } 1345 1346 physmap_idx += 2; 1347 *physmap_idxp = physmap_idx; 1348 if (physmap_idx == PHYSMAP_SIZE) { 1349 printf( 1350 "Too many segments in the physical address map, giving up\n"); 1351 return (0); 1352 } 1353 1354 /* 1355 * Move the last 'N' entries down to make room for the new 1356 * entry if needed. 1357 */ 1358 for (i = physmap_idx; i > insert_idx; i -= 2) { 1359 physmap[i] = physmap[i - 2]; 1360 physmap[i + 1] = physmap[i - 1]; 1361 } 1362 1363 /* Insert the new entry. */ 1364 physmap[insert_idx] = smap->base; 1365 physmap[insert_idx + 1] = smap->base + smap->length; 1366 return (1); 1367} 1368 1369/* 1370 * Populate the (physmap) array with base/bound pairs describing the 1371 * available physical memory in the system, then test this memory and 1372 * build the phys_avail array describing the actually-available memory. 1373 * 1374 * Total memory size may be set by the kernel environment variable 1375 * hw.physmem or the compile-time define MAXMEM. 1376 * 1377 * XXX first should be vm_paddr_t. 1378 */ 1379static void 1380getmemsize(caddr_t kmdp, u_int64_t first) 1381{ 1382 int i, physmap_idx, pa_indx, da_indx; 1383 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1384 u_long physmem_start, physmem_tunable, memtest; 1385 pt_entry_t *pte; 1386 struct bios_smap *smapbase, *smap, *smapend; 1387 u_int32_t smapsize; 1388 quad_t dcons_addr, dcons_size; 1389 1390 bzero(physmap, sizeof(physmap)); 1391 basemem = 0; 1392 physmap_idx = 0; 1393 1394 /* 1395 * get memory map from INT 15:E820, kindly supplied by the loader. 1396 * 1397 * subr_module.c says: 1398 * "Consumer may safely assume that size value precedes data." 1399 * ie: an int32_t immediately precedes smap. 1400 */ 1401 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1402 MODINFO_METADATA | MODINFOMD_SMAP); 1403 if (smapbase == NULL) 1404 panic("No BIOS smap info from loader!"); 1405 1406 smapsize = *((u_int32_t *)smapbase - 1); 1407 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1408 1409 for (smap = smapbase; smap < smapend; smap++) 1410 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1411 break; 1412 1413 /* 1414 * Find the 'base memory' segment for SMP 1415 */ 1416 basemem = 0; 1417 for (i = 0; i <= physmap_idx; i += 2) { 1418 if (physmap[i] == 0x00000000) { 1419 basemem = physmap[i + 1] / 1024; 1420 break; 1421 } 1422 } 1423 if (basemem == 0) 1424 panic("BIOS smap did not include a basemem segment!"); 1425 1426#ifdef SMP 1427 /* make hole for AP bootstrap code */ 1428 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1429#endif 1430 1431 /* 1432 * Maxmem isn't the "maximum memory", it's one larger than the 1433 * highest page of the physical address space. It should be 1434 * called something like "Maxphyspage". We may adjust this 1435 * based on ``hw.physmem'' and the results of the memory test. 1436 */ 1437 Maxmem = atop(physmap[physmap_idx + 1]); 1438 1439#ifdef MAXMEM 1440 Maxmem = MAXMEM / 4; 1441#endif 1442 1443 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1444 Maxmem = atop(physmem_tunable); 1445 1446 /* 1447 * By default enable the memory test on real hardware, and disable 1448 * it if we appear to be running in a VM. This avoids touching all 1449 * pages unnecessarily, which doesn't matter on real hardware but is 1450 * bad for shared VM hosts. Use a general name so that 1451 * one could eventually do more with the code than just disable it. 1452 */ 1453 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1454 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1455 1456 /* 1457 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1458 * in the system. 1459 */ 1460 if (Maxmem > atop(physmap[physmap_idx + 1])) 1461 Maxmem = atop(physmap[physmap_idx + 1]); 1462 1463 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1464 (boothowto & RB_VERBOSE)) 1465 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1466 1467 /* call pmap initialization to make new kernel address space */ 1468 pmap_bootstrap(&first); 1469 1470 /* 1471 * Size up each available chunk of physical memory. 1472 * 1473 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1474 * By default, mask off the first 16 pages unless we appear to be 1475 * running in a VM. 1476 */ 1477 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1478 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1479 if (physmem_start < PAGE_SIZE) 1480 physmap[0] = PAGE_SIZE; 1481 else if (physmem_start >= physmap[1]) 1482 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1483 else 1484 physmap[0] = round_page(physmem_start); 1485 pa_indx = 0; 1486 da_indx = 1; 1487 phys_avail[pa_indx++] = physmap[0]; 1488 phys_avail[pa_indx] = physmap[0]; 1489 dump_avail[da_indx] = physmap[0]; 1490 pte = CMAP1; 1491 1492 /* 1493 * Get dcons buffer address 1494 */ 1495 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1496 getenv_quad("dcons.size", &dcons_size) == 0) 1497 dcons_addr = 0; 1498 1499 /* 1500 * physmap is in bytes, so when converting to page boundaries, 1501 * round up the start address and round down the end address. 1502 */ 1503 for (i = 0; i <= physmap_idx; i += 2) { 1504 vm_paddr_t end; 1505 1506 end = ptoa((vm_paddr_t)Maxmem); 1507 if (physmap[i + 1] < end) 1508 end = trunc_page(physmap[i + 1]); 1509 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1510 int tmp, page_bad, full; 1511 int *ptr = (int *)CADDR1; 1512 1513 full = FALSE; 1514 /* 1515 * block out kernel memory as not available. 1516 */ 1517 if (pa >= (vm_paddr_t)kernphys && pa < first) 1518 goto do_dump_avail; 1519 1520 /* 1521 * block out dcons buffer 1522 */ 1523 if (dcons_addr > 0 1524 && pa >= trunc_page(dcons_addr) 1525 && pa < dcons_addr + dcons_size) 1526 goto do_dump_avail; 1527 1528 page_bad = FALSE; 1529 if (memtest == 0) 1530 goto skip_memtest; 1531 1532 /* 1533 * map page into kernel: valid, read/write,non-cacheable 1534 */ 1535 *pte = pa | PG_V | PG_RW | PG_N; 1536 invltlb(); 1537 1538 tmp = *(int *)ptr; 1539 /* 1540 * Test for alternating 1's and 0's 1541 */ 1542 *(volatile int *)ptr = 0xaaaaaaaa; 1543 if (*(volatile int *)ptr != 0xaaaaaaaa) 1544 page_bad = TRUE; 1545 /* 1546 * Test for alternating 0's and 1's 1547 */ 1548 *(volatile int *)ptr = 0x55555555; 1549 if (*(volatile int *)ptr != 0x55555555) 1550 page_bad = TRUE; 1551 /* 1552 * Test for all 1's 1553 */ 1554 *(volatile int *)ptr = 0xffffffff; 1555 if (*(volatile int *)ptr != 0xffffffff) 1556 page_bad = TRUE; 1557 /* 1558 * Test for all 0's 1559 */ 1560 *(volatile int *)ptr = 0x0; 1561 if (*(volatile int *)ptr != 0x0) 1562 page_bad = TRUE; 1563 /* 1564 * Restore original value. 1565 */ 1566 *(int *)ptr = tmp; 1567 1568skip_memtest: 1569 /* 1570 * Adjust array of valid/good pages. 1571 */ 1572 if (page_bad == TRUE) 1573 continue; 1574 /* 1575 * If this good page is a continuation of the 1576 * previous set of good pages, then just increase 1577 * the end pointer. Otherwise start a new chunk. 1578 * Note that "end" points one higher than end, 1579 * making the range >= start and < end. 1580 * If we're also doing a speculative memory 1581 * test and we at or past the end, bump up Maxmem 1582 * so that we keep going. The first bad page 1583 * will terminate the loop. 1584 */ 1585 if (phys_avail[pa_indx] == pa) { 1586 phys_avail[pa_indx] += PAGE_SIZE; 1587 } else { 1588 pa_indx++; 1589 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1590 printf( 1591 "Too many holes in the physical address space, giving up\n"); 1592 pa_indx--; 1593 full = TRUE; 1594 goto do_dump_avail; 1595 } 1596 phys_avail[pa_indx++] = pa; /* start */ 1597 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1598 } 1599 physmem++; 1600do_dump_avail: 1601 if (dump_avail[da_indx] == pa) { 1602 dump_avail[da_indx] += PAGE_SIZE; 1603 } else { 1604 da_indx++; 1605 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1606 da_indx--; 1607 goto do_next; 1608 } 1609 dump_avail[da_indx++] = pa; /* start */ 1610 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1611 } 1612do_next: 1613 if (full) 1614 break; 1615 } 1616 } 1617 *pte = 0; 1618 invltlb(); 1619 1620 /* 1621 * XXX 1622 * The last chunk must contain at least one page plus the message 1623 * buffer to avoid complicating other code (message buffer address 1624 * calculation, etc.). 1625 */ 1626 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1627 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1628 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1629 phys_avail[pa_indx--] = 0; 1630 phys_avail[pa_indx--] = 0; 1631 } 1632 1633 Maxmem = atop(phys_avail[pa_indx]); 1634 1635 /* Trim off space for the message buffer. */ 1636 phys_avail[pa_indx] -= round_page(msgbufsize); 1637 1638 /* Map the message buffer. */ 1639 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1640} 1641 1642u_int64_t 1643hammer_time(u_int64_t modulep, u_int64_t physfree) 1644{ 1645 caddr_t kmdp; 1646 int gsel_tss, x; 1647 struct pcpu *pc; 1648 struct nmi_pcpu *np; 1649 struct xstate_hdr *xhdr; 1650 u_int64_t msr; 1651 char *env; 1652 size_t kstack0_sz; 1653 1654 thread0.td_kstack = physfree + KERNBASE; 1655 thread0.td_kstack_pages = KSTACK_PAGES; 1656 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1657 bzero((void *)thread0.td_kstack, kstack0_sz); 1658 physfree += kstack0_sz; 1659 1660 /* 1661 * This may be done better later if it gets more high level 1662 * components in it. If so just link td->td_proc here. 1663 */ 1664 proc_linkup0(&proc0, &thread0); 1665 1666 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1667 preload_bootstrap_relocate(KERNBASE); 1668 kmdp = preload_search_by_type("elf kernel"); 1669 if (kmdp == NULL) 1670 kmdp = preload_search_by_type("elf64 kernel"); 1671 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1672 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1673#ifdef DDB 1674 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1675 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1676#endif 1677 1678 /* Init basic tunables, hz etc */ 1679 init_param1(); 1680 1681 /* 1682 * make gdt memory segments 1683 */ 1684 for (x = 0; x < NGDT; x++) { 1685 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1686 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1687 ssdtosd(&gdt_segs[x], &gdt[x]); 1688 } 1689 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1690 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1691 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1692 1693 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1694 r_gdt.rd_base = (long) gdt; 1695 lgdt(&r_gdt); 1696 pc = &__pcpu[0]; 1697 1698 wrmsr(MSR_FSBASE, 0); /* User value */ 1699 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1700 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1701 1702 pcpu_init(pc, 0, sizeof(struct pcpu)); 1703 dpcpu_init((void *)(physfree + KERNBASE), 0); 1704 physfree += DPCPU_SIZE; 1705 PCPU_SET(prvspace, pc); 1706 PCPU_SET(curthread, &thread0); 1707 PCPU_SET(tssp, &common_tss[0]); 1708 PCPU_SET(commontssp, &common_tss[0]); 1709 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1710 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1711 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1712 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1713 1714 /* 1715 * Initialize mutexes. 1716 * 1717 * icu_lock: in order to allow an interrupt to occur in a critical 1718 * section, to set pcpu->ipending (etc...) properly, we 1719 * must be able to get the icu lock, so it can't be 1720 * under witness. 1721 */ 1722 mutex_init(); 1723 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1724 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1725 1726 /* exceptions */ 1727 for (x = 0; x < NIDT; x++) 1728 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1729 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1730 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1731 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1732 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1733 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1734 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1735 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1736 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1737 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1738 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1739 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1740 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1741 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1742 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1743 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1744 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1745 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1746 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1747 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1748#ifdef KDTRACE_HOOKS 1749 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1750#endif 1751 1752 r_idt.rd_limit = sizeof(idt0) - 1; 1753 r_idt.rd_base = (long) idt; 1754 lidt(&r_idt); 1755 1756 /* 1757 * Initialize the i8254 before the console so that console 1758 * initialization can use DELAY(). 1759 */ 1760 i8254_init(); 1761 1762 /* 1763 * Initialize the console before we print anything out. 1764 */ 1765 cninit(); 1766 1767#ifdef DEV_ISA 1768#ifdef DEV_ATPIC 1769 elcr_probe(); 1770 atpic_startup(); 1771#else 1772 /* Reset and mask the atpics and leave them shut down. */ 1773 atpic_reset(); 1774 1775 /* 1776 * Point the ICU spurious interrupt vectors at the APIC spurious 1777 * interrupt handler. 1778 */ 1779 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1780 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1781#endif 1782#else 1783#error "have you forgotten the isa device?"; 1784#endif 1785 1786 kdb_init(); 1787 1788#ifdef KDB 1789 if (boothowto & RB_KDB) 1790 kdb_enter(KDB_WHY_BOOTFLAGS, 1791 "Boot flags requested debugger"); 1792#endif 1793 1794 identify_cpu(); /* Final stage of CPU initialization */ 1795 initializecpu(); /* Initialize CPU registers */ 1796 initializecpucache(); 1797 1798 /* doublefault stack space, runs on ist1 */ 1799 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1800 1801 /* 1802 * NMI stack, runs on ist2. The pcpu pointer is stored just 1803 * above the start of the ist2 stack. 1804 */ 1805 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1806 np->np_pcpu = (register_t) pc; 1807 common_tss[0].tss_ist2 = (long) np; 1808 1809 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1810 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1811 IOPAGES * PAGE_SIZE; 1812 1813 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1814 ltr(gsel_tss); 1815 1816 /* Set up the fast syscall stuff */ 1817 msr = rdmsr(MSR_EFER) | EFER_SCE; 1818 wrmsr(MSR_EFER, msr); 1819 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1820 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1821 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1822 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1823 wrmsr(MSR_STAR, msr); 1824 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1825 1826 getmemsize(kmdp, physfree); 1827 init_param2(physmem); 1828 1829 /* now running on new page tables, configured,and u/iom is accessible */ 1830 1831 msgbufinit(msgbufp, msgbufsize); 1832 fpuinit(); 1833 1834 /* 1835 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1836 * area size. Zero out the extended state header in fpu save 1837 * area. 1838 */ 1839 thread0.td_pcb = get_pcb_td(&thread0); 1840 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1841 if (use_xsave) { 1842 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1843 1); 1844 xhdr->xstate_bv = xsave_mask; 1845 } 1846 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1847 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1848 /* Ensure the stack is aligned to 16 bytes */ 1849 common_tss[0].tss_rsp0 &= ~0xFul; 1850 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1851 PCPU_SET(curpcb, thread0.td_pcb); 1852 1853 /* transfer to user mode */ 1854 1855 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1856 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1857 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1858 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1859 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1860 1861 load_ds(_udatasel); 1862 load_es(_udatasel); 1863 load_fs(_ufssel); 1864 1865 /* setup proc 0's pcb */ 1866 thread0.td_pcb->pcb_flags = 0; 1867 thread0.td_pcb->pcb_cr3 = KPML4phys; 1868 thread0.td_frame = &proc0_tf; 1869 1870 env = getenv("kernelname"); 1871 if (env != NULL) 1872 strlcpy(kernelname, env, sizeof(kernelname)); 1873 1874#ifdef XENHVM 1875 if (inw(0x10) == 0x49d2) { 1876 if (bootverbose) 1877 printf("Xen detected: disabling emulated block and network devices\n"); 1878 outw(0x10, 3); 1879 } 1880#endif 1881 1882 cpu_probe_amdc1e(); 1883 1884 /* Location of kernel stack for locore */ 1885 return ((u_int64_t)thread0.td_pcb); 1886} 1887 1888void 1889cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1890{ 1891 1892 pcpu->pc_acpi_id = 0xffffffff; 1893} 1894 1895void 1896spinlock_enter(void) 1897{ 1898 struct thread *td; 1899 register_t flags; 1900 1901 td = curthread; 1902 if (td->td_md.md_spinlock_count == 0) { 1903 flags = intr_disable(); 1904 td->td_md.md_spinlock_count = 1; 1905 td->td_md.md_saved_flags = flags; 1906 } else 1907 td->td_md.md_spinlock_count++; 1908 critical_enter(); 1909} 1910 1911void 1912spinlock_exit(void) 1913{ 1914 struct thread *td; 1915 register_t flags; 1916 1917 td = curthread; 1918 critical_exit(); 1919 flags = td->td_md.md_saved_flags; 1920 td->td_md.md_spinlock_count--; 1921 if (td->td_md.md_spinlock_count == 0) 1922 intr_restore(flags); 1923} 1924 1925/* 1926 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1927 * we want to start a backtrace from the function that caused us to enter 1928 * the debugger. We have the context in the trapframe, but base the trace 1929 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1930 * enough for a backtrace. 1931 */ 1932void 1933makectx(struct trapframe *tf, struct pcb *pcb) 1934{ 1935 1936 pcb->pcb_r12 = tf->tf_r12; 1937 pcb->pcb_r13 = tf->tf_r13; 1938 pcb->pcb_r14 = tf->tf_r14; 1939 pcb->pcb_r15 = tf->tf_r15; 1940 pcb->pcb_rbp = tf->tf_rbp; 1941 pcb->pcb_rbx = tf->tf_rbx; 1942 pcb->pcb_rip = tf->tf_rip; 1943 pcb->pcb_rsp = tf->tf_rsp; 1944} 1945 1946int 1947ptrace_set_pc(struct thread *td, unsigned long addr) 1948{ 1949 td->td_frame->tf_rip = addr; 1950 return (0); 1951} 1952 1953int 1954ptrace_single_step(struct thread *td) 1955{ 1956 td->td_frame->tf_rflags |= PSL_T; 1957 return (0); 1958} 1959 1960int 1961ptrace_clear_single_step(struct thread *td) 1962{ 1963 td->td_frame->tf_rflags &= ~PSL_T; 1964 return (0); 1965} 1966 1967int 1968fill_regs(struct thread *td, struct reg *regs) 1969{ 1970 struct trapframe *tp; 1971 1972 tp = td->td_frame; 1973 return (fill_frame_regs(tp, regs)); 1974} 1975 1976int 1977fill_frame_regs(struct trapframe *tp, struct reg *regs) 1978{ 1979 regs->r_r15 = tp->tf_r15; 1980 regs->r_r14 = tp->tf_r14; 1981 regs->r_r13 = tp->tf_r13; 1982 regs->r_r12 = tp->tf_r12; 1983 regs->r_r11 = tp->tf_r11; 1984 regs->r_r10 = tp->tf_r10; 1985 regs->r_r9 = tp->tf_r9; 1986 regs->r_r8 = tp->tf_r8; 1987 regs->r_rdi = tp->tf_rdi; 1988 regs->r_rsi = tp->tf_rsi; 1989 regs->r_rbp = tp->tf_rbp; 1990 regs->r_rbx = tp->tf_rbx; 1991 regs->r_rdx = tp->tf_rdx; 1992 regs->r_rcx = tp->tf_rcx; 1993 regs->r_rax = tp->tf_rax; 1994 regs->r_rip = tp->tf_rip; 1995 regs->r_cs = tp->tf_cs; 1996 regs->r_rflags = tp->tf_rflags; 1997 regs->r_rsp = tp->tf_rsp; 1998 regs->r_ss = tp->tf_ss; 1999 if (tp->tf_flags & TF_HASSEGS) { 2000 regs->r_ds = tp->tf_ds; 2001 regs->r_es = tp->tf_es; 2002 regs->r_fs = tp->tf_fs; 2003 regs->r_gs = tp->tf_gs; 2004 } else { 2005 regs->r_ds = 0; 2006 regs->r_es = 0; 2007 regs->r_fs = 0; 2008 regs->r_gs = 0; 2009 } 2010 return (0); 2011} 2012 2013int 2014set_regs(struct thread *td, struct reg *regs) 2015{ 2016 struct trapframe *tp; 2017 register_t rflags; 2018 2019 tp = td->td_frame; 2020 rflags = regs->r_rflags & 0xffffffff; 2021 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2022 return (EINVAL); 2023 tp->tf_r15 = regs->r_r15; 2024 tp->tf_r14 = regs->r_r14; 2025 tp->tf_r13 = regs->r_r13; 2026 tp->tf_r12 = regs->r_r12; 2027 tp->tf_r11 = regs->r_r11; 2028 tp->tf_r10 = regs->r_r10; 2029 tp->tf_r9 = regs->r_r9; 2030 tp->tf_r8 = regs->r_r8; 2031 tp->tf_rdi = regs->r_rdi; 2032 tp->tf_rsi = regs->r_rsi; 2033 tp->tf_rbp = regs->r_rbp; 2034 tp->tf_rbx = regs->r_rbx; 2035 tp->tf_rdx = regs->r_rdx; 2036 tp->tf_rcx = regs->r_rcx; 2037 tp->tf_rax = regs->r_rax; 2038 tp->tf_rip = regs->r_rip; 2039 tp->tf_cs = regs->r_cs; 2040 tp->tf_rflags = rflags; 2041 tp->tf_rsp = regs->r_rsp; 2042 tp->tf_ss = regs->r_ss; 2043 if (0) { /* XXXKIB */ 2044 tp->tf_ds = regs->r_ds; 2045 tp->tf_es = regs->r_es; 2046 tp->tf_fs = regs->r_fs; 2047 tp->tf_gs = regs->r_gs; 2048 tp->tf_flags = TF_HASSEGS; 2049 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2050 } 2051 return (0); 2052} 2053 2054/* XXX check all this stuff! */ 2055/* externalize from sv_xmm */ 2056static void 2057fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2058{ 2059 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2060 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2061 int i; 2062 2063 /* pcb -> fpregs */ 2064 bzero(fpregs, sizeof(*fpregs)); 2065 2066 /* FPU control/status */ 2067 penv_fpreg->en_cw = penv_xmm->en_cw; 2068 penv_fpreg->en_sw = penv_xmm->en_sw; 2069 penv_fpreg->en_tw = penv_xmm->en_tw; 2070 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2071 penv_fpreg->en_rip = penv_xmm->en_rip; 2072 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2073 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2074 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2075 2076 /* FPU registers */ 2077 for (i = 0; i < 8; ++i) 2078 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2079 2080 /* SSE registers */ 2081 for (i = 0; i < 16; ++i) 2082 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2083} 2084 2085/* internalize from fpregs into sv_xmm */ 2086static void 2087set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2088{ 2089 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2090 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2091 int i; 2092 2093 /* fpregs -> pcb */ 2094 /* FPU control/status */ 2095 penv_xmm->en_cw = penv_fpreg->en_cw; 2096 penv_xmm->en_sw = penv_fpreg->en_sw; 2097 penv_xmm->en_tw = penv_fpreg->en_tw; 2098 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2099 penv_xmm->en_rip = penv_fpreg->en_rip; 2100 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2101 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2102 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2103 2104 /* FPU registers */ 2105 for (i = 0; i < 8; ++i) 2106 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2107 2108 /* SSE registers */ 2109 for (i = 0; i < 16; ++i) 2110 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2111} 2112 2113/* externalize from td->pcb */ 2114int 2115fill_fpregs(struct thread *td, struct fpreg *fpregs) 2116{ 2117 2118 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2119 P_SHOULDSTOP(td->td_proc), 2120 ("not suspended thread %p", td)); 2121 fpugetregs(td); 2122 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2123 return (0); 2124} 2125 2126/* internalize to td->pcb */ 2127int 2128set_fpregs(struct thread *td, struct fpreg *fpregs) 2129{ 2130 2131 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2132 fpuuserinited(td); 2133 return (0); 2134} 2135 2136/* 2137 * Get machine context. 2138 */ 2139int 2140get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2141{ 2142 struct pcb *pcb; 2143 struct trapframe *tp; 2144 2145 pcb = td->td_pcb; 2146 tp = td->td_frame; 2147 PROC_LOCK(curthread->td_proc); 2148 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2149 PROC_UNLOCK(curthread->td_proc); 2150 mcp->mc_r15 = tp->tf_r15; 2151 mcp->mc_r14 = tp->tf_r14; 2152 mcp->mc_r13 = tp->tf_r13; 2153 mcp->mc_r12 = tp->tf_r12; 2154 mcp->mc_r11 = tp->tf_r11; 2155 mcp->mc_r10 = tp->tf_r10; 2156 mcp->mc_r9 = tp->tf_r9; 2157 mcp->mc_r8 = tp->tf_r8; 2158 mcp->mc_rdi = tp->tf_rdi; 2159 mcp->mc_rsi = tp->tf_rsi; 2160 mcp->mc_rbp = tp->tf_rbp; 2161 mcp->mc_rbx = tp->tf_rbx; 2162 mcp->mc_rcx = tp->tf_rcx; 2163 mcp->mc_rflags = tp->tf_rflags; 2164 if (flags & GET_MC_CLEAR_RET) { 2165 mcp->mc_rax = 0; 2166 mcp->mc_rdx = 0; 2167 mcp->mc_rflags &= ~PSL_C; 2168 } else { 2169 mcp->mc_rax = tp->tf_rax; 2170 mcp->mc_rdx = tp->tf_rdx; 2171 } 2172 mcp->mc_rip = tp->tf_rip; 2173 mcp->mc_cs = tp->tf_cs; 2174 mcp->mc_rsp = tp->tf_rsp; 2175 mcp->mc_ss = tp->tf_ss; 2176 mcp->mc_ds = tp->tf_ds; 2177 mcp->mc_es = tp->tf_es; 2178 mcp->mc_fs = tp->tf_fs; 2179 mcp->mc_gs = tp->tf_gs; 2180 mcp->mc_flags = tp->tf_flags; 2181 mcp->mc_len = sizeof(*mcp); 2182 get_fpcontext(td, mcp, NULL, 0); 2183 mcp->mc_fsbase = pcb->pcb_fsbase; 2184 mcp->mc_gsbase = pcb->pcb_gsbase; 2185 mcp->mc_xfpustate = 0; 2186 mcp->mc_xfpustate_len = 0; 2187 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2188 return (0); 2189} 2190 2191/* 2192 * Set machine context. 2193 * 2194 * However, we don't set any but the user modifiable flags, and we won't 2195 * touch the cs selector. 2196 */ 2197int 2198set_mcontext(struct thread *td, const mcontext_t *mcp) 2199{ 2200 struct pcb *pcb; 2201 struct trapframe *tp; 2202 char *xfpustate; 2203 long rflags; 2204 int ret; 2205 2206 pcb = td->td_pcb; 2207 tp = td->td_frame; 2208 if (mcp->mc_len != sizeof(*mcp) || 2209 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2210 return (EINVAL); 2211 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2212 (tp->tf_rflags & ~PSL_USERCHANGE); 2213 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2214 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2215 sizeof(struct savefpu)) 2216 return (EINVAL); 2217 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2218 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2219 mcp->mc_xfpustate_len); 2220 if (ret != 0) 2221 return (ret); 2222 } else 2223 xfpustate = NULL; 2224 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2225 if (ret != 0) 2226 return (ret); 2227 tp->tf_r15 = mcp->mc_r15; 2228 tp->tf_r14 = mcp->mc_r14; 2229 tp->tf_r13 = mcp->mc_r13; 2230 tp->tf_r12 = mcp->mc_r12; 2231 tp->tf_r11 = mcp->mc_r11; 2232 tp->tf_r10 = mcp->mc_r10; 2233 tp->tf_r9 = mcp->mc_r9; 2234 tp->tf_r8 = mcp->mc_r8; 2235 tp->tf_rdi = mcp->mc_rdi; 2236 tp->tf_rsi = mcp->mc_rsi; 2237 tp->tf_rbp = mcp->mc_rbp; 2238 tp->tf_rbx = mcp->mc_rbx; 2239 tp->tf_rdx = mcp->mc_rdx; 2240 tp->tf_rcx = mcp->mc_rcx; 2241 tp->tf_rax = mcp->mc_rax; 2242 tp->tf_rip = mcp->mc_rip; 2243 tp->tf_rflags = rflags; 2244 tp->tf_rsp = mcp->mc_rsp; 2245 tp->tf_ss = mcp->mc_ss; 2246 tp->tf_flags = mcp->mc_flags; 2247 if (tp->tf_flags & TF_HASSEGS) { 2248 tp->tf_ds = mcp->mc_ds; 2249 tp->tf_es = mcp->mc_es; 2250 tp->tf_fs = mcp->mc_fs; 2251 tp->tf_gs = mcp->mc_gs; 2252 } 2253 if (mcp->mc_flags & _MC_HASBASES) { 2254 pcb->pcb_fsbase = mcp->mc_fsbase; 2255 pcb->pcb_gsbase = mcp->mc_gsbase; 2256 } 2257 set_pcb_flags(pcb, PCB_FULL_IRET); 2258 return (0); 2259} 2260 2261static void 2262get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2263 size_t xfpusave_len) 2264{ 2265 size_t max_len, len; 2266 2267 mcp->mc_ownedfp = fpugetregs(td); 2268 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2269 sizeof(mcp->mc_fpstate)); 2270 mcp->mc_fpformat = fpuformat(); 2271 if (!use_xsave || xfpusave_len == 0) 2272 return; 2273 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2274 len = xfpusave_len; 2275 if (len > max_len) { 2276 len = max_len; 2277 bzero(xfpusave + max_len, len - max_len); 2278 } 2279 mcp->mc_flags |= _MC_HASFPXSTATE; 2280 mcp->mc_xfpustate_len = len; 2281 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2282} 2283 2284static int 2285set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2286 size_t xfpustate_len) 2287{ 2288 struct savefpu *fpstate; 2289 int error; 2290 2291 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2292 return (0); 2293 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2294 return (EINVAL); 2295 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2296 /* We don't care what state is left in the FPU or PCB. */ 2297 fpstate_drop(td); 2298 error = 0; 2299 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2300 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2301 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2302 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2303 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2304 } else 2305 return (EINVAL); 2306 return (error); 2307} 2308 2309void 2310fpstate_drop(struct thread *td) 2311{ 2312 2313 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2314 critical_enter(); 2315 if (PCPU_GET(fpcurthread) == td) 2316 fpudrop(); 2317 /* 2318 * XXX force a full drop of the fpu. The above only drops it if we 2319 * owned it. 2320 * 2321 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2322 * drop. Dropping only to the pcb matches fnsave's behaviour. 2323 * We only need to drop to !PCB_INITDONE in sendsig(). But 2324 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2325 * have too many layers. 2326 */ 2327 clear_pcb_flags(curthread->td_pcb, 2328 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2329 critical_exit(); 2330} 2331 2332int 2333fill_dbregs(struct thread *td, struct dbreg *dbregs) 2334{ 2335 struct pcb *pcb; 2336 2337 if (td == NULL) { 2338 dbregs->dr[0] = rdr0(); 2339 dbregs->dr[1] = rdr1(); 2340 dbregs->dr[2] = rdr2(); 2341 dbregs->dr[3] = rdr3(); 2342 dbregs->dr[6] = rdr6(); 2343 dbregs->dr[7] = rdr7(); 2344 } else { 2345 pcb = td->td_pcb; 2346 dbregs->dr[0] = pcb->pcb_dr0; 2347 dbregs->dr[1] = pcb->pcb_dr1; 2348 dbregs->dr[2] = pcb->pcb_dr2; 2349 dbregs->dr[3] = pcb->pcb_dr3; 2350 dbregs->dr[6] = pcb->pcb_dr6; 2351 dbregs->dr[7] = pcb->pcb_dr7; 2352 } 2353 dbregs->dr[4] = 0; 2354 dbregs->dr[5] = 0; 2355 dbregs->dr[8] = 0; 2356 dbregs->dr[9] = 0; 2357 dbregs->dr[10] = 0; 2358 dbregs->dr[11] = 0; 2359 dbregs->dr[12] = 0; 2360 dbregs->dr[13] = 0; 2361 dbregs->dr[14] = 0; 2362 dbregs->dr[15] = 0; 2363 return (0); 2364} 2365 2366int 2367set_dbregs(struct thread *td, struct dbreg *dbregs) 2368{ 2369 struct pcb *pcb; 2370 int i; 2371 2372 if (td == NULL) { 2373 load_dr0(dbregs->dr[0]); 2374 load_dr1(dbregs->dr[1]); 2375 load_dr2(dbregs->dr[2]); 2376 load_dr3(dbregs->dr[3]); 2377 load_dr6(dbregs->dr[6]); 2378 load_dr7(dbregs->dr[7]); 2379 } else { 2380 /* 2381 * Don't let an illegal value for dr7 get set. Specifically, 2382 * check for undefined settings. Setting these bit patterns 2383 * result in undefined behaviour and can lead to an unexpected 2384 * TRCTRAP or a general protection fault right here. 2385 * Upper bits of dr6 and dr7 must not be set 2386 */ 2387 for (i = 0; i < 4; i++) { 2388 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2389 return (EINVAL); 2390 if (td->td_frame->tf_cs == _ucode32sel && 2391 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2392 return (EINVAL); 2393 } 2394 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2395 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2396 return (EINVAL); 2397 2398 pcb = td->td_pcb; 2399 2400 /* 2401 * Don't let a process set a breakpoint that is not within the 2402 * process's address space. If a process could do this, it 2403 * could halt the system by setting a breakpoint in the kernel 2404 * (if ddb was enabled). Thus, we need to check to make sure 2405 * that no breakpoints are being enabled for addresses outside 2406 * process's address space. 2407 * 2408 * XXX - what about when the watched area of the user's 2409 * address space is written into from within the kernel 2410 * ... wouldn't that still cause a breakpoint to be generated 2411 * from within kernel mode? 2412 */ 2413 2414 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2415 /* dr0 is enabled */ 2416 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2417 return (EINVAL); 2418 } 2419 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2420 /* dr1 is enabled */ 2421 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2422 return (EINVAL); 2423 } 2424 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2425 /* dr2 is enabled */ 2426 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2427 return (EINVAL); 2428 } 2429 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2430 /* dr3 is enabled */ 2431 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2432 return (EINVAL); 2433 } 2434 2435 pcb->pcb_dr0 = dbregs->dr[0]; 2436 pcb->pcb_dr1 = dbregs->dr[1]; 2437 pcb->pcb_dr2 = dbregs->dr[2]; 2438 pcb->pcb_dr3 = dbregs->dr[3]; 2439 pcb->pcb_dr6 = dbregs->dr[6]; 2440 pcb->pcb_dr7 = dbregs->dr[7]; 2441 2442 set_pcb_flags(pcb, PCB_DBREGS); 2443 } 2444 2445 return (0); 2446} 2447 2448void 2449reset_dbregs(void) 2450{ 2451 2452 load_dr7(0); /* Turn off the control bits first */ 2453 load_dr0(0); 2454 load_dr1(0); 2455 load_dr2(0); 2456 load_dr3(0); 2457 load_dr6(0); 2458} 2459 2460/* 2461 * Return > 0 if a hardware breakpoint has been hit, and the 2462 * breakpoint was in user space. Return 0, otherwise. 2463 */ 2464int 2465user_dbreg_trap(void) 2466{ 2467 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2468 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2469 int nbp; /* number of breakpoints that triggered */ 2470 caddr_t addr[4]; /* breakpoint addresses */ 2471 int i; 2472 2473 dr7 = rdr7(); 2474 if ((dr7 & 0x000000ff) == 0) { 2475 /* 2476 * all GE and LE bits in the dr7 register are zero, 2477 * thus the trap couldn't have been caused by the 2478 * hardware debug registers 2479 */ 2480 return 0; 2481 } 2482 2483 nbp = 0; 2484 dr6 = rdr6(); 2485 bp = dr6 & 0x0000000f; 2486 2487 if (!bp) { 2488 /* 2489 * None of the breakpoint bits are set meaning this 2490 * trap was not caused by any of the debug registers 2491 */ 2492 return 0; 2493 } 2494 2495 /* 2496 * at least one of the breakpoints were hit, check to see 2497 * which ones and if any of them are user space addresses 2498 */ 2499 2500 if (bp & 0x01) { 2501 addr[nbp++] = (caddr_t)rdr0(); 2502 } 2503 if (bp & 0x02) { 2504 addr[nbp++] = (caddr_t)rdr1(); 2505 } 2506 if (bp & 0x04) { 2507 addr[nbp++] = (caddr_t)rdr2(); 2508 } 2509 if (bp & 0x08) { 2510 addr[nbp++] = (caddr_t)rdr3(); 2511 } 2512 2513 for (i = 0; i < nbp; i++) { 2514 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2515 /* 2516 * addr[i] is in user space 2517 */ 2518 return nbp; 2519 } 2520 } 2521 2522 /* 2523 * None of the breakpoints are in user space. 2524 */ 2525 return 0; 2526} 2527 2528#ifdef KDB 2529 2530/* 2531 * Provide inb() and outb() as functions. They are normally only available as 2532 * inline functions, thus cannot be called from the debugger. 2533 */ 2534 2535/* silence compiler warnings */ 2536u_char inb_(u_short); 2537void outb_(u_short, u_char); 2538 2539u_char 2540inb_(u_short port) 2541{ 2542 return inb(port); 2543} 2544 2545void 2546outb_(u_short port, u_char data) 2547{ 2548 outb(port, data); 2549} 2550 2551#endif /* KDB */ 2552