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$FreeBSD: head/lib/libpmc/pmc.p6.3 183084 2008-09-16 16:34:55Z jkoshy $
.Dd September 16, 2008 .Os .Dt PMC.P6 3 .Sh NAME .Nm pmc.p6 .Nd measurement events for .Tn Intel Pentium Pro, P-II, P-III family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS n pmc.h .Sh DESCRIPTION Intel P6 PMCs are present in Intel .Tn "Pentium Pro" , .Tn "Pentium II" , .Tn Celeron , .Tn "Pentium III" and .Tn "Pentium M" processors.
p They are documented in .Rs .%B "IA-32 Intel(R) Architecture Software Developer's Manual" .%T "Volume 3: System Programming Guide" .%N "Order Number 245472-012" .%D 2003 .%Q "Intel Corporation" .Re
p Some of these events are affected by processor errata described in .Rs .%B "Intel(R) Pentium(R) III Processor Specification Update" .%N "Document Number: 244453-054" .%D "April 2005" .%Q "Intel Corporation" .Re .Ss PMC Features These CPUs have two counters, each 40 bits wide. Some events may only be used on specific counters and some events are defined only on specific processor models. These PMCs support the following capabilities: l -column "PMC_CAP_INTERRUPT" "Support" t Em Capability Ta Em Support t PMC_CAP_CASCADE Ta No t PMC_CAP_EDGE Ta Yes t PMC_CAP_INTERRUPT Ta Yes t PMC_CAP_INVERT Ta Yes t PMC_CAP_READ Ta Yes t PMC_CAP_PRECISE Ta No t PMC_CAP_SYSTEM Ta Yes t PMC_CAP_TAGGING Ta No t PMC_CAP_THRESHOLD Ta Yes t PMC_CAP_USER Ta Yes t PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for Intel P6 PMCs can have the following common qualifiers: l -tag -width indent t Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . t Li edge Configure the PMC to count the number of deasserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. t Li inv Invert the sense of comparision when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. t Li os Configure the PMC to count events happening at processor privilege level 0. t Li umask= Ns Ar value This qualifier is used to further qualify the event selected (see below). t Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El
p If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both.
p The event specifiers supported by Intel P6 PMCs are: l -tag -width indent t Li p6-baclears Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction. t Li p6-br-bac-missp-exec
q Tn "Pentium M" Count the number of branch instructions executed that where mispredicted at the Front End (BAC). t Li p6-br-bogus Count the number of bogus branches. t Li p6-br-call-exec
q Tn "Pentium M" Count the number of call instructions executed. t Li p6-br-call-missp-exec
q Tn "Pentium M" Count the number of call instructions executed that were mispredicted. t Li p6-br-cnd-exec
q Tn "Pentium M" Count the number of conditional branch instructions executed. t Li p6-br-cnd-missp-exec
q Tn "Pentium M" Count the number of conditional branch instructions executed that were mispredicted. t Li p6-br-ind-call-exec
q Tn "Pentium M" Count the number of indirect call instructions executed. t Li p6-br-ind-exec
q Tn "Pentium M" Count the number of indirect branch instructions executed. t Li p6-br-ind-missp-exec
q Tn "Pentium M" Count the number of indirect branch instructions executed that were mispredicted. t Li p6-br-inst-decoded Count the number of branch instructions decoded. t Li p6-br-inst-exec
q Tn "Pentium M" Count the number of branch instructions executed but necessarily retired. t Li p6-br-inst-retired Count the number of branch instructions retired. t Li p6-br-miss-pred-retired Count the number of mispredicted branch instructions retired. t Li p6-br-miss-pred-taken-ret Count the number of taken mispredicted branches retired. t Li p6-br-missp-exec
q Tn "Pentium M" Count the number of branch instructions executed that were mispredicted at execution. t Li p6-br-ret-bac-missp-exec
q Tn "Pentium M" Count the number of return instructions executed that were mispredicted at the Front End (BAC). t Li p6-br-ret-exec
q Tn "Pentium M" Count the number of return instructions executed. t Li p6-br-ret-missp-exec
q Tn "Pentium M" Count the number of return instructions executed that were mispredicted at execution. t Li p6-br-taken-retired Count the number of taken branches retired. t Li p6-btb-misses Count the number of branches for which the BTB did not produce a prediction. t Li p6-bus-bnr-drv Count the number of bus clock cycles during which this processor is driving the BNR# pin. t Li p6-bus-data-rcv Count the number of bus clock cycles during which this processor is receiving data. t Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier Count the number of clocks during which DRDY# is asserted. An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-hit-drv Count the number of bus clock cycles during which this processor is driving the HIT# pin. t Li p6-bus-hitm-drv Count the number of bus clock cycles during which this processor is driving the HITM# pin. t Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier Count the number of clocks during with LOCK# is asserted on the external system bus. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-req-outstanding Count the number of bus requests outstanding in any given cycle. t Li p6-bus-snoop-stall Count the number of clock cycles during which the bus is snoop stalled. t Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier Count the number of completed bus transactions of any kind. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier Count the number of burst read transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier Count the number of completed burst transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier Count the number of completed deferred transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier Count the number of completed instruction fetch transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier Count the number of completed invalidate transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier Count the number of completed memory transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier Count the number of completed partial write transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier Count the number of completed read-for-ownership transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier Count the number of completed I/O transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier Count the number of completed partial transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier Count the number of completed write-back transactions. An additional qualifier may be specified and comprises one of the following keywords:
p l -tag -width indent -compact t Li any Count transactions generated by any agent on the bus. t Li self Count transactions generated by this processor. .El
p The default is to count operations generated by this processor. t Li p6-cpu-clk-unhalted Count the number of cycles during with the processor was not halted.
p
q Tn "Pentium M" Count the number of cycles during with the processor was not halted and not in a thermal trip. t Li p6-cycles-div-busy Count the number of cycles during which the divider is busy and cannot accept new divides. This event is only allocated on counter 0. t Li p6-cycles-in-pending-and-masked Count the number of processor cycles for which interrupts were disabled and interrupts were pending. t Li p6-cycles-int-masked Count the number of processor cycles for which interrupts were disabled. t Li p6-data-mem-refs Count all loads and all stores using any memory type, including internal retries. Each part of a split store is counted separately. t Li p6-dcu-lines-in Count the total lines allocated in the data cache unit. t Li p6-dcu-m-lines-in Count the number of M state lines allocated in the data cache unit. t Li p6-dcu-m-lines-out Count the number of M state lines evicted from the data cache unit. t Li p6-dcu-miss-outstanding Count the weighted number of cycles while a data cache unit miss is outstanding, incremented by the number of outstanding cache misses at any time. t Li p6-div Count the number of integer and floating-point divides including speculative divides. This event is only allocated on counter 1. t Li p6-emon-esp-uops
q Tn "Pentium M" Count the total number of micro-ops. t Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
q Tn "Pentium M" Count the number of .Tn "Enhanced Intel SpeedStep" transitions. An additional qualifier may be specified, and can be one of the following keywords:
p l -tag -width indent -compact t Li all Count all transitions. t Li freq Count only frequency transitions. .El
p The default is to count all transitions. t Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
q Tn "Pentium M" Count the number of retired fused micro-ops. An additional qualifier may be specified, and may be one of the following keywords:
p l -tag -width indent -compact t Li all Count all fused micro-ops. t Li loadop Count only load and op micro-ops. t Li stdsta Count only STD/STA micro-ops. .El
p The default is to count all fused micro-ops. t Li p6-emon-kni-comp-inst-ret
q Tn "Pentium III" Count the number of SSE computational instructions retired. An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li packed-and-scalar Count packed and scalar operations. t Li scalar Count scalar operations only. .El
p The default is to count packed and scalar operations. t Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
q Tn "Pentium III" Count the number of SSE instructions retired. An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li packed-and-scalar Count packed and scalar operations. t Li scalar Count scalar operations only. .El
p The default is to count packed and scalar operations. t Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
q Tn "Pentium III" Count the number of SSE prefetch or weakly ordered instructions dispatched (including speculative prefetches). An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li nta Count non-temporal prefetches. t Li t1 Count prefetches to L1. t Li t2 Count prefetches to L2. t Li wos Count weakly ordered stores. .El
p The default is to count non-temporal prefetches. t Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
q Tn "Pentium III" Count the number of prefetch or weakly ordered instructions that miss all caches. An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li nta Count non-temporal prefetches. t Li t1 Count prefetches to L1. t Li t2 Count prefetches to L2. t Li wos Count weakly ordered stores. .El
p The default is to count non-temporal prefetches. t Li p6-emon-pref-rqsts-dn
q Tn "Pentium M" Count the number of downward prefetches issued. t Li p6-emon-pref-rqsts-up
q Tn "Pentium M" Count the number of upward prefetches issued. t Li p6-emon-simd-instr-retired
q Tn "Pentium M" Count the number of retired .Tn MMX instructions. t Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
q Tn "Pentium M" Count the number of computational SSE instructions retired. An additional qualifier may be specified and can be one of the following keywords:
p l -tag -width indent -compact t Li sse-packed-single Count SSE packed-single instructions. t Li sse-scalar-single Count SSE scalar-single instructions. t Li sse2-packed-double Count SSE2 packed-double instructions. t Li sse2-scalar-double Count SSE2 scalar-double instructions. .El
p The default is to count SSE packed-single instructions. t Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifer
p
q Tn "Pentium M" Count the number of SSE instructions retired. An additional qualifier can be specified, and can be one of the following keywords:
p l -tag -width indent -compact t Li sse-packed-single Count SSE packed-single instructions. t Li sse-packed-single-scalar-single Count SSE packed-single and scalar-single instructions. t Li sse2-packed-double Count SSE2 packed-double instructions. t Li sse2-scalar-double Count SSE2 scalar-double instructions. .El
p The default is to count SSE packed-single instructions. t Li p6-emon-synch-uops
q Tn "Pentium M" Count the number of sync micro-ops. t Li p6-emon-thermal-trip
q Tn "Pentium M" Count the duration or occurrences of thermal trips. Use the .Dq Li edge qualifier to count occurrences of thermal trips. t Li p6-emon-unfusion
q Tn "Pentium M" Count the number of unfusion events in the reorder buffer. t Li p6-flops Count the number of computational floating point operations retired. This event is only allocated on counter 0. t Li p6-fp-assist Count the number of floating point exceptions handled by microcode. This event is only allocated on counter 1. t Li p6-fp-comps-ops-exe Count the number of computation floating point operations executed. This event is only allocated on counter 0. t Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
q Tn "Pentium II" , Tn "Pentium III" Count the number of transitions between MMX and floating-point instructions. An additional qualifier may be specified, and comprises one of the following keywords:
p l -tag -width indent -compact t Li mmxtofp Count transitions from MMX instructions to floating-point instructions. t Li fptommx Count transitions from floating-point instructions to MMX instructions. .El
p The default is to count MMX to floating-point transitions. t Li p6-hw-int-rx Count the number of hardware interrupts received. t Li p6-ifu-fetch Count the number of instruction fetches, both cacheable and non-cacheable. t Li p6-ifu-fetch-miss Count the number of instruction fetch misses (i.e., those that produce memory accesses). t Li p6-ifu-mem-stall Count the number of cycles instruction fetch is stalled for any reason. t Li p6-ild-stall Count the number of cycles the instruction length decoder is stalled. t Li p6-inst-decoded Count the number of instructions decoded. t Li p6-inst-retired Count the number of instructions retired. t Li p6-itlb-miss Count the number of instruction TLB misses. t Li p6-l2-ads Count the number of L2 address strobes. t Li p6-l2-dbus-busy Count the number of cycles during which the L2 cache data bus was busy. t Li p6-l2-dbus-busy-rd Count the number of cycles during which the L2 cache data bus was busy transferring read data from L2 to the processor. t Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier Count the number of L2 instruction fetches. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li e Count operations affecting E (exclusive) state lines. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li s Count operations affecting S (shared) state lines. .El
p The default is to count operations affecting all (MESI) state lines. t Li p6-l2-ld Op Li ,umask= Ns Ar qualifier Count the number of L2 data loads. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li both
q Tn "Pentium M" Count both hardware-prefetched lines and non-hardware-prefetched lines. t Li e Count operations affecting E (exclusive) state lines. t Li hw
q Tn "Pentium M" Count hardware-prefetched lines only. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li nonhw
q Tn "Pentium M" Exclude hardware-prefetched lines. t Li s Count operations affecting S (shared) state lines. .El
p The default on processors other than .Tn "Pentium M" processors is to count operations affecting all (MESI) state lines. The default on .Tn "Pentium M" processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines.
q Errata This event is affected by processor errata E53. t Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier Count the number of L2 lines allocated. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li both
q Tn "Pentium M" Count both hardware-prefetched lines and non-hardware-prefetched lines. t Li e Count operations affecting E (exclusive) state lines. t Li hw
q Tn "Pentium M" Count hardware-prefetched lines only. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li nonhw
q Tn "Pentium M" Exclude hardware-prefetched lines. t Li s Count operations affecting S (shared) state lines. .El
p The default on processors other than .Tn "Pentium M" processors is to count operations affecting all (MESI) state lines. The default on .Tn "Pentium M" processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines.
q Errata This event is affected by processor errata E45. t Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier Count the number of L2 lines evicted. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li both
q Tn "Pentium M" Count both hardware-prefetched lines and non-hardware-prefetched lines. t Li e Count operations affecting E (exclusive) state lines. t Li hw
q Tn "Pentium M" Count hardware-prefetched lines only. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li nonhw
q Tn "Pentium M" only Exclude hardware-prefetched lines. t Li s Count operations affecting S (shared) state lines. .El
p The default on processors other than .Tn "Pentium M" processors is to count operations affecting all (MESI) state lines. The default on .Tn "Pentium M" processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines.
q Errata This event is affected by processor errata E45. t Li p6-l2-m-lines-inm Count the number of modified lines allocated in L2 cache. t Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier Count the number of L2 M-state lines evicted.
p
q Tn "Pentium M" On these processors an additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li both Count both hardware-prefetched lines and non-hardware-prefetched lines. t Li hw Count hardware-prefetched lines only. t Li nonhw Exclude hardware-prefetched lines. .El
p The default is to count both hardware-prefetched and non-hardware-prefetch operations.
q Errata This event is affected by processor errata E53. t Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier Count the total number of L2 requests. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li e Count operations affecting E (exclusive) state lines. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li s Count operations affecting S (shared) state lines. .El
p The default is to count operations affecting all (MESI) state lines. t Li p6-l2-st Count the number of L2 data stores. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li e Count operations affecting E (exclusive) state lines. t Li i Count operations affecting I (invalid) state lines. t Li m Count operations affecting M (modified) state lines. t Li s Count operations affecting S (shared) state lines. .El
p The default is to count operations affecting all (MESI) state lines. t Li p6-ld-blocks Count the number of load operations delayed due to store buffer blocks. t Li p6-misalign-mem-ref Count the number of misaligned data memory references (crossing a 64 bit boundary). t Li p6-mmx-assist
q Tn "Pentium II" , Tn "Pentium III" Count the number of MMX assists executed. t Li p6-mmx-instr-exec
q Tn Celeron , Tn "Pentium II" Count the number of MMX instructions executed, except MOVQ and MOVD stores from register to memory. t Li p6-mmx-instr-ret
q Tn "Pentium II" Count the number of MMX instructions retired. t Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
q Tn "Pentium II" , Tn "Pentium III" Count the number of MMX instructions executed. An additional qualifier may be specified and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li pack Count MMX pack operation instructions. t Li packed-arithmetic Count MMX packed arithmetic instructions. t Li packed-logical Count MMX packed logical instructions. t Li packed-multiply Count MMX packed multiply instructions. t Li packed-shift Count MMX packed shift instructions. t Li unpack Count MMX unpack operation instructions. .El
p The default is to count all operations. t Li p6-mmx-sat-instr-exec
q Tn "Pentium II" , Tn "Pentium III" Count the number of MMX saturating instructions executed. t Li p6-mmx-uops-exec
q Tn "Pentium II" , Tn "Pentium III" Count the number of MMX micro-ops executed. t Li p6-mul Count the number of integer and floating-point multiplies, including speculative multiplies. This event is only allocated on counter 1. t Li p6-partial-rat-stalls Count the number of cycles or events for partial stalls. t Li p6-resource-stalls Count the number of cycles there was a resource related stall of any kind. t Li p6-ret-seg-renames
q Tn "Pentium II" , Tn "Pentium III" Count the number of segment register rename events retired. t Li p6-sb-drains Count the number of cycles the store buffer is draining. t Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
q Tn "Pentium II" , Tn "Pentium III" Count the number of segment register renames. An additional qualifier may be specified, and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li ds Count renames for segment register DS. t Li es Count renames for segment register ES. t Li fs Count renames for segment register FS. t Li gs Count renames for segment register GS. .El
p The default is to count operations affecting all segment registers. t Li p6-seg-rename-stalls
q Tn "Pentium II" , Tn "Pentium III" Count the number of segment register renaming stalls. An additional qualifier may be specified, and comprises a list of the following keywords separated by .Ql + characters:
p l -tag -width indent -compact t Li ds Count stalls for segment register DS. t Li es Count stalls for segment register ES. t Li fs Count stalls for segment register FS. t Li gs Count stalls for segment register GS. .El
p The default is to count operations affecting all the segment registers. t Li p6-segment-reg-loads Count the number of segment register loads. t Li p6-uops-retired Count the number of micro-ops retired. .El .Ss Event Name Aliases The following table shows the mapping between the PMC-independent aliases supported by .Lb libpmc and the underlying hardware events used. l -column "branch-mispredicts" "Description" t Em Alias Ta Em Event t Li branches Ta Li p6-br-inst-retired t Li branch-mispredicts Ta Li p6-br-miss-pred-retired t Li dc-misses Ta Li p6-dcu-lines-in t Li ic-misses Ta Li p6-ifu-fetch-miss t Li instructions Ta Li p6-inst-retired t Li interrupts Ta Li p6-hw-int-rx t Li unhalted-cycles Ta Li p6-cpu-clk-unhalted .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.tsc 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org .