167117Sdfr.file "__divsi3.s" 267117Sdfr 367117Sdfr// 467117Sdfr// Copyright (c) 2000, Intel Corporation 567117Sdfr// All rights reserved. 667117Sdfr// 767117Sdfr// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 867117Sdfr// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 967117Sdfr// Intel Corporation. 1067117Sdfr// 1167117Sdfr// WARRANTY DISCLAIMER 1267117Sdfr// 1367117Sdfr// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1467117Sdfr// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1567117Sdfr// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1667117Sdfr// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 1767117Sdfr// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 1867117Sdfr// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1967117Sdfr// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2067117Sdfr// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 2167117Sdfr// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 2267117Sdfr// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 2367117Sdfr// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2467117Sdfr// 2567117Sdfr// Intel Corporation is the author of this code, and requests that all 2667117Sdfr// problem reports or change requests be submitted to it directly at 2767117Sdfr// http://developer.intel.com/opensource. 2867117Sdfr// 2967117Sdfr 30111777Sobrien#include <machine/asm.h> 31111777Sobrien__FBSDID("$FreeBSD$"); 32111777Sobrien 3367117Sdfr.section .text 3467117Sdfr 3567117Sdfr// 32-bit signed integer divide 3667117Sdfr 3767117Sdfr.proc __divsi3# 3867117Sdfr.align 32 3967117Sdfr.global __divsi3# 4067117Sdfr.align 32 4167117Sdfr 4267117Sdfr__divsi3: 4367117Sdfr 4467117Sdfr{ .mii 4567117Sdfr alloc r31=ar.pfs,2,0,0,0 4667117Sdfr nop.i 0 4767117Sdfr nop.i 0;; 4867117Sdfr} { .mii 4967117Sdfr nop.m 0 5067117Sdfr 5167117Sdfr // 32-BIT SIGNED INTEGER DIVIDE BEGINS HERE 5267117Sdfr 5367117Sdfr // general register used: 5467117Sdfr // r32 - 32-bit signed integer dividend 5567117Sdfr // r33 - 32-bit signed integer divisor 5667117Sdfr // r8 - 32-bit signed integer result 5767117Sdfr // r2 - scratch register 5867117Sdfr // floating-point registers used: f6, f7, f8, f9 5967117Sdfr // predicate registers used: p6 6067117Sdfr 6167117Sdfr sxt4 r32=r32 6267117Sdfr sxt4 r33=r33;; 6367117Sdfr} { .mmb 6467117Sdfr setf.sig f6=r32 6567117Sdfr setf.sig f7=r33 6667117Sdfr nop.b 0;; 6767117Sdfr} { .mfi 6867117Sdfr nop.m 0 6967117Sdfr fcvt.xf f6=f6 7067117Sdfr nop.i 0 7167117Sdfr} { .mfi 7267117Sdfr nop.m 0 7367117Sdfr fcvt.xf f7=f7 7467117Sdfr mov r2 = 0x0ffdd;; 7567117Sdfr} { .mfi 7667117Sdfr setf.exp f9 = r2 7767117Sdfr // (1) y0 7867117Sdfr frcpa.s1 f8,p6=f6,f7 7967117Sdfr nop.i 0;; 8067117Sdfr} { .mfi 8167117Sdfr nop.m 0 8267117Sdfr // (2) q0 = a * y0 8367117Sdfr (p6) fma.s1 f6=f6,f8,f0 8467117Sdfr nop.i 0 8567117Sdfr} { .mfi 8667117Sdfr nop.m 0 8767117Sdfr // (3) e0 = 1 - b * y0 8867117Sdfr (p6) fnma.s1 f7=f7,f8,f1 8967117Sdfr nop.i 0;; 9067117Sdfr} { .mfi 9167117Sdfr nop.m 0 9267117Sdfr // (4) q1 = q0 + e0 * q0 9367117Sdfr (p6) fma.s1 f6=f7,f6,f6 9467117Sdfr nop.i 0 9567117Sdfr} { .mfi 9667117Sdfr nop.m 0 9767117Sdfr // (5) e1 = e0 * e0 + 2^-34 9867117Sdfr (p6) fma.s1 f7=f7,f7,f9 9967117Sdfr nop.i 0;; 10067117Sdfr} { .mfi 10167117Sdfr nop.m 0 10267117Sdfr // (6) q2 = q1 + e1 * q1 10367117Sdfr (p6) fma.s1 f8=f7,f6,f6 10467117Sdfr nop.i 0;; 10567117Sdfr} { .mfi 10667117Sdfr nop.m 0 10767117Sdfr // (7) q = trunc(q2) 10867117Sdfr fcvt.fx.trunc.s1 f8=f8 10967117Sdfr nop.i 0;; 11067117Sdfr} { .mmi 11167117Sdfr // quotient will be in the least significant 32 bits of r8 (if b != 0) 11267117Sdfr getf.sig r8=f8 11367117Sdfr nop.m 0 11467117Sdfr nop.i 0;; 11567117Sdfr} 11667117Sdfr 11767117Sdfr // 32-BIT SIGNED INTEGER DIVIDE ENDS HERE 11867117Sdfr 11967117Sdfr{ .mmb 12067117Sdfr nop.m 0 12167117Sdfr nop.m 0 12267117Sdfr br.ret.sptk b0;; 12367117Sdfr} 12467117Sdfr 12567117Sdfr.endp __divsi3 126