1201360Srdivacky//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2201360Srdivacky//
3201360Srdivacky//                     The LLVM Compiler Infrastructure
4201360Srdivacky//
5201360Srdivacky// This file is distributed under the University of Illinois Open Source
6201360Srdivacky// License. See LICENSE.TXT for details.
7201360Srdivacky//
8201360Srdivacky//===----------------------------------------------------------------------===//
9201360Srdivacky//
10201360Srdivacky// This file is part of the X86 Disassembler Emitter.
11201360Srdivacky// It contains the interface of a single recognizable instruction.
12201360Srdivacky// Documentation for the disassembler emitter in general can be found in
13201360Srdivacky//  X86DisasemblerEmitter.h.
14201360Srdivacky//
15201360Srdivacky//===----------------------------------------------------------------------===//
16201360Srdivacky
17201360Srdivacky#ifndef X86RECOGNIZABLEINSTR_H
18201360Srdivacky#define X86RECOGNIZABLEINSTR_H
19201360Srdivacky
20252723Sdim#include "CodeGenTarget.h"
21201360Srdivacky#include "X86DisassemblerTables.h"
22252723Sdim#include "llvm/ADT/SmallVector.h"
23252723Sdim#include "llvm/Support/DataTypes.h"
24226890Sdim#include "llvm/TableGen/Record.h"
25201360Srdivacky
26201360Srdivackynamespace llvm {
27201360Srdivacky
28201360Srdivackynamespace X86Disassembler {
29201360Srdivacky
30201360Srdivacky/// RecognizableInstr - Encapsulates all information required to decode a single
31201360Srdivacky///   instruction, as extracted from the LLVM instruction tables.  Has methods
32201360Srdivacky///   to interpret the information available in the LLVM tables, and to emit the
33201360Srdivacky///   instruction into DisassemblerTables.
34201360Srdivackyclass RecognizableInstr {
35201360Srdivackyprivate:
36201360Srdivacky  /// The opcode of the instruction, as used in an MCInst
37201360Srdivacky  InstrUID UID;
38201360Srdivacky  /// The record from the .td files corresponding to this instruction
39201360Srdivacky  const Record* Rec;
40201360Srdivacky  /// The prefix field from the record
41201360Srdivacky  uint8_t Prefix;
42201360Srdivacky  /// The opcode field from the record; this is the opcode used in the Intel
43201360Srdivacky  /// encoding and therefore distinct from the UID
44201360Srdivacky  uint8_t Opcode;
45201360Srdivacky  /// The form field from the record
46201360Srdivacky  uint8_t Form;
47201360Srdivacky  /// The segment override field from the record
48201360Srdivacky  uint8_t SegOvr;
49201360Srdivacky  /// The hasOpSizePrefix field from the record
50201360Srdivacky  bool HasOpSizePrefix;
51235633Sdim  /// The hasAdSizePrefix field from the record
52235633Sdim  bool HasAdSizePrefix;
53201360Srdivacky  /// The hasREX_WPrefix field from the record
54201360Srdivacky  bool HasREX_WPrefix;
55221345Sdim  /// The hasVEXPrefix field from the record
56221345Sdim  bool HasVEXPrefix;
57210299Sed  /// The hasVEX_4VPrefix field from the record
58210299Sed  bool HasVEX_4VPrefix;
59235633Sdim  /// The hasVEX_4VOp3Prefix field from the record
60235633Sdim  bool HasVEX_4VOp3Prefix;
61221345Sdim  /// The hasVEX_WPrefix field from the record
62221345Sdim  bool HasVEX_WPrefix;
63221345Sdim  /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
64221345Sdim  bool HasVEX_LPrefix;
65235633Sdim  /// The hasMemOp4Prefix field from the record
66235633Sdim  bool HasMemOp4Prefix;
67235633Sdim  /// The ignoreVEX_L field from the record
68226890Sdim  bool IgnoresVEX_L;
69263509Sdim  /// The hasEVEXPrefix field from the record
70263509Sdim  bool HasEVEXPrefix;
71263509Sdim  /// The hasEVEX_L2Prefix field from the record
72263509Sdim  bool HasEVEX_L2Prefix;
73263509Sdim  /// The hasEVEX_K field from the record
74263509Sdim  bool HasEVEX_K;
75263509Sdim  /// The hasEVEX_KZ field from the record
76263509Sdim  bool HasEVEX_KZ;
77263509Sdim  /// The hasEVEX_B field from the record
78263509Sdim  bool HasEVEX_B;
79201360Srdivacky  /// The hasLockPrefix field from the record
80201360Srdivacky  bool HasLockPrefix;
81201360Srdivacky  /// The isCodeGenOnly filed from the record
82201360Srdivacky  bool IsCodeGenOnly;
83226890Sdim  // Whether the instruction has the predicate "In64BitMode"
84224145Sdim  bool Is64Bit;
85226890Sdim  // Whether the instruction has the predicate "In32BitMode"
86226890Sdim  bool Is32Bit;
87235633Sdim
88201360Srdivacky  /// The instruction name as listed in the tables
89201360Srdivacky  std::string Name;
90201360Srdivacky  /// The AT&T AsmString for the instruction
91201360Srdivacky  std::string AsmString;
92201360Srdivacky
93201360Srdivacky  /// Indicates whether the instruction is SSE
94201360Srdivacky  bool IsSSE;
95201360Srdivacky  /// Indicates whether the instruction has FR operands - MOVs with FR operands
96201360Srdivacky  /// are typically ignored
97201360Srdivacky  bool HasFROperands;
98201360Srdivacky  /// Indicates whether the instruction should be emitted into the decode
99201360Srdivacky  /// tables; regardless, it will be emitted into the instruction info table
100201360Srdivacky  bool ShouldBeEmitted;
101201360Srdivacky
102201360Srdivacky  /// The operands of the instruction, as listed in the CodeGenInstruction.
103201360Srdivacky  /// They are not one-to-one with operands listed in the MCInst; for example,
104201360Srdivacky  /// memory operands expand to 5 operands in the MCInst
105218893Sdim  const std::vector<CGIOperandList::OperandInfo>* Operands;
106218893Sdim
107201360Srdivacky  /// The description of the instruction that is emitted into the instruction
108201360Srdivacky  /// info table
109201360Srdivacky  InstructionSpecifier* Spec;
110201360Srdivacky
111201360Srdivacky  /// insnContext - Returns the primary context in which the instruction is
112201360Srdivacky  ///   valid.
113201360Srdivacky  ///
114201360Srdivacky  /// @return - The context in which the instruction is valid.
115201360Srdivacky  InstructionContext insnContext() const;
116201360Srdivacky
117201360Srdivacky  enum filter_ret {
118201360Srdivacky    FILTER_STRONG,    // instruction has no place in the instruction tables
119201360Srdivacky    FILTER_WEAK,      // instruction may conflict, and should be eliminated if
120201360Srdivacky                      // it does
121201360Srdivacky    FILTER_NORMAL     // instruction should have high priority and generate an
122201360Srdivacky                      // error if it conflcits with any other FILTER_NORMAL
123201360Srdivacky                      // instruction
124201360Srdivacky  };
125221345Sdim
126201360Srdivacky  /// filter - Determines whether the instruction should be decodable.  Some
127201360Srdivacky  ///   instructions are pure intrinsics and use unencodable operands; many
128201360Srdivacky  ///   synthetic instructions are duplicates of other instructions; other
129201360Srdivacky  ///   instructions only differ in the logical way in which they are used, and
130201360Srdivacky  ///   have the same decoding.  Because these would cause decode conflicts,
131201360Srdivacky  ///   they must be filtered out.
132201360Srdivacky  ///
133201360Srdivacky  /// @return - The degree of filtering to be applied (see filter_ret).
134201360Srdivacky  filter_ret filter() const;
135221345Sdim
136221345Sdim  /// hasFROperands - Returns true if any operand is a FR operand.
137221345Sdim  bool hasFROperands() const;
138245431Sdim
139201360Srdivacky  /// typeFromString - Translates an operand type from the string provided in
140201360Srdivacky  ///   the LLVM tables to an OperandType for use in the operand specifier.
141201360Srdivacky  ///
142201360Srdivacky  /// @param s              - The string, as extracted by calling Rec->getName()
143201360Srdivacky  ///                         on a CodeGenInstruction::OperandInfo.
144201360Srdivacky  /// @param isSSE          - Indicates whether the instruction is an SSE
145201360Srdivacky  ///                         instruction.  For SSE instructions, immediates are
146201360Srdivacky  ///                         fixed-size rather than being affected by the
147201360Srdivacky  ///                         mandatory OpSize prefix.
148201360Srdivacky  /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
149201360Srdivacky  ///                         prefix.  If it does, 32-bit register operands stay
150201360Srdivacky  ///                         32-bit regardless of the operand size.
151245431Sdim  /// @param hasOpSizePrefix  Indicates whether the instruction has an OpSize
152201360Srdivacky  ///                         prefix.  If it does not, then 16-bit register
153201360Srdivacky  ///                         operands stay 16-bit.
154201360Srdivacky  /// @return               - The operand's type.
155201360Srdivacky  static OperandType typeFromString(const std::string& s,
156201360Srdivacky                                    bool isSSE,
157201360Srdivacky                                    bool hasREX_WPrefix,
158201360Srdivacky                                    bool hasOpSizePrefix);
159201360Srdivacky
160201360Srdivacky  /// immediateEncodingFromString - Translates an immediate encoding from the
161201360Srdivacky  ///   string provided in the LLVM tables to an OperandEncoding for use in
162201360Srdivacky  ///   the operand specifier.
163201360Srdivacky  ///
164201360Srdivacky  /// @param s                - See typeFromString().
165201360Srdivacky  /// @param hasOpSizePrefix  - Indicates whether the instruction has an OpSize
166201360Srdivacky  ///                           prefix.  If it does not, then 16-bit immediate
167201360Srdivacky  ///                           operands stay 16-bit.
168201360Srdivacky  /// @return                 - The operand's encoding.
169201360Srdivacky  static OperandEncoding immediateEncodingFromString(const std::string &s,
170201360Srdivacky                                                     bool hasOpSizePrefix);
171201360Srdivacky
172201360Srdivacky  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
173201360Srdivacky  ///   handles operands that are in the REG field of the ModR/M byte.
174201360Srdivacky  static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
175201360Srdivacky                                                      bool hasOpSizePrefix);
176201360Srdivacky
177201360Srdivacky  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
178201360Srdivacky  ///   handles operands that are in the REG field of the ModR/M byte.
179201360Srdivacky  static OperandEncoding roRegisterEncodingFromString(const std::string &s,
180201360Srdivacky                                                      bool hasOpSizePrefix);
181201360Srdivacky  static OperandEncoding memoryEncodingFromString(const std::string &s,
182201360Srdivacky                                                  bool hasOpSizePrefix);
183201360Srdivacky  static OperandEncoding relocationEncodingFromString(const std::string &s,
184201360Srdivacky                                                      bool hasOpSizePrefix);
185201360Srdivacky  static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
186201360Srdivacky                                                          bool hasOpSizePrefix);
187221345Sdim  static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
188221345Sdim                                                        bool HasOpSizePrefix);
189263509Sdim  static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
190263509Sdim                                                             bool HasOpSizePrefix);
191201360Srdivacky
192201360Srdivacky  /// handleOperand - Converts a single operand from the LLVM table format to
193201360Srdivacky  ///   the emitted table format, handling any duplicate operands it encounters
194201360Srdivacky  ///   and then one non-duplicate.
195201360Srdivacky  ///
196201360Srdivacky  /// @param optional             - Determines whether to assert that the
197201360Srdivacky  ///                               operand exists.
198201360Srdivacky  /// @param operandIndex         - The index into the generated operand table.
199201360Srdivacky  ///                               Incremented by this function one or more
200201360Srdivacky  ///                               times to reflect possible duplicate
201201360Srdivacky  ///                               operands).
202201360Srdivacky  /// @param physicalOperandIndex - The index of the current operand into the
203201360Srdivacky  ///                               set of non-duplicate ('physical') operands.
204201360Srdivacky  ///                               Incremented by this function once.
205201360Srdivacky  /// @param numPhysicalOperands  - The number of non-duplicate operands in the
206201360Srdivacky  ///                               instructions.
207201360Srdivacky  /// @param operandMapping       - The operand mapping, which has an entry for
208201360Srdivacky  ///                               each operand that indicates whether it is a
209201360Srdivacky  ///                               duplicate, and of what.
210201360Srdivacky  void handleOperand(bool optional,
211201360Srdivacky                     unsigned &operandIndex,
212201360Srdivacky                     unsigned &physicalOperandIndex,
213201360Srdivacky                     unsigned &numPhysicalOperands,
214245431Sdim                     const unsigned *operandMapping,
215201360Srdivacky                     OperandEncoding (*encodingFromString)
216201360Srdivacky                       (const std::string&,
217201360Srdivacky                        bool hasOpSizePrefix));
218201360Srdivacky
219201360Srdivacky  /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
220201360Srdivacky  ///   filters out many instructions, at various points in decoding we
221201360Srdivacky  ///   determine that the instruction should not actually be decodable.  In
222201360Srdivacky  ///   particular, MMX MOV instructions aren't emitted, but they're only
223201360Srdivacky  ///   identified during operand parsing.
224201360Srdivacky  ///
225201360Srdivacky  /// @return - true if at this point we believe the instruction should be
226201360Srdivacky  ///   emitted; false if not.  This will return false if filter() returns false
227201360Srdivacky  ///   once emitInstructionSpecifier() has been called.
228201360Srdivacky  bool shouldBeEmitted() const {
229201360Srdivacky    return ShouldBeEmitted;
230201360Srdivacky  }
231201360Srdivacky
232201360Srdivacky  /// emitInstructionSpecifier - Loads the instruction specifier for the current
233201360Srdivacky  ///   instruction into a DisassemblerTables.
234201360Srdivacky  ///
235245431Sdim  /// \param tables The DisassemblerTables to populate with the specifier for
236201360Srdivacky  ///               the current instruction.
237201360Srdivacky  void emitInstructionSpecifier(DisassemblerTables &tables);
238201360Srdivacky
239201360Srdivacky  /// emitDecodePath - Populates the proper fields in the decode tables
240201360Srdivacky  ///   corresponding to the decode paths for this instruction.
241201360Srdivacky  ///
242245431Sdim  /// \param tables The DisassemblerTables to populate with the decode
243201360Srdivacky  ///               decode information for the current instruction.
244201360Srdivacky  void emitDecodePath(DisassemblerTables &tables) const;
245201360Srdivacky
246201360Srdivacky  /// Constructor - Initializes a RecognizableInstr with the appropriate fields
247201360Srdivacky  ///   from a CodeGenInstruction.
248201360Srdivacky  ///
249245431Sdim  /// \param tables The DisassemblerTables that the specifier will be added to.
250245431Sdim  /// \param insn   The CodeGenInstruction to extract information from.
251245431Sdim  /// \param uid    The unique ID of the current instruction.
252201360Srdivacky  RecognizableInstr(DisassemblerTables &tables,
253201360Srdivacky                    const CodeGenInstruction &insn,
254201360Srdivacky                    InstrUID uid);
255201360Srdivackypublic:
256201360Srdivacky  /// processInstr - Accepts a CodeGenInstruction and loads decode information
257201360Srdivacky  ///   for it into a DisassemblerTables if appropriate.
258201360Srdivacky  ///
259245431Sdim  /// \param tables The DiassemblerTables to be populated with decode
260201360Srdivacky  ///               information.
261245431Sdim  /// \param insn   The CodeGenInstruction to be used as a source for this
262201360Srdivacky  ///               information.
263245431Sdim  /// \param uid    The unique ID of the instruction.
264201360Srdivacky  static void processInstr(DisassemblerTables &tables,
265201360Srdivacky                           const CodeGenInstruction &insn,
266201360Srdivacky                           InstrUID uid);
267201360Srdivacky};
268201360Srdivacky
269201360Srdivacky} // namespace X86Disassembler
270201360Srdivacky
271201360Srdivacky} // namespace llvm
272201360Srdivacky
273201360Srdivacky#endif
274